2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/printk.h>
20 #include <linux/pci_ids.h>
21 #include <linux/netdevice.h>
22 #include <linux/sched.h>
23 #include <linux/mmc/sdio.h>
24 #include <asm/unaligned.h>
29 #include <brcmu_wifi.h>
30 #include <brcmu_utils.h>
36 /* ARM trap handling */
38 /* Trap types defined by ARM (see arminc.h) */
40 /* Trap locations in lo memory */
42 #define FIRST_TRAP TR_RST
43 #define LAST_TRAP (TR_FIQ * TRAP_STRIDE)
45 #if defined(__ARM_ARCH_4T__)
46 #define MAX_TRAP_TYPE (TR_FIQ + 1)
47 #elif defined(__ARM_ARCH_7M__)
48 #define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS)
49 #endif /* __ARM_ARCH_7M__ */
51 /* The trap structure is defined here as offsets for assembly */
57 #define TR_REG(n) (TR_REGS + (n) * 4)
58 #define TR_SP TR_REG(13)
59 #define TR_LR TR_REG(14)
60 #define TR_PC TR_REG(15)
62 #define TRAP_T_SIZE 80
64 typedef struct _trap_struct {
87 #define CBUF_LEN (128)
89 #define LOG_BUF_LEN 1024
92 u32 buf; /* Can't be pointer on (64-bit) hosts */
95 char *_buf_compat; /* Redundant pointer for backward compat. */
100 * When there is no UART (e.g. Quickturn),
101 * the host should write a complete
102 * input line directly into cbuf and then write
103 * the length into vcons_in.
104 * This may also be used when there is a real UART
105 * (at risk of conflicting with
106 * the real UART). vcons_out is currently unused.
108 volatile uint vcons_in;
109 volatile uint vcons_out;
111 /* Output (logging) buffer
112 * Console output is written to a ring buffer log_buf at index log_idx.
113 * The host may read the output when it sees log_idx advance.
114 * Output will be lost if the output wraps around faster than the host
119 /* Console input line buffer
120 * Characters are read one at a time into cbuf
121 * until <CR> is received, then
122 * the buffer is processed as a command line.
123 * Also used for virtual UART.
129 #endif /* DHD_DEBUG */
130 #include <chipcommon.h>
134 #include <dngl_stats.h>
137 #include <dhd_proto.h>
142 #ifndef DHDSDIO_MEM_DUMP_FNAME
143 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
146 #define TXQLEN 2048 /* bulk tx queue length */
147 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
148 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
151 #define TXRETRIES 2 /* # of retries for tx frames */
153 #if defined(CONFIG_MACH_SANDGATE2G)
154 #define DHD_RXBOUND 250 /* Default for max rx frames in
157 #define DHD_RXBOUND 50 /* Default for max rx frames in
159 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
161 #define DHD_TXBOUND 20 /* Default for max tx frames in
164 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
166 #define MEMBLOCK 2048 /* Block size used for downloading
168 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
169 biggest possible glom */
171 /* Packet alignment for most efficient SDIO (can change based on platform) */
173 #define DHD_SDALIGN 32
175 #if !ISPOWEROF2(DHD_SDALIGN)
176 #error DHD_SDALIGN is not a power of 2!
179 #ifndef DHD_FIRSTREAD
180 #define DHD_FIRSTREAD 32
182 #if !ISPOWEROF2(DHD_FIRSTREAD)
183 #error DHD_FIRSTREAD is not a power of 2!
186 /* Total length of frame header for dongle protocol */
187 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
189 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
191 #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
195 * Software allocation of To SB Mailbox resources
198 /* tosbmailbox bits corresponding to intstatus bits */
199 #define SMB_NAK (1 << 0) /* Frame NAK */
200 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
201 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
202 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
204 /* tosbmailboxdata */
205 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
208 * Software allocation of To Host Mailbox resources
212 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
213 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
214 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
215 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
217 /* tohostmailboxdata */
218 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
219 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
220 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
221 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
223 #define HMB_DATA_FCDATA_MASK 0xff000000
224 #define HMB_DATA_FCDATA_SHIFT 24
226 #define HMB_DATA_VERSION_MASK 0x00ff0000
227 #define HMB_DATA_VERSION_SHIFT 16
230 * Software-defined protocol header
233 /* Current protocol version */
234 #define SDPCM_PROT_VERSION 4
236 /* SW frame header */
237 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
239 #define SDPCM_CHANNEL_MASK 0x00000f00
240 #define SDPCM_CHANNEL_SHIFT 8
241 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
243 #define SDPCM_NEXTLEN_OFFSET 2
245 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
246 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
247 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
248 #define SDPCM_DOFFSET_MASK 0xff000000
249 #define SDPCM_DOFFSET_SHIFT 24
250 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
251 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
252 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
253 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
255 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
257 /* logical channel numbers */
258 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
259 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
260 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
261 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
262 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
264 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
266 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
268 /* For TEST_CHANNEL packets, define another 4-byte header */
269 #define SDPCM_TEST_HDRLEN 4 /*
270 * Generally: Cmd(1), Ext(1), Len(2);
271 * Semantics of Ext byte depend on
272 * command. Len is current or requested
273 * frame length, not including test
274 * header; sent little-endian.
276 #define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext:pattern id. */
277 #define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext:pattern id. */
278 #define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext:pattern id. */
279 #define SDPCM_TEST_BURST 0x04 /*
280 * Receiver to send a burst.
281 * Ext is a frame count
283 #define SDPCM_TEST_SEND 0x05 /*
284 * Receiver sets send mode.
285 * Ext is boolean on/off
288 /* Handy macro for filling in datagen packets with a pattern */
289 #define SDPCM_TEST_FILL(byteno, id) ((u8)(id + byteno))
292 * Shared structure between dongle and the host.
293 * The structure contains pointers to trap or assert information.
295 #define SDPCM_SHARED_VERSION 0x0002
296 #define SDPCM_SHARED_VERSION_MASK 0x00FF
297 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
298 #define SDPCM_SHARED_ASSERT 0x0200
299 #define SDPCM_SHARED_TRAP 0x0400
302 /* Space for header read, limit for data packets */
304 #define MAX_HDR_READ 32
306 #if !ISPOWEROF2(MAX_HDR_READ)
307 #error MAX_HDR_READ is not a power of 2!
310 #define MAX_RX_DATASZ 2048
312 /* Maximum milliseconds to wait for F2 to come up */
313 #define DHD_WAIT_F2RDY 3000
315 /* Bump up limit on waiting for HT to account for first startup;
316 * if the image is doing a CRC calculation before programming the PMU
317 * for HT availability, it could take a couple hundred ms more, so
318 * max out at a 1 second (1000000us).
320 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
321 #undef PMU_MAX_TRANSITION_DLY
322 #define PMU_MAX_TRANSITION_DLY 1000000
325 /* Value for ChipClockCSR during initial setup */
326 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
327 SBSDIO_ALP_AVAIL_REQ)
328 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
330 /* Flags for SDH calls */
331 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
334 #define SBIM_IBE 0x20000 /* inbanderror */
335 #define SBIM_TO 0x40000 /* timeout */
336 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
337 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
340 #define SBTML_RESET 0x0001 /* reset */
341 #define SBTML_REJ_MASK 0x0006 /* reject field */
342 #define SBTML_REJ 0x0002 /* reject */
343 #define SBTML_TMPREJ 0x0004 /* temporary reject, for error recovery */
345 #define SBTML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */
348 #define SBTMH_SERR 0x0001 /* serror */
349 #define SBTMH_INT 0x0002 /* interrupt */
350 #define SBTMH_BUSY 0x0004 /* busy */
351 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
353 #define SBTMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */
356 #define SBIDL_INIT 0x80 /* initiator */
359 #define SBIDH_RC_MASK 0x000f /* revision code */
360 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
361 #define SBIDH_RCE_SHIFT 8
362 #define SBCOREREV(sbidh) \
363 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
364 #define SBIDH_CC_MASK 0x8ff0 /* core code */
365 #define SBIDH_CC_SHIFT 4
366 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
367 #define SBIDH_VC_SHIFT 16
370 * Conversion of 802.1D priority to precedence level
372 #define PRIO2PREC(prio) \
373 (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
376 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
377 extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
380 /* Core reg address translation */
381 #define CORE_CC_REG(base, field) (base + offsetof(chipcregs_t, field))
382 #define CORE_BUS_REG(base, field) \
383 (base + offsetof(struct sdpcmd_regs, field))
384 #define CORE_SB(base, field) \
385 (base + SBCONFIGOFF + offsetof(sbconfig_t, field))
388 /* Device console log buffer state */
389 typedef struct dhd_console {
390 uint count; /* Poll interval msec counter */
391 uint log_addr; /* Log struct address (fixed) */
392 rte_log_t log; /* Log struct (host copy) */
393 uint bufsize; /* Size of log buffer */
394 u8 *buf; /* Log buffer (host copy) */
395 uint last; /* Last buffer read index */
397 #endif /* DHD_DEBUG */
399 struct sdpcm_shared {
403 u32 assert_file_addr;
405 u32 console_addr; /* Address of rte_cons_t */
411 /* misc chip info needed by some of the routines */
427 /* Private data for SDIO bus interaction */
428 typedef struct dhd_bus {
431 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
432 struct chip_info *ci; /* Chip info struct */
433 char *vars; /* Variables (from CIS and/or other) */
434 uint varsz; /* Size of variables buffer */
435 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
437 struct sdpcmd_regs *regs; /* SDIO core */
438 uint sdpcmrev; /* SDIO core revision */
439 uint armrev; /* CPU core revision */
440 uint ramrev; /* SOCRAM core revision */
441 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
442 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
444 u32 bus; /* gSPI or SDIO bus */
445 u32 hostintmask; /* Copy of Host Interrupt Mask */
446 u32 intstatus; /* Intstatus bits (events) pending */
447 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
448 bool fcstate; /* State of dongle flow-control */
450 u16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
451 char *fw_path; /* module_param: path to firmware image */
452 char *nv_path; /* module_param: path to nvram vars file */
453 const char *nvram_params; /* user specified nvram params. */
455 uint blocksize; /* Block size of SDIO transfers */
456 uint roundup; /* Max roundup limit */
458 struct pktq txq; /* Queue length used for flow-control */
459 u8 flowcontrol; /* per prio flow control bitmask */
460 u8 tx_seq; /* Transmit sequence number (next) */
461 u8 tx_max; /* Maximum transmit sequence allowed */
463 u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
464 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
465 u16 nextlen; /* Next Read Len from last header */
466 u8 rx_seq; /* Receive sequence number (expected) */
467 bool rxskip; /* Skip receive (awaiting NAK ACK) */
469 struct sk_buff *glomd; /* Packet containing glomming descriptor */
470 struct sk_buff *glom; /* Packet chain for glommed superframe */
471 uint glomerr; /* Glom packet read errors */
473 u8 *rxbuf; /* Buffer for receiving control packets */
474 uint rxblen; /* Allocated length of rxbuf */
475 u8 *rxctl; /* Aligned pointer into rxbuf */
476 u8 *databuf; /* Buffer for receiving big glom packet */
477 u8 *dataptr; /* Aligned pointer into databuf */
478 uint rxlen; /* Length of valid data in buffer */
480 u8 sdpcm_ver; /* Bus protocol reported by dongle */
482 bool intr; /* Use interrupts */
483 bool poll; /* Use polling */
484 bool ipend; /* Device interrupt is pending */
485 bool intdis; /* Interrupts disabled by isr */
486 uint intrcount; /* Count of device interrupt callbacks */
487 uint lastintrs; /* Count as of last watchdog timer */
488 uint spurious; /* Count of spurious interrupts */
489 uint pollrate; /* Ticks between device polls */
490 uint polltick; /* Tick counter */
491 uint pollcnt; /* Count of active polls */
494 dhd_console_t console; /* Console output polling support */
495 uint console_addr; /* Console address from shared struct */
496 #endif /* DHD_DEBUG */
498 uint regfails; /* Count of R_REG/W_REG failures */
500 uint clkstate; /* State of sd and backplane clock(s) */
501 bool activity; /* Activity flag for clock down */
502 s32 idletime; /* Control for activity timeout */
503 s32 idlecount; /* Activity timeout counter */
504 s32 idleclock; /* How to set bus driver when idle */
505 s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
506 bool use_rxchain; /* If dhd should use PKT chains */
507 bool sleeping; /* Is SDIO bus sleeping? */
508 bool rxflow_mode; /* Rx flow control mode */
509 bool rxflow; /* Is rx flow control on */
510 uint prev_rxlim_hit; /* Is prev rx limit exceeded
511 (per dpc schedule) */
512 bool alp_only; /* Don't use HT clock (ALP only) */
513 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
517 /* external loopback */
521 /* pktgen configuration */
522 uint pktgen_freq; /* Ticks between bursts */
523 uint pktgen_count; /* Packets to send each burst */
524 uint pktgen_print; /* Bursts between count displays */
525 uint pktgen_total; /* Stop after this many */
526 uint pktgen_minlen; /* Minimum packet data len */
527 uint pktgen_maxlen; /* Maximum packet data len */
528 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
529 uint pktgen_stop; /* Number of tx failures causing stop */
531 /* active pktgen fields */
532 uint pktgen_tick; /* Tick counter for bursts */
533 uint pktgen_ptick; /* Burst counter for printing */
534 uint pktgen_sent; /* Number of test packets generated */
535 uint pktgen_rcvd; /* Number of test packets received */
536 uint pktgen_fail; /* Number of failed send attempts */
537 u16 pktgen_len; /* Length of next packet to send */
540 /* Some additional counters */
541 uint tx_sderrs; /* Count of tx attempts with sd errors */
542 uint fcqueued; /* Tx packets that got queued */
543 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
544 uint rx_toolong; /* Receive frames too long to receive */
545 uint rxc_errors; /* SDIO errors when reading control frames */
546 uint rx_hdrfail; /* SDIO errors on header reads */
547 uint rx_badhdr; /* Bad received headers (roosync?) */
548 uint rx_badseq; /* Mismatched rx sequence number */
549 uint fc_rcvd; /* Number of flow-control events received */
550 uint fc_xoff; /* Number which turned on flow-control */
551 uint fc_xon; /* Number which turned off flow-control */
552 uint rxglomfail; /* Failed deglom attempts */
553 uint rxglomframes; /* Number of glom frames (superframes) */
554 uint rxglompkts; /* Number of packets from glom frames */
555 uint f2rxhdrs; /* Number of header reads */
556 uint f2rxdata; /* Number of frame data reads */
557 uint f2txdata; /* Number of f2 frame writes */
558 uint f1regdata; /* Number of f1 register accesses */
562 bool ctrl_frame_stat;
565 typedef volatile struct _sbconfig {
567 u32 sbipsflag; /* initiator port ocp slave flag */
569 u32 sbtpsflag; /* target port ocp slave flag */
571 u32 sbtmerrloga; /* (sonics >= 2.3) */
573 u32 sbtmerrlog; /* (sonics >= 2.3) */
575 u32 sbadmatch3; /* address match3 */
577 u32 sbadmatch2; /* address match2 */
579 u32 sbadmatch1; /* address match1 */
581 u32 sbimstate; /* initiator agent state */
582 u32 sbintvec; /* interrupt mask */
583 u32 sbtmstatelow; /* target state */
584 u32 sbtmstatehigh; /* target state */
585 u32 sbbwa0; /* bandwidth allocation table0 */
587 u32 sbimconfiglow; /* initiator configuration */
588 u32 sbimconfighigh; /* initiator configuration */
589 u32 sbadmatch0; /* address match0 */
591 u32 sbtmconfiglow; /* target configuration */
592 u32 sbtmconfighigh; /* target configuration */
593 u32 sbbconfig; /* broadcast configuration */
595 u32 sbbstate; /* broadcast state */
597 u32 sbactcnfg; /* activate configuration */
599 u32 sbflagst; /* current sbflags */
601 u32 sbidlow; /* identification */
602 u32 sbidhigh; /* identification */
608 #define CLK_PENDING 2 /* Not used yet */
611 #define DHD_NOPMU(dhd) (false)
614 static int qcount[NUMPRIO];
615 static int tx_packets[NUMPRIO];
616 #endif /* DHD_DEBUG */
618 /* Deferred transmit */
619 const uint dhd_deferred_tx = 1;
621 extern uint dhd_watchdog_ms;
622 extern void dhd_os_wd_timer(void *bus, uint wdtick);
629 /* override the RAM size if possible */
630 #define DONGLE_MIN_MEMSIZE (128 * 1024)
631 int dhd_dongle_memsize;
633 static bool dhd_alignctl;
637 static bool retrydata;
638 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
640 static const uint watermark = 8;
641 static const uint firstread = DHD_FIRSTREAD;
643 #define HDATLEN (firstread - (SDPCM_HDRLEN))
645 /* Retry count for register access failures */
646 static const uint retry_limit = 2;
648 /* Force even SD lengths (some host controllers mess up on odd bytes) */
649 static bool forcealign;
653 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
654 extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
657 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
658 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
659 #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
660 #define PKTALIGN(_p, _len, _align) \
663 datalign = (unsigned long)((_p)->data); \
664 datalign = roundup(datalign, (_align)) - datalign; \
665 ASSERT(datalign < (_align)); \
666 ASSERT((_p)->len >= ((_len) + datalign)); \
668 skb_pull((_p), datalign); \
669 __skb_trim((_p), (_len)); \
672 /* Limit on rounding up frames */
673 static const uint max_roundup = 512;
675 /* Try doing readahead */
676 static bool dhd_readahead;
678 /* To check if there's window offered */
679 #define DATAOK(bus) \
680 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
681 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
683 /* Macros to get register read/write status */
684 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
685 #define R_SDREG(regvar, regaddr, retryvar) \
689 regvar = R_REG(regaddr); \
690 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
692 bus->regfails += (retryvar-1); \
693 if (retryvar > retry_limit) { \
694 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
695 __func__, __LINE__)); \
701 #define W_SDREG(regval, regaddr, retryvar) \
705 W_REG(regaddr, regval); \
706 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
708 bus->regfails += (retryvar-1); \
709 if (retryvar > retry_limit) \
710 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
711 __func__, __LINE__)); \
715 #define DHD_BUS SDIO_BUS
717 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
719 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
722 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
723 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
727 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size);
728 static int dhdsdio_mem_dump(dhd_bus_t *bus);
729 #endif /* DHD_DEBUG */
730 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
732 static void dhdsdio_release(dhd_bus_t *bus);
733 static void dhdsdio_release_malloc(dhd_bus_t *bus);
734 static void dhdsdio_disconnect(void *ptr);
735 static bool dhdsdio_chipmatch(u16 chipid);
736 static bool dhdsdio_probe_attach(dhd_bus_t *bus, void *sdh,
737 void *regsva, u16 devid);
738 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh);
739 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh);
740 static void dhdsdio_release_dongle(dhd_bus_t *bus);
742 static uint process_nvram_vars(char *varbuf, uint len);
744 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
745 static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
746 uint flags, u8 *buf, uint nbytes,
747 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
750 static bool dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh);
751 static int _dhdsdio_download_firmware(struct dhd_bus *bus);
753 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
754 static int dhdsdio_download_nvram(struct dhd_bus *bus);
755 static void dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase);
756 static int dhdsdio_chip_attach(struct dhd_bus *bus, void *regs);
757 static void dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase);
758 static void dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus,
760 static void dhdsdio_chip_detach(struct dhd_bus *bus);
762 /* Packet free applicable unconditionally for sdio and sdspi.
763 * Conditional if bufpool was present for gspi bus.
765 static void dhdsdio_pktfree2(dhd_bus_t *bus, struct sk_buff *pkt)
767 dhd_os_sdlock_rxq(bus->dhd);
768 if ((bus->bus != SPI_BUS) || bus->usebufpool)
769 brcmu_pkt_buf_free_skb(pkt);
770 dhd_os_sdunlock_rxq(bus->dhd);
773 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
775 s32 min_size = DONGLE_MIN_MEMSIZE;
776 /* Restrict the memsize to user specified limit */
777 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
778 dhd_dongle_memsize, min_size));
779 if ((dhd_dongle_memsize > min_size) &&
780 (dhd_dongle_memsize < (s32) bus->orig_ramsize))
781 bus->ramsize = dhd_dongle_memsize;
784 static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
787 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
788 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
790 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
791 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
793 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
794 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
799 /* Turn backplane clock on or off */
800 static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
803 u8 clkctl, clkreq, devctl;
806 DHD_TRACE(("%s: Enter\n", __func__));
808 #if defined(OOB_INTR_ONLY)
815 /* Request HT Avail */
817 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
819 if ((bus->ci->chip == BCM4329_CHIP_ID)
820 && (bus->ci->chiprev == 0))
821 clkreq |= SBSDIO_FORCE_ALP;
823 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
826 DHD_ERROR(("%s: HT Avail request error: %d\n",
831 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
832 && (bus->ci->buscorerev == 9))) {
834 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
837 /* Check current status */
839 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
842 DHD_ERROR(("%s: HT Avail read error: %d\n",
847 /* Go to pending and await interrupt if appropriate */
848 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
849 /* Allow only clock-available interrupt */
851 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
854 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
859 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
860 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
862 DHD_INFO(("CLKCTL: set PENDING\n"));
863 bus->clkstate = CLK_PENDING;
866 } else if (bus->clkstate == CLK_PENDING) {
867 /* Cancel CA-only interrupt filter */
869 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
871 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
872 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
876 /* Otherwise, wait here (polling) for HT Avail */
877 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
878 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
880 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
881 SBSDIO_FUNC1_CHIPCLKCSR,
883 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
884 PMU_MAX_TRANSITION_DLY);
887 DHD_ERROR(("%s: HT Avail request error: %d\n",
891 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
892 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
893 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
897 /* Mark clock available */
898 bus->clkstate = CLK_AVAIL;
899 DHD_INFO(("CLKCTL: turned ON\n"));
901 #if defined(DHD_DEBUG)
902 if (bus->alp_only == true) {
903 #if !defined(BCMLXSDMMC)
904 if (!SBSDIO_ALPONLY(clkctl)) {
905 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
908 #endif /* !defined(BCMLXSDMMC) */
910 if (SBSDIO_ALPONLY(clkctl)) {
911 DHD_ERROR(("%s: HT Clock should be on.\n",
915 #endif /* defined (DHD_DEBUG) */
917 bus->activity = true;
921 if (bus->clkstate == CLK_PENDING) {
922 /* Cancel CA-only interrupt filter */
924 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
926 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
927 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
931 bus->clkstate = CLK_SDONLY;
932 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
934 DHD_INFO(("CLKCTL: turned OFF\n"));
936 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
944 /* Change idle/active SD state */
945 static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
947 DHD_TRACE(("%s: Enter\n", __func__));
950 bus->clkstate = CLK_SDONLY;
952 bus->clkstate = CLK_NONE;
957 /* Transition SD and backplane clock readiness */
958 static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
961 uint oldstate = bus->clkstate;
962 #endif /* DHD_DEBUG */
964 DHD_TRACE(("%s: Enter\n", __func__));
966 /* Early exit if we're already there */
967 if (bus->clkstate == target) {
968 if (target == CLK_AVAIL) {
969 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
970 bus->activity = true;
977 /* Make sure SD clock is available */
978 if (bus->clkstate == CLK_NONE)
979 dhdsdio_sdclk(bus, true);
980 /* Now request HT Avail on the backplane */
981 dhdsdio_htclk(bus, true, pendok);
982 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
983 bus->activity = true;
987 /* Remove HT request, or bring up SD clock */
988 if (bus->clkstate == CLK_NONE)
989 dhdsdio_sdclk(bus, true);
990 else if (bus->clkstate == CLK_AVAIL)
991 dhdsdio_htclk(bus, false, false);
993 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
994 bus->clkstate, target));
995 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
999 /* Make sure to remove HT request */
1000 if (bus->clkstate == CLK_AVAIL)
1001 dhdsdio_htclk(bus, false, false);
1002 /* Now remove the SD clock */
1003 dhdsdio_sdclk(bus, false);
1004 dhd_os_wd_timer(bus->dhd, 0);
1008 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
1009 #endif /* DHD_DEBUG */
1014 int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
1016 bcmsdh_info_t *sdh = bus->sdh;
1017 struct sdpcmd_regs *regs = bus->regs;
1020 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
1021 (sleep ? "SLEEP" : "WAKE"),
1022 (bus->sleeping ? "SLEEP" : "WAKE")));
1024 /* Done if we're already in the requested state */
1025 if (sleep == bus->sleeping)
1028 /* Going to sleep: set the alarm and turn off the lights... */
1030 /* Don't sleep if something is pending */
1031 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1034 /* Disable SDIO interrupts (no longer interested) */
1035 bcmsdh_intr_disable(bus->sdh);
1037 /* Make sure the controller has the bus up */
1038 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1040 /* Tell device to start using OOB wakeup */
1041 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
1042 if (retries > retry_limit)
1043 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1045 /* Turn off our contribution to the HT clock request */
1046 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1048 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
1049 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1051 /* Isolate the bus */
1052 if (bus->ci->chip != BCM4329_CHIP_ID
1053 && bus->ci->chip != BCM4319_CHIP_ID) {
1054 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
1055 SBSDIO_DEVCTL_PADS_ISO, NULL);
1059 bus->sleeping = true;
1062 /* Waking up: bus power up is ok, set local state */
1064 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
1067 /* Force pad isolation off if possible
1068 (in case power never toggled) */
1069 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1070 && (bus->ci->buscorerev >= 10))
1071 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
1074 /* Make sure the controller has the bus up */
1075 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1077 /* Send misc interrupt to indicate OOB not needed */
1078 W_SDREG(0, ®s->tosbmailboxdata, retries);
1079 if (retries <= retry_limit)
1080 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
1082 if (retries > retry_limit)
1083 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
1085 /* Make sure we have SD bus access */
1086 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1089 bus->sleeping = false;
1091 /* Enable interrupts again */
1092 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
1093 bus->intdis = false;
1094 bcmsdh_intr_enable(bus->sdh);
1101 #if defined(OOB_INTR_ONLY)
1102 void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
1105 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
1107 sdpcmd_regs_t *regs = bus->regs;
1110 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1111 if (enable == true) {
1113 /* Tell device to start using OOB wakeup */
1114 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
1115 if (retries > retry_limit)
1116 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1119 /* Send misc interrupt to indicate OOB not needed */
1120 W_SDREG(0, ®s->tosbmailboxdata, retries);
1121 if (retries <= retry_limit)
1122 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
1125 /* Turn off our contribution to the HT clock request */
1126 dhdsdio_clkctl(bus, CLK_SDONLY, false);
1127 #endif /* !defined(HW_OOB) */
1129 #endif /* defined(OOB_INTR_ONLY) */
1131 #define BUS_WAKE(bus) \
1133 if ((bus)->sleeping) \
1134 dhdsdio_bussleep((bus), false); \
1137 /* Writes a HW/SW header into the packet and sends it. */
1138 /* Assumes: (a) header space already there, (b) caller holds lock */
1139 static int dhdsdio_txpkt(dhd_bus_t *bus, struct sk_buff *pkt, uint chan,
1148 struct sk_buff *new;
1151 DHD_TRACE(("%s: Enter\n", __func__));
1155 if (bus->dhd->dongle_reset) {
1160 frame = (u8 *) (pkt->data);
1162 /* Add alignment padding, allocate new packet if needed */
1163 pad = ((unsigned long)frame % DHD_SDALIGN);
1165 if (skb_headroom(pkt) < pad) {
1166 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
1167 __func__, skb_headroom(pkt), pad));
1168 bus->dhd->tx_realloc++;
1169 new = brcmu_pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
1171 DHD_ERROR(("%s: couldn't allocate new %d-byte "
1173 __func__, pkt->len + DHD_SDALIGN));
1178 PKTALIGN(new, pkt->len, DHD_SDALIGN);
1179 memcpy(new->data, pkt->data, pkt->len);
1181 brcmu_pkt_buf_free_skb(pkt);
1182 /* free the pkt if canned one is not used */
1185 frame = (u8 *) (pkt->data);
1186 ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
1190 frame = (u8 *) (pkt->data);
1192 ASSERT((pad + SDPCM_HDRLEN) <= (int)(pkt->len));
1193 memset(frame, 0, pad + SDPCM_HDRLEN);
1196 ASSERT(pad < DHD_SDALIGN);
1198 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1199 len = (u16) (pkt->len);
1200 *(u16 *) frame = cpu_to_le16(len);
1201 *(((u16 *) frame) + 1) = cpu_to_le16(~len);
1203 /* Software tag: channel, sequence number, data offset */
1205 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
1207 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1209 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1210 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1213 tx_packets[pkt->priority]++;
1214 if (DHD_BYTES_ON() &&
1215 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
1216 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
1217 printk(KERN_DEBUG "Tx Frame:\n");
1218 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
1219 } else if (DHD_HDRS_ON()) {
1220 printk(KERN_DEBUG "TxHdr:\n");
1221 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1222 frame, min_t(u16, len, 16));
1226 /* Raise len to next SDIO block to eliminate tail command */
1227 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1228 u16 pad = bus->blocksize - (len % bus->blocksize);
1229 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1231 if (pad <= skb_tailroom(pkt))
1232 #endif /* NOTUSED */
1234 } else if (len % DHD_SDALIGN) {
1235 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1238 /* Some controllers have trouble with odd bytes -- round to even */
1239 if (forcealign && (len & (ALIGNMENT - 1))) {
1241 if (skb_tailroom(pkt))
1243 len = roundup(len, ALIGNMENT);
1246 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1253 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1254 F2SYNC, frame, len, pkt, NULL, NULL);
1256 ASSERT(ret != -BCME_PENDING);
1259 /* On failure, abort the command
1260 and terminate the frame */
1261 DHD_INFO(("%s: sdio error %d, abort command and "
1262 "terminate frame.\n", __func__, ret));
1265 bcmsdh_abort(sdh, SDIO_FUNC_2);
1266 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1267 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1271 for (i = 0; i < 3; i++) {
1273 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1274 SBSDIO_FUNC1_WFRAMEBCHI,
1276 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1277 SBSDIO_FUNC1_WFRAMEBCLO,
1279 bus->f1regdata += 2;
1280 if ((hi == 0) && (lo == 0))
1286 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1288 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1291 /* restore pkt buffer pointer before calling tx complete routine */
1292 skb_pull(pkt, SDPCM_HDRLEN + pad);
1293 dhd_os_sdunlock(bus->dhd);
1294 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1295 dhd_os_sdlock(bus->dhd);
1298 brcmu_pkt_buf_free_skb(pkt);
1303 int dhd_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
1308 DHD_TRACE(("%s: Enter\n", __func__));
1313 /* Push the test header if doing loopback */
1314 if (bus->ext_loop) {
1316 skb_push(pkt, SDPCM_TEST_HDRLEN);
1318 *data++ = SDPCM_TEST_ECHOREQ;
1319 *data++ = (u8) bus->loopid++;
1320 *data++ = (datalen >> 0);
1321 *data++ = (datalen >> 8);
1322 datalen += SDPCM_TEST_HDRLEN;
1326 /* Add space for the header */
1327 skb_push(pkt, SDPCM_HDRLEN);
1328 ASSERT(IS_ALIGNED((unsigned long)(pkt->data), 2));
1330 prec = PRIO2PREC((pkt->priority & PRIOMASK));
1332 /* Check for existing queue, current flow-control,
1333 pending event, or pending clock */
1334 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1335 || bus->dpc_sched || (!DATAOK(bus))
1336 || (bus->flowcontrol & NBITVAL(prec))
1337 || (bus->clkstate != CLK_AVAIL)) {
1338 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1339 pktq_len(&bus->txq)));
1342 /* Priority based enq */
1343 dhd_os_sdlock_txq(bus->dhd);
1344 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1345 skb_pull(pkt, SDPCM_HDRLEN);
1346 dhd_txcomplete(bus->dhd, pkt, false);
1347 brcmu_pkt_buf_free_skb(pkt);
1348 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1353 dhd_os_sdunlock_txq(bus->dhd);
1355 if (pktq_len(&bus->txq) >= TXHI)
1356 dhd_txflowcontrol(bus->dhd, 0, ON);
1359 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1360 qcount[prec] = pktq_plen(&bus->txq, prec);
1362 /* Schedule DPC if needed to send queued packet(s) */
1363 if (dhd_deferred_tx && !bus->dpc_sched) {
1364 bus->dpc_sched = true;
1365 dhd_sched_dpc(bus->dhd);
1368 /* Lock: we're about to use shared data/code (and SDIO) */
1369 dhd_os_sdlock(bus->dhd);
1371 /* Otherwise, send it now */
1373 /* Make sure back plane ht clk is on, no pending allowed */
1374 dhdsdio_clkctl(bus, CLK_AVAIL, true);
1377 DHD_TRACE(("%s: calling txpkt\n", __func__));
1378 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1380 ret = dhdsdio_txpkt(bus, pkt,
1381 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1382 SDPCM_DATA_CHANNEL), true);
1385 bus->dhd->tx_errors++;
1387 bus->dhd->dstats.tx_bytes += datalen;
1389 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1390 bus->activity = false;
1391 dhdsdio_clkctl(bus, CLK_NONE, true);
1394 dhd_os_sdunlock(bus->dhd);
1400 static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1402 struct sk_buff *pkt;
1405 int ret = 0, prec_out;
1410 dhd_pub_t *dhd = bus->dhd;
1411 struct sdpcmd_regs *regs = bus->regs;
1413 DHD_TRACE(("%s: Enter\n", __func__));
1415 tx_prec_map = ~bus->flowcontrol;
1417 /* Send frames until the limit or some other event */
1418 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1419 dhd_os_sdlock_txq(bus->dhd);
1420 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1422 dhd_os_sdunlock_txq(bus->dhd);
1425 dhd_os_sdunlock_txq(bus->dhd);
1426 datalen = pkt->len - SDPCM_HDRLEN;
1429 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1431 ret = dhdsdio_txpkt(bus, pkt,
1432 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1433 SDPCM_DATA_CHANNEL), true);
1436 bus->dhd->tx_errors++;
1438 bus->dhd->dstats.tx_bytes += datalen;
1440 /* In poll mode, need to check for other events */
1441 if (!bus->intr && cnt) {
1442 /* Check device status, signal pending interrupt */
1443 R_SDREG(intstatus, ®s->intstatus, retries);
1445 if (bcmsdh_regfail(bus->sdh))
1447 if (intstatus & bus->hostintmask)
1452 /* Deflow-control stack if needed */
1453 if (dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1454 dhd->txoff && (pktq_len(&bus->txq) < TXLOW))
1455 dhd_txflowcontrol(dhd, 0, OFF);
1460 int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1466 bcmsdh_info_t *sdh = bus->sdh;
1471 DHD_TRACE(("%s: Enter\n", __func__));
1473 if (bus->dhd->dongle_reset)
1476 /* Back the pointer to make a room for bus header */
1477 frame = msg - SDPCM_HDRLEN;
1478 len = (msglen += SDPCM_HDRLEN);
1480 /* Add alignment padding (optional for ctl frames) */
1482 doff = ((unsigned long)frame % DHD_SDALIGN);
1487 memset(frame, 0, doff + SDPCM_HDRLEN);
1489 ASSERT(doff < DHD_SDALIGN);
1491 doff += SDPCM_HDRLEN;
1493 /* Round send length to next SDIO block */
1494 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1495 u16 pad = bus->blocksize - (len % bus->blocksize);
1496 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1498 } else if (len % DHD_SDALIGN) {
1499 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1502 /* Satisfy length-alignment requirements */
1503 if (forcealign && (len & (ALIGNMENT - 1)))
1504 len = roundup(len, ALIGNMENT);
1506 ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1508 /* Need to lock here to protect txseq and SDIO tx calls */
1509 dhd_os_sdlock(bus->dhd);
1513 /* Make sure backplane clock is on */
1514 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1516 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1517 *(u16 *) frame = cpu_to_le16((u16) msglen);
1518 *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1520 /* Software tag: channel, sequence number, data offset */
1522 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1524 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1525 SDPCM_DOFFSET_MASK);
1526 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1527 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1530 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1531 __func__, bus->tx_max, bus->tx_seq));
1532 bus->ctrl_frame_stat = true;
1534 bus->ctrl_frame_buf = frame;
1535 bus->ctrl_frame_len = len;
1537 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1539 if (bus->ctrl_frame_stat == false) {
1540 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1543 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1550 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
1551 printk(KERN_DEBUG "Tx Frame:\n");
1552 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1554 } else if (DHD_HDRS_ON()) {
1555 printk(KERN_DEBUG "TxHdr:\n");
1556 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1557 frame, min_t(u16, len, 16));
1562 bus->ctrl_frame_stat = false;
1564 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1565 SDIO_FUNC_2, F2SYNC, frame, len,
1568 ASSERT(ret != -BCME_PENDING);
1571 /* On failure, abort the command and
1572 terminate the frame */
1573 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1577 bcmsdh_abort(sdh, SDIO_FUNC_2);
1579 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1580 SBSDIO_FUNC1_FRAMECTRL,
1584 for (i = 0; i < 3; i++) {
1586 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1587 SBSDIO_FUNC1_WFRAMEBCHI,
1589 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1590 SBSDIO_FUNC1_WFRAMEBCLO,
1592 bus->f1regdata += 2;
1593 if ((hi == 0) && (lo == 0))
1600 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1602 } while ((ret < 0) && retries++ < TXRETRIES);
1605 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1606 bus->activity = false;
1607 dhdsdio_clkctl(bus, CLK_NONE, true);
1610 dhd_os_sdunlock(bus->dhd);
1613 bus->dhd->tx_ctlerrs++;
1615 bus->dhd->tx_ctlpkts++;
1617 return ret ? -EIO : 0;
1620 int dhd_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1626 DHD_TRACE(("%s: Enter\n", __func__));
1628 if (bus->dhd->dongle_reset)
1631 /* Wait until control frame is available */
1632 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1634 dhd_os_sdlock(bus->dhd);
1636 memcpy(msg, bus->rxctl, min(msglen, rxlen));
1638 dhd_os_sdunlock(bus->dhd);
1641 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1642 __func__, rxlen, msglen));
1643 } else if (timeleft == 0) {
1644 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1646 dhd_os_sdlock(bus->dhd);
1647 dhdsdio_checkdied(bus, NULL, 0);
1648 dhd_os_sdunlock(bus->dhd);
1649 #endif /* DHD_DEBUG */
1650 } else if (pending == true) {
1651 DHD_CTL(("%s: cancelled\n", __func__));
1652 return -ERESTARTSYS;
1654 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1656 dhd_os_sdlock(bus->dhd);
1657 dhdsdio_checkdied(bus, NULL, 0);
1658 dhd_os_sdunlock(bus->dhd);
1659 #endif /* DHD_DEBUG */
1663 bus->dhd->rx_ctlpkts++;
1665 bus->dhd->rx_ctlerrs++;
1667 return rxlen ? (int)rxlen : -ETIMEDOUT;
1706 const struct brcmu_iovar dhdsdio_iovars[] = {
1707 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1708 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1709 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1710 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1711 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1712 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1713 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1714 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1715 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1716 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1717 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1718 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1719 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1720 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1721 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1722 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1724 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1726 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1728 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1730 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1732 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1734 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1736 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1738 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1741 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1743 #endif /* DHD_DEBUG */
1744 #endif /* DHD_DEBUG */
1746 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1748 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1756 dhd_dump_pct(struct brcmu_strbuf *strbuf, char *desc, uint num, uint div)
1761 brcmu_bprintf(strbuf, "%s N/A", desc);
1764 q2 = (100 * (num - (q1 * div))) / div;
1765 brcmu_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1769 void dhd_bus_dump(dhd_pub_t *dhdp, struct brcmu_strbuf *strbuf)
1771 dhd_bus_t *bus = dhdp->bus;
1773 brcmu_bprintf(strbuf, "Bus SDIO structure:\n");
1774 brcmu_bprintf(strbuf,
1775 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1776 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1777 brcmu_bprintf(strbuf,
1778 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1779 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1780 bus->rxskip, bus->rxlen, bus->rx_seq);
1781 brcmu_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1782 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1783 brcmu_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1784 bus->pollrate, bus->pollcnt, bus->regfails);
1786 brcmu_bprintf(strbuf, "\nAdditional counters:\n");
1787 brcmu_bprintf(strbuf,
1788 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1789 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1791 brcmu_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1792 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1793 brcmu_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n",
1794 bus->fc_rcvd, bus->fc_xoff, bus->fc_xon);
1795 brcmu_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1796 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1797 brcmu_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs"
1799 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1800 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1802 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1803 (bus->f2rxhdrs + bus->f2rxdata));
1804 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1806 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1807 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1808 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1810 brcmu_bprintf(strbuf, "\n");
1812 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1813 bus->dhd->rx_packets);
1814 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1816 brcmu_bprintf(strbuf, "\n");
1818 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1820 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1822 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1823 (bus->f2txdata + bus->f1regdata));
1824 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1826 brcmu_bprintf(strbuf, "\n");
1828 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1829 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1830 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1831 dhd_dump_pct(strbuf, ", pkts/f1sd",
1832 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1834 dhd_dump_pct(strbuf, ", pkts/sd",
1835 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1836 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1838 dhd_dump_pct(strbuf, ", pkts/int",
1839 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1841 brcmu_bprintf(strbuf, "\n\n");
1845 if (bus->pktgen_count) {
1846 brcmu_bprintf(strbuf, "pktgen config and count:\n");
1847 brcmu_bprintf(strbuf,
1848 "freq %d count %d print %d total %d min %d len %d\n",
1849 bus->pktgen_freq, bus->pktgen_count,
1850 bus->pktgen_print, bus->pktgen_total,
1851 bus->pktgen_minlen, bus->pktgen_maxlen);
1852 brcmu_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1853 bus->pktgen_sent, bus->pktgen_rcvd,
1858 brcmu_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1860 (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1861 brcmu_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1863 #endif /* DHD_DEBUG */
1864 brcmu_bprintf(strbuf,
1865 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1866 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1870 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1872 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1874 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1875 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1876 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1877 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1878 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1879 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1883 static int dhdsdio_pktgen_get(dhd_bus_t *bus, u8 *arg)
1885 dhd_pktgen_t pktgen;
1887 pktgen.version = DHD_PKTGEN_VERSION;
1888 pktgen.freq = bus->pktgen_freq;
1889 pktgen.count = bus->pktgen_count;
1890 pktgen.print = bus->pktgen_print;
1891 pktgen.total = bus->pktgen_total;
1892 pktgen.minlen = bus->pktgen_minlen;
1893 pktgen.maxlen = bus->pktgen_maxlen;
1894 pktgen.numsent = bus->pktgen_sent;
1895 pktgen.numrcvd = bus->pktgen_rcvd;
1896 pktgen.numfail = bus->pktgen_fail;
1897 pktgen.mode = bus->pktgen_mode;
1898 pktgen.stop = bus->pktgen_stop;
1900 memcpy(arg, &pktgen, sizeof(pktgen));
1905 static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
1907 dhd_pktgen_t pktgen;
1908 uint oldcnt, oldmode;
1910 memcpy(&pktgen, arg, sizeof(pktgen));
1911 if (pktgen.version != DHD_PKTGEN_VERSION)
1914 oldcnt = bus->pktgen_count;
1915 oldmode = bus->pktgen_mode;
1917 bus->pktgen_freq = pktgen.freq;
1918 bus->pktgen_count = pktgen.count;
1919 bus->pktgen_print = pktgen.print;
1920 bus->pktgen_total = pktgen.total;
1921 bus->pktgen_minlen = pktgen.minlen;
1922 bus->pktgen_maxlen = pktgen.maxlen;
1923 bus->pktgen_mode = pktgen.mode;
1924 bus->pktgen_stop = pktgen.stop;
1926 bus->pktgen_tick = bus->pktgen_ptick = 0;
1927 bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1928 bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1930 /* Clear counts for a new pktgen (mode change, or was stopped) */
1931 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1932 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1939 dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1946 /* Determine initial transfer parameters */
1947 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1948 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1949 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1953 /* Set the backplane window to include the start address */
1954 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1956 DHD_ERROR(("%s: window change failed\n", __func__));
1960 /* Do the transfer(s) */
1962 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1963 __func__, (write ? "write" : "read"), dsize,
1964 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
1966 bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
1968 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
1972 /* Adjust for next transfer (if any) */
1977 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1979 DHD_ERROR(("%s: window change failed\n",
1984 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
1989 /* Return the window to backplane enumeration space for core access */
1990 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
1991 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
1992 __func__, bcmsdh_cur_sbwad(bus->sdh)));
1999 static int dhdsdio_readshared(dhd_bus_t *bus, struct sdpcm_shared *sh)
2004 /* Read last word in memory to determine address of
2005 sdpcm_shared structure */
2006 rv = dhdsdio_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr, 4);
2010 addr = le32_to_cpu(addr);
2012 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
2015 * Check if addr is valid.
2016 * NVRAM length at the end of memory should have been overwritten.
2018 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
2019 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
2024 /* Read rte_shared structure */
2025 rv = dhdsdio_membytes(bus, false, addr, (u8 *) sh,
2026 sizeof(struct sdpcm_shared));
2031 sh->flags = le32_to_cpu(sh->flags);
2032 sh->trap_addr = le32_to_cpu(sh->trap_addr);
2033 sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
2034 sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
2035 sh->assert_line = le32_to_cpu(sh->assert_line);
2036 sh->console_addr = le32_to_cpu(sh->console_addr);
2037 sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
2039 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
2040 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
2041 "is different than sdpcm_shared version %d in dongle\n",
2042 __func__, SDPCM_SHARED_VERSION,
2043 sh->flags & SDPCM_SHARED_VERSION_MASK));
2050 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
2054 char *mbuffer = NULL;
2055 uint maxstrlen = 256;
2058 struct sdpcm_shared sdpcm_shared;
2059 struct brcmu_strbuf strbuf;
2061 DHD_TRACE(("%s: Enter\n", __func__));
2065 * Called after a rx ctrl timeout. "data" is NULL.
2066 * allocate memory to trace the trap or assert.
2069 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
2070 if (mbuffer == NULL) {
2071 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
2078 str = kmalloc(maxstrlen, GFP_ATOMIC);
2080 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
2085 bcmerror = dhdsdio_readshared(bus, &sdpcm_shared);
2089 brcmu_binit(&strbuf, data, size);
2091 brcmu_bprintf(&strbuf,
2092 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
2093 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
2095 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
2096 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2097 * (Avoids conflict with real asserts for programmatic
2098 * parsing of output.)
2100 brcmu_bprintf(&strbuf, "Assrt not built in dongle\n");
2103 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
2105 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
2106 * (Avoids conflict with real asserts for programmatic
2107 * parsing of output.)
2109 brcmu_bprintf(&strbuf, "No trap%s in dongle",
2110 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
2113 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
2114 /* Download assert */
2115 brcmu_bprintf(&strbuf, "Dongle assert");
2116 if (sdpcm_shared.assert_exp_addr != 0) {
2118 bcmerror = dhdsdio_membytes(bus, false,
2119 sdpcm_shared.assert_exp_addr,
2120 (u8 *) str, maxstrlen);
2124 str[maxstrlen - 1] = '\0';
2125 brcmu_bprintf(&strbuf, " expr \"%s\"", str);
2128 if (sdpcm_shared.assert_file_addr != 0) {
2130 bcmerror = dhdsdio_membytes(bus, false,
2131 sdpcm_shared.assert_file_addr,
2132 (u8 *) str, maxstrlen);
2136 str[maxstrlen - 1] = '\0';
2137 brcmu_bprintf(&strbuf, " file \"%s\"", str);
2140 brcmu_bprintf(&strbuf, " line %d ",
2141 sdpcm_shared.assert_line);
2144 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2145 bcmerror = dhdsdio_membytes(bus, false,
2146 sdpcm_shared.trap_addr, (u8 *)&tr,
2151 brcmu_bprintf(&strbuf,
2152 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
2153 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
2154 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
2155 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
2156 tr.r14, tr.pc, sdpcm_shared.trap_addr,
2157 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
2162 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
2163 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
2166 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2167 /* Mem dump to a file on device */
2168 dhdsdio_mem_dump(bus);
2170 #endif /* DHD_DEBUG */
2179 static int dhdsdio_mem_dump(dhd_bus_t *bus)
2182 int size; /* Full mem size */
2183 int start = 0; /* Start address */
2184 int read_size = 0; /* Read size of each iteration */
2185 u8 *buf = NULL, *databuf = NULL;
2187 /* Get full mem size */
2188 size = bus->ramsize;
2189 buf = kmalloc(size, GFP_ATOMIC);
2191 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
2195 /* Read mem content */
2196 printk(KERN_DEBUG "Dump dongle memory");
2199 read_size = min(MEMBLOCK, size);
2200 ret = dhdsdio_membytes(bus, false, start, databuf, read_size);
2202 DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
2208 /* Decrement size and increment start address */
2211 databuf += read_size;
2213 printk(KERN_DEBUG "Done\n");
2215 /* free buf before return !!! */
2216 if (write_to_file(bus->dhd, buf, bus->ramsize)) {
2217 DHD_ERROR(("%s: Error writing to files\n", __func__));
2221 /* buf free handled in write_to_file, not here */
2225 #define CONSOLE_LINE_MAX 192
2227 static int dhdsdio_readconsole(dhd_bus_t *bus)
2229 dhd_console_t *c = &bus->console;
2230 u8 line[CONSOLE_LINE_MAX], ch;
2234 /* Don't do anything until FWREADY updates console address */
2235 if (bus->console_addr == 0)
2238 /* Read console log struct */
2239 addr = bus->console_addr + offsetof(rte_cons_t, log);
2240 rv = dhdsdio_membytes(bus, false, addr, (u8 *)&c->log,
2245 /* Allocate console buffer (one time only) */
2246 if (c->buf == NULL) {
2247 c->bufsize = le32_to_cpu(c->log.buf_size);
2248 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2253 idx = le32_to_cpu(c->log.idx);
2255 /* Protect against corrupt value */
2256 if (idx > c->bufsize)
2259 /* Skip reading the console buffer if the index pointer
2264 /* Read the console buffer */
2265 addr = le32_to_cpu(c->log.buf);
2266 rv = dhdsdio_membytes(bus, false, addr, c->buf, c->bufsize);
2270 while (c->last != idx) {
2271 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2272 if (c->last == idx) {
2273 /* This would output a partial line.
2275 * the buffer pointer and output this
2276 * line next time around.
2281 c->last = c->bufsize - n;
2284 ch = c->buf[c->last];
2285 c->last = (c->last + 1) % c->bufsize;
2292 if (line[n - 1] == '\r')
2295 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2302 #endif /* DHD_DEBUG */
2304 int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2308 DHD_TRACE(("%s: Enter\n", __func__));
2310 /* Basic sanity checks */
2312 bcmerror = -EISCONN;
2316 bcmerror = -EOVERFLOW;
2320 /* Free the old ones and replace with passed variables */
2323 bus->vars = kmalloc(len, GFP_ATOMIC);
2324 bus->varsz = bus->vars ? len : 0;
2325 if (bus->vars == NULL) {
2330 /* Copy the passed variables, which should include the
2331 terminating double-null */
2332 memcpy(bus->vars, arg, bus->varsz);
2338 dhdsdio_doiovar(dhd_bus_t *bus, const struct brcmu_iovar *vi, u32 actionid,
2339 const char *name, void *params, int plen, void *arg, int len,
2346 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2347 "len %d val_size %d\n",
2348 __func__, actionid, name, params, plen, arg, len, val_size));
2350 bcmerror = brcmu_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2354 if (plen >= (int)sizeof(int_val))
2355 memcpy(&int_val, params, sizeof(int_val));
2357 bool_val = (int_val != 0) ? true : false;
2359 /* Some ioctls use the bus */
2360 dhd_os_sdlock(bus->dhd);
2362 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2363 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2364 actionid == IOV_GVAL(IOV_DEVRESET))) {
2369 /* Handle sleep stuff before any clock mucking */
2370 if (vi->varid == IOV_SLEEP) {
2371 if (IOV_ISSET(actionid)) {
2372 bcmerror = dhdsdio_bussleep(bus, bool_val);
2374 int_val = (s32) bus->sleeping;
2375 memcpy(arg, &int_val, val_size);
2380 /* Request clock to allow SDIO accesses */
2381 if (!bus->dhd->dongle_reset) {
2383 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2387 case IOV_GVAL(IOV_INTR):
2388 int_val = (s32) bus->intr;
2389 memcpy(arg, &int_val, val_size);
2392 case IOV_SVAL(IOV_INTR):
2393 bus->intr = bool_val;
2394 bus->intdis = false;
2397 DHD_INTR(("%s: enable SDIO device interrupts\n",
2399 bcmsdh_intr_enable(bus->sdh);
2401 DHD_INTR(("%s: disable SDIO interrupts\n",
2403 bcmsdh_intr_disable(bus->sdh);
2408 case IOV_GVAL(IOV_POLLRATE):
2409 int_val = (s32) bus->pollrate;
2410 memcpy(arg, &int_val, val_size);
2413 case IOV_SVAL(IOV_POLLRATE):
2414 bus->pollrate = (uint) int_val;
2415 bus->poll = (bus->pollrate != 0);
2418 case IOV_GVAL(IOV_IDLETIME):
2419 int_val = bus->idletime;
2420 memcpy(arg, &int_val, val_size);
2423 case IOV_SVAL(IOV_IDLETIME):
2424 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2427 bus->idletime = int_val;
2430 case IOV_GVAL(IOV_IDLECLOCK):
2431 int_val = (s32) bus->idleclock;
2432 memcpy(arg, &int_val, val_size);
2435 case IOV_SVAL(IOV_IDLECLOCK):
2436 bus->idleclock = int_val;
2439 case IOV_GVAL(IOV_SD1IDLE):
2440 int_val = (s32) sd1idle;
2441 memcpy(arg, &int_val, val_size);
2444 case IOV_SVAL(IOV_SD1IDLE):
2448 case IOV_SVAL(IOV_MEMBYTES):
2449 case IOV_GVAL(IOV_MEMBYTES):
2455 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2457 ASSERT(plen >= 2 * sizeof(int));
2459 address = (u32) int_val;
2460 memcpy(&int_val, (char *)params + sizeof(int_val),
2462 size = (uint) int_val;
2464 /* Do some validation */
2465 dsize = set ? plen - (2 * sizeof(int)) : len;
2467 DHD_ERROR(("%s: error on %s membytes, addr "
2468 "0x%08x size %d dsize %d\n",
2469 __func__, (set ? "set" : "get"),
2470 address, size, dsize));
2475 DHD_INFO(("%s: Request to %s %d bytes at address "
2477 __func__, (set ? "write" : "read"), size, address));
2479 /* If we know about SOCRAM, check for a fit */
2480 if ((bus->orig_ramsize) &&
2481 ((address > bus->orig_ramsize)
2482 || (address + size > bus->orig_ramsize))) {
2483 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2484 "bytes at 0x%08x\n",
2485 __func__, bus->orig_ramsize, size, address));
2490 /* Generate the actual data pointer */
2492 set ? (u8 *) params +
2493 2 * sizeof(int) : (u8 *) arg;
2495 /* Call to do the transfer */
2497 dhdsdio_membytes(bus, set, address, data, size);
2502 case IOV_GVAL(IOV_MEMSIZE):
2503 int_val = (s32) bus->ramsize;
2504 memcpy(arg, &int_val, val_size);
2507 case IOV_GVAL(IOV_SDIOD_DRIVE):
2508 int_val = (s32) dhd_sdiod_drive_strength;
2509 memcpy(arg, &int_val, val_size);
2512 case IOV_SVAL(IOV_SDIOD_DRIVE):
2513 dhd_sdiod_drive_strength = int_val;
2514 dhdsdio_sdiod_drive_strength_init(bus,
2515 dhd_sdiod_drive_strength);
2518 case IOV_SVAL(IOV_DOWNLOAD):
2519 bcmerror = dhdsdio_download_state(bus, bool_val);
2522 case IOV_SVAL(IOV_VARS):
2523 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2526 case IOV_GVAL(IOV_READAHEAD):
2527 int_val = (s32) dhd_readahead;
2528 memcpy(arg, &int_val, val_size);
2531 case IOV_SVAL(IOV_READAHEAD):
2532 if (bool_val && !dhd_readahead)
2534 dhd_readahead = bool_val;
2537 case IOV_GVAL(IOV_SDRXCHAIN):
2538 int_val = (s32) bus->use_rxchain;
2539 memcpy(arg, &int_val, val_size);
2542 case IOV_SVAL(IOV_SDRXCHAIN):
2543 if (bool_val && !bus->sd_rxchain)
2544 bcmerror = -ENOTSUPP;
2546 bus->use_rxchain = bool_val;
2548 case IOV_GVAL(IOV_ALIGNCTL):
2549 int_val = (s32) dhd_alignctl;
2550 memcpy(arg, &int_val, val_size);
2553 case IOV_SVAL(IOV_ALIGNCTL):
2554 dhd_alignctl = bool_val;
2557 case IOV_GVAL(IOV_SDALIGN):
2558 int_val = DHD_SDALIGN;
2559 memcpy(arg, &int_val, val_size);
2563 case IOV_GVAL(IOV_VARS):
2564 if (bus->varsz < (uint) len)
2565 memcpy(arg, bus->vars, bus->varsz);
2567 bcmerror = -EOVERFLOW;
2569 #endif /* DHD_DEBUG */
2572 case IOV_GVAL(IOV_SDREG):
2577 sd_ptr = (sdreg_t *) params;
2579 addr = (unsigned long)bus->regs + sd_ptr->offset;
2580 size = sd_ptr->func;
2581 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2582 if (bcmsdh_regfail(bus->sdh))
2584 memcpy(arg, &int_val, sizeof(s32));
2588 case IOV_SVAL(IOV_SDREG):
2593 sd_ptr = (sdreg_t *) params;
2595 addr = (unsigned long)bus->regs + sd_ptr->offset;
2596 size = sd_ptr->func;
2597 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2598 if (bcmsdh_regfail(bus->sdh))
2603 /* Same as above, but offset is not backplane
2605 case IOV_GVAL(IOV_SBREG):
2610 memcpy(&sdreg, params, sizeof(sdreg));
2612 addr = SI_ENUM_BASE + sdreg.offset;
2614 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2615 if (bcmsdh_regfail(bus->sdh))
2617 memcpy(arg, &int_val, sizeof(s32));
2621 case IOV_SVAL(IOV_SBREG):
2626 memcpy(&sdreg, params, sizeof(sdreg));
2628 addr = SI_ENUM_BASE + sdreg.offset;
2630 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2631 if (bcmsdh_regfail(bus->sdh))
2636 case IOV_GVAL(IOV_SDCIS):
2640 strcat(arg, "\nFunc 0\n");
2641 bcmsdh_cis_read(bus->sdh, 0x10,
2642 (u8 *) arg + strlen(arg),
2643 SBSDIO_CIS_SIZE_LIMIT);
2644 strcat(arg, "\nFunc 1\n");
2645 bcmsdh_cis_read(bus->sdh, 0x11,
2646 (u8 *) arg + strlen(arg),
2647 SBSDIO_CIS_SIZE_LIMIT);
2648 strcat(arg, "\nFunc 2\n");
2649 bcmsdh_cis_read(bus->sdh, 0x12,
2650 (u8 *) arg + strlen(arg),
2651 SBSDIO_CIS_SIZE_LIMIT);
2655 case IOV_GVAL(IOV_FORCEEVEN):
2656 int_val = (s32) forcealign;
2657 memcpy(arg, &int_val, val_size);
2660 case IOV_SVAL(IOV_FORCEEVEN):
2661 forcealign = bool_val;
2664 case IOV_GVAL(IOV_TXBOUND):
2665 int_val = (s32) dhd_txbound;
2666 memcpy(arg, &int_val, val_size);
2669 case IOV_SVAL(IOV_TXBOUND):
2670 dhd_txbound = (uint) int_val;
2673 case IOV_GVAL(IOV_RXBOUND):
2674 int_val = (s32) dhd_rxbound;
2675 memcpy(arg, &int_val, val_size);
2678 case IOV_SVAL(IOV_RXBOUND):
2679 dhd_rxbound = (uint) int_val;
2682 case IOV_GVAL(IOV_TXMINMAX):
2683 int_val = (s32) dhd_txminmax;
2684 memcpy(arg, &int_val, val_size);
2687 case IOV_SVAL(IOV_TXMINMAX):
2688 dhd_txminmax = (uint) int_val;
2690 #endif /* DHD_DEBUG */
2693 case IOV_GVAL(IOV_EXTLOOP):
2694 int_val = (s32) bus->ext_loop;
2695 memcpy(arg, &int_val, val_size);
2698 case IOV_SVAL(IOV_EXTLOOP):
2699 bus->ext_loop = bool_val;
2702 case IOV_GVAL(IOV_PKTGEN):
2703 bcmerror = dhdsdio_pktgen_get(bus, arg);
2706 case IOV_SVAL(IOV_PKTGEN):
2707 bcmerror = dhdsdio_pktgen_set(bus, arg);
2711 case IOV_SVAL(IOV_DEVRESET):
2712 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2714 __func__, bool_val, bus->dhd->dongle_reset,
2715 bus->dhd->busstate));
2717 dhd_bus_devreset(bus->dhd, (u8) bool_val);
2721 case IOV_GVAL(IOV_DEVRESET):
2722 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2724 /* Get its status */
2725 int_val = (bool) bus->dhd->dongle_reset;
2726 memcpy(arg, &int_val, val_size);
2731 bcmerror = -ENOTSUPP;
2736 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2737 bus->activity = false;
2738 dhdsdio_clkctl(bus, CLK_NONE, true);
2741 dhd_os_sdunlock(bus->dhd);
2743 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2744 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2749 static int dhdsdio_write_vars(dhd_bus_t *bus)
2757 char *nvram_ularray;
2758 #endif /* DHD_DEBUG */
2760 /* Even if there are no vars are to be written, we still
2761 need to set the ramsize. */
2762 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2763 varaddr = (bus->ramsize - 4) - varsize;
2766 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2770 memcpy(vbuffer, bus->vars, bus->varsz);
2772 /* Write the vars list */
2774 dhdsdio_membytes(bus, true, varaddr, vbuffer, varsize);
2776 /* Verify NVRAM bytes */
2777 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2778 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2782 /* Upload image to verify downloaded contents. */
2783 memset(nvram_ularray, 0xaa, varsize);
2785 /* Read the vars list to temp buffer for comparison */
2787 dhdsdio_membytes(bus, false, varaddr, nvram_ularray,
2790 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2791 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2793 /* Compare the org NVRAM with the one read from RAM */
2794 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2795 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2798 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2801 kfree(nvram_ularray);
2802 #endif /* DHD_DEBUG */
2807 /* adjust to the user specified RAM */
2808 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2809 bus->orig_ramsize, bus->ramsize));
2810 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2811 varsize = ((bus->orig_ramsize - 4) - varaddr);
2814 * Determine the length token:
2815 * Varsize, converted to words, in lower 16-bits, checksum
2821 varsizew = varsize / 4;
2822 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2823 varsizew = cpu_to_le32(varsizew);
2826 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2829 /* Write the length token to the last word */
2830 bcmerror = dhdsdio_membytes(bus, true, (bus->orig_ramsize - 4),
2831 (u8 *)&varsizew, 4);
2836 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2842 /* To enter download state, disable ARM and reset SOCRAM.
2843 * To exit download state, simply reset ARM (default is RAM boot).
2846 bus->alp_only = true;
2848 dhdsdio_chip_disablecore(bus->sdh, bus->ci->armcorebase);
2850 dhdsdio_chip_resetcore(bus->sdh, bus->ci->ramcorebase);
2852 /* Clear the top bit of memory */
2855 dhdsdio_membytes(bus, true, bus->ramsize - 4,
2859 regdata = bcmsdh_reg_read(bus->sdh,
2860 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
2861 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
2862 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
2863 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
2864 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2870 bcmerror = dhdsdio_write_vars(bus);
2872 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2876 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2878 dhdsdio_chip_resetcore(bus->sdh, bus->ci->armcorebase);
2880 /* Allow HT Clock now that the ARM is running. */
2881 bus->alp_only = false;
2883 bus->dhd->busstate = DHD_BUS_LOAD;
2890 dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2891 void *params, int plen, void *arg, int len, bool set)
2893 dhd_bus_t *bus = dhdp->bus;
2894 const struct brcmu_iovar *vi = NULL;
2899 DHD_TRACE(("%s: Enter\n", __func__));
2904 /* Get MUST have return space */
2905 ASSERT(set || (arg && len));
2907 /* Set does NOT take qualifiers */
2908 ASSERT(!set || (!params && !plen));
2910 /* Look up var locally; if not found pass to host driver */
2911 vi = brcmu_iovar_lookup(dhdsdio_iovars, name);
2913 dhd_os_sdlock(bus->dhd);
2917 /* Turn on clock in case SD command needs backplane */
2918 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2921 bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2924 /* Similar check for blocksize change */
2925 if (set && strcmp(name, "sd_blocksize") == 0) {
2928 (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2929 &bus->blocksize, sizeof(s32),
2932 DHD_ERROR(("%s: fail on %s get\n", __func__,
2935 DHD_INFO(("%s: noted %s update, value now %d\n",
2936 __func__, "sd_blocksize",
2940 bus->roundup = min(max_roundup, bus->blocksize);
2942 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2943 bus->activity = false;
2944 dhdsdio_clkctl(bus, CLK_NONE, true);
2947 dhd_os_sdunlock(bus->dhd);
2951 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2952 name, (set ? "set" : "get"), len, plen));
2954 /* set up 'params' pointer in case this is a set command so that
2955 * the convenience int and bool code can be common to set and get
2957 if (params == NULL) {
2962 if (vi->type == IOVT_VOID)
2964 else if (vi->type == IOVT_BUFFER)
2967 /* all other types are integer sized */
2968 val_size = sizeof(int);
2970 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
2972 dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
2979 void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2981 u32 local_hostintmask;
2986 DHD_TRACE(("%s: Enter\n", __func__));
2989 dhd_os_sdlock(bus->dhd);
2993 /* Enable clock for device interrupts */
2994 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2996 /* Disable and clear interrupts at the chip level also */
2997 W_SDREG(0, &bus->regs->hostintmask, retries);
2998 local_hostintmask = bus->hostintmask;
2999 bus->hostintmask = 0;
3001 /* Change our idea of bus state */
3002 bus->dhd->busstate = DHD_BUS_DOWN;
3004 /* Force clocks on backplane to be sure F2 interrupt propagates */
3006 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3009 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3010 (saveclk | SBSDIO_FORCE_HT), &err);
3013 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3017 /* Turn off the bus (F2), free any pending packets */
3018 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3019 bcmsdh_intr_disable(bus->sdh);
3020 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
3021 SDIO_FUNC_ENABLE_1, NULL);
3023 /* Clear any pending interrupts now that F2 is disabled */
3024 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
3026 /* Turn off the backplane clock (only) */
3027 dhdsdio_clkctl(bus, CLK_SDONLY, false);
3029 /* Clear the data packet queues */
3030 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
3032 /* Clear any held glomming stuff */
3034 brcmu_pkt_buf_free_skb(bus->glomd);
3037 brcmu_pkt_buf_free_skb(bus->glom);
3039 bus->glom = bus->glomd = NULL;
3041 /* Clear rx control and wake any waiters */
3043 dhd_os_ioctl_resp_wake(bus->dhd);
3045 /* Reset some F2 state stuff */
3046 bus->rxskip = false;
3047 bus->tx_seq = bus->rx_seq = 0;
3050 dhd_os_sdunlock(bus->dhd);
3053 int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
3055 dhd_bus_t *bus = dhdp->bus;
3062 DHD_TRACE(("%s: Enter\n", __func__));
3069 dhd_os_sdlock(bus->dhd);
3071 /* Make sure backplane clock is on, needed to generate F2 interrupt */
3072 dhdsdio_clkctl(bus, CLK_AVAIL, false);
3073 if (bus->clkstate != CLK_AVAIL)
3076 /* Force clocks on backplane to be sure F2 interrupt propagates */
3078 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3081 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3082 (saveclk | SBSDIO_FORCE_HT), &err);
3085 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
3090 /* Enable function 2 (frame transfers) */
3091 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
3092 &bus->regs->tosbmailboxdata, retries);
3093 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
3095 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, enable, NULL);
3097 /* Give the dongle some time to do its thing and set IOR2 */
3098 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
3101 while (ready != enable && !dhd_timeout_expired(&tmo))
3103 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IORx,
3106 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
3107 __func__, enable, ready, tmo.elapsed));
3109 /* If F2 successfully enabled, set core and enable interrupts */
3110 if (ready == enable) {
3111 /* Set up the interrupt mask and enable interrupts */
3112 bus->hostintmask = HOSTINTMASK;
3113 W_SDREG(bus->hostintmask,
3114 (unsigned int *)CORE_BUS_REG(bus->ci->buscorebase,
3115 hostintmask), retries);
3117 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
3118 (u8) watermark, &err);
3120 /* Set bus state according to enable result */
3121 dhdp->busstate = DHD_BUS_DATA;
3123 /* bcmsdh_intr_unmask(bus->sdh); */
3125 bus->intdis = false;
3127 DHD_INTR(("%s: enable SDIO device interrupts\n",
3129 bcmsdh_intr_enable(bus->sdh);
3131 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3132 bcmsdh_intr_disable(bus->sdh);
3138 /* Disable F2 again */
3139 enable = SDIO_FUNC_ENABLE_1;
3140 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, enable,
3144 /* Restore previous clock setting */
3145 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3148 /* If we didn't come up, turn off backplane clock */
3149 if (dhdp->busstate != DHD_BUS_DATA)
3150 dhdsdio_clkctl(bus, CLK_NONE, false);
3154 dhd_os_sdunlock(bus->dhd);
3159 static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3161 bcmsdh_info_t *sdh = bus->sdh;
3162 struct sdpcmd_regs *regs = bus->regs;
3168 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3169 (abort ? "abort command, " : ""),
3170 (rtx ? ", send NAK" : "")));
3173 bcmsdh_abort(sdh, SDIO_FUNC_2);
3175 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3179 /* Wait until the packet has been flushed (device/FIFO stable) */
3180 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3181 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3183 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3185 bus->f1regdata += 2;
3187 if ((hi == 0) && (lo == 0))
3190 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3191 DHD_ERROR(("%s: count growing: last 0x%04x now "
3193 __func__, lastrbc, ((hi << 8) + lo)));
3195 lastrbc = (hi << 8) + lo;
3199 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3200 __func__, lastrbc));
3202 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3203 (0xffff - retries)));
3208 W_SDREG(SMB_NAK, ®s->tosbmailbox, retries);
3210 if (retries <= retry_limit)
3214 /* Clear partial in any case */
3217 /* If we can't reach the device, signal failure */
3218 if (err || bcmsdh_regfail(sdh))
3219 bus->dhd->busstate = DHD_BUS_DOWN;
3223 dhdsdio_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3225 bcmsdh_info_t *sdh = bus->sdh;
3230 DHD_TRACE(("%s: Enter\n", __func__));
3232 /* Control data already received in aligned rxctl */
3233 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3237 /* Set rxctl for frame (w/optional alignment) */
3238 bus->rxctl = bus->rxbuf;
3240 bus->rxctl += firstread;
3241 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3243 bus->rxctl += (DHD_SDALIGN - pad);
3244 bus->rxctl -= firstread;
3246 ASSERT(bus->rxctl >= bus->rxbuf);
3248 /* Copy the already-read portion over */
3249 memcpy(bus->rxctl, hdr, firstread);
3250 if (len <= firstread)
3253 /* Copy the full data pkt in gSPI case and process ioctl. */
3254 if (bus->bus == SPI_BUS) {
3255 memcpy(bus->rxctl, hdr, len);
3259 /* Raise rdlen to next SDIO block to avoid tail command */
3260 rdlen = len - firstread;
3261 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3262 pad = bus->blocksize - (rdlen % bus->blocksize);
3263 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3264 ((len + pad) < bus->dhd->maxctl))
3266 } else if (rdlen % DHD_SDALIGN) {
3267 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3270 /* Satisfy length-alignment requirements */
3271 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3272 rdlen = roundup(rdlen, ALIGNMENT);
3274 /* Drop if the read is too big or it exceeds our maximum */
3275 if ((rdlen + firstread) > bus->dhd->maxctl) {
3276 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3277 __func__, rdlen, bus->dhd->maxctl));
3278 bus->dhd->rx_errors++;
3279 dhdsdio_rxfail(bus, false, false);
3283 if ((len - doff) > bus->dhd->maxctl) {
3284 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3286 __func__, len, (len - doff), bus->dhd->maxctl));
3287 bus->dhd->rx_errors++;
3289 dhdsdio_rxfail(bus, false, false);
3293 /* Read remainder of frame body into the rxctl buffer */
3294 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3295 F2SYNC, (bus->rxctl + firstread), rdlen,
3298 ASSERT(sdret != -BCME_PENDING);
3300 /* Control frame failures need retransmission */
3302 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3303 __func__, rdlen, sdret));
3304 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3305 dhdsdio_rxfail(bus, true, true);
3312 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
3313 printk(KERN_DEBUG "RxCtrl:\n");
3314 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
3318 /* Point to valid data and indicate its length */
3320 bus->rxlen = len - doff;
3323 /* Awake any waiters */
3324 dhd_os_ioctl_resp_wake(bus->dhd);
3327 static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq)
3333 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3336 u8 chan, seq, doff, sfdoff;
3340 bool usechain = bus->use_rxchain;
3342 /* If packets, issue read(s) and send up packet chain */
3343 /* Return sequence numbers consumed? */
3345 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3348 /* If there's a descriptor, generate the packet chain */
3350 dhd_os_sdlock_rxq(bus->dhd);
3352 pfirst = plast = pnext = NULL;
3353 dlen = (u16) (bus->glomd->len);
3354 dptr = bus->glomd->data;
3355 if (!dlen || (dlen & 1)) {
3356 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3361 for (totlen = num = 0; dlen; num++) {
3362 /* Get (and move past) next length */
3363 sublen = get_unaligned_le16(dptr);
3364 dlen -= sizeof(u16);
3365 dptr += sizeof(u16);
3366 if ((sublen < SDPCM_HDRLEN) ||
3367 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3368 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3369 __func__, num, sublen));
3373 if (sublen % DHD_SDALIGN) {
3374 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3375 __func__, sublen, DHD_SDALIGN));
3380 /* For last frame, adjust read len so total
3381 is a block multiple */
3384 (roundup(totlen, bus->blocksize) - totlen);
3385 totlen = roundup(totlen, bus->blocksize);
3388 /* Allocate/chain packet for next subframe */
3389 pnext = brcmu_pkt_buf_get_skb(sublen + DHD_SDALIGN);
3390 if (pnext == NULL) {
3391 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed, "
3392 "num %d len %d\n", __func__,
3396 ASSERT(!(pnext->prev));
3399 pfirst = plast = pnext;
3402 plast->next = pnext;
3406 /* Adhere to start alignment requirements */
3407 PKTALIGN(pnext, sublen, DHD_SDALIGN);
3410 /* If all allocations succeeded, save packet chain
3413 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3414 "subframes\n", __func__, totlen, num));
3415 if (DHD_GLOM_ON() && bus->nextlen) {
3416 if (totlen != bus->nextlen) {
3417 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3418 __func__, bus->nextlen,
3423 pfirst = pnext = NULL;
3426 brcmu_pkt_buf_free_skb(pfirst);
3431 /* Done with descriptor packet */
3432 brcmu_pkt_buf_free_skb(bus->glomd);
3436 dhd_os_sdunlock_rxq(bus->dhd);
3439 /* Ok -- either we just generated a packet chain,
3440 or had one from before */
3442 if (DHD_GLOM_ON()) {
3443 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3445 for (pnext = bus->glom; pnext; pnext = pnext->next) {
3446 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3447 pnext, (u8 *) (pnext->data),
3448 pnext->len, pnext->len));
3453 dlen = (u16) brcmu_pkttotlen(pfirst);
3455 /* Do an SDIO read for the superframe. Configurable iovar to
3456 * read directly into the chained packet, or allocate a large
3457 * packet and and copy into the chain.
3460 errcode = bcmsdh_recv_buf(bus,
3461 bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3462 F2SYNC, (u8 *) pfirst->data, dlen,
3463 pfirst, NULL, NULL);
3464 } else if (bus->dataptr) {
3465 errcode = bcmsdh_recv_buf(bus,
3466 bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3467 F2SYNC, bus->dataptr, dlen,
3469 sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen,
3471 if (sublen != dlen) {
3472 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3473 __func__, dlen, sublen));
3478 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3483 ASSERT(errcode != -BCME_PENDING);
3485 /* On failure, kill the superframe, allow a couple retries */
3487 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3488 __func__, dlen, errcode));
3489 bus->dhd->rx_errors++;
3491 if (bus->glomerr++ < 3) {
3492 dhdsdio_rxfail(bus, true, true);
3495 dhdsdio_rxfail(bus, true, false);
3496 dhd_os_sdlock_rxq(bus->dhd);
3497 brcmu_pkt_buf_free_skb(bus->glom);
3498 dhd_os_sdunlock_rxq(bus->dhd);
3505 if (DHD_GLOM_ON()) {
3506 printk(KERN_DEBUG "SUPERFRAME:\n");
3507 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3508 pfirst->data, min_t(int, pfirst->len, 48));
3512 /* Validate the superframe header */
3513 dptr = (u8 *) (pfirst->data);
3514 sublen = get_unaligned_le16(dptr);
3515 check = get_unaligned_le16(dptr + sizeof(u16));
3517 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3518 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3519 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3520 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3521 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3522 __func__, bus->nextlen, seq));
3525 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3526 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3529 if ((u16)~(sublen ^ check)) {
3530 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3531 "0x%04x/0x%04x\n", __func__, sublen, check));
3533 } else if (roundup(sublen, bus->blocksize) != dlen) {
3534 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3535 "0x%04x, expect 0x%04x\n",
3537 roundup(sublen, bus->blocksize), dlen));
3539 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3540 SDPCM_GLOM_CHANNEL) {
3541 DHD_ERROR(("%s (superframe): bad channel %d\n",
3543 SDPCM_PACKET_CHANNEL(&dptr
3544 [SDPCM_FRAMETAG_LEN])));
3546 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3547 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3550 } else if ((doff < SDPCM_HDRLEN) ||
3551 (doff > (pfirst->len - SDPCM_HDRLEN))) {
3552 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3554 __func__, doff, sublen,
3555 pfirst->len, SDPCM_HDRLEN));
3559 /* Check sequence number of superframe SW header */
3561 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3562 __func__, seq, rxseq));
3567 /* Check window for sanity */
3568 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3569 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3570 __func__, txmax, bus->tx_seq));
3571 txmax = bus->tx_seq + 2;
3573 bus->tx_max = txmax;
3575 /* Remove superframe header, remember offset */
3576 skb_pull(pfirst, doff);
3579 /* Validate all the subframe headers */
3580 for (num = 0, pnext = pfirst; pnext && !errcode;
3581 num++, pnext = pnext->next) {
3582 dptr = (u8 *) (pnext->data);
3583 dlen = (u16) (pnext->len);
3584 sublen = get_unaligned_le16(dptr);
3585 check = get_unaligned_le16(dptr + sizeof(u16));
3586 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3587 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3589 if (DHD_GLOM_ON()) {
3590 printk(KERN_DEBUG "subframe:\n");
3591 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3596 if ((u16)~(sublen ^ check)) {
3597 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3598 "len/check 0x%04x/0x%04x\n",
3599 __func__, num, sublen, check));
3601 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3602 DHD_ERROR(("%s (subframe %d): length mismatch: "
3603 "len 0x%04x, expect 0x%04x\n",
3604 __func__, num, sublen, dlen));
3606 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3607 (chan != SDPCM_EVENT_CHANNEL)) {
3608 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3609 __func__, num, chan));
3611 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3612 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3613 __func__, num, doff, sublen,
3620 /* Terminate frame on error, request
3622 if (bus->glomerr++ < 3) {
3623 /* Restore superframe header space */
3624 skb_push(pfirst, sfdoff);
3625 dhdsdio_rxfail(bus, true, true);
3628 dhdsdio_rxfail(bus, true, false);
3629 dhd_os_sdlock_rxq(bus->dhd);
3630 brcmu_pkt_buf_free_skb(bus->glom);
3631 dhd_os_sdunlock_rxq(bus->dhd);
3639 /* Basic SD framing looks ok - process each packet (header) */
3640 save_pfirst = pfirst;
3644 dhd_os_sdlock_rxq(bus->dhd);
3645 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3646 pnext = pfirst->next;
3647 pfirst->next = NULL;
3649 dptr = (u8 *) (pfirst->data);
3650 sublen = get_unaligned_le16(dptr);
3651 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3652 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3653 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3655 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3657 __func__, num, pfirst, pfirst->data,
3658 pfirst->len, sublen, chan, seq));
3660 ASSERT((chan == SDPCM_DATA_CHANNEL)
3661 || (chan == SDPCM_EVENT_CHANNEL));
3664 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3665 __func__, seq, rxseq));
3670 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3671 printk(KERN_DEBUG "Rx Subframe Data:\n");
3672 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3677 __skb_trim(pfirst, sublen);
3678 skb_pull(pfirst, doff);
3680 if (pfirst->len == 0) {
3681 brcmu_pkt_buf_free_skb(pfirst);
3683 plast->next = pnext;
3685 ASSERT(save_pfirst == pfirst);
3686 save_pfirst = pnext;
3689 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3691 DHD_ERROR(("%s: rx protocol error\n",
3693 bus->dhd->rx_errors++;
3694 brcmu_pkt_buf_free_skb(pfirst);
3696 plast->next = pnext;
3698 ASSERT(save_pfirst == pfirst);
3699 save_pfirst = pnext;
3704 /* this packet will go up, link back into
3705 chain and count it */
3706 pfirst->next = pnext;
3711 if (DHD_GLOM_ON()) {
3712 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3714 __func__, num, pfirst, pfirst->data,
3715 pfirst->len, pfirst->next,
3717 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3719 min_t(int, pfirst->len, 32));
3721 #endif /* DHD_DEBUG */
3723 dhd_os_sdunlock_rxq(bus->dhd);
3725 dhd_os_sdunlock(bus->dhd);
3726 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3727 dhd_os_sdlock(bus->dhd);
3730 bus->rxglomframes++;
3731 bus->rxglompkts += num;
3736 /* Return true if there may be more frames to read */
3737 static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3739 bcmsdh_info_t *sdh = bus->sdh;
3741 u16 len, check; /* Extracted hardware header fields */
3742 u8 chan, seq, doff; /* Extracted software header fields */
3743 u8 fcbits; /* Extracted fcbits from software header */
3745 struct sk_buff *pkt; /* Packet for event or data frames */
3746 u16 pad; /* Number of pad bytes to read */
3747 u16 rdlen; /* Total number of bytes to read */
3748 u8 rxseq; /* Next sequence number to expect */
3749 uint rxleft = 0; /* Remaining number of frames allowed */
3750 int sdret; /* Return code from bcmsdh calls */
3751 u8 txmax; /* Maximum tx sequence offered */
3752 bool len_consistent; /* Result of comparing readahead len and
3756 uint rxcount = 0; /* Total frames read */
3758 #if defined(DHD_DEBUG) || defined(SDTEST)
3759 bool sdtest = false; /* To limit message spew from test mode */
3762 DHD_TRACE(("%s: Enter\n", __func__));
3767 /* Allow pktgen to override maxframes */
3768 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3769 maxframes = bus->pktgen_count;
3774 /* Not finished unless we encounter no more frames indication */
3777 for (rxseq = bus->rx_seq, rxleft = maxframes;
3778 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3779 rxseq++, rxleft--) {
3781 /* Handle glomming separately */
3782 if (bus->glom || bus->glomd) {
3784 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3785 __func__, bus->glomd, bus->glom));
3786 cnt = dhdsdio_rxglom(bus, rxseq);
3787 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3789 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3793 /* Try doing single read if we can */
3794 if (dhd_readahead && bus->nextlen) {
3795 u16 nextlen = bus->nextlen;
3798 if (bus->bus == SPI_BUS) {
3799 rdlen = len = nextlen;
3801 rdlen = len = nextlen << 4;
3803 /* Pad read to blocksize for efficiency */
3804 if (bus->roundup && bus->blocksize
3805 && (rdlen > bus->blocksize)) {
3808 (rdlen % bus->blocksize);
3809 if ((pad <= bus->roundup)
3810 && (pad < bus->blocksize)
3811 && ((rdlen + pad + firstread) <
3814 } else if (rdlen % DHD_SDALIGN) {
3816 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3820 /* We use bus->rxctl buffer in WinXP for initial
3821 * control pkt receives.
3822 * Later we use buffer-poll for data as well
3823 * as control packets.
3824 * This is required because dhd receives full
3825 * frame in gSPI unlike SDIO.
3826 * After the frame is received we have to
3827 * distinguish whether it is data
3828 * or non-data frame.
3830 /* Allocate a packet buffer */
3831 dhd_os_sdlock_rxq(bus->dhd);
3832 pkt = brcmu_pkt_buf_get_skb(rdlen + DHD_SDALIGN);
3834 if (bus->bus == SPI_BUS) {
3835 bus->usebufpool = false;
3836 bus->rxctl = bus->rxbuf;
3838 bus->rxctl += firstread;
3839 pad = ((unsigned long)bus->rxctl %
3843 (DHD_SDALIGN - pad);
3844 bus->rxctl -= firstread;
3846 ASSERT(bus->rxctl >= bus->rxbuf);
3848 /* Read the entire frame */
3849 sdret = bcmsdh_recv_buf(bus,
3850 bcmsdh_cur_sbwad(sdh),
3851 SDIO_FUNC_2, F2SYNC,
3855 ASSERT(sdret != -BCME_PENDING);
3857 /* Control frame failures need
3860 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3863 /* dhd.rx_ctlerrs is higher */
3865 dhd_os_sdunlock_rxq(bus->dhd);
3866 dhdsdio_rxfail(bus, true,
3874 request rtx of events */
3875 DHD_ERROR(("%s (nextlen): "
3876 "brcmu_pkt_buf_get_skb "
3878 " len %d rdlen %d expected"
3879 " rxseq %d\n", __func__,
3880 len, rdlen, rxseq));
3881 /* Just go try again w/normal
3883 dhd_os_sdunlock_rxq(bus->dhd);
3887 if (bus->bus == SPI_BUS)
3888 bus->usebufpool = true;
3890 ASSERT(!(pkt->prev));
3891 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
3892 rxbuf = (u8 *) (pkt->data);
3893 /* Read the entire frame */
3894 sdret = bcmsdh_recv_buf(bus,
3895 bcmsdh_cur_sbwad(sdh),
3896 SDIO_FUNC_2, F2SYNC,
3900 ASSERT(sdret != -BCME_PENDING);
3903 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3904 __func__, rdlen, sdret));
3905 brcmu_pkt_buf_free_skb(pkt);
3906 bus->dhd->rx_errors++;
3907 dhd_os_sdunlock_rxq(bus->dhd);
3908 /* Force retry w/normal header read.
3909 * Don't attempt NAK for
3912 dhdsdio_rxfail(bus, true,
3919 dhd_os_sdunlock_rxq(bus->dhd);
3921 /* Now check the header */
3922 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3924 /* Extract hardware header fields */
3925 len = get_unaligned_le16(bus->rxhdr);
3926 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3928 /* All zeros means readahead info was bad */
3929 if (!(len | check)) {
3930 DHD_INFO(("%s (nextlen): read zeros in HW "
3931 "header???\n", __func__));
3932 dhdsdio_pktfree2(bus, pkt);
3936 /* Validate check bytes */
3937 if ((u16)~(len ^ check)) {
3938 DHD_ERROR(("%s (nextlen): HW hdr error:"
3939 " nextlen/len/check"
3940 " 0x%04x/0x%04x/0x%04x\n",
3941 __func__, nextlen, len, check));
3943 dhdsdio_rxfail(bus, false, false);
3944 dhdsdio_pktfree2(bus, pkt);
3948 /* Validate frame length */
3949 if (len < SDPCM_HDRLEN) {
3950 DHD_ERROR(("%s (nextlen): HW hdr length "
3951 "invalid: %d\n", __func__, len));
3952 dhdsdio_pktfree2(bus, pkt);
3956 /* Check for consistency withreadahead info */
3957 len_consistent = (nextlen != (roundup(len, 16) >> 4));
3958 if (len_consistent) {
3959 /* Mismatch, force retry w/normal
3960 header (may be >4K) */
3961 DHD_ERROR(("%s (nextlen): mismatch, "
3962 "nextlen %d len %d rnd %d; "
3963 "expected rxseq %d\n",
3965 len, roundup(len, 16), rxseq));
3966 dhdsdio_rxfail(bus, true, (bus->bus != SPI_BUS));
3967 dhdsdio_pktfree2(bus, pkt);
3971 /* Extract software header fields */
3972 chan = SDPCM_PACKET_CHANNEL(
3973 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3974 seq = SDPCM_PACKET_SEQUENCE(
3975 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3976 doff = SDPCM_DOFFSET_VALUE(
3977 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3978 txmax = SDPCM_WINDOW_VALUE(
3979 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3982 bus->rxhdr[SDPCM_FRAMETAG_LEN +
3983 SDPCM_NEXTLEN_OFFSET];
3984 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3985 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
3986 __func__, bus->nextlen, seq));
3990 bus->dhd->rx_readahead_cnt++;
3992 /* Handle Flow Control */
3993 fcbits = SDPCM_FCMASK_VALUE(
3994 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3996 if (bus->flowcontrol != fcbits) {
3997 if (~bus->flowcontrol & fcbits)
4000 if (bus->flowcontrol & ~fcbits)
4004 bus->flowcontrol = fcbits;
4007 /* Check and update sequence number */
4009 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
4010 "%d\n", __func__, seq, rxseq));
4015 /* Check window for sanity */
4016 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4017 DHD_ERROR(("%s: got unlikely tx max %d with "
4019 __func__, txmax, bus->tx_seq));
4020 txmax = bus->tx_seq + 2;
4022 bus->tx_max = txmax;
4025 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4026 printk(KERN_DEBUG "Rx Data:\n");
4027 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4029 } else if (DHD_HDRS_ON()) {
4030 printk(KERN_DEBUG "RxHdr:\n");
4031 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4032 bus->rxhdr, SDPCM_HDRLEN);
4036 if (chan == SDPCM_CONTROL_CHANNEL) {
4037 if (bus->bus == SPI_BUS) {
4038 dhdsdio_read_control(bus, rxbuf, len,
4041 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
4043 /* Force retry w/normal header read */
4045 dhdsdio_rxfail(bus, false, true);
4047 dhdsdio_pktfree2(bus, pkt);
4051 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
4052 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
4057 /* Validate data offset */
4058 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4059 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
4060 __func__, doff, len, SDPCM_HDRLEN));
4061 dhdsdio_rxfail(bus, false, false);
4062 dhdsdio_pktfree2(bus, pkt);
4066 /* All done with this one -- now deliver the packet */
4069 /* gSPI frames should not be handled in fractions */
4070 if (bus->bus == SPI_BUS)
4073 /* Read frame header (hardware and software) */
4074 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh),
4075 SDIO_FUNC_2, F2SYNC, bus->rxhdr, firstread,
4078 ASSERT(sdret != -BCME_PENDING);
4081 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
4084 dhdsdio_rxfail(bus, true, true);
4088 if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
4089 printk(KERN_DEBUG "RxHdr:\n");
4090 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4091 bus->rxhdr, SDPCM_HDRLEN);
4095 /* Extract hardware header fields */
4096 len = get_unaligned_le16(bus->rxhdr);
4097 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
4099 /* All zeros means no more frames */
4100 if (!(len | check)) {
4105 /* Validate check bytes */
4106 if ((u16) ~(len ^ check)) {
4107 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
4108 __func__, len, check));
4110 dhdsdio_rxfail(bus, false, false);
4114 /* Validate frame length */
4115 if (len < SDPCM_HDRLEN) {
4116 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
4121 /* Extract software header fields */
4122 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4123 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4124 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4125 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4127 /* Validate data offset */
4128 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4129 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
4131 __func__, doff, len, SDPCM_HDRLEN, seq));
4134 dhdsdio_rxfail(bus, false, false);
4138 /* Save the readahead length if there is one */
4140 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4141 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4142 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4144 __func__, bus->nextlen, seq));
4148 /* Handle Flow Control */
4149 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4151 if (bus->flowcontrol != fcbits) {
4152 if (~bus->flowcontrol & fcbits)
4155 if (bus->flowcontrol & ~fcbits)
4159 bus->flowcontrol = fcbits;
4162 /* Check and update sequence number */
4164 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4170 /* Check window for sanity */
4171 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4172 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4173 __func__, txmax, bus->tx_seq));
4174 txmax = bus->tx_seq + 2;
4176 bus->tx_max = txmax;
4178 /* Call a separate function for control frames */
4179 if (chan == SDPCM_CONTROL_CHANNEL) {
4180 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4184 ASSERT((chan == SDPCM_DATA_CHANNEL)
4185 || (chan == SDPCM_EVENT_CHANNEL)
4186 || (chan == SDPCM_TEST_CHANNEL)
4187 || (chan == SDPCM_GLOM_CHANNEL));
4189 /* Length to read */
4190 rdlen = (len > firstread) ? (len - firstread) : 0;
4192 /* May pad read to blocksize for efficiency */
4193 if (bus->roundup && bus->blocksize &&
4194 (rdlen > bus->blocksize)) {
4195 pad = bus->blocksize - (rdlen % bus->blocksize);
4196 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4197 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4199 } else if (rdlen % DHD_SDALIGN) {
4200 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4203 /* Satisfy length-alignment requirements */
4204 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4205 rdlen = roundup(rdlen, ALIGNMENT);
4207 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4208 /* Too long -- skip this frame */
4209 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4210 __func__, len, rdlen));
4211 bus->dhd->rx_errors++;
4213 dhdsdio_rxfail(bus, false, false);
4217 dhd_os_sdlock_rxq(bus->dhd);
4218 pkt = brcmu_pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
4220 /* Give up on data, request rtx of events */
4221 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed: rdlen %d"
4222 " chan %d\n", __func__, rdlen, chan));
4223 bus->dhd->rx_dropped++;
4224 dhd_os_sdunlock_rxq(bus->dhd);
4225 dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
4228 dhd_os_sdunlock_rxq(bus->dhd);
4230 ASSERT(!(pkt->prev));
4232 /* Leave room for what we already read, and align remainder */
4233 ASSERT(firstread < pkt->len);
4234 skb_pull(pkt, firstread);
4235 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
4237 /* Read the remaining frame data */
4238 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4239 F2SYNC, ((u8 *) (pkt->data)), rdlen,
4242 ASSERT(sdret != -BCME_PENDING);
4245 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4248 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4250 ? "data" : "test")),
4252 dhd_os_sdlock_rxq(bus->dhd);
4253 brcmu_pkt_buf_free_skb(pkt);
4254 dhd_os_sdunlock_rxq(bus->dhd);
4255 bus->dhd->rx_errors++;
4256 dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
4260 /* Copy the already-read portion */
4261 skb_push(pkt, firstread);
4262 memcpy(pkt->data, bus->rxhdr, firstread);
4265 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4266 printk(KERN_DEBUG "Rx Data:\n");
4267 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4273 /* Save superframe descriptor and allocate packet frame */
4274 if (chan == SDPCM_GLOM_CHANNEL) {
4275 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4276 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4279 if (DHD_GLOM_ON()) {
4280 printk(KERN_DEBUG "Glom Data:\n");
4281 print_hex_dump_bytes("",
4286 __skb_trim(pkt, len);
4287 ASSERT(doff == SDPCM_HDRLEN);
4288 skb_pull(pkt, SDPCM_HDRLEN);
4291 DHD_ERROR(("%s: glom superframe w/o "
4292 "descriptor!\n", __func__));
4293 dhdsdio_rxfail(bus, false, false);
4298 /* Fill in packet len and prio, deliver upward */
4299 __skb_trim(pkt, len);
4300 skb_pull(pkt, doff);
4303 /* Test channel packets are processed separately */
4304 if (chan == SDPCM_TEST_CHANNEL) {
4305 dhdsdio_testrcv(bus, pkt, seq);
4310 if (pkt->len == 0) {
4311 dhd_os_sdlock_rxq(bus->dhd);
4312 brcmu_pkt_buf_free_skb(pkt);
4313 dhd_os_sdunlock_rxq(bus->dhd);
4315 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4316 DHD_ERROR(("%s: rx protocol error\n", __func__));
4317 dhd_os_sdlock_rxq(bus->dhd);
4318 brcmu_pkt_buf_free_skb(pkt);
4319 dhd_os_sdunlock_rxq(bus->dhd);
4320 bus->dhd->rx_errors++;
4324 /* Unlock during rx call */
4325 dhd_os_sdunlock(bus->dhd);
4326 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4327 dhd_os_sdlock(bus->dhd);
4329 rxcount = maxframes - rxleft;
4331 /* Message if we hit the limit */
4332 if (!rxleft && !sdtest)
4333 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4336 #endif /* DHD_DEBUG */
4337 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4338 /* Back off rxseq if awaiting rtx, update rx_seq */
4341 bus->rx_seq = rxseq;
4346 static u32 dhdsdio_hostmail(dhd_bus_t *bus)
4348 struct sdpcmd_regs *regs = bus->regs;
4354 DHD_TRACE(("%s: Enter\n", __func__));
4356 /* Read mailbox data and ack that we did so */
4357 R_SDREG(hmb_data, ®s->tohostmailboxdata, retries);
4358 if (retries <= retry_limit)
4359 W_SDREG(SMB_INT_ACK, ®s->tosbmailbox, retries);
4360 bus->f1regdata += 2;
4362 /* Dongle recomposed rx frames, accept them again */
4363 if (hmb_data & HMB_DATA_NAKHANDLED) {
4364 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4367 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4369 bus->rxskip = false;
4370 intstatus |= I_HMB_FRAME_IND;
4374 * DEVREADY does not occur with gSPI.
4376 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4378 (hmb_data & HMB_DATA_VERSION_MASK) >>
4379 HMB_DATA_VERSION_SHIFT;
4380 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4381 DHD_ERROR(("Version mismatch, dongle reports %d, "
4383 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4385 DHD_INFO(("Dongle ready, protocol version %d\n",
4390 * Flow Control has been moved into the RX headers and this out of band
4391 * method isn't used any more.
4392 * remaining backward compatible with older dongles.
4394 if (hmb_data & HMB_DATA_FC) {
4395 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
4396 HMB_DATA_FCDATA_SHIFT;
4398 if (fcbits & ~bus->flowcontrol)
4401 if (bus->flowcontrol & ~fcbits)
4405 bus->flowcontrol = fcbits;
4408 /* Shouldn't be any others */
4409 if (hmb_data & ~(HMB_DATA_DEVREADY |
4410 HMB_DATA_NAKHANDLED |
4413 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4414 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4420 bool dhdsdio_dpc(dhd_bus_t *bus)
4422 bcmsdh_info_t *sdh = bus->sdh;
4423 struct sdpcmd_regs *regs = bus->regs;
4424 u32 intstatus, newstatus = 0;
4426 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4427 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4428 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4429 bool rxdone = true; /* Flag for no more read data */
4430 bool resched = false; /* Flag indicating resched wanted */
4432 DHD_TRACE(("%s: Enter\n", __func__));
4434 /* Start with leftover status bits */
4435 intstatus = bus->intstatus;
4437 dhd_os_sdlock(bus->dhd);
4439 /* If waiting for HTAVAIL, check status */
4440 if (bus->clkstate == CLK_PENDING) {
4442 u8 clkctl, devctl = 0;
4445 /* Check for inconsistent device control */
4447 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4449 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4451 bus->dhd->busstate = DHD_BUS_DOWN;
4453 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4455 #endif /* DHD_DEBUG */
4457 /* Read CSR, if clock on switch to AVAIL, else ignore */
4459 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4462 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4464 bus->dhd->busstate = DHD_BUS_DOWN;
4467 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4470 if (SBSDIO_HTAV(clkctl)) {
4472 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4475 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4477 bus->dhd->busstate = DHD_BUS_DOWN;
4479 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4480 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4483 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4485 bus->dhd->busstate = DHD_BUS_DOWN;
4487 bus->clkstate = CLK_AVAIL;
4495 /* Make sure backplane clock is on */
4496 dhdsdio_clkctl(bus, CLK_AVAIL, true);
4497 if (bus->clkstate == CLK_PENDING)
4500 /* Pending interrupt indicates new device status */
4503 R_SDREG(newstatus, ®s->intstatus, retries);
4505 if (bcmsdh_regfail(bus->sdh))
4507 newstatus &= bus->hostintmask;
4508 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4510 W_SDREG(newstatus, ®s->intstatus, retries);
4515 /* Merge new bits with previous */
4516 intstatus |= newstatus;
4519 /* Handle flow-control change: read new state in case our ack
4520 * crossed another change interrupt. If change still set, assume
4521 * FC ON for safety, let next loop through do the debounce.
4523 if (intstatus & I_HMB_FC_CHANGE) {
4524 intstatus &= ~I_HMB_FC_CHANGE;
4525 W_SDREG(I_HMB_FC_CHANGE, ®s->intstatus, retries);
4526 R_SDREG(newstatus, ®s->intstatus, retries);
4527 bus->f1regdata += 2;
4529 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4530 intstatus |= (newstatus & bus->hostintmask);
4533 /* Handle host mailbox indication */
4534 if (intstatus & I_HMB_HOST_INT) {
4535 intstatus &= ~I_HMB_HOST_INT;
4536 intstatus |= dhdsdio_hostmail(bus);
4539 /* Generally don't ask for these, can get CRC errors... */
4540 if (intstatus & I_WR_OOSYNC) {
4541 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4542 intstatus &= ~I_WR_OOSYNC;
4545 if (intstatus & I_RD_OOSYNC) {
4546 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4547 intstatus &= ~I_RD_OOSYNC;
4550 if (intstatus & I_SBINT) {
4551 DHD_ERROR(("Dongle reports SBINT\n"));
4552 intstatus &= ~I_SBINT;
4555 /* Would be active due to wake-wlan in gSPI */
4556 if (intstatus & I_CHIPACTIVE) {
4557 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4558 intstatus &= ~I_CHIPACTIVE;
4561 /* Ignore frame indications if rxskip is set */
4563 intstatus &= ~I_HMB_FRAME_IND;
4565 /* On frame indication, read available frames */
4566 if (PKT_AVAILABLE()) {
4567 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4568 if (rxdone || bus->rxskip)
4569 intstatus &= ~I_HMB_FRAME_IND;
4570 rxlimit -= min(framecnt, rxlimit);
4573 /* Keep still-pending events for next scheduling */
4574 bus->intstatus = intstatus;
4577 #if defined(OOB_INTR_ONLY)
4578 bcmsdh_oob_intr_set(1);
4579 #endif /* (OOB_INTR_ONLY) */
4580 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4581 * or clock availability. (Allows tx loop to check ipend if desired.)
4582 * (Unless register access seems hosed, as we may not be able to ACK...)
4584 if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4585 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4586 __func__, rxdone, framecnt));
4587 bus->intdis = false;
4588 bcmsdh_intr_enable(sdh);
4591 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4592 (bus->clkstate == CLK_AVAIL)) {
4596 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4597 F2SYNC, (u8 *) bus->ctrl_frame_buf,
4598 (u32) bus->ctrl_frame_len, NULL,
4600 ASSERT(ret != -BCME_PENDING);
4603 /* On failure, abort the command and
4604 terminate the frame */
4605 DHD_INFO(("%s: sdio error %d, abort command and "
4606 "terminate frame.\n", __func__, ret));
4609 bcmsdh_abort(sdh, SDIO_FUNC_2);
4611 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4612 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4616 for (i = 0; i < 3; i++) {
4618 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4619 SBSDIO_FUNC1_WFRAMEBCHI,
4621 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4622 SBSDIO_FUNC1_WFRAMEBCLO,
4624 bus->f1regdata += 2;
4625 if ((hi == 0) && (lo == 0))
4631 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4633 DHD_INFO(("Return_dpc value is : %d\n", ret));
4634 bus->ctrl_frame_stat = false;
4635 dhd_wait_event_wakeup(bus->dhd);
4637 /* Send queued frames (limit 1 if rx may still be pending) */
4638 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4639 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4641 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4642 framecnt = dhdsdio_sendfromq(bus, framecnt);
4643 txlimit -= framecnt;
4646 /* Resched if events or tx frames are pending,
4647 else await next interrupt */
4648 /* On failed register access, all bets are off:
4649 no resched or interrupts */
4650 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4651 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4652 "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4653 bus->dhd->busstate = DHD_BUS_DOWN;
4655 } else if (bus->clkstate == CLK_PENDING) {
4656 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4657 "I_CHIPACTIVE interrupt\n", __func__));
4659 } else if (bus->intstatus || bus->ipend ||
4660 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
4661 && DATAOK(bus)) || PKT_AVAILABLE()) {
4665 bus->dpc_sched = resched;
4667 /* If we're done for now, turn off clock request. */
4668 if ((bus->clkstate != CLK_PENDING)
4669 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4670 bus->activity = false;
4671 dhdsdio_clkctl(bus, CLK_NONE, false);
4674 dhd_os_sdunlock(bus->dhd);
4679 bool dhd_bus_dpc(struct dhd_bus *bus)
4683 /* Call the DPC directly. */
4684 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4685 resched = dhdsdio_dpc(bus);
4690 void dhdsdio_isr(void *arg)
4692 dhd_bus_t *bus = (dhd_bus_t *) arg;
4695 DHD_TRACE(("%s: Enter\n", __func__));
4698 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4703 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4704 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4708 /* Count the interrupt call */
4712 /* Shouldn't get this interrupt if we're sleeping? */
4713 if (bus->sleeping) {
4714 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4718 /* Disable additional interrupts (is this needed now)? */
4720 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4722 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4724 bcmsdh_intr_disable(sdh);
4727 #if defined(SDIO_ISR_THREAD)
4728 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4729 while (dhdsdio_dpc(bus))
4732 bus->dpc_sched = true;
4733 dhd_sched_dpc(bus->dhd);
4739 static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4741 /* Default to specified length, or full range */
4742 if (dhd_pktgen_len) {
4743 bus->pktgen_maxlen = min(dhd_pktgen_len, MAX_PKTGEN_LEN);
4744 bus->pktgen_minlen = bus->pktgen_maxlen;
4746 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4747 bus->pktgen_minlen = 0;
4749 bus->pktgen_len = (u16) bus->pktgen_minlen;
4751 /* Default to per-watchdog burst with 10s print time */
4752 bus->pktgen_freq = 1;
4753 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4754 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4756 /* Default to echo mode */
4757 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4758 bus->pktgen_stop = 1;
4761 static void dhdsdio_pktgen(dhd_bus_t *bus)
4763 struct sk_buff *pkt;
4769 /* Display current count if appropriate */
4770 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4771 bus->pktgen_ptick = 0;
4772 printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4773 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4776 /* For recv mode, just make sure dongle has started sending */
4777 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4778 if (!bus->pktgen_rcvd)
4779 dhdsdio_sdtest_set(bus, true);
4783 /* Otherwise, generate or request the specified number of packets */
4784 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4785 /* Stop if total has been reached */
4786 if (bus->pktgen_total
4787 && (bus->pktgen_sent >= bus->pktgen_total)) {
4788 bus->pktgen_count = 0;
4792 /* Allocate an appropriate-sized packet */
4793 len = bus->pktgen_len;
4794 pkt = brcmu_pkt_buf_get_skb(
4795 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4798 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed!\n",
4802 PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4804 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4806 /* Write test header cmd and extra based on mode */
4807 switch (bus->pktgen_mode) {
4808 case DHD_PKTGEN_ECHO:
4809 *data++ = SDPCM_TEST_ECHOREQ;
4810 *data++ = (u8) bus->pktgen_sent;
4813 case DHD_PKTGEN_SEND:
4814 *data++ = SDPCM_TEST_DISCARD;
4815 *data++ = (u8) bus->pktgen_sent;
4818 case DHD_PKTGEN_RXBURST:
4819 *data++ = SDPCM_TEST_BURST;
4820 *data++ = (u8) bus->pktgen_count;
4824 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4826 brcmu_pkt_buf_free_skb(pkt, true);
4827 bus->pktgen_count = 0;
4831 /* Write test header length field */
4832 *data++ = (len >> 0);
4833 *data++ = (len >> 8);
4835 /* Then fill in the remainder -- N/A for burst,
4837 for (fillbyte = 0; fillbyte < len; fillbyte++)
4839 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4842 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4843 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4844 printk(KERN_DEBUG "dhdsdio_pktgen: Tx Data:\n");
4845 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, data,
4846 pkt->len - SDPCM_HDRLEN);
4851 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4853 if (bus->pktgen_stop
4854 && bus->pktgen_stop == bus->pktgen_fail)
4855 bus->pktgen_count = 0;
4859 /* Bump length if not fixed, wrap at max */
4860 if (++bus->pktgen_len > bus->pktgen_maxlen)
4861 bus->pktgen_len = (u16) bus->pktgen_minlen;
4863 /* Special case for burst mode: just send one request! */
4864 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4869 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4871 struct sk_buff *pkt;
4874 /* Allocate the packet */
4875 pkt = brcmu_pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
4878 DHD_ERROR(("%s: brcmu_pkt_buf_get_skb failed!\n", __func__));
4881 PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4882 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4884 /* Fill in the test header */
4885 *data++ = SDPCM_TEST_SEND;
4887 *data++ = (bus->pktgen_maxlen >> 0);
4888 *data++ = (bus->pktgen_maxlen >> 8);
4891 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4895 static void dhdsdio_testrcv(dhd_bus_t *bus, struct sk_buff *pkt, uint seq)
4905 /* Check for min length */
4907 if (pktlen < SDPCM_TEST_HDRLEN) {
4908 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4910 brcmu_pkt_buf_free_skb(pkt, false);
4914 /* Extract header fields */
4919 len += *data++ << 8;
4921 /* Check length for relevant commands */
4922 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4923 || cmd == SDPCM_TEST_ECHORSP) {
4924 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4925 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4926 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4927 pktlen, seq, cmd, extra, len));
4928 brcmu_pkt_buf_free_skb(pkt, false);
4933 /* Process as per command */
4935 case SDPCM_TEST_ECHOREQ:
4936 /* Rx->Tx turnaround ok (even on NDIS w/current
4938 *(u8 *) (pkt->data) = SDPCM_TEST_ECHORSP;
4939 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0) {
4943 brcmu_pkt_buf_free_skb(pkt, false);
4948 case SDPCM_TEST_ECHORSP:
4949 if (bus->ext_loop) {
4950 brcmu_pkt_buf_free_skb(pkt, false);
4955 for (offset = 0; offset < len; offset++, data++) {
4956 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4957 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4959 SDPCM_TEST_FILL(offset, extra), *data));
4963 brcmu_pkt_buf_free_skb(pkt, false);
4967 case SDPCM_TEST_DISCARD:
4968 brcmu_pkt_buf_free_skb(pkt, false);
4972 case SDPCM_TEST_BURST:
4973 case SDPCM_TEST_SEND:
4975 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
4976 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4977 pktlen, seq, cmd, extra, len));
4978 brcmu_pkt_buf_free_skb(pkt, false);
4982 /* For recv mode, stop at limie (and tell dongle to stop sending) */
4983 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4984 if (bus->pktgen_total
4985 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
4986 bus->pktgen_count = 0;
4987 dhdsdio_sdtest_set(bus, false);
4993 extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
4997 DHD_TIMER(("%s: Enter\n", __func__));
5001 if (bus->dhd->dongle_reset)
5004 /* Ignore the timer if simulating bus down */
5008 dhd_os_sdlock(bus->dhd);
5010 /* Poll period: check device if appropriate. */
5011 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
5014 /* Reset poll tick */
5017 /* Check device if no interrupts */
5018 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
5020 if (!bus->dpc_sched) {
5022 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
5026 devpend & (INTR_STATUS_FUNC1 |
5030 /* If there is something, make like the ISR and
5036 bcmsdh_intr_disable(bus->sdh);
5038 bus->dpc_sched = true;
5039 dhd_sched_dpc(bus->dhd);
5044 /* Update interrupt tracking */
5045 bus->lastintrs = bus->intrcount;
5048 /* Poll for console output periodically */
5049 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
5050 bus->console.count += dhd_watchdog_ms;
5051 if (bus->console.count >= dhd_console_ms) {
5052 bus->console.count -= dhd_console_ms;
5053 /* Make sure backplane clock is on */
5054 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5055 if (dhdsdio_readconsole(bus) < 0)
5056 dhd_console_ms = 0; /* On error,
5060 #endif /* DHD_DEBUG */
5063 /* Generate packets if configured */
5064 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
5065 /* Make sure backplane clock is on */
5066 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5067 bus->pktgen_tick = 0;
5068 dhdsdio_pktgen(bus);
5072 /* On idle timeout clear activity flag and/or turn off clock */
5073 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
5074 if (++bus->idlecount >= bus->idletime) {
5076 if (bus->activity) {
5077 bus->activity = false;
5078 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
5080 dhdsdio_clkctl(bus, CLK_NONE, false);
5085 dhd_os_sdunlock(bus->dhd);
5091 extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
5093 dhd_bus_t *bus = dhdp->bus;
5096 struct sk_buff *pkt;
5098 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
5099 if (bus->console_addr == 0)
5102 /* Exclusive bus access */
5103 dhd_os_sdlock(bus->dhd);
5105 /* Don't allow input if dongle is in reset */
5106 if (bus->dhd->dongle_reset) {
5107 dhd_os_sdunlock(bus->dhd);
5111 /* Request clock to allow SDIO accesses */
5113 /* No pend allowed since txpkt is called later, ht clk has to be on */
5114 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5116 /* Zero cbuf_index */
5117 addr = bus->console_addr + offsetof(rte_cons_t, cbuf_idx);
5118 val = cpu_to_le32(0);
5119 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5123 /* Write message into cbuf */
5124 addr = bus->console_addr + offsetof(rte_cons_t, cbuf);
5125 rv = dhdsdio_membytes(bus, true, addr, (u8 *)msg, msglen);
5129 /* Write length into vcons_in */
5130 addr = bus->console_addr + offsetof(rte_cons_t, vcons_in);
5131 val = cpu_to_le32(msglen);
5132 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5136 /* Bump dongle by sending an empty event pkt.
5137 * sdpcm_sendup (RX) checks for virtual console input.
5139 pkt = brcmu_pkt_buf_get_skb(4 + SDPCM_RESERVE);
5140 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5141 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5144 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5145 bus->activity = false;
5146 dhdsdio_clkctl(bus, CLK_NONE, true);
5149 dhd_os_sdunlock(bus->dhd);
5153 #endif /* DHD_DEBUG */
5155 static bool dhdsdio_chipmatch(u16 chipid)
5157 if (chipid == BCM4325_CHIP_ID)
5159 if (chipid == BCM4329_CHIP_ID)
5161 if (chipid == BCM4319_CHIP_ID)
5166 static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5167 u16 slot, u16 func, uint bustype, void *regsva,
5173 /* Init global variables at run-time, not as part of the declaration.
5174 * This is required to support init/de-init of the driver.
5176 * of globals as part of the declaration results in non-deterministic
5177 * behavior since the value of the globals may be different on the
5178 * first time that the driver is initialized vs subsequent
5181 dhd_txbound = DHD_TXBOUND;
5182 dhd_rxbound = DHD_RXBOUND;
5183 dhd_alignctl = true;
5185 dhd_readahead = true;
5187 dhd_dongle_memsize = 0;
5188 dhd_txminmax = DHD_TXMINMAX;
5194 DHD_TRACE(("%s: Enter\n", __func__));
5195 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5197 /* We make assumptions about address window mappings */
5198 ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5200 /* BCMSDH passes venid and devid based on CIS parsing -- but
5202 * means early parse could fail, so here we should get either an ID
5203 * we recognize OR (-1) indicating we must request power first.
5205 /* Check the Vendor ID */
5208 case PCI_VENDOR_ID_BROADCOM:
5211 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5215 /* Check the Device ID and make sure it's one that we support */
5217 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5218 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5219 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5220 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5222 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5223 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5224 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5226 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5228 case BCM4319_D11N_ID: /* 4319 802.11n id */
5229 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5230 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5231 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5234 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5239 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5240 __func__, venid, devid));
5244 /* Allocate private bus interface state */
5245 bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5247 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5251 bus->cl_devid = (u16) devid;
5253 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5254 bus->usebufpool = false; /* Use bufpool if allocated,
5255 else use locally malloced rxbuf */
5257 /* attempt to attach to the dongle */
5258 if (!(dhdsdio_probe_attach(bus, sdh, regsva, devid))) {
5259 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5263 /* Attach to the dhd/OS/network interface */
5264 bus->dhd = dhd_attach(bus, SDPCM_RESERVE);
5266 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5270 /* Allocate buffers */
5271 if (!(dhdsdio_probe_malloc(bus, sdh))) {
5272 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5276 if (!(dhdsdio_probe_init(bus, sdh))) {
5277 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5281 /* Register interrupt callback, but mask it (not operational yet). */
5282 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5284 bcmsdh_intr_disable(sdh);
5285 ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5287 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5291 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5293 DHD_INFO(("%s: completed!!\n", __func__));
5295 /* if firmware path present try to download and bring up bus */
5296 ret = dhd_bus_start(bus->dhd);
5298 if (ret == -ENOLINK) {
5299 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5303 /* Ok, have the per-port tell the stack we're open for business */
5304 if (dhd_net_attach(bus->dhd, 0) != 0) {
5305 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5312 dhdsdio_release(bus);
5317 dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
5322 bus->alp_only = true;
5324 /* Return the window to backplane enumeration space for core access */
5325 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5326 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5329 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5330 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5332 #endif /* DHD_DEBUG */
5335 * Force PLL off until dhdsdio_chip_attach()
5336 * programs PLL control regs
5339 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5340 DHD_INIT_CLKCTL1, &err);
5343 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5346 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5347 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5348 "0x%02x read 0x%02x\n",
5349 err, DHD_INIT_CLKCTL1, clkctl));
5353 if (dhdsdio_chip_attach(bus, regsva)) {
5354 DHD_ERROR(("%s: dhdsdio_chip_attach failed!\n", __func__));
5358 bcmsdh_chipinfo(sdh, bus->ci->chip, bus->ci->chiprev);
5360 if (!dhdsdio_chipmatch((u16) bus->ci->chip)) {
5361 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5362 __func__, bus->ci->chip));
5366 dhdsdio_sdiod_drive_strength_init(bus, dhd_sdiod_drive_strength);
5368 /* Get info on the ARM and SOCRAM cores... */
5369 if (!DHD_NOPMU(bus)) {
5370 bus->armrev = SBCOREREV(bcmsdh_reg_read(bus->sdh,
5371 CORE_SB(bus->ci->armcorebase, sbidhigh), 4));
5372 bus->orig_ramsize = bus->ci->ramsize;
5373 if (!(bus->orig_ramsize)) {
5374 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5378 bus->ramsize = bus->orig_ramsize;
5379 if (dhd_dongle_memsize)
5380 dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5382 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5383 bus->ramsize, bus->orig_ramsize));
5386 bus->regs = (void *)bus->ci->buscorebase;
5388 /* Set core control so an SDIO reset does a backplane reset */
5389 OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
5391 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
5393 /* Locate an appropriately-aligned portion of hdrbuf */
5394 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5396 /* Set the poll and/or interrupt flags */
5397 bus->intr = (bool) dhd_intr;
5398 bus->poll = (bool) dhd_poll;
5408 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh)
5410 DHD_TRACE(("%s: Enter\n", __func__));
5412 if (bus->dhd->maxctl) {
5414 roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5415 ALIGNMENT) + DHD_SDALIGN;
5416 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5417 if (!(bus->rxbuf)) {
5418 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5419 __func__, bus->rxblen));
5424 /* Allocate buffer to receive glomed packet */
5425 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5426 if (!(bus->databuf)) {
5427 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5428 __func__, MAX_DATA_BUF));
5429 /* release rxbuf which was already located as above */
5435 /* Align the buffer */
5436 if ((unsigned long)bus->databuf % DHD_SDALIGN)
5438 bus->databuf + (DHD_SDALIGN -
5439 ((unsigned long)bus->databuf % DHD_SDALIGN));
5441 bus->dataptr = bus->databuf;
5449 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh)
5453 DHD_TRACE(("%s: Enter\n", __func__));
5456 dhdsdio_pktgen_init(bus);
5459 /* Disable F2 to clear any intermediate frame state on the dongle */
5460 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx, SDIO_FUNC_ENABLE_1,
5463 bus->dhd->busstate = DHD_BUS_DOWN;
5464 bus->sleeping = false;
5465 bus->rxflow = false;
5466 bus->prev_rxlim_hit = 0;
5468 /* Done with backplane-dependent accesses, can drop clock... */
5469 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5471 /* ...and initialize clock/power states */
5472 bus->clkstate = CLK_SDONLY;
5473 bus->idletime = (s32) dhd_idletime;
5474 bus->idleclock = DHD_IDLE_ACTIVE;
5476 /* Query the F2 block size, set roundup accordingly */
5478 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5479 &bus->blocksize, sizeof(s32), false) != 0) {
5481 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5483 DHD_INFO(("%s: Initial value for %s is %d\n",
5484 __func__, "sd_blocksize", bus->blocksize));
5486 bus->roundup = min(max_roundup, bus->blocksize);
5488 /* Query if bus module supports packet chaining,
5489 default to use if supported */
5490 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5491 &bus->sd_rxchain, sizeof(s32),
5493 bus->sd_rxchain = false;
5495 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5497 (bus->sd_rxchain ? "supports" : "does not support")));
5499 bus->use_rxchain = (bool) bus->sd_rxchain;
5505 dhd_bus_download_firmware(struct dhd_bus *bus, char *fw_path, char *nv_path)
5508 bus->fw_path = fw_path;
5509 bus->nv_path = nv_path;
5511 ret = dhdsdio_download_firmware(bus, bus->sdh);
5517 dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh)
5521 /* Download the firmware */
5522 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5524 ret = _dhdsdio_download_firmware(bus) == 0;
5526 dhdsdio_clkctl(bus, CLK_SDONLY, false);
5531 /* Detach and free everything */
5532 static void dhdsdio_release(dhd_bus_t *bus)
5534 DHD_TRACE(("%s: Enter\n", __func__));
5537 /* De-register interrupt handler */
5538 bcmsdh_intr_disable(bus->sdh);
5539 bcmsdh_intr_dereg(bus->sdh);
5542 dhd_detach(bus->dhd);
5543 dhdsdio_release_dongle(bus);
5547 dhdsdio_release_malloc(bus);
5552 DHD_TRACE(("%s: Disconnected\n", __func__));
5555 static void dhdsdio_release_malloc(dhd_bus_t *bus)
5557 DHD_TRACE(("%s: Enter\n", __func__));
5559 if (bus->dhd && bus->dhd->dongle_reset)
5564 bus->rxctl = bus->rxbuf = NULL;
5568 kfree(bus->databuf);
5569 bus->databuf = NULL;
5572 static void dhdsdio_release_dongle(dhd_bus_t *bus)
5574 DHD_TRACE(("%s: Enter\n", __func__));
5576 if (bus->dhd && bus->dhd->dongle_reset)
5580 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5581 dhdsdio_clkctl(bus, CLK_NONE, false);
5582 dhdsdio_chip_detach(bus);
5583 if (bus->vars && bus->varsz)
5588 DHD_TRACE(("%s: Disconnected\n", __func__));
5591 static void dhdsdio_disconnect(void *ptr)
5593 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5595 DHD_TRACE(("%s: Enter\n", __func__));
5599 dhdsdio_release(bus);
5602 DHD_TRACE(("%s: Disconnected\n", __func__));
5605 /* Register/Unregister functions are called by the main DHD entry
5606 * point (e.g. module insertion) to link with the bus driver, in
5607 * order to look for or await the device.
5610 static bcmsdh_driver_t dhd_sdio = {
5615 int dhd_bus_register(void)
5617 DHD_TRACE(("%s: Enter\n", __func__));
5619 return bcmsdh_register(&dhd_sdio);
5622 void dhd_bus_unregister(void)
5624 DHD_TRACE(("%s: Enter\n", __func__));
5626 bcmsdh_unregister();
5629 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5635 u8 *memblock = NULL, *memptr;
5637 DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5639 image = dhd_os_open_image(fw_path);
5643 memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5644 if (memblock == NULL) {
5645 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5646 __func__, MEMBLOCK));
5649 if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5651 (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5653 /* Download image */
5655 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5656 bcmerror = dhdsdio_membytes(bus, true, offset, memptr, len);
5658 DHD_ERROR(("%s: error %d on writing %d membytes at "
5659 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5670 dhd_os_close_image(image);
5676 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5677 * and ending in a NUL.
5678 * Removes carriage returns, empty lines, comment lines, and converts
5680 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5684 static uint process_nvram_vars(char *varbuf, uint len)
5693 findNewline = false;
5696 for (n = 0; n < len; n++) {
5699 if (varbuf[n] == '\r')
5701 if (findNewline && varbuf[n] != '\n')
5703 findNewline = false;
5704 if (varbuf[n] == '#') {
5708 if (varbuf[n] == '\n') {
5718 buf_len = dp - varbuf;
5720 while (dp < varbuf + n)
5727 EXAMPLE: nvram_array
5730 Use carriage return at the end of each assignment,
5731 and an empty string with
5732 carriage return at the end of array.
5735 unsigned char nvram_array[] = {"name1=value1\n",
5736 "name2=value2\n", "\n"};
5737 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5739 Search "EXAMPLE: nvram_array" to see how the array is activated.
5742 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5744 bus->nvram_params = nvram_params;
5747 static int dhdsdio_download_nvram(struct dhd_bus *bus)
5752 char *memblock = NULL;
5755 bool nvram_file_exists;
5757 nv_path = bus->nv_path;
5759 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5760 if (!nvram_file_exists && (bus->nvram_params == NULL))
5763 if (nvram_file_exists) {
5764 image = dhd_os_open_image(nv_path);
5769 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5770 if (memblock == NULL) {
5771 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5772 __func__, MEMBLOCK));
5776 /* Download variables */
5777 if (nvram_file_exists) {
5778 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5780 len = strlen(bus->nvram_params);
5781 ASSERT(len <= MEMBLOCK);
5784 memcpy(memblock, bus->nvram_params, len);
5787 if (len > 0 && len < MEMBLOCK) {
5788 bufp = (char *)memblock;
5790 len = process_nvram_vars(bufp, len);
5794 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5796 DHD_ERROR(("%s: error downloading vars: %d\n",
5797 __func__, bcmerror));
5800 DHD_ERROR(("%s: error reading nvram file: %d\n",
5809 dhd_os_close_image(image);
5814 static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5818 bool embed = false; /* download embedded firmware */
5819 bool dlok = false; /* download firmware succeeded */
5821 /* Out immediately if no image to download */
5822 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0'))
5825 /* Keep arm in reset */
5826 if (dhdsdio_download_state(bus, true)) {
5827 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5831 /* External image takes precedence if specified */
5832 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5833 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5834 DHD_ERROR(("%s: dongle image file download failed\n",
5843 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5847 /* EXAMPLE: nvram_array */
5848 /* If a valid nvram_arry is specified as above, it can be passed
5850 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5852 /* External nvram takes precedence if specified */
5853 if (dhdsdio_download_nvram(bus)) {
5854 DHD_ERROR(("%s: dongle nvram file download failed\n",
5858 /* Take arm out of reset */
5859 if (dhdsdio_download_state(bus, false)) {
5860 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5873 dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5874 u8 *buf, uint nbytes, struct sk_buff *pkt,
5875 bcmsdh_cmplt_fn_t complete, void *handle)
5877 return bcmsdh_send_buf
5878 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
5882 uint dhd_bus_chip(struct dhd_bus *bus)
5884 ASSERT(bus->ci != NULL);
5885 return bus->ci->chip;
5888 void *dhd_bus_pub(struct dhd_bus *bus)
5893 void *dhd_bus_txq(struct dhd_bus *bus)
5898 uint dhd_bus_hdrlen(struct dhd_bus *bus)
5900 return SDPCM_HDRLEN;
5903 int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
5911 if (!bus->dhd->dongle_reset) {
5912 /* Expect app to have torn down any
5913 connection before calling */
5914 /* Stop the bus, disable F2 */
5915 dhd_bus_stop(bus, false);
5917 /* Clean tx/rx buffer pointers,
5918 detach from the dongle */
5919 dhdsdio_release_dongle(bus);
5921 bus->dhd->dongle_reset = true;
5922 bus->dhd->up = false;
5924 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
5925 /* App can now remove power from device */
5929 /* App must have restored power to device before calling */
5931 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
5933 if (bus->dhd->dongle_reset) {
5935 /* Reset SD client */
5936 bcmsdh_reset(bus->sdh);
5938 /* Attempt to re-attach & download */
5939 if (dhdsdio_probe_attach(bus, bus->sdh,
5940 (u32 *) SI_ENUM_BASE,
5942 /* Attempt to download binary to the dongle */
5943 if (dhdsdio_probe_init
5945 && dhdsdio_download_firmware(bus,
5948 /* Re-init bus, enable F2 transfer */
5949 dhd_bus_init((dhd_pub_t *) bus->dhd,
5952 #if defined(OOB_INTR_ONLY)
5953 dhd_enable_oob_intr(bus, true);
5954 #endif /* defined(OOB_INTR_ONLY) */
5956 bus->dhd->dongle_reset = false;
5957 bus->dhd->up = true;
5959 DHD_TRACE(("%s: WLAN ON DONE\n",
5966 bcmerror = -EISCONN;
5967 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
5968 "is on\n", __func__));
5976 dhdsdio_chip_recognition(bcmsdh_info_t *sdh, struct chip_info *ci, void *regs)
5982 * Chipid is assume to be at offset 0 from regs arg
5983 * For different chiptypes or old sdio hosts w/o chipcommon,
5984 * other ways of recognition should be added here.
5986 ci->cccorebase = (u32)regs;
5987 regdata = bcmsdh_reg_read(sdh, CORE_CC_REG(ci->cccorebase, chipid), 4);
5988 ci->chip = regdata & CID_ID_MASK;
5989 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
5991 DHD_INFO(("%s: chipid=0x%x chiprev=%d\n",
5992 __func__, ci->chip, ci->chiprev));
5994 /* Address of cores for new chips should be added here */
5996 case BCM4329_CHIP_ID:
5997 ci->buscorebase = BCM4329_CORE_BUS_BASE;
5998 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
5999 ci->armcorebase = BCM4329_CORE_ARM_BASE;
6000 ci->ramsize = BCM4329_RAMSIZE;
6003 DHD_ERROR(("%s: chipid 0x%x is not supported\n",
6004 __func__, ci->chip));
6008 regdata = bcmsdh_reg_read(sdh,
6009 CORE_SB(ci->cccorebase, sbidhigh), 4);
6010 ci->ccrev = SBCOREREV(regdata);
6012 regdata = bcmsdh_reg_read(sdh,
6013 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
6014 ci->pmurev = regdata & PCAP_REV_MASK;
6016 regdata = bcmsdh_reg_read(sdh, CORE_SB(ci->buscorebase, sbidhigh), 4);
6017 ci->buscorerev = SBCOREREV(regdata);
6018 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
6020 DHD_INFO(("%s: ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
6021 __func__, ci->ccrev, ci->pmurev,
6022 ci->buscorerev, ci->buscoretype));
6024 /* get chipcommon capabilites */
6025 ci->cccaps = bcmsdh_reg_read(sdh,
6026 CORE_CC_REG(ci->cccorebase, capabilities), 4);
6032 dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase)
6036 regdata = bcmsdh_reg_read(sdh,
6037 CORE_SB(corebase, sbtmstatelow), 4);
6038 if (regdata & SBTML_RESET)
6041 regdata = bcmsdh_reg_read(sdh,
6042 CORE_SB(corebase, sbtmstatelow), 4);
6043 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
6045 * set target reject and spin until busy is clear
6046 * (preserve core-specific bits)
6048 regdata = bcmsdh_reg_read(sdh,
6049 CORE_SB(corebase, sbtmstatelow), 4);
6050 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6051 regdata | SBTML_REJ);
6053 regdata = bcmsdh_reg_read(sdh,
6054 CORE_SB(corebase, sbtmstatelow), 4);
6056 SPINWAIT((bcmsdh_reg_read(sdh,
6057 CORE_SB(corebase, sbtmstatehigh), 4) &
6058 SBTMH_BUSY), 100000);
6060 regdata = bcmsdh_reg_read(sdh,
6061 CORE_SB(corebase, sbtmstatehigh), 4);
6062 if (regdata & SBTMH_BUSY)
6063 DHD_ERROR(("%s: ARM core still busy\n", __func__));
6065 regdata = bcmsdh_reg_read(sdh,
6066 CORE_SB(corebase, sbidlow), 4);
6067 if (regdata & SBIDL_INIT) {
6068 regdata = bcmsdh_reg_read(sdh,
6069 CORE_SB(corebase, sbimstate), 4) |
6071 bcmsdh_reg_write(sdh,
6072 CORE_SB(corebase, sbimstate), 4,
6074 regdata = bcmsdh_reg_read(sdh,
6075 CORE_SB(corebase, sbimstate), 4);
6077 SPINWAIT((bcmsdh_reg_read(sdh,
6078 CORE_SB(corebase, sbimstate), 4) &
6082 /* set reset and reject while enabling the clocks */
6083 bcmsdh_reg_write(sdh,
6084 CORE_SB(corebase, sbtmstatelow), 4,
6085 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6086 SBTML_REJ | SBTML_RESET));
6087 regdata = bcmsdh_reg_read(sdh,
6088 CORE_SB(corebase, sbtmstatelow), 4);
6091 /* clear the initiator reject bit */
6092 regdata = bcmsdh_reg_read(sdh,
6093 CORE_SB(corebase, sbidlow), 4);
6094 if (regdata & SBIDL_INIT) {
6095 regdata = bcmsdh_reg_read(sdh,
6096 CORE_SB(corebase, sbimstate), 4) &
6098 bcmsdh_reg_write(sdh,
6099 CORE_SB(corebase, sbimstate), 4,
6104 /* leave reset and reject asserted */
6105 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6106 (SBTML_REJ | SBTML_RESET));
6111 dhdsdio_chip_attach(struct dhd_bus *bus, void *regs)
6113 struct chip_info *ci;
6117 DHD_TRACE(("%s: Enter\n", __func__));
6119 /* alloc chip_info_t */
6120 ci = kmalloc(sizeof(struct chip_info), GFP_ATOMIC);
6122 DHD_ERROR(("%s: malloc failed!\n", __func__));
6126 memset((unsigned char *)ci, 0, sizeof(struct chip_info));
6128 /* bus/core/clk setup for register access */
6129 /* Try forcing SDIO core to do ALPAvail request only */
6130 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
6131 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
6134 DHD_ERROR(("%s: error writing for HT off\n", __func__));
6138 /* If register supported, wait for ALPAvail and then force ALP */
6139 /* This may take up to 15 milliseconds */
6140 clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6141 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
6142 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
6144 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6145 SBSDIO_FUNC1_CHIPCLKCSR,
6147 !SBSDIO_ALPAV(clkval)),
6148 PMU_MAX_TRANSITION_DLY);
6149 if (!SBSDIO_ALPAV(clkval)) {
6150 DHD_ERROR(("%s: timeout on ALPAV wait, clkval 0x%02x\n",
6155 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
6157 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
6158 SBSDIO_FUNC1_CHIPCLKCSR,
6162 DHD_ERROR(("%s: ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
6163 __func__, clkset, clkval));
6168 /* Also, disable the extra SDIO pull-ups */
6169 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0,
6172 err = dhdsdio_chip_recognition(bus->sdh, ci, regs);
6177 * Make sure any on-chip ARM is off (in case strapping is wrong),
6178 * or downloaded code was already running.
6180 dhdsdio_chip_disablecore(bus->sdh, ci->armcorebase);
6182 bcmsdh_reg_write(bus->sdh,
6183 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
6184 bcmsdh_reg_write(bus->sdh,
6185 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
6187 /* Disable F2 to clear any intermediate frame state on the dongle */
6188 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIO_CCCR_IOEx,
6189 SDIO_FUNC_ENABLE_1, NULL);
6191 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
6192 clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6195 /* Done with backplane-dependent accesses, can drop clock... */
6196 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0,
6208 dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase)
6213 * Must do the disable sequence first to work for
6214 * arbitrary current core state.
6216 dhdsdio_chip_disablecore(sdh, corebase);
6219 * Now do the initialization sequence.
6220 * set reset while enabling the clock and
6221 * forcing them on throughout the core
6223 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6224 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6228 regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbtmstatehigh), 4);
6229 if (regdata & SBTMH_SERR)
6230 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatehigh), 4, 0);
6232 regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbimstate), 4);
6233 if (regdata & (SBIM_IBE | SBIM_TO))
6234 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbimstate), 4,
6235 regdata & ~(SBIM_IBE | SBIM_TO));
6237 /* clear reset and allow it to propagate throughout the core */
6238 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6239 (SICF_FGC << SBTML_SICF_SHIFT) |
6240 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6243 /* leave clock enabled */
6244 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6245 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6249 /* SDIO Pad drive strength to select value mappings */
6250 struct sdiod_drive_str {
6251 u8 strength; /* Pad Drive Strength in mA */
6252 u8 sel; /* Chip-specific select value */
6255 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
6256 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
6264 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
6265 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
6276 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
6277 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
6289 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
6292 dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus, u32 drivestrength) {
6293 struct sdiod_drive_str *str_tab = NULL;
6298 if (!(bus->ci->cccaps & CC_CAP_PMU))
6301 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
6302 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
6303 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
6304 str_mask = 0x30000000;
6307 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
6308 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
6309 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
6310 str_mask = 0x00003800;
6313 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
6314 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
6315 str_mask = 0x00003800;
6319 DHD_ERROR(("No SDIO Drive strength init"
6320 "done for chip %s rev %d pmurev %d\n",
6321 brcmu_chipname(bus->ci->chip, chn, 8),
6322 bus->ci->chiprev, bus->ci->pmurev));
6326 if (str_tab != NULL) {
6327 u32 drivestrength_sel = 0;
6331 for (i = 0; str_tab[i].strength != 0; i++) {
6332 if (drivestrength >= str_tab[i].strength) {
6333 drivestrength_sel = str_tab[i].sel;
6338 bcmsdh_reg_write(bus->sdh,
6339 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6341 cc_data_temp = bcmsdh_reg_read(bus->sdh,
6342 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
6343 cc_data_temp &= ~str_mask;
6344 drivestrength_sel <<= str_shift;
6345 cc_data_temp |= drivestrength_sel;
6346 bcmsdh_reg_write(bus->sdh,
6347 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6350 DHD_INFO(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
6351 drivestrength, cc_data_temp));
6356 dhdsdio_chip_detach(struct dhd_bus *bus)
6358 DHD_TRACE(("%s: Enter\n", __func__));
git.openpandora.org / pandora-kernel.git / blob