drivers/staging/brcm80211/brcmfmac/dhd_sdio.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/types.h>
  18 #include <linux/kernel.h>
  19 #include <linux/printk.h>
  20 #include <linux/pci_ids.h>
  21 #include <linux/netdevice.h>
  22 #include <bcmdefs.h>
  23 #include <bcmsdh.h>
  24
  25 #ifdef BCMEMBEDIMAGE
  26 #include BCMEMBEDIMAGE
  27 #endif                          /* BCMEMBEDIMAGE */
  28
  29 #include <bcmdefs.h>
  30 #include <bcmutils.h>
  31 #include <bcmdevs.h>
  32
  33 #include <bcmsoc.h>
  34 #ifdef DHD_DEBUG
  35
  36 /* ARM trap handling */
  37
  38 /* Trap types defined by ARM (see arminc.h) */
  39
  40 /* Trap locations in lo memory */
  41 #define TRAP_STRIDE     4
  42 #define FIRST_TRAP      TR_RST
  43 #define LAST_TRAP       (TR_FIQ * TRAP_STRIDE)
  44
  45 #if defined(__ARM_ARCH_4T__)
  46 #define MAX_TRAP_TYPE   (TR_FIQ + 1)
  47 #elif defined(__ARM_ARCH_7M__)
  48 #define MAX_TRAP_TYPE   (TR_ISR + ARMCM3_NUMINTS)
  49 #endif                          /* __ARM_ARCH_7M__ */
  50
  51 /* The trap structure is defined here as offsets for assembly */
  52 #define TR_TYPE         0x00
  53 #define TR_EPC          0x04
  54 #define TR_CPSR         0x08
  55 #define TR_SPSR         0x0c
  56 #define TR_REGS         0x10
  57 #define TR_REG(n)       (TR_REGS + (n) * 4)
  58 #define TR_SP           TR_REG(13)
  59 #define TR_LR           TR_REG(14)
  60 #define TR_PC           TR_REG(15)
  61
  62 #define TRAP_T_SIZE     80
  63
  64 #ifndef _LANGUAGE_ASSEMBLY
  65
  66 typedef struct _trap_struct {
  67         u32 type;
  68         u32 epc;
  69         u32 cpsr;
  70         u32 spsr;
  71         u32 r0;
  72         u32 r1;
  73         u32 r2;
  74         u32 r3;
  75         u32 r4;
  76         u32 r5;
  77         u32 r6;
  78         u32 r7;
  79         u32 r8;
  80         u32 r9;
  81         u32 r10;
  82         u32 r11;
  83         u32 r12;
  84         u32 r13;
  85         u32 r14;
  86         u32 pc;
  87 } trap_t;
  88
  89 #endif                          /* !_LANGUAGE_ASSEMBLY */
  90
  91 #define CBUF_LEN        (128)
  92
  93 #define LOG_BUF_LEN     1024
  94
  95 typedef struct {
  96         u32 buf;                /* Can't be pointer on (64-bit) hosts */
  97         uint buf_size;
  98         uint idx;
  99         char *_buf_compat;      /* Redundant pointer for backward compat. */
 100 } rte_log_t;
 101
 102 typedef struct {
 103         /* Virtual UART
 104          * When there is no UART (e.g. Quickturn),
 105          * the host should write a complete
 106          * input line directly into cbuf and then write
 107          * the length into vcons_in.
 108          * This may also be used when there is a real UART
 109          * (at risk of conflicting with
 110          * the real UART).  vcons_out is currently unused.
 111          */
 112         volatile uint vcons_in;
 113         volatile uint vcons_out;
 114
 115         /* Output (logging) buffer
 116          * Console output is written to a ring buffer log_buf at index log_idx.
 117          * The host may read the output when it sees log_idx advance.
 118          * Output will be lost if the output wraps around faster than the host
 119          * polls.
 120          */
 121         rte_log_t log;
 122
 123         /* Console input line buffer
 124          * Characters are read one at a time into cbuf
 125          * until <CR> is received, then
 126          * the buffer is processed as a command line.
 127          * Also used for virtual UART.
 128          */
 129         uint cbuf_idx;
 130         char cbuf[CBUF_LEN];
 131 } rte_cons_t;
 132
 133 #endif                          /* DHD_DEBUG */
 134 #include <sbchipc.h>
 135 #include <sbdma.h>
 136
 137 #include <sdio.h>
 138 #include <sbsdio.h>
 139 #include <sbsdpcmdev.h>
 140 #include <bcmsdpcm.h>
 141
 142 #include <dngl_stats.h>
 143 #include <dhd.h>
 144 #include <dhd_bus.h>
 145 #include <dhd_proto.h>
 146 #include <dhd_dbg.h>
 147 #include <sdiovar.h>
 148 #include <bcmchip.h>
 149
 150 #ifndef DHDSDIO_MEM_DUMP_FNAME
 151 #define DHDSDIO_MEM_DUMP_FNAME         "mem_dump"
 152 #endif
 153
 154 #define TXQLEN          2048    /* bulk tx queue length */
 155 #define TXHI            (TXQLEN - 256)  /* turn on flow control above TXHI */
 156 #define TXLOW           (TXHI - 256)    /* turn off flow control below TXLOW */
 157 #define PRIOMASK        7
 158
 159 #define TXRETRIES       2       /* # of retries for tx frames */
 160
 161 #if defined(CONFIG_MACH_SANDGATE2G)
 162 #define DHD_RXBOUND     250     /* Default for max rx frames in
 163                                  one scheduling */
 164 #else
 165 #define DHD_RXBOUND     50      /* Default for max rx frames in
 166                                  one scheduling */
 167 #endif                          /* defined(CONFIG_MACH_SANDGATE2G) */
 168
 169 #define DHD_TXBOUND     20      /* Default for max tx frames in
 170                                  one scheduling */
 171
 172 #define DHD_TXMINMAX    1       /* Max tx frames if rx still pending */
 173
 174 #define MEMBLOCK        2048    /* Block size used for downloading
 175                                  of dongle image */
 176 #define MAX_DATA_BUF    (32 * 1024)     /* Must be large enough to hold
 177                                  biggest possible glom */
 178
 179 /* Packet alignment for most efficient SDIO (can change based on platform) */
 180 #ifndef DHD_SDALIGN
 181 #define DHD_SDALIGN     32
 182 #endif
 183 #if !ISPOWEROF2(DHD_SDALIGN)
 184 #error DHD_SDALIGN is not a power of 2!
 185 #endif
 186
 187 #ifndef DHD_FIRSTREAD
 188 #define DHD_FIRSTREAD   32
 189 #endif
 190 #if !ISPOWEROF2(DHD_FIRSTREAD)
 191 #error DHD_FIRSTREAD is not a power of 2!
 192 #endif
 193
 194 /* Total length of frame header for dongle protocol */
 195 #define SDPCM_HDRLEN    (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
 196 #ifdef SDTEST
 197 #define SDPCM_RESERVE   (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
 198 #else
 199 #define SDPCM_RESERVE   (SDPCM_HDRLEN + DHD_SDALIGN)
 200 #endif
 201
 202 /* Space for header read, limit for data packets */
 203 #ifndef MAX_HDR_READ
 204 #define MAX_HDR_READ    32
 205 #endif
 206 #if !ISPOWEROF2(MAX_HDR_READ)
 207 #error MAX_HDR_READ is not a power of 2!
 208 #endif
 209
 210 #define MAX_RX_DATASZ   2048
 211
 212 /* Maximum milliseconds to wait for F2 to come up */
 213 #define DHD_WAIT_F2RDY  3000
 214
 215 /* Bump up limit on waiting for HT to account for first startup;
 216  * if the image is doing a CRC calculation before programming the PMU
 217  * for HT availability, it could take a couple hundred ms more, so
 218  * max out at a 1 second (1000000us).
 219  */
 220 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
 221 #undef PMU_MAX_TRANSITION_DLY
 222 #define PMU_MAX_TRANSITION_DLY 1000000
 223 #endif
 224
 225 /* Value for ChipClockCSR during initial setup */
 226 #define DHD_INIT_CLKCTL1        (SBSDIO_FORCE_HW_CLKREQ_OFF |   \
 227                                         SBSDIO_ALP_AVAIL_REQ)
 228 #define DHD_INIT_CLKCTL2        (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
 229
 230 /* Flags for SDH calls */
 231 #define F2SYNC  (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
 232
 233 /* sbimstate */
 234 #define SBIM_IBE                0x20000 /* inbanderror */
 235 #define SBIM_TO                 0x40000 /* timeout */
 236 #define SBIM_BY                 0x01800000      /* busy (sonics >= 2.3) */
 237 #define SBIM_RJ                 0x02000000      /* reject (sonics >= 2.3) */
 238
 239 /* sbtmstatelow */
 240 #define SBTML_RESET             0x0001  /* reset */
 241 #define SBTML_REJ_MASK          0x0006  /* reject field */
 242 #define SBTML_REJ               0x0002  /* reject */
 243 #define SBTML_TMPREJ            0x0004  /* temporary reject, for error recovery */
 244
 245 #define SBTML_SICF_SHIFT        16      /* Shift to locate the SI control flags in sbtml */
 246
 247 /* sbtmstatehigh */
 248 #define SBTMH_SERR              0x0001  /* serror */
 249 #define SBTMH_INT               0x0002  /* interrupt */
 250 #define SBTMH_BUSY              0x0004  /* busy */
 251 #define SBTMH_TO                0x0020  /* timeout (sonics >= 2.3) */
 252
 253 #define SBTMH_SISF_SHIFT        16      /* Shift to locate the SI status flags in sbtmh */
 254
 255 /* sbidlow */
 256 #define SBIDL_INIT              0x80    /* initiator */
 257
 258 /* sbidhigh */
 259 #define SBIDH_RC_MASK           0x000f  /* revision code */
 260 #define SBIDH_RCE_MASK          0x7000  /* revision code extension field */
 261 #define SBIDH_RCE_SHIFT         8
 262 #define SBCOREREV(sbidh) \
 263         ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
 264 #define SBIDH_CC_MASK           0x8ff0  /* core code */
 265 #define SBIDH_CC_SHIFT          4
 266 #define SBIDH_VC_MASK           0xffff0000      /* vendor code */
 267 #define SBIDH_VC_SHIFT          16
 268
 269 /*
 270  * Conversion of 802.1D priority to precedence level
 271  */
 272 #define PRIO2PREC(prio) \
 273         (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
 274         ((prio^2)) : (prio))
 275
 276 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
 277 extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
 278                             uint len);
 279
 280 /* Core reg address translation */
 281 #define CORE_CC_REG(base, field)        (base + offsetof(chipcregs_t, field))
 282 #define CORE_BUS_REG(base, field)       (base + offsetof(sdpcmd_regs_t, field))
 283 #define CORE_SB(base, field) \
 284                 (base + SBCONFIGOFF + offsetof(sbconfig_t, field))
 285
 286 #ifdef DHD_DEBUG
 287 /* Device console log buffer state */
 288 typedef struct dhd_console {
 289         uint count;             /* Poll interval msec counter */
 290         uint log_addr;          /* Log struct address (fixed) */
 291         rte_log_t log;  /* Log struct (host copy) */
 292         uint bufsize;           /* Size of log buffer */
 293         u8 *buf;                /* Log buffer (host copy) */
 294         uint last;              /* Last buffer read index */
 295 } dhd_console_t;
 296 #endif                          /* DHD_DEBUG */
 297
 298 /* misc chip info needed by some of the routines */
 299 struct chip_info {
 300         u32 chip;
 301         u32 chiprev;
 302         u32 cccorebase;
 303         u32 ccrev;
 304         u32 cccaps;
 305         u32 buscorebase;
 306         u32 buscorerev;
 307         u32 buscoretype;
 308         u32 ramcorebase;
 309         u32 armcorebase;
 310         u32 pmurev;
 311         u32 ramsize;
 312 };
 313
 314 /* Private data for SDIO bus interaction */
 315 typedef struct dhd_bus {
 316         dhd_pub_t *dhd;
 317
 318         bcmsdh_info_t *sdh;     /* Handle for BCMSDH calls */
 319         struct chip_info *ci;   /* Chip info struct */
 320         char *vars;             /* Variables (from CIS and/or other) */
 321         uint varsz;             /* Size of variables buffer */
 322         u32 sbaddr;             /* Current SB window pointer (-1, invalid) */
 323
 324         sdpcmd_regs_t *regs;    /* Registers for SDIO core */
 325         uint sdpcmrev;          /* SDIO core revision */
 326         uint armrev;            /* CPU core revision */
 327         uint ramrev;            /* SOCRAM core revision */
 328         u32 ramsize;            /* Size of RAM in SOCRAM (bytes) */
 329         u32 orig_ramsize;       /* Size of RAM in SOCRAM (bytes) */
 330
 331         u32 bus;                /* gSPI or SDIO bus */
 332         u32 hostintmask;        /* Copy of Host Interrupt Mask */
 333         u32 intstatus;  /* Intstatus bits (events) pending */
 334         bool dpc_sched;         /* Indicates DPC schedule (intrpt rcvd) */
 335         bool fcstate;           /* State of dongle flow-control */
 336
 337         u16 cl_devid;   /* cached devid for dhdsdio_probe_attach() */
 338         char *fw_path;          /* module_param: path to firmware image */
 339         char *nv_path;          /* module_param: path to nvram vars file */
 340         const char *nvram_params;       /* user specified nvram params. */
 341
 342         uint blocksize;         /* Block size of SDIO transfers */
 343         uint roundup;           /* Max roundup limit */
 344
 345         struct pktq txq;        /* Queue length used for flow-control */
 346         u8 flowcontrol; /* per prio flow control bitmask */
 347         u8 tx_seq;              /* Transmit sequence number (next) */
 348         u8 tx_max;              /* Maximum transmit sequence allowed */
 349
 350         u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
 351         u8 *rxhdr;              /* Header of current rx frame (in hdrbuf) */
 352         u16 nextlen;            /* Next Read Len from last header */
 353         u8 rx_seq;              /* Receive sequence number (expected) */
 354         bool rxskip;            /* Skip receive (awaiting NAK ACK) */
 355
 356         struct sk_buff *glomd;  /* Packet containing glomming descriptor */
 357         struct sk_buff *glom;   /* Packet chain for glommed superframe */
 358         uint glomerr;           /* Glom packet read errors */
 359
 360         u8 *rxbuf;              /* Buffer for receiving control packets */
 361         uint rxblen;            /* Allocated length of rxbuf */
 362         u8 *rxctl;              /* Aligned pointer into rxbuf */
 363         u8 *databuf;            /* Buffer for receiving big glom packet */
 364         u8 *dataptr;            /* Aligned pointer into databuf */
 365         uint rxlen;             /* Length of valid data in buffer */
 366
 367         u8 sdpcm_ver;   /* Bus protocol reported by dongle */
 368
 369         bool intr;              /* Use interrupts */
 370         bool poll;              /* Use polling */
 371         bool ipend;             /* Device interrupt is pending */
 372         bool intdis;            /* Interrupts disabled by isr */
 373         uint intrcount;         /* Count of device interrupt callbacks */
 374         uint lastintrs;         /* Count as of last watchdog timer */
 375         uint spurious;          /* Count of spurious interrupts */
 376         uint pollrate;          /* Ticks between device polls */
 377         uint polltick;          /* Tick counter */
 378         uint pollcnt;           /* Count of active polls */
 379
 380 #ifdef DHD_DEBUG
 381         dhd_console_t console;  /* Console output polling support */
 382         uint console_addr;      /* Console address from shared struct */
 383 #endif                          /* DHD_DEBUG */
 384
 385         uint regfails;          /* Count of R_REG/W_REG failures */
 386
 387         uint clkstate;          /* State of sd and backplane clock(s) */
 388         bool activity;          /* Activity flag for clock down */
 389         s32 idletime;           /* Control for activity timeout */
 390         s32 idlecount;  /* Activity timeout counter */
 391         s32 idleclock;  /* How to set bus driver when idle */
 392         s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
 393         bool use_rxchain;       /* If dhd should use PKT chains */
 394         bool sleeping;          /* Is SDIO bus sleeping? */
 395         bool rxflow_mode;       /* Rx flow control mode */
 396         bool rxflow;            /* Is rx flow control on */
 397         uint prev_rxlim_hit;    /* Is prev rx limit exceeded
 398                                          (per dpc schedule) */
 399         bool alp_only;          /* Don't use HT clock (ALP only) */
 400 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
 401         bool usebufpool;
 402
 403 #ifdef SDTEST
 404         /* external loopback */
 405         bool ext_loop;
 406         u8 loopid;
 407
 408         /* pktgen configuration */
 409         uint pktgen_freq;       /* Ticks between bursts */
 410         uint pktgen_count;      /* Packets to send each burst */
 411         uint pktgen_print;      /* Bursts between count displays */
 412         uint pktgen_total;      /* Stop after this many */
 413         uint pktgen_minlen;     /* Minimum packet data len */
 414         uint pktgen_maxlen;     /* Maximum packet data len */
 415         uint pktgen_mode;       /* Configured mode: tx, rx, or echo */
 416         uint pktgen_stop;       /* Number of tx failures causing stop */
 417
 418         /* active pktgen fields */
 419         uint pktgen_tick;       /* Tick counter for bursts */
 420         uint pktgen_ptick;      /* Burst counter for printing */
 421         uint pktgen_sent;       /* Number of test packets generated */
 422         uint pktgen_rcvd;       /* Number of test packets received */
 423         uint pktgen_fail;       /* Number of failed send attempts */
 424         u16 pktgen_len; /* Length of next packet to send */
 425 #endif                          /* SDTEST */
 426
 427         /* Some additional counters */
 428         uint tx_sderrs;         /* Count of tx attempts with sd errors */
 429         uint fcqueued;          /* Tx packets that got queued */
 430         uint rxrtx;             /* Count of rtx requests (NAK to dongle) */
 431         uint rx_toolong;        /* Receive frames too long to receive */
 432         uint rxc_errors;        /* SDIO errors when reading control frames */
 433         uint rx_hdrfail;        /* SDIO errors on header reads */
 434         uint rx_badhdr;         /* Bad received headers (roosync?) */
 435         uint rx_badseq;         /* Mismatched rx sequence number */
 436         uint fc_rcvd;           /* Number of flow-control events received */
 437         uint fc_xoff;           /* Number which turned on flow-control */
 438         uint fc_xon;            /* Number which turned off flow-control */
 439         uint rxglomfail;        /* Failed deglom attempts */
 440         uint rxglomframes;      /* Number of glom frames (superframes) */
 441         uint rxglompkts;        /* Number of packets from glom frames */
 442         uint f2rxhdrs;          /* Number of header reads */
 443         uint f2rxdata;          /* Number of frame data reads */
 444         uint f2txdata;          /* Number of f2 frame writes */
 445         uint f1regdata;         /* Number of f1 register accesses */
 446
 447         u8 *ctrl_frame_buf;
 448         u32 ctrl_frame_len;
 449         bool ctrl_frame_stat;
 450 } dhd_bus_t;
 451
 452 #ifndef _LANGUAGE_ASSEMBLY
 453
 454 typedef volatile struct _sbconfig {
 455         u32 PAD[2];
 456         u32 sbipsflag;  /* initiator port ocp slave flag */
 457         u32 PAD[3];
 458         u32 sbtpsflag;  /* target port ocp slave flag */
 459         u32 PAD[11];
 460         u32 sbtmerrloga;        /* (sonics >= 2.3) */
 461         u32 PAD;
 462         u32 sbtmerrlog; /* (sonics >= 2.3) */
 463         u32 PAD[3];
 464         u32 sbadmatch3; /* address match3 */
 465         u32 PAD;
 466         u32 sbadmatch2; /* address match2 */
 467         u32 PAD;
 468         u32 sbadmatch1; /* address match1 */
 469         u32 PAD[7];
 470         u32 sbimstate;  /* initiator agent state */
 471         u32 sbintvec;   /* interrupt mask */
 472         u32 sbtmstatelow;       /* target state */
 473         u32 sbtmstatehigh;      /* target state */
 474         u32 sbbwa0;             /* bandwidth allocation table0 */
 475         u32 PAD;
 476         u32 sbimconfiglow;      /* initiator configuration */
 477         u32 sbimconfighigh;     /* initiator configuration */
 478         u32 sbadmatch0; /* address match0 */
 479         u32 PAD;
 480         u32 sbtmconfiglow;      /* target configuration */
 481         u32 sbtmconfighigh;     /* target configuration */
 482         u32 sbbconfig;  /* broadcast configuration */
 483         u32 PAD;
 484         u32 sbbstate;   /* broadcast state */
 485         u32 PAD[3];
 486         u32 sbactcnfg;  /* activate configuration */
 487         u32 PAD[3];
 488         u32 sbflagst;   /* current sbflags */
 489         u32 PAD[3];
 490         u32 sbidlow;            /* identification */
 491         u32 sbidhigh;   /* identification */
 492 } sbconfig_t;
 493
 494 #endif                          /* _LANGUAGE_ASSEMBLY */
 495
 496 /* clkstate */
 497 #define CLK_NONE        0
 498 #define CLK_SDONLY      1
 499 #define CLK_PENDING     2       /* Not used yet */
 500 #define CLK_AVAIL       3
 501
 502 #define DHD_NOPMU(dhd)  (false)
 503
 504 #ifdef DHD_DEBUG
 505 static int qcount[NUMPRIO];
 506 static int tx_packets[NUMPRIO];
 507 #endif                          /* DHD_DEBUG */
 508
 509 /* Deferred transmit */
 510 const uint dhd_deferred_tx = 1;
 511
 512 extern uint dhd_watchdog_ms;
 513 extern void dhd_os_wd_timer(void *bus, uint wdtick);
 514
 515 /* Tx/Rx bounds */
 516 uint dhd_txbound;
 517 uint dhd_rxbound;
 518 uint dhd_txminmax;
 519
 520 /* override the RAM size if possible */
 521 #define DONGLE_MIN_MEMSIZE (128 * 1024)
 522 int dhd_dongle_memsize;
 523
 524 static bool dhd_alignctl;
 525
 526 static bool sd1idle;
 527
 528 static bool retrydata;
 529 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
 530
 531 static const uint watermark = 8;
 532 static const uint firstread = DHD_FIRSTREAD;
 533
 534 #define HDATLEN (firstread - (SDPCM_HDRLEN))
 535
 536 /* Retry count for register access failures */
 537 static const uint retry_limit = 2;
 538
 539 /* Force even SD lengths (some host controllers mess up on odd bytes) */
 540 static bool forcealign;
 541
 542 #define ALIGNMENT  4
 543
 544 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
 545 extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
 546 #endif
 547
 548 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
 549 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
 550 #endif  /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
 551 #define PKTALIGN(_p, _len, _align)                              \
 552         do {                                                            \
 553                 uint datalign;                                          \
 554                 datalign = (unsigned long)((_p)->data);                 \
 555                 datalign = roundup(datalign, (_align)) - datalign;      \
 556                 ASSERT(datalign < (_align));                            \
 557                 ASSERT((_p)->len >= ((_len) + datalign));               \
 558                 if (datalign)                                           \
 559                         skb_pull((_p), datalign);                       \
 560                 __skb_trim((_p), (_len));                               \
 561         } while (0)
 562
 563 /* Limit on rounding up frames */
 564 static const uint max_roundup = 512;
 565
 566 /* Try doing readahead */
 567 static bool dhd_readahead;
 568
 569 /* To check if there's window offered */
 570 #define DATAOK(bus) \
 571         (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
 572         (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
 573
 574 /* Macros to get register read/write status */
 575 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
 576 #define R_SDREG(regvar, regaddr, retryvar) \
 577 do { \
 578         retryvar = 0; \
 579         do { \
 580                 regvar = R_REG(regaddr); \
 581         } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
 582         if (retryvar) { \
 583                 bus->regfails += (retryvar-1); \
 584                 if (retryvar > retry_limit) { \
 585                         DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
 586                         __func__, __LINE__)); \
 587                         regvar = 0; \
 588                 } \
 589         } \
 590 } while (0)
 591
 592 #define W_SDREG(regval, regaddr, retryvar) \
 593 do { \
 594         retryvar = 0; \
 595         do { \
 596                 W_REG(regaddr, regval); \
 597         } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
 598         if (retryvar) { \
 599                 bus->regfails += (retryvar-1); \
 600                 if (retryvar > retry_limit) \
 601                         DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
 602                         __func__, __LINE__)); \
 603         } \
 604 } while (0)
 605
 606 #define DHD_BUS                 SDIO_BUS
 607
 608 #define PKT_AVAILABLE()         (intstatus & I_HMB_FRAME_IND)
 609
 610 #define HOSTINTMASK             (I_HMB_SW_MASK | I_CHIPACTIVE)
 611
 612 #ifdef SDTEST
 613 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
 614 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
 615 #endif
 616
 617 #ifdef DHD_DEBUG
 618 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size);
 619 static int dhdsdio_mem_dump(dhd_bus_t *bus);
 620 #endif                          /* DHD_DEBUG  */
 621 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
 622
 623 static void dhdsdio_release(dhd_bus_t *bus);
 624 static void dhdsdio_release_malloc(dhd_bus_t *bus);
 625 static void dhdsdio_disconnect(void *ptr);
 626 static bool dhdsdio_chipmatch(u16 chipid);
 627 static bool dhdsdio_probe_attach(dhd_bus_t *bus, void *sdh,
 628                                  void *regsva, u16 devid);
 629 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh);
 630 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh);
 631 static void dhdsdio_release_dongle(dhd_bus_t *bus);
 632
 633 static uint process_nvram_vars(char *varbuf, uint len);
 634
 635 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
 636 static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
 637                                uint flags, u8 *buf, uint nbytes,
 638                                struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
 639                                void *handle);
 640
 641 static bool dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh);
 642 static int _dhdsdio_download_firmware(struct dhd_bus *bus);
 643
 644 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
 645 static int dhdsdio_download_nvram(struct dhd_bus *bus);
 646 #ifdef BCMEMBEDIMAGE
 647 static int dhdsdio_download_code_array(struct dhd_bus *bus);
 648 #endif
 649 static void dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase);
 650 static int dhdsdio_chip_attach(struct dhd_bus *bus, void *regs);
 651 static void dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase);
 652 static void dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus,
 653                                         u32 drivestrength);
 654 static void dhdsdio_chip_detach(struct dhd_bus *bus);
 655
 656 /* Packet free applicable unconditionally for sdio and sdspi.
 657  * Conditional if bufpool was present for gspi bus.
 658  */
 659 static void dhdsdio_pktfree2(dhd_bus_t *bus, struct sk_buff *pkt)
 660 {
 661         dhd_os_sdlock_rxq(bus->dhd);
 662         if ((bus->bus != SPI_BUS) || bus->usebufpool)
 663                 bcm_pkt_buf_free_skb(pkt);
 664         dhd_os_sdunlock_rxq(bus->dhd);
 665 }
 666
 667 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
 668 {
 669         s32 min_size = DONGLE_MIN_MEMSIZE;
 670         /* Restrict the memsize to user specified limit */
 671         DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
 672                 dhd_dongle_memsize, min_size));
 673         if ((dhd_dongle_memsize > min_size) &&
 674             (dhd_dongle_memsize < (s32) bus->orig_ramsize))
 675                 bus->ramsize = dhd_dongle_memsize;
 676 }
 677
 678 static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
 679 {
 680         int err = 0;
 681         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
 682                          (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
 683         if (!err)
 684                 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
 685                                  (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
 686         if (!err)
 687                 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
 688                                  (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
 689                                  &err);
 690         return err;
 691 }
 692
 693 /* Turn backplane clock on or off */
 694 static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
 695 {
 696         int err;
 697         u8 clkctl, clkreq, devctl;
 698         bcmsdh_info_t *sdh;
 699
 700         DHD_TRACE(("%s: Enter\n", __func__));
 701
 702 #if defined(OOB_INTR_ONLY)
 703         pendok = false;
 704 #endif
 705         clkctl = 0;
 706         sdh = bus->sdh;
 707
 708         if (on) {
 709                 /* Request HT Avail */
 710                 clkreq =
 711                     bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
 712
 713                 if ((bus->ci->chip == BCM4329_CHIP_ID)
 714                     && (bus->ci->chiprev == 0))
 715                         clkreq |= SBSDIO_FORCE_ALP;
 716
 717                 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
 718                                  clkreq, &err);
 719                 if (err) {
 720                         DHD_ERROR(("%s: HT Avail request error: %d\n",
 721                                    __func__, err));
 722                         return -EBADE;
 723                 }
 724
 725                 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
 726                                && (bus->ci->buscorerev == 9))) {
 727                         u32 dummy, retries;
 728                         R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
 729                 }
 730
 731                 /* Check current status */
 732                 clkctl =
 733                     bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
 734                                     &err);
 735                 if (err) {
 736                         DHD_ERROR(("%s: HT Avail read error: %d\n",
 737                                    __func__, err));
 738                         return -EBADE;
 739                 }
 740
 741                 /* Go to pending and await interrupt if appropriate */
 742                 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
 743                         /* Allow only clock-available interrupt */
 744                         devctl =
 745                             bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
 746                                             &err);
 747                         if (err) {
 748                                 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
 749                                         __func__, err));
 750                                 return -EBADE;
 751                         }
 752
 753                         devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
 754                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
 755                                          devctl, &err);
 756                         DHD_INFO(("CLKCTL: set PENDING\n"));
 757                         bus->clkstate = CLK_PENDING;
 758
 759                         return 0;
 760                 } else if (bus->clkstate == CLK_PENDING) {
 761                         /* Cancel CA-only interrupt filter */
 762                         devctl =
 763                             bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
 764                                             &err);
 765                         devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
 766                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
 767                                          devctl, &err);
 768                 }
 769
 770                 /* Otherwise, wait here (polling) for HT Avail */
 771                 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
 772                         SPINWAIT_SLEEP(sdioh_spinwait_sleep,
 773                                        ((clkctl =
 774                                          bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
 775                                                  SBSDIO_FUNC1_CHIPCLKCSR,
 776                                                          &err)),
 777                                         !SBSDIO_CLKAV(clkctl, bus->alp_only)),
 778                                        PMU_MAX_TRANSITION_DLY);
 779                 }
 780                 if (err) {
 781                         DHD_ERROR(("%s: HT Avail request error: %d\n",
 782                                    __func__, err));
 783                         return -EBADE;
 784                 }
 785                 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
 786                         DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
 787                                    __func__, PMU_MAX_TRANSITION_DLY, clkctl));
 788                         return -EBADE;
 789                 }
 790
 791                 /* Mark clock available */
 792                 bus->clkstate = CLK_AVAIL;
 793                 DHD_INFO(("CLKCTL: turned ON\n"));
 794
 795 #if defined(DHD_DEBUG)
 796                 if (bus->alp_only == true) {
 797 #if !defined(BCMLXSDMMC)
 798                         if (!SBSDIO_ALPONLY(clkctl)) {
 799                                 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
 800                                            __func__));
 801                         }
 802 #endif                          /* !defined(BCMLXSDMMC) */
 803                 } else {
 804                         if (SBSDIO_ALPONLY(clkctl)) {
 805                                 DHD_ERROR(("%s: HT Clock should be on.\n",
 806                                            __func__));
 807                         }
 808                 }
 809 #endif                          /* defined (DHD_DEBUG) */
 810
 811                 bus->activity = true;
 812         } else {
 813                 clkreq = 0;
 814
 815                 if (bus->clkstate == CLK_PENDING) {
 816                         /* Cancel CA-only interrupt filter */
 817                         devctl =
 818                             bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
 819                                             &err);
 820                         devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
 821                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
 822                                          devctl, &err);
 823                 }
 824
 825                 bus->clkstate = CLK_SDONLY;
 826                 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
 827                                  clkreq, &err);
 828                 DHD_INFO(("CLKCTL: turned OFF\n"));
 829                 if (err) {
 830                         DHD_ERROR(("%s: Failed access turning clock off: %d\n",
 831                                    __func__, err));
 832                         return -EBADE;
 833                 }
 834         }
 835         return 0;
 836 }
 837
 838 /* Change idle/active SD state */
 839 static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
 840 {
 841         DHD_TRACE(("%s: Enter\n", __func__));
 842
 843         if (on)
 844                 bus->clkstate = CLK_SDONLY;
 845         else
 846                 bus->clkstate = CLK_NONE;
 847
 848         return 0;
 849 }
 850
 851 /* Transition SD and backplane clock readiness */
 852 static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
 853 {
 854 #ifdef DHD_DEBUG
 855         uint oldstate = bus->clkstate;
 856 #endif                          /* DHD_DEBUG */
 857
 858         DHD_TRACE(("%s: Enter\n", __func__));
 859
 860         /* Early exit if we're already there */
 861         if (bus->clkstate == target) {
 862                 if (target == CLK_AVAIL) {
 863                         dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
 864                         bus->activity = true;
 865                 }
 866                 return 0;
 867         }
 868
 869         switch (target) {
 870         case CLK_AVAIL:
 871                 /* Make sure SD clock is available */
 872                 if (bus->clkstate == CLK_NONE)
 873                         dhdsdio_sdclk(bus, true);
 874                 /* Now request HT Avail on the backplane */
 875                 dhdsdio_htclk(bus, true, pendok);
 876                 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
 877                 bus->activity = true;
 878                 break;
 879
 880         case CLK_SDONLY:
 881                 /* Remove HT request, or bring up SD clock */
 882                 if (bus->clkstate == CLK_NONE)
 883                         dhdsdio_sdclk(bus, true);
 884                 else if (bus->clkstate == CLK_AVAIL)
 885                         dhdsdio_htclk(bus, false, false);
 886                 else
 887                         DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
 888                                    bus->clkstate, target));
 889                 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
 890                 break;
 891
 892         case CLK_NONE:
 893                 /* Make sure to remove HT request */
 894                 if (bus->clkstate == CLK_AVAIL)
 895                         dhdsdio_htclk(bus, false, false);
 896                 /* Now remove the SD clock */
 897                 dhdsdio_sdclk(bus, false);
 898                 dhd_os_wd_timer(bus->dhd, 0);
 899                 break;
 900         }
 901 #ifdef DHD_DEBUG
 902         DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
 903 #endif                          /* DHD_DEBUG */
 904
 905         return 0;
 906 }
 907
 908 int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
 909 {
 910         bcmsdh_info_t *sdh = bus->sdh;
 911         sdpcmd_regs_t *regs = bus->regs;
 912         uint retries = 0;
 913
 914         DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
 915                   (sleep ? "SLEEP" : "WAKE"),
 916                   (bus->sleeping ? "SLEEP" : "WAKE")));
 917
 918         /* Done if we're already in the requested state */
 919         if (sleep == bus->sleeping)
 920                 return 0;
 921
 922         /* Going to sleep: set the alarm and turn off the lights... */
 923         if (sleep) {
 924                 /* Don't sleep if something is pending */
 925                 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
 926                         return -EBUSY;
 927
 928                 /* Disable SDIO interrupts (no longer interested) */
 929                 bcmsdh_intr_disable(bus->sdh);
 930
 931                 /* Make sure the controller has the bus up */
 932                 dhdsdio_clkctl(bus, CLK_AVAIL, false);
 933
 934                 /* Tell device to start using OOB wakeup */
 935                 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
 936                 if (retries > retry_limit)
 937                         DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
 938
 939                 /* Turn off our contribution to the HT clock request */
 940                 dhdsdio_clkctl(bus, CLK_SDONLY, false);
 941
 942                 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
 943                                  SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
 944
 945                 /* Isolate the bus */
 946                 if (bus->ci->chip != BCM4329_CHIP_ID
 947                     && bus->ci->chip != BCM4319_CHIP_ID) {
 948                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
 949                                          SBSDIO_DEVCTL_PADS_ISO, NULL);
 950                 }
 951
 952                 /* Change state */
 953                 bus->sleeping = true;
 954
 955         } else {
 956                 /* Waking up: bus power up is ok, set local state */
 957
 958                 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
 959                                  0, NULL);
 960
 961                 /* Force pad isolation off if possible
 962                          (in case power never toggled) */
 963                 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
 964                     && (bus->ci->buscorerev >= 10))
 965                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
 966                                          NULL);
 967
 968                 /* Make sure the controller has the bus up */
 969                 dhdsdio_clkctl(bus, CLK_AVAIL, false);
 970
 971                 /* Send misc interrupt to indicate OOB not needed */
 972                 W_SDREG(0, &regs->tosbmailboxdata, retries);
 973                 if (retries <= retry_limit)
 974                         W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
 975
 976                 if (retries > retry_limit)
 977                         DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
 978
 979                 /* Make sure we have SD bus access */
 980                 dhdsdio_clkctl(bus, CLK_SDONLY, false);
 981
 982                 /* Change state */
 983                 bus->sleeping = false;
 984
 985                 /* Enable interrupts again */
 986                 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
 987                         bus->intdis = false;
 988                         bcmsdh_intr_enable(bus->sdh);
 989                 }
 990         }
 991
 992         return 0;
 993 }
 994
 995 #if defined(OOB_INTR_ONLY)
 996 void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
 997 {
 998 #if defined(HW_OOB)
 999         bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
1000 #else
1001         sdpcmd_regs_t *regs = bus->regs;
1002         uint retries = 0;
1003
1004         dhdsdio_clkctl(bus, CLK_AVAIL, false);
1005         if (enable == true) {
1006
1007                 /* Tell device to start using OOB wakeup */
1008                 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
1009                 if (retries > retry_limit)
1010                         DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
1011
1012         } else {
1013                 /* Send misc interrupt to indicate OOB not needed */
1014                 W_SDREG(0, &regs->tosbmailboxdata, retries);
1015                 if (retries <= retry_limit)
1016                         W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
1017         }
1018
1019         /* Turn off our contribution to the HT clock request */
1020         dhdsdio_clkctl(bus, CLK_SDONLY, false);
1021 #endif                          /* !defined(HW_OOB) */
1022 }
1023 #endif                          /* defined(OOB_INTR_ONLY) */
1024
1025 #define BUS_WAKE(bus) \
1026         do { \
1027                 if ((bus)->sleeping) \
1028                         dhdsdio_bussleep((bus), false); \
1029         } while (0);
1030
1031 /* Writes a HW/SW header into the packet and sends it. */
1032 /* Assumes: (a) header space already there, (b) caller holds lock */
1033 static int dhdsdio_txpkt(dhd_bus_t *bus, struct sk_buff *pkt, uint chan,
1034                          bool free_pkt)
1035 {
1036         int ret;
1037         u8 *frame;
1038         u16 len, pad = 0;
1039         u32 swheader;
1040         uint retries = 0;
1041         bcmsdh_info_t *sdh;
1042         struct sk_buff *new;
1043         int i;
1044
1045         DHD_TRACE(("%s: Enter\n", __func__));
1046
1047         sdh = bus->sdh;
1048
1049         if (bus->dhd->dongle_reset) {
1050                 ret = -EPERM;
1051                 goto done;
1052         }
1053
1054         frame = (u8 *) (pkt->data);
1055
1056         /* Add alignment padding, allocate new packet if needed */
1057         pad = ((unsigned long)frame % DHD_SDALIGN);
1058         if (pad) {
1059                 if (skb_headroom(pkt) < pad) {
1060                         DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
1061                                   __func__, skb_headroom(pkt), pad));
1062                         bus->dhd->tx_realloc++;
1063                         new = bcm_pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
1064                         if (!new) {
1065                                 DHD_ERROR(("%s: couldn't allocate new %d-byte "
1066                                         "packet\n",
1067                                         __func__, pkt->len + DHD_SDALIGN));
1068                                 ret = -ENOMEM;
1069                                 goto done;
1070                         }
1071
1072                         PKTALIGN(new, pkt->len, DHD_SDALIGN);
1073                         memcpy(new->data, pkt->data, pkt->len);
1074                         if (free_pkt)
1075                                 bcm_pkt_buf_free_skb(pkt);
1076                         /* free the pkt if canned one is not used */
1077                         free_pkt = true;
1078                         pkt = new;
1079                         frame = (u8 *) (pkt->data);
1080                         ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
1081                         pad = 0;
1082                 } else {
1083                         skb_push(pkt, pad);
1084                         frame = (u8 *) (pkt->data);
1085
1086                         ASSERT((pad + SDPCM_HDRLEN) <= (int)(pkt->len));
1087                         memset(frame, 0, pad + SDPCM_HDRLEN);
1088                 }
1089         }
1090         ASSERT(pad < DHD_SDALIGN);
1091
1092         /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1093         len = (u16) (pkt->len);
1094         *(u16 *) frame = cpu_to_le16(len);
1095         *(((u16 *) frame) + 1) = cpu_to_le16(~len);
1096
1097         /* Software tag: channel, sequence number, data offset */
1098         swheader =
1099             ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
1100             (((pad +
1101                SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1102
1103         put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1104         put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1105
1106 #ifdef DHD_DEBUG
1107         tx_packets[pkt->priority]++;
1108         if (DHD_BYTES_ON() &&
1109             (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
1110               (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
1111                 printk(KERN_DEBUG "Tx Frame:\n");
1112                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
1113         } else if (DHD_HDRS_ON()) {
1114                 printk(KERN_DEBUG "TxHdr:\n");
1115                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1116                                      frame, min_t(u16, len, 16));
1117         }
1118 #endif
1119
1120         /* Raise len to next SDIO block to eliminate tail command */
1121         if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1122                 u16 pad = bus->blocksize - (len % bus->blocksize);
1123                 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1124 #ifdef NOTUSED
1125                         if (pad <= skb_tailroom(pkt))
1126 #endif                          /* NOTUSED */
1127                                 len += pad;
1128         } else if (len % DHD_SDALIGN) {
1129                 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1130         }
1131
1132         /* Some controllers have trouble with odd bytes -- round to even */
1133         if (forcealign && (len & (ALIGNMENT - 1))) {
1134 #ifdef NOTUSED
1135                 if (skb_tailroom(pkt))
1136 #endif
1137                         len = roundup(len, ALIGNMENT);
1138 #ifdef NOTUSED
1139                 else
1140                         DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1141                                    __func__, len));
1142 #endif
1143         }
1144
1145         do {
1146                 ret =
1147                     dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1148                                         F2SYNC, frame, len, pkt, NULL, NULL);
1149                 bus->f2txdata++;
1150                 ASSERT(ret != -BCME_PENDING);
1151
1152                 if (ret < 0) {
1153                         /* On failure, abort the command
1154                          and terminate the frame */
1155                         DHD_INFO(("%s: sdio error %d, abort command and "
1156                                 "terminate frame.\n", __func__, ret));
1157                         bus->tx_sderrs++;
1158
1159                         bcmsdh_abort(sdh, SDIO_FUNC_2);
1160                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1161                                          SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1162                                          NULL);
1163                         bus->f1regdata++;
1164
1165                         for (i = 0; i < 3; i++) {
1166                                 u8 hi, lo;
1167                                 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1168                                                      SBSDIO_FUNC1_WFRAMEBCHI,
1169                                                      NULL);
1170                                 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1171                                                      SBSDIO_FUNC1_WFRAMEBCLO,
1172                                                      NULL);
1173                                 bus->f1regdata += 2;
1174                                 if ((hi == 0) && (lo == 0))
1175                                         break;
1176                         }
1177
1178                 }
1179                 if (ret == 0)
1180                         bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1181
1182         } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1183
1184 done:
1185         /* restore pkt buffer pointer before calling tx complete routine */
1186         skb_pull(pkt, SDPCM_HDRLEN + pad);
1187         dhd_os_sdunlock(bus->dhd);
1188         dhd_txcomplete(bus->dhd, pkt, ret != 0);
1189         dhd_os_sdlock(bus->dhd);
1190
1191         if (free_pkt)
1192                 bcm_pkt_buf_free_skb(pkt);
1193
1194         return ret;
1195 }
1196
1197 int dhd_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
1198 {
1199         int ret = -EBADE;
1200         uint datalen, prec;
1201
1202         DHD_TRACE(("%s: Enter\n", __func__));
1203
1204         datalen = pkt->len;
1205
1206 #ifdef SDTEST
1207         /* Push the test header if doing loopback */
1208         if (bus->ext_loop) {
1209                 u8 *data;
1210                 skb_push(pkt, SDPCM_TEST_HDRLEN);
1211                 data = pkt->data;
1212                 *data++ = SDPCM_TEST_ECHOREQ;
1213                 *data++ = (u8) bus->loopid++;
1214                 *data++ = (datalen >> 0);
1215                 *data++ = (datalen >> 8);
1216                 datalen += SDPCM_TEST_HDRLEN;
1217         }
1218 #endif                          /* SDTEST */
1219
1220         /* Add space for the header */
1221         skb_push(pkt, SDPCM_HDRLEN);
1222         ASSERT(IS_ALIGNED((unsigned long)(pkt->data), 2));
1223
1224         prec = PRIO2PREC((pkt->priority & PRIOMASK));
1225
1226         /* Check for existing queue, current flow-control,
1227                          pending event, or pending clock */
1228         if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1229             || bus->dpc_sched || (!DATAOK(bus))
1230             || (bus->flowcontrol & NBITVAL(prec))
1231             || (bus->clkstate != CLK_AVAIL)) {
1232                 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1233                            pktq_len(&bus->txq)));
1234                 bus->fcqueued++;
1235
1236                 /* Priority based enq */
1237                 dhd_os_sdlock_txq(bus->dhd);
1238                 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1239                         skb_pull(pkt, SDPCM_HDRLEN);
1240                         dhd_txcomplete(bus->dhd, pkt, false);
1241                         bcm_pkt_buf_free_skb(pkt);
1242                         DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1243                         ret = -ENOSR;
1244                 } else {
1245                         ret = 0;
1246                 }
1247                 dhd_os_sdunlock_txq(bus->dhd);
1248
1249                 if (pktq_len(&bus->txq) >= TXHI)
1250                         dhd_txflowcontrol(bus->dhd, 0, ON);
1251
1252 #ifdef DHD_DEBUG
1253                 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1254                         qcount[prec] = pktq_plen(&bus->txq, prec);
1255 #endif
1256                 /* Schedule DPC if needed to send queued packet(s) */
1257                 if (dhd_deferred_tx && !bus->dpc_sched) {
1258                         bus->dpc_sched = true;
1259                         dhd_sched_dpc(bus->dhd);
1260                 }
1261         } else {
1262                 /* Lock: we're about to use shared data/code (and SDIO) */
1263                 dhd_os_sdlock(bus->dhd);
1264
1265                 /* Otherwise, send it now */
1266                 BUS_WAKE(bus);
1267                 /* Make sure back plane ht clk is on, no pending allowed */
1268                 dhdsdio_clkctl(bus, CLK_AVAIL, true);
1269
1270 #ifndef SDTEST
1271                 DHD_TRACE(("%s: calling txpkt\n", __func__));
1272                 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1273 #else
1274                 ret = dhdsdio_txpkt(bus, pkt,
1275                                     (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1276                                      SDPCM_DATA_CHANNEL), true);
1277 #endif
1278                 if (ret)
1279                         bus->dhd->tx_errors++;
1280                 else
1281                         bus->dhd->dstats.tx_bytes += datalen;
1282
1283                 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1284                         bus->activity = false;
1285                         dhdsdio_clkctl(bus, CLK_NONE, true);
1286                 }
1287
1288                 dhd_os_sdunlock(bus->dhd);
1289         }
1290
1291         return ret;
1292 }
1293
1294 static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1295 {
1296         struct sk_buff *pkt;
1297         u32 intstatus = 0;
1298         uint retries = 0;
1299         int ret = 0, prec_out;
1300         uint cnt = 0;
1301         uint datalen;
1302         u8 tx_prec_map;
1303
1304         dhd_pub_t *dhd = bus->dhd;
1305         sdpcmd_regs_t *regs = bus->regs;
1306
1307         DHD_TRACE(("%s: Enter\n", __func__));
1308
1309         tx_prec_map = ~bus->flowcontrol;
1310
1311         /* Send frames until the limit or some other event */
1312         for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1313                 dhd_os_sdlock_txq(bus->dhd);
1314                 pkt = bcm_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1315                 if (pkt == NULL) {
1316                         dhd_os_sdunlock_txq(bus->dhd);
1317                         break;
1318                 }
1319                 dhd_os_sdunlock_txq(bus->dhd);
1320                 datalen = pkt->len - SDPCM_HDRLEN;
1321
1322 #ifndef SDTEST
1323                 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1324 #else
1325                 ret = dhdsdio_txpkt(bus, pkt,
1326                                     (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1327                                      SDPCM_DATA_CHANNEL), true);
1328 #endif
1329                 if (ret)
1330                         bus->dhd->tx_errors++;
1331                 else
1332                         bus->dhd->dstats.tx_bytes += datalen;
1333
1334                 /* In poll mode, need to check for other events */
1335                 if (!bus->intr && cnt) {
1336                         /* Check device status, signal pending interrupt */
1337                         R_SDREG(intstatus, &regs->intstatus, retries);
1338                         bus->f2txdata++;
1339                         if (bcmsdh_regfail(bus->sdh))
1340                                 break;
1341                         if (intstatus & bus->hostintmask)
1342                                 bus->ipend = true;
1343                 }
1344         }
1345
1346         /* Deflow-control stack if needed */
1347         if (dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1348             dhd->txoff && (pktq_len(&bus->txq) < TXLOW))
1349                 dhd_txflowcontrol(dhd, 0, OFF);
1350
1351         return cnt;
1352 }
1353
1354 int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1355 {
1356         u8 *frame;
1357         u16 len;
1358         u32 swheader;
1359         uint retries = 0;
1360         bcmsdh_info_t *sdh = bus->sdh;
1361         u8 doff = 0;
1362         int ret = -1;
1363         int i;
1364
1365         DHD_TRACE(("%s: Enter\n", __func__));
1366
1367         if (bus->dhd->dongle_reset)
1368                 return -EIO;
1369
1370         /* Back the pointer to make a room for bus header */
1371         frame = msg - SDPCM_HDRLEN;
1372         len = (msglen += SDPCM_HDRLEN);
1373
1374         /* Add alignment padding (optional for ctl frames) */
1375         if (dhd_alignctl) {
1376                 doff = ((unsigned long)frame % DHD_SDALIGN);
1377                 if (doff) {
1378                         frame -= doff;
1379                         len += doff;
1380                         msglen += doff;
1381                         memset(frame, 0, doff + SDPCM_HDRLEN);
1382                 }
1383                 ASSERT(doff < DHD_SDALIGN);
1384         }
1385         doff += SDPCM_HDRLEN;
1386
1387         /* Round send length to next SDIO block */
1388         if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1389                 u16 pad = bus->blocksize - (len % bus->blocksize);
1390                 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1391                         len += pad;
1392         } else if (len % DHD_SDALIGN) {
1393                 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1394         }
1395
1396         /* Satisfy length-alignment requirements */
1397         if (forcealign && (len & (ALIGNMENT - 1)))
1398                 len = roundup(len, ALIGNMENT);
1399
1400         ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1401
1402         /* Need to lock here to protect txseq and SDIO tx calls */
1403         dhd_os_sdlock(bus->dhd);
1404
1405         BUS_WAKE(bus);
1406
1407         /* Make sure backplane clock is on */
1408         dhdsdio_clkctl(bus, CLK_AVAIL, false);
1409
1410         /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1411         *(u16 *) frame = cpu_to_le16((u16) msglen);
1412         *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1413
1414         /* Software tag: channel, sequence number, data offset */
1415         swheader =
1416             ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1417              SDPCM_CHANNEL_MASK)
1418             | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1419                              SDPCM_DOFFSET_MASK);
1420         put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1421         put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1422
1423         if (!DATAOK(bus)) {
1424                 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1425                           __func__, bus->tx_max, bus->tx_seq));
1426                 bus->ctrl_frame_stat = true;
1427                 /* Send from dpc */
1428                 bus->ctrl_frame_buf = frame;
1429                 bus->ctrl_frame_len = len;
1430
1431                 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1432
1433                 if (bus->ctrl_frame_stat == false) {
1434                         DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1435                         ret = 0;
1436                 } else {
1437                         DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1438                         ret = -1;
1439                 }
1440         }
1441
1442         if (ret == -1) {
1443 #ifdef DHD_DEBUG
1444                 if (DHD_BYTES_ON() && DHD_CTL_ON()) {
1445                         printk(KERN_DEBUG "Tx Frame:\n");
1446                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1447                                              frame, len);
1448                 } else if (DHD_HDRS_ON()) {
1449                         printk(KERN_DEBUG "TxHdr:\n");
1450                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1451                                              frame, min_t(u16, len, 16));
1452                 }
1453 #endif
1454
1455                 do {
1456                         bus->ctrl_frame_stat = false;
1457                         ret =
1458                             dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1459                                                 SDIO_FUNC_2, F2SYNC, frame, len,
1460                                                 NULL, NULL, NULL);
1461
1462                         ASSERT(ret != -BCME_PENDING);
1463
1464                         if (ret < 0) {
1465                                 /* On failure, abort the command and
1466                                  terminate the frame */
1467                                 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1468                                         __func__, ret));
1469                                 bus->tx_sderrs++;
1470
1471                                 bcmsdh_abort(sdh, SDIO_FUNC_2);
1472
1473                                 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1474                                                  SBSDIO_FUNC1_FRAMECTRL,
1475                                                  SFC_WF_TERM, NULL);
1476                                 bus->f1regdata++;
1477
1478                                 for (i = 0; i < 3; i++) {
1479                                         u8 hi, lo;
1480                                         hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1481                                              SBSDIO_FUNC1_WFRAMEBCHI,
1482                                              NULL);
1483                                         lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1484                                              SBSDIO_FUNC1_WFRAMEBCLO,
1485                                                              NULL);
1486                                         bus->f1regdata += 2;
1487                                         if ((hi == 0) && (lo == 0))
1488                                                 break;
1489                                 }
1490
1491                         }
1492                         if (ret == 0) {
1493                                 bus->tx_seq =
1494                                     (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1495                         }
1496                 } while ((ret < 0) && retries++ < TXRETRIES);
1497         }
1498
1499         if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1500                 bus->activity = false;
1501                 dhdsdio_clkctl(bus, CLK_NONE, true);
1502         }
1503
1504         dhd_os_sdunlock(bus->dhd);
1505
1506         if (ret)
1507                 bus->dhd->tx_ctlerrs++;
1508         else
1509                 bus->dhd->tx_ctlpkts++;
1510
1511         return ret ? -EIO : 0;
1512 }
1513
1514 int dhd_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1515 {
1516         int timeleft;
1517         uint rxlen = 0;
1518         bool pending;
1519
1520         DHD_TRACE(("%s: Enter\n", __func__));
1521
1522         if (bus->dhd->dongle_reset)
1523                 return -EIO;
1524
1525         /* Wait until control frame is available */
1526         timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1527
1528         dhd_os_sdlock(bus->dhd);
1529         rxlen = bus->rxlen;
1530         memcpy(msg, bus->rxctl, min(msglen, rxlen));
1531         bus->rxlen = 0;
1532         dhd_os_sdunlock(bus->dhd);
1533
1534         if (rxlen) {
1535                 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1536                          __func__, rxlen, msglen));
1537         } else if (timeleft == 0) {
1538                 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1539 #ifdef DHD_DEBUG
1540                 dhd_os_sdlock(bus->dhd);
1541                 dhdsdio_checkdied(bus, NULL, 0);
1542                 dhd_os_sdunlock(bus->dhd);
1543 #endif                          /* DHD_DEBUG */
1544         } else if (pending == true) {
1545                 DHD_CTL(("%s: cancelled\n", __func__));
1546                 return -ERESTARTSYS;
1547         } else {
1548                 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1549 #ifdef DHD_DEBUG
1550                 dhd_os_sdlock(bus->dhd);
1551                 dhdsdio_checkdied(bus, NULL, 0);
1552                 dhd_os_sdunlock(bus->dhd);
1553 #endif                          /* DHD_DEBUG */
1554         }
1555
1556         if (rxlen)
1557                 bus->dhd->rx_ctlpkts++;
1558         else
1559                 bus->dhd->rx_ctlerrs++;
1560
1561         return rxlen ? (int)rxlen : -ETIMEDOUT;
1562 }
1563
1564 /* IOVar table */
1565 enum {
1566         IOV_INTR = 1,
1567         IOV_POLLRATE,
1568         IOV_SDREG,
1569         IOV_SBREG,
1570         IOV_SDCIS,
1571         IOV_MEMBYTES,
1572         IOV_MEMSIZE,
1573 #ifdef DHD_DEBUG
1574         IOV_CHECKDIED,
1575 #endif
1576         IOV_DOWNLOAD,
1577         IOV_FORCEEVEN,
1578         IOV_SDIOD_DRIVE,
1579         IOV_READAHEAD,
1580         IOV_SDRXCHAIN,
1581         IOV_ALIGNCTL,
1582         IOV_SDALIGN,
1583         IOV_DEVRESET,
1584         IOV_CPU,
1585 #ifdef SDTEST
1586         IOV_PKTGEN,
1587         IOV_EXTLOOP,
1588 #endif                          /* SDTEST */
1589         IOV_SPROM,
1590         IOV_TXBOUND,
1591         IOV_RXBOUND,
1592         IOV_TXMINMAX,
1593         IOV_IDLETIME,
1594         IOV_IDLECLOCK,
1595         IOV_SD1IDLE,
1596         IOV_SLEEP,
1597         IOV_VARS
1598 };
1599
1600 const bcm_iovar_t dhdsdio_iovars[] = {
1601         {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1602         {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1603         {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1604         {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1605         {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1606         {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1607         {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1608         {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1609         {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1610         {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1611         {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1612         {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1613         {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1614         {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1615         {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1616         {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1617 #ifdef DHD_DEBUG
1618         {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1619         ,
1620         {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1621         ,
1622         {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1623         ,
1624         {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1625         ,
1626         {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1627         ,
1628         {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1629         ,
1630         {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1631         ,
1632         {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1633         ,
1634 #ifdef DHD_DEBUG
1635         {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1636         ,
1637 #endif                          /* DHD_DEBUG  */
1638 #endif                          /* DHD_DEBUG */
1639 #ifdef SDTEST
1640         {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1641         ,
1642         {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1643         ,
1644 #endif                          /* SDTEST */
1645
1646         {NULL, 0, 0, 0, 0}
1647 };
1648
1649 static void
1650 dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
1651 {
1652         uint q1, q2;
1653
1654         if (!div) {
1655                 bcm_bprintf(strbuf, "%s N/A", desc);
1656         } else {
1657                 q1 = num / div;
1658                 q2 = (100 * (num - (q1 * div))) / div;
1659                 bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1660         }
1661 }
1662
1663 void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
1664 {
1665         dhd_bus_t *bus = dhdp->bus;
1666
1667         bcm_bprintf(strbuf, "Bus SDIO structure:\n");
1668         bcm_bprintf(strbuf,
1669                     "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1670                     bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1671         bcm_bprintf(strbuf,
1672                     "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1673                     bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1674                     bus->rxskip, bus->rxlen, bus->rx_seq);
1675         bcm_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1676                     bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1677         bcm_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1678                     bus->pollrate, bus->pollcnt, bus->regfails);
1679
1680         bcm_bprintf(strbuf, "\nAdditional counters:\n");
1681         bcm_bprintf(strbuf,
1682                     "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1683                     bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1684                     bus->rxc_errors);
1685         bcm_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1686                     bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1687         bcm_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n", bus->fc_rcvd,
1688                     bus->fc_xoff, bus->fc_xon);
1689         bcm_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1690                     bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1691         bcm_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs %d\n",
1692                     (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1693                     bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1694         {
1695                 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1696                              (bus->f2rxhdrs + bus->f2rxdata));
1697                 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1698                              bus->f1regdata);
1699                 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1700                              (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1701                 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1702                              bus->intrcount);
1703                 bcm_bprintf(strbuf, "\n");
1704
1705                 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1706                              bus->dhd->rx_packets);
1707                 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1708                              bus->rxglomframes);
1709                 bcm_bprintf(strbuf, "\n");
1710
1711                 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1712                              bus->f2txdata);
1713                 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1714                              bus->f1regdata);
1715                 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1716                              (bus->f2txdata + bus->f1regdata));
1717                 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1718                              bus->intrcount);
1719                 bcm_bprintf(strbuf, "\n");
1720
1721                 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1722                              (bus->dhd->tx_packets + bus->dhd->rx_packets),
1723                              (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1724                 dhd_dump_pct(strbuf, ", pkts/f1sd",
1725                              (bus->dhd->tx_packets + bus->dhd->rx_packets),
1726                              bus->f1regdata);
1727                 dhd_dump_pct(strbuf, ", pkts/sd",
1728                              (bus->dhd->tx_packets + bus->dhd->rx_packets),
1729                              (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1730                               bus->f1regdata));
1731                 dhd_dump_pct(strbuf, ", pkts/int",
1732                              (bus->dhd->tx_packets + bus->dhd->rx_packets),
1733                              bus->intrcount);
1734                 bcm_bprintf(strbuf, "\n\n");
1735         }
1736
1737 #ifdef SDTEST
1738         if (bus->pktgen_count) {
1739                 bcm_bprintf(strbuf, "pktgen config and count:\n");
1740                 bcm_bprintf(strbuf,
1741                             "freq %d count %d print %d total %d min %d len %d\n",
1742                             bus->pktgen_freq, bus->pktgen_count,
1743                             bus->pktgen_print, bus->pktgen_total,
1744                             bus->pktgen_minlen, bus->pktgen_maxlen);
1745                 bcm_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1746                             bus->pktgen_sent, bus->pktgen_rcvd,
1747                             bus->pktgen_fail);
1748         }
1749 #endif                          /* SDTEST */
1750 #ifdef DHD_DEBUG
1751         bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1752                     bus->dpc_sched,
1753                     (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1754         bcm_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1755                     bus->roundup);
1756 #endif                          /* DHD_DEBUG */
1757         bcm_bprintf(strbuf,
1758                     "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1759                     bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1760                     bus->sleeping);
1761 }
1762
1763 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1764 {
1765         dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1766
1767         bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1768         bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1769         bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1770         bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1771         bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1772         bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1773 }
1774
1775 #ifdef SDTEST
1776 static int dhdsdio_pktgen_get(dhd_bus_t *bus, u8 *arg)
1777 {
1778         dhd_pktgen_t pktgen;
1779
1780         pktgen.version = DHD_PKTGEN_VERSION;
1781         pktgen.freq = bus->pktgen_freq;
1782         pktgen.count = bus->pktgen_count;
1783         pktgen.print = bus->pktgen_print;
1784         pktgen.total = bus->pktgen_total;
1785         pktgen.minlen = bus->pktgen_minlen;
1786         pktgen.maxlen = bus->pktgen_maxlen;
1787         pktgen.numsent = bus->pktgen_sent;
1788         pktgen.numrcvd = bus->pktgen_rcvd;
1789         pktgen.numfail = bus->pktgen_fail;
1790         pktgen.mode = bus->pktgen_mode;
1791         pktgen.stop = bus->pktgen_stop;
1792
1793         memcpy(arg, &pktgen, sizeof(pktgen));
1794
1795         return 0;
1796 }
1797
1798 static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
1799 {
1800         dhd_pktgen_t pktgen;
1801         uint oldcnt, oldmode;
1802
1803         memcpy(&pktgen, arg, sizeof(pktgen));
1804         if (pktgen.version != DHD_PKTGEN_VERSION)
1805                 return -EINVAL;
1806
1807         oldcnt = bus->pktgen_count;
1808         oldmode = bus->pktgen_mode;
1809
1810         bus->pktgen_freq = pktgen.freq;
1811         bus->pktgen_count = pktgen.count;
1812         bus->pktgen_print = pktgen.print;
1813         bus->pktgen_total = pktgen.total;
1814         bus->pktgen_minlen = pktgen.minlen;
1815         bus->pktgen_maxlen = pktgen.maxlen;
1816         bus->pktgen_mode = pktgen.mode;
1817         bus->pktgen_stop = pktgen.stop;
1818
1819         bus->pktgen_tick = bus->pktgen_ptick = 0;
1820         bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1821         bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1822
1823         /* Clear counts for a new pktgen (mode change, or was stopped) */
1824         if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1825                 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1826
1827         return 0;
1828 }
1829 #endif                          /* SDTEST */
1830
1831 static int
1832 dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1833                  uint size)
1834 {
1835         int bcmerror = 0;
1836         u32 sdaddr;
1837         uint dsize;
1838
1839         /* Determine initial transfer parameters */
1840         sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1841         if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1842                 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1843         else
1844                 dsize = size;
1845
1846         /* Set the backplane window to include the start address */
1847         bcmerror = dhdsdio_set_siaddr_window(bus, address);
1848         if (bcmerror) {
1849                 DHD_ERROR(("%s: window change failed\n", __func__));
1850                 goto xfer_done;
1851         }
1852
1853         /* Do the transfer(s) */
1854         while (size) {
1855                 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1856                           __func__, (write ? "write" : "read"), dsize,
1857                           sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
1858                 bcmerror =
1859                      bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
1860                 if (bcmerror) {
1861                         DHD_ERROR(("%s: membytes transfer failed\n", __func__));
1862                         break;
1863                 }
1864
1865                 /* Adjust for next transfer (if any) */
1866                 size -= dsize;
1867                 if (size) {
1868                         data += dsize;
1869                         address += dsize;
1870                         bcmerror = dhdsdio_set_siaddr_window(bus, address);
1871                         if (bcmerror) {
1872                                 DHD_ERROR(("%s: window change failed\n",
1873                                            __func__));
1874                                 break;
1875                         }
1876                         sdaddr = 0;
1877                         dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
1878                 }
1879         }
1880
1881 xfer_done:
1882         /* Return the window to backplane enumeration space for core access */
1883         if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
1884                 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
1885                            __func__, bcmsdh_cur_sbwad(bus->sdh)));
1886         }
1887
1888         return bcmerror;
1889 }
1890
1891 #ifdef DHD_DEBUG
1892 static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
1893 {
1894         u32 addr;
1895         int rv;
1896
1897         /* Read last word in memory to determine address of
1898                          sdpcm_shared structure */
1899         rv = dhdsdio_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr, 4);
1900         if (rv < 0)
1901                 return rv;
1902
1903         addr = le32_to_cpu(addr);
1904
1905         DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
1906
1907         /*
1908          * Check if addr is valid.
1909          * NVRAM length at the end of memory should have been overwritten.
1910          */
1911         if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
1912                 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
1913                            __func__, addr));
1914                 return -EBADE;
1915         }
1916
1917         /* Read rte_shared structure */
1918         rv = dhdsdio_membytes(bus, false, addr, (u8 *) sh,
1919                               sizeof(sdpcm_shared_t));
1920         if (rv < 0)
1921                 return rv;
1922
1923         /* Endianness */
1924         sh->flags = le32_to_cpu(sh->flags);
1925         sh->trap_addr = le32_to_cpu(sh->trap_addr);
1926         sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
1927         sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
1928         sh->assert_line = le32_to_cpu(sh->assert_line);
1929         sh->console_addr = le32_to_cpu(sh->console_addr);
1930         sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
1931
1932         if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
1933                 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
1934                            "is different than sdpcm_shared version %d in dongle\n",
1935                            __func__, SDPCM_SHARED_VERSION,
1936                            sh->flags & SDPCM_SHARED_VERSION_MASK));
1937                 return -EBADE;
1938         }
1939
1940         return 0;
1941 }
1942
1943 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
1944 {
1945         int bcmerror = 0;
1946         uint msize = 512;
1947         char *mbuffer = NULL;
1948         uint maxstrlen = 256;
1949         char *str = NULL;
1950         trap_t tr;
1951         sdpcm_shared_t sdpcm_shared;
1952         struct bcmstrbuf strbuf;
1953
1954         DHD_TRACE(("%s: Enter\n", __func__));
1955
1956         if (data == NULL) {
1957                 /*
1958                  * Called after a rx ctrl timeout. "data" is NULL.
1959                  * allocate memory to trace the trap or assert.
1960                  */
1961                 size = msize;
1962                 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
1963                 if (mbuffer == NULL) {
1964                         DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
1965                                    msize));
1966                         bcmerror = -ENOMEM;
1967                         goto done;
1968                 }
1969         }
1970
1971         str = kmalloc(maxstrlen, GFP_ATOMIC);
1972         if (str == NULL) {
1973                 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
1974                 bcmerror = -ENOMEM;
1975                 goto done;
1976         }
1977
1978         bcmerror = dhdsdio_readshared(bus, &sdpcm_shared);
1979         if (bcmerror < 0)
1980                 goto done;
1981
1982         bcm_binit(&strbuf, data, size);
1983
1984         bcm_bprintf(&strbuf,
1985                     "msgtrace address : 0x%08X\nconsole address  : 0x%08X\n",
1986                     sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
1987
1988         if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
1989                 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1990                  * (Avoids conflict with real asserts for programmatic
1991                  * parsing of output.)
1992                  */
1993                 bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
1994         }
1995
1996         if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
1997             0) {
1998                 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1999                  * (Avoids conflict with real asserts for programmatic
2000                  * parsing of output.)
2001                  */
2002                 bcm_bprintf(&strbuf, "No trap%s in dongle",
2003                             (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
2004                             ? "/assrt" : "");
2005         } else {
2006                 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
2007                         /* Download assert */
2008                         bcm_bprintf(&strbuf, "Dongle assert");
2009                         if (sdpcm_shared.assert_exp_addr != 0) {
2010                                 str[0] = '\0';
2011                                 bcmerror = dhdsdio_membytes(bus, false,
2012                                                 sdpcm_shared.assert_exp_addr,
2013                                                 (u8 *) str, maxstrlen);
2014                                 if (bcmerror < 0)
2015                                         goto done;
2016
2017                                 str[maxstrlen - 1] = '\0';
2018                                 bcm_bprintf(&strbuf, " expr \"%s\"", str);
2019                         }
2020
2021                         if (sdpcm_shared.assert_file_addr != 0) {
2022                                 str[0] = '\0';
2023                                 bcmerror = dhdsdio_membytes(bus, false,
2024                                                 sdpcm_shared.assert_file_addr,
2025                                                 (u8 *) str, maxstrlen);
2026                                 if (bcmerror < 0)
2027                                         goto done;
2028
2029                                 str[maxstrlen - 1] = '\0';
2030                                 bcm_bprintf(&strbuf, " file \"%s\"", str);
2031                         }
2032
2033                         bcm_bprintf(&strbuf, " line %d ",
2034                                     sdpcm_shared.assert_line);
2035                 }
2036
2037                 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2038                         bcmerror = dhdsdio_membytes(bus, false,
2039                                         sdpcm_shared.trap_addr, (u8 *)&tr,
2040                                         sizeof(trap_t));
2041                         if (bcmerror < 0)
2042                                 goto done;
2043
2044                         bcm_bprintf(&strbuf,
2045                                     "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
2046                                     "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
2047                                     "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
2048                                     tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
2049                                     tr.r14, tr.pc, sdpcm_shared.trap_addr,
2050                                     tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
2051                                     tr.r6, tr.r7);
2052                 }
2053         }
2054
2055         if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
2056                 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
2057
2058 #ifdef DHD_DEBUG
2059         if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
2060                 /* Mem dump to a file on device */
2061                 dhdsdio_mem_dump(bus);
2062         }
2063 #endif                          /* DHD_DEBUG */
2064
2065 done:
2066         kfree(mbuffer);
2067         kfree(str);
2068
2069         return bcmerror;
2070 }
2071
2072 static int dhdsdio_mem_dump(dhd_bus_t *bus)
2073 {
2074         int ret = 0;
2075         int size;               /* Full mem size */
2076         int start = 0;          /* Start address */
2077         int read_size = 0;      /* Read size of each iteration */
2078         u8 *buf = NULL, *databuf = NULL;
2079
2080         /* Get full mem size */
2081         size = bus->ramsize;
2082         buf = kmalloc(size, GFP_ATOMIC);
2083         if (!buf) {
2084                 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
2085                 return -1;
2086         }
2087
2088         /* Read mem content */
2089         printk(KERN_DEBUG "Dump dongle memory");
2090         databuf = buf;
2091         while (size) {
2092                 read_size = min(MEMBLOCK, size);
2093                 ret = dhdsdio_membytes(bus, false, start, databuf, read_size);
2094                 if (ret) {
2095                         DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
2096                         kfree(buf);
2097                         return -1;
2098                 }
2099                 printk(".");
2100
2101                 /* Decrement size and increment start address */
2102                 size -= read_size;
2103                 start += read_size;
2104                 databuf += read_size;
2105         }
2106         printk(KERN_DEBUG "Done\n");
2107
2108         /* free buf before return !!! */
2109         if (write_to_file(bus->dhd, buf, bus->ramsize)) {
2110                 DHD_ERROR(("%s: Error writing to files\n", __func__));
2111                 return -1;
2112         }
2113
2114         /* buf free handled in write_to_file, not here */
2115         return 0;
2116 }
2117
2118 #define CONSOLE_LINE_MAX        192
2119
2120 static int dhdsdio_readconsole(dhd_bus_t *bus)
2121 {
2122         dhd_console_t *c = &bus->console;
2123         u8 line[CONSOLE_LINE_MAX], ch;
2124         u32 n, idx, addr;
2125         int rv;
2126
2127         /* Don't do anything until FWREADY updates console address */
2128         if (bus->console_addr == 0)
2129                 return 0;
2130
2131         /* Read console log struct */
2132         addr = bus->console_addr + offsetof(rte_cons_t, log);
2133         rv = dhdsdio_membytes(bus, false, addr, (u8 *)&c->log,
2134                                 sizeof(c->log));
2135         if (rv < 0)
2136                 return rv;
2137
2138         /* Allocate console buffer (one time only) */
2139         if (c->buf == NULL) {
2140                 c->bufsize = le32_to_cpu(c->log.buf_size);
2141                 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2142                 if (c->buf == NULL)
2143                         return -ENOMEM;
2144         }
2145
2146         idx = le32_to_cpu(c->log.idx);
2147
2148         /* Protect against corrupt value */
2149         if (idx > c->bufsize)
2150                 return -EBADE;
2151
2152         /* Skip reading the console buffer if the index pointer
2153          has not moved */
2154         if (idx == c->last)
2155                 return 0;
2156
2157         /* Read the console buffer */
2158         addr = le32_to_cpu(c->log.buf);
2159         rv = dhdsdio_membytes(bus, false, addr, c->buf, c->bufsize);
2160         if (rv < 0)
2161                 return rv;
2162
2163         while (c->last != idx) {
2164                 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2165                         if (c->last == idx) {
2166                                 /* This would output a partial line.
2167                                  * Instead, back up
2168                                  * the buffer pointer and output this
2169                                  * line next time around.
2170                                  */
2171                                 if (c->last >= n)
2172                                         c->last -= n;
2173                                 else
2174                                         c->last = c->bufsize - n;
2175                                 goto break2;
2176                         }
2177                         ch = c->buf[c->last];
2178                         c->last = (c->last + 1) % c->bufsize;
2179                         if (ch == '\n')
2180                                 break;
2181                         line[n] = ch;
2182                 }
2183
2184                 if (n > 0) {
2185                         if (line[n - 1] == '\r')
2186                                 n--;
2187                         line[n] = 0;
2188                         printk(KERN_DEBUG "CONSOLE: %s\n", line);
2189                 }
2190         }
2191 break2:
2192
2193         return 0;
2194 }
2195 #endif                          /* DHD_DEBUG */
2196
2197 int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2198 {
2199         int bcmerror = 0;
2200
2201         DHD_TRACE(("%s: Enter\n", __func__));
2202
2203         /* Basic sanity checks */
2204         if (bus->dhd->up) {
2205                 bcmerror = -EISCONN;
2206                 goto err;
2207         }
2208         if (!len) {
2209                 bcmerror = -EOVERFLOW;
2210                 goto err;
2211         }
2212
2213         /* Free the old ones and replace with passed variables */
2214         kfree(bus->vars);
2215
2216         bus->vars = kmalloc(len, GFP_ATOMIC);
2217         bus->varsz = bus->vars ? len : 0;
2218         if (bus->vars == NULL) {
2219                 bcmerror = -ENOMEM;
2220                 goto err;
2221         }
2222
2223         /* Copy the passed variables, which should include the
2224                  terminating double-null */
2225         memcpy(bus->vars, arg, bus->varsz);
2226 err:
2227         return bcmerror;
2228 }
2229
2230 static int
2231 dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, u32 actionid,
2232                 const char *name, void *params, int plen, void *arg, int len,
2233                 int val_size)
2234 {
2235         int bcmerror = 0;
2236         s32 int_val = 0;
2237         bool bool_val = 0;
2238
2239         DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2240                 "len %d val_size %d\n",
2241                 __func__, actionid, name, params, plen, arg, len, val_size));
2242
2243         bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2244         if (bcmerror != 0)
2245                 goto exit;
2246
2247         if (plen >= (int)sizeof(int_val))
2248                 memcpy(&int_val, params, sizeof(int_val));
2249
2250         bool_val = (int_val != 0) ? true : false;
2251
2252         /* Some ioctls use the bus */
2253         dhd_os_sdlock(bus->dhd);
2254
2255         /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2256         if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2257                                         actionid == IOV_GVAL(IOV_DEVRESET))) {
2258                 bcmerror = -EPERM;
2259                 goto exit;
2260         }
2261
2262         /* Handle sleep stuff before any clock mucking */
2263         if (vi->varid == IOV_SLEEP) {
2264                 if (IOV_ISSET(actionid)) {
2265                         bcmerror = dhdsdio_bussleep(bus, bool_val);
2266                 } else {
2267                         int_val = (s32) bus->sleeping;
2268                         memcpy(arg, &int_val, val_size);
2269                 }
2270                 goto exit;
2271         }
2272
2273         /* Request clock to allow SDIO accesses */
2274         if (!bus->dhd->dongle_reset) {
2275                 BUS_WAKE(bus);
2276                 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2277         }
2278
2279         switch (actionid) {
2280         case IOV_GVAL(IOV_INTR):
2281                 int_val = (s32) bus->intr;
2282                 memcpy(arg, &int_val, val_size);
2283                 break;
2284
2285         case IOV_SVAL(IOV_INTR):
2286                 bus->intr = bool_val;
2287                 bus->intdis = false;
2288                 if (bus->dhd->up) {
2289                         if (bus->intr) {
2290                                 DHD_INTR(("%s: enable SDIO device interrupts\n",
2291                                           __func__));
2292                                 bcmsdh_intr_enable(bus->sdh);
2293                         } else {
2294                                 DHD_INTR(("%s: disable SDIO interrupts\n",
2295                                           __func__));
2296                                 bcmsdh_intr_disable(bus->sdh);
2297                         }
2298                 }
2299                 break;
2300
2301         case IOV_GVAL(IOV_POLLRATE):
2302                 int_val = (s32) bus->pollrate;
2303                 memcpy(arg, &int_val, val_size);
2304                 break;
2305
2306         case IOV_SVAL(IOV_POLLRATE):
2307                 bus->pollrate = (uint) int_val;
2308                 bus->poll = (bus->pollrate != 0);
2309                 break;
2310
2311         case IOV_GVAL(IOV_IDLETIME):
2312                 int_val = bus->idletime;
2313                 memcpy(arg, &int_val, val_size);
2314                 break;
2315
2316         case IOV_SVAL(IOV_IDLETIME):
2317                 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2318                         bcmerror = -EINVAL;
2319                 else
2320                         bus->idletime = int_val;
2321                 break;
2322
2323         case IOV_GVAL(IOV_IDLECLOCK):
2324                 int_val = (s32) bus->idleclock;
2325                 memcpy(arg, &int_val, val_size);
2326                 break;
2327
2328         case IOV_SVAL(IOV_IDLECLOCK):
2329                 bus->idleclock = int_val;
2330                 break;
2331
2332         case IOV_GVAL(IOV_SD1IDLE):
2333                 int_val = (s32) sd1idle;
2334                 memcpy(arg, &int_val, val_size);
2335                 break;
2336
2337         case IOV_SVAL(IOV_SD1IDLE):
2338                 sd1idle = bool_val;
2339                 break;
2340
2341         case IOV_SVAL(IOV_MEMBYTES):
2342         case IOV_GVAL(IOV_MEMBYTES):
2343                 {
2344                         u32 address;
2345                         uint size, dsize;
2346                         u8 *data;
2347
2348                         bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2349
2350                         ASSERT(plen >= 2 * sizeof(int));
2351
2352                         address = (u32) int_val;
2353                         memcpy(&int_val, (char *)params + sizeof(int_val),
2354                                sizeof(int_val));
2355                         size = (uint) int_val;
2356
2357                         /* Do some validation */
2358                         dsize = set ? plen - (2 * sizeof(int)) : len;
2359                         if (dsize < size) {
2360                                 DHD_ERROR(("%s: error on %s membytes, addr "
2361                                 "0x%08x size %d dsize %d\n",
2362                                 __func__, (set ? "set" : "get"),
2363                                 address, size, dsize));
2364                                 bcmerror = -EINVAL;
2365                                 break;
2366                         }
2367
2368                         DHD_INFO(("%s: Request to %s %d bytes at address "
2369                         "0x%08x\n",
2370                         __func__, (set ? "write" : "read"), size, address));
2371
2372                         /* If we know about SOCRAM, check for a fit */
2373                         if ((bus->orig_ramsize) &&
2374                             ((address > bus->orig_ramsize)
2375                              || (address + size > bus->orig_ramsize))) {
2376                                 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2377                                 "bytes at 0x%08x\n",
2378                                 __func__, bus->orig_ramsize, size, address));
2379                                 bcmerror = -EINVAL;
2380                                 break;
2381                         }
2382
2383                         /* Generate the actual data pointer */
2384                         data =
2385                             set ? (u8 *) params +
2386                             2 * sizeof(int) : (u8 *) arg;
2387
2388                         /* Call to do the transfer */
2389                         bcmerror =
2390                             dhdsdio_membytes(bus, set, address, data, size);
2391
2392                         break;
2393                 }
2394
2395         case IOV_GVAL(IOV_MEMSIZE):
2396                 int_val = (s32) bus->ramsize;
2397                 memcpy(arg, &int_val, val_size);
2398                 break;
2399
2400         case IOV_GVAL(IOV_SDIOD_DRIVE):
2401                 int_val = (s32) dhd_sdiod_drive_strength;
2402                 memcpy(arg, &int_val, val_size);
2403                 break;
2404
2405         case IOV_SVAL(IOV_SDIOD_DRIVE):
2406                 dhd_sdiod_drive_strength = int_val;
2407                 dhdsdio_sdiod_drive_strength_init(bus,
2408                                              dhd_sdiod_drive_strength);
2409                 break;
2410
2411         case IOV_SVAL(IOV_DOWNLOAD):
2412                 bcmerror = dhdsdio_download_state(bus, bool_val);
2413                 break;
2414
2415         case IOV_SVAL(IOV_VARS):
2416                 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2417                 break;
2418
2419         case IOV_GVAL(IOV_READAHEAD):
2420                 int_val = (s32) dhd_readahead;
2421                 memcpy(arg, &int_val, val_size);
2422                 break;
2423
2424         case IOV_SVAL(IOV_READAHEAD):
2425                 if (bool_val && !dhd_readahead)
2426                         bus->nextlen = 0;
2427                 dhd_readahead = bool_val;
2428                 break;
2429
2430         case IOV_GVAL(IOV_SDRXCHAIN):
2431                 int_val = (s32) bus->use_rxchain;
2432                 memcpy(arg, &int_val, val_size);
2433                 break;
2434
2435         case IOV_SVAL(IOV_SDRXCHAIN):
2436                 if (bool_val && !bus->sd_rxchain)
2437                         bcmerror = -ENOTSUPP;
2438                 else
2439                         bus->use_rxchain = bool_val;
2440                 break;
2441         case IOV_GVAL(IOV_ALIGNCTL):
2442                 int_val = (s32) dhd_alignctl;
2443                 memcpy(arg, &int_val, val_size);
2444                 break;
2445
2446         case IOV_SVAL(IOV_ALIGNCTL):
2447                 dhd_alignctl = bool_val;
2448                 break;
2449
2450         case IOV_GVAL(IOV_SDALIGN):
2451                 int_val = DHD_SDALIGN;
2452                 memcpy(arg, &int_val, val_size);
2453                 break;
2454
2455 #ifdef DHD_DEBUG
2456         case IOV_GVAL(IOV_VARS):
2457                 if (bus->varsz < (uint) len)
2458                         memcpy(arg, bus->vars, bus->varsz);
2459                 else
2460                         bcmerror = -EOVERFLOW;
2461                 break;
2462 #endif                          /* DHD_DEBUG */
2463
2464 #ifdef DHD_DEBUG
2465         case IOV_GVAL(IOV_SDREG):
2466                 {
2467                         sdreg_t *sd_ptr;
2468                         u32 addr, size;
2469
2470                         sd_ptr = (sdreg_t *) params;
2471
2472                         addr = (unsigned long)bus->regs + sd_ptr->offset;
2473                         size = sd_ptr->func;
2474                         int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2475                         if (bcmsdh_regfail(bus->sdh))
2476                                 bcmerror = -EIO;
2477                         memcpy(arg, &int_val, sizeof(s32));
2478                         break;
2479                 }
2480
2481         case IOV_SVAL(IOV_SDREG):
2482                 {
2483                         sdreg_t *sd_ptr;
2484                         u32 addr, size;
2485
2486                         sd_ptr = (sdreg_t *) params;
2487
2488                         addr = (unsigned long)bus->regs + sd_ptr->offset;
2489                         size = sd_ptr->func;
2490                         bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2491                         if (bcmsdh_regfail(bus->sdh))
2492                                 bcmerror = -EIO;
2493                         break;
2494                 }
2495
2496                 /* Same as above, but offset is not backplane
2497                  (not SDIO core) */
2498         case IOV_GVAL(IOV_SBREG):
2499                 {
2500                         sdreg_t sdreg;
2501                         u32 addr, size;
2502
2503                         memcpy(&sdreg, params, sizeof(sdreg));
2504
2505                         addr = SI_ENUM_BASE + sdreg.offset;
2506                         size = sdreg.func;
2507                         int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2508                         if (bcmsdh_regfail(bus->sdh))
2509                                 bcmerror = -EIO;
2510                         memcpy(arg, &int_val, sizeof(s32));
2511                         break;
2512                 }
2513
2514         case IOV_SVAL(IOV_SBREG):
2515                 {
2516                         sdreg_t sdreg;
2517                         u32 addr, size;
2518
2519                         memcpy(&sdreg, params, sizeof(sdreg));
2520
2521                         addr = SI_ENUM_BASE + sdreg.offset;
2522                         size = sdreg.func;
2523                         bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2524                         if (bcmsdh_regfail(bus->sdh))
2525                                 bcmerror = -EIO;
2526                         break;
2527                 }
2528
2529         case IOV_GVAL(IOV_SDCIS):
2530                 {
2531                         *(char *)arg = 0;
2532
2533                         strcat(arg, "\nFunc 0\n");
2534                         bcmsdh_cis_read(bus->sdh, 0x10,
2535                                         (u8 *) arg + strlen(arg),
2536                                         SBSDIO_CIS_SIZE_LIMIT);
2537                         strcat(arg, "\nFunc 1\n");
2538                         bcmsdh_cis_read(bus->sdh, 0x11,
2539                                         (u8 *) arg + strlen(arg),
2540                                         SBSDIO_CIS_SIZE_LIMIT);
2541                         strcat(arg, "\nFunc 2\n");
2542                         bcmsdh_cis_read(bus->sdh, 0x12,
2543                                         (u8 *) arg + strlen(arg),
2544                                         SBSDIO_CIS_SIZE_LIMIT);
2545                         break;
2546                 }
2547
2548         case IOV_GVAL(IOV_FORCEEVEN):
2549                 int_val = (s32) forcealign;
2550                 memcpy(arg, &int_val, val_size);
2551                 break;
2552
2553         case IOV_SVAL(IOV_FORCEEVEN):
2554                 forcealign = bool_val;
2555                 break;
2556
2557         case IOV_GVAL(IOV_TXBOUND):
2558                 int_val = (s32) dhd_txbound;
2559                 memcpy(arg, &int_val, val_size);
2560                 break;
2561
2562         case IOV_SVAL(IOV_TXBOUND):
2563                 dhd_txbound = (uint) int_val;
2564                 break;
2565
2566         case IOV_GVAL(IOV_RXBOUND):
2567                 int_val = (s32) dhd_rxbound;
2568                 memcpy(arg, &int_val, val_size);
2569                 break;
2570
2571         case IOV_SVAL(IOV_RXBOUND):
2572                 dhd_rxbound = (uint) int_val;
2573                 break;
2574
2575         case IOV_GVAL(IOV_TXMINMAX):
2576                 int_val = (s32) dhd_txminmax;
2577                 memcpy(arg, &int_val, val_size);
2578                 break;
2579
2580         case IOV_SVAL(IOV_TXMINMAX):
2581                 dhd_txminmax = (uint) int_val;
2582                 break;
2583 #endif                          /* DHD_DEBUG */
2584
2585 #ifdef SDTEST
2586         case IOV_GVAL(IOV_EXTLOOP):
2587                 int_val = (s32) bus->ext_loop;
2588                 memcpy(arg, &int_val, val_size);
2589                 break;
2590
2591         case IOV_SVAL(IOV_EXTLOOP):
2592                 bus->ext_loop = bool_val;
2593                 break;
2594
2595         case IOV_GVAL(IOV_PKTGEN):
2596                 bcmerror = dhdsdio_pktgen_get(bus, arg);
2597                 break;
2598
2599         case IOV_SVAL(IOV_PKTGEN):
2600                 bcmerror = dhdsdio_pktgen_set(bus, arg);
2601                 break;
2602 #endif                          /* SDTEST */
2603
2604         case IOV_SVAL(IOV_DEVRESET):
2605                 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2606                         "busstate=%d\n",
2607                         __func__, bool_val, bus->dhd->dongle_reset,
2608                         bus->dhd->busstate));
2609
2610                 dhd_bus_devreset(bus->dhd, (u8) bool_val);
2611
2612                 break;
2613
2614         case IOV_GVAL(IOV_DEVRESET):
2615                 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2616
2617                 /* Get its status */
2618                 int_val = (bool) bus->dhd->dongle_reset;
2619                 memcpy(arg, &int_val, val_size);
2620
2621                 break;
2622
2623         default:
2624                 bcmerror = -ENOTSUPP;
2625                 break;
2626         }
2627
2628 exit:
2629         if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2630                 bus->activity = false;
2631                 dhdsdio_clkctl(bus, CLK_NONE, true);
2632         }
2633
2634         dhd_os_sdunlock(bus->dhd);
2635
2636         if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2637                 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2638
2639         return bcmerror;
2640 }
2641
2642 static int dhdsdio_write_vars(dhd_bus_t *bus)
2643 {
2644         int bcmerror = 0;
2645         u32 varsize;
2646         u32 varaddr;
2647         u8 *vbuffer;
2648         u32 varsizew;
2649 #ifdef DHD_DEBUG
2650         char *nvram_ularray;
2651 #endif                          /* DHD_DEBUG */
2652
2653         /* Even if there are no vars are to be written, we still
2654                  need to set the ramsize. */
2655         varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2656         varaddr = (bus->ramsize - 4) - varsize;
2657
2658         if (bus->vars) {
2659                 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2660                 if (!vbuffer)
2661                         return -ENOMEM;
2662
2663                 memcpy(vbuffer, bus->vars, bus->varsz);
2664
2665                 /* Write the vars list */
2666                 bcmerror =
2667                     dhdsdio_membytes(bus, true, varaddr, vbuffer, varsize);
2668 #ifdef DHD_DEBUG
2669                 /* Verify NVRAM bytes */
2670                 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2671                 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2672                 if (!nvram_ularray)
2673                         return -ENOMEM;
2674
2675                 /* Upload image to verify downloaded contents. */
2676                 memset(nvram_ularray, 0xaa, varsize);
2677
2678                 /* Read the vars list to temp buffer for comparison */
2679                 bcmerror =
2680                     dhdsdio_membytes(bus, false, varaddr, nvram_ularray,
2681                                      varsize);
2682                 if (bcmerror) {
2683                         DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2684                         "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2685                 }
2686                 /* Compare the org NVRAM with the one read from RAM */
2687                 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2688                         DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2689                                    __func__));
2690                 } else
2691                         DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2692                                 __func__));
2693
2694                 kfree(nvram_ularray);
2695 #endif                          /* DHD_DEBUG */
2696
2697                 kfree(vbuffer);
2698         }
2699
2700         /* adjust to the user specified RAM */
2701         DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2702                   bus->orig_ramsize, bus->ramsize));
2703         DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2704         varsize = ((bus->orig_ramsize - 4) - varaddr);
2705
2706         /*
2707          * Determine the length token:
2708          * Varsize, converted to words, in lower 16-bits, checksum
2709          * in upper 16-bits.
2710          */
2711         if (bcmerror) {
2712                 varsizew = 0;
2713         } else {
2714                 varsizew = varsize / 4;
2715                 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2716                 varsizew = cpu_to_le32(varsizew);
2717         }
2718
2719         DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2720                   varsizew));
2721
2722         /* Write the length token to the last word */
2723         bcmerror = dhdsdio_membytes(bus, true, (bus->orig_ramsize - 4),
2724                                     (u8 *)&varsizew, 4);
2725
2726         return bcmerror;
2727 }
2728
2729 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2730 {
2731         uint retries;
2732         u32 regdata;
2733         int bcmerror = 0;
2734
2735         /* To enter download state, disable ARM and reset SOCRAM.
2736          * To exit download state, simply reset ARM (default is RAM boot).
2737          */
2738         if (enter) {
2739                 bus->alp_only = true;
2740
2741                 dhdsdio_chip_disablecore(bus->sdh, bus->ci->armcorebase);
2742
2743                 dhdsdio_chip_resetcore(bus->sdh, bus->ci->ramcorebase);
2744
2745                 /* Clear the top bit of memory */
2746                 if (bus->ramsize) {
2747                         u32 zeros = 0;
2748                         dhdsdio_membytes(bus, true, bus->ramsize - 4,
2749                                          (u8 *)&zeros, 4);
2750                 }
2751         } else {
2752                 regdata = bcmsdh_reg_read(bus->sdh,
2753                         CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
2754                 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
2755                         (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
2756                 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
2757                         DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2758                                    __func__));
2759                         bcmerror = -EBADE;
2760                         goto fail;
2761                 }
2762
2763                 bcmerror = dhdsdio_write_vars(bus);
2764                 if (bcmerror) {
2765                         DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2766                         bcmerror = 0;
2767                 }
2768
2769                 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2770
2771                 dhdsdio_chip_resetcore(bus->sdh, bus->ci->armcorebase);
2772
2773                 /* Allow HT Clock now that the ARM is running. */
2774                 bus->alp_only = false;
2775
2776                 bus->dhd->busstate = DHD_BUS_LOAD;
2777         }
2778 fail:
2779         return bcmerror;
2780 }
2781
2782 int
2783 dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2784                  void *params, int plen, void *arg, int len, bool set)
2785 {
2786         dhd_bus_t *bus = dhdp->bus;
2787         const bcm_iovar_t *vi = NULL;
2788         int bcmerror = 0;
2789         int val_size;
2790         u32 actionid;
2791
2792         DHD_TRACE(("%s: Enter\n", __func__));
2793
2794         ASSERT(name);
2795         ASSERT(len >= 0);
2796
2797         /* Get MUST have return space */
2798         ASSERT(set || (arg && len));
2799
2800         /* Set does NOT take qualifiers */
2801         ASSERT(!set || (!params && !plen));
2802
2803         /* Look up var locally; if not found pass to host driver */
2804         vi = bcm_iovar_lookup(dhdsdio_iovars, name);
2805         if (vi == NULL) {
2806                 dhd_os_sdlock(bus->dhd);
2807
2808                 BUS_WAKE(bus);
2809
2810                 /* Turn on clock in case SD command needs backplane */
2811                 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2812
2813                 bcmerror =
2814                     bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2815                                     set);
2816
2817                 /* Similar check for blocksize change */
2818                 if (set && strcmp(name, "sd_blocksize") == 0) {
2819                         s32 fnum = 2;
2820                         if (bcmsdh_iovar_op
2821                             (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2822                              &bus->blocksize, sizeof(s32),
2823                              false) != 0) {
2824                                 bus->blocksize = 0;
2825                                 DHD_ERROR(("%s: fail on %s get\n", __func__,
2826                                            "sd_blocksize"));
2827                         } else {
2828                                 DHD_INFO(("%s: noted %s update, value now %d\n",
2829                                           __func__, "sd_blocksize",
2830                                           bus->blocksize));
2831                         }
2832                 }
2833                 bus->roundup = min(max_roundup, bus->blocksize);
2834
2835                 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2836                         bus->activity = false;
2837                         dhdsdio_clkctl(bus, CLK_NONE, true);
2838                 }
2839
2840                 dhd_os_sdunlock(bus->dhd);
2841                 goto exit;
2842         }
2843
2844         DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2845                  name, (set ? "set" : "get"), len, plen));
2846
2847         /* set up 'params' pointer in case this is a set command so that
2848          * the convenience int and bool code can be common to set and get
2849          */
2850         if (params == NULL) {
2851                 params = arg;
2852                 plen = len;
2853         }
2854
2855         if (vi->type == IOVT_VOID)
2856                 val_size = 0;
2857         else if (vi->type == IOVT_BUFFER)
2858                 val_size = len;
2859         else
2860                 /* all other types are integer sized */
2861                 val_size = sizeof(int);
2862
2863         actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
2864         bcmerror =
2865             dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
2866                             val_size);
2867
2868 exit:
2869         return bcmerror;
2870 }
2871
2872 void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2873 {
2874         u32 local_hostintmask;
2875         u8 saveclk;
2876         uint retries;
2877         int err;
2878
2879         DHD_TRACE(("%s: Enter\n", __func__));
2880
2881         if (enforce_mutex)
2882                 dhd_os_sdlock(bus->dhd);
2883
2884         BUS_WAKE(bus);
2885
2886         /* Enable clock for device interrupts */
2887         dhdsdio_clkctl(bus, CLK_AVAIL, false);
2888
2889         /* Disable and clear interrupts at the chip level also */
2890         W_SDREG(0, &bus->regs->hostintmask, retries);
2891         local_hostintmask = bus->hostintmask;
2892         bus->hostintmask = 0;
2893
2894         /* Change our idea of bus state */
2895         bus->dhd->busstate = DHD_BUS_DOWN;
2896
2897         /* Force clocks on backplane to be sure F2 interrupt propagates */
2898         saveclk =
2899             bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2900                             &err);
2901         if (!err) {
2902                 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2903                                  (saveclk | SBSDIO_FORCE_HT), &err);
2904         }
2905         if (err) {
2906                 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2907                            __func__, err));
2908         }
2909
2910         /* Turn off the bus (F2), free any pending packets */
2911         DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2912         bcmsdh_intr_disable(bus->sdh);
2913         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
2914                          SDIO_FUNC_ENABLE_1, NULL);
2915
2916         /* Clear any pending interrupts now that F2 is disabled */
2917         W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
2918
2919         /* Turn off the backplane clock (only) */
2920         dhdsdio_clkctl(bus, CLK_SDONLY, false);
2921
2922         /* Clear the data packet queues */
2923         bcm_pktq_flush(&bus->txq, true, NULL, NULL);
2924
2925         /* Clear any held glomming stuff */
2926         if (bus->glomd)
2927                 bcm_pkt_buf_free_skb(bus->glomd);
2928
2929         if (bus->glom)
2930                 bcm_pkt_buf_free_skb(bus->glom);
2931
2932         bus->glom = bus->glomd = NULL;
2933
2934         /* Clear rx control and wake any waiters */
2935         bus->rxlen = 0;
2936         dhd_os_ioctl_resp_wake(bus->dhd);
2937
2938         /* Reset some F2 state stuff */
2939         bus->rxskip = false;
2940         bus->tx_seq = bus->rx_seq = 0;
2941
2942         if (enforce_mutex)
2943                 dhd_os_sdunlock(bus->dhd);
2944 }
2945
2946 int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
2947 {
2948         dhd_bus_t *bus = dhdp->bus;
2949         dhd_timeout_t tmo;
2950         uint retries = 0;
2951         u8 ready, enable;
2952         int err, ret = 0;
2953         u8 saveclk;
2954
2955         DHD_TRACE(("%s: Enter\n", __func__));
2956
2957         ASSERT(bus->dhd);
2958         if (!bus->dhd)
2959                 return 0;
2960
2961         if (enforce_mutex)
2962                 dhd_os_sdlock(bus->dhd);
2963
2964         /* Make sure backplane clock is on, needed to generate F2 interrupt */
2965         dhdsdio_clkctl(bus, CLK_AVAIL, false);
2966         if (bus->clkstate != CLK_AVAIL)
2967                 goto exit;
2968
2969         /* Force clocks on backplane to be sure F2 interrupt propagates */
2970         saveclk =
2971             bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2972                             &err);
2973         if (!err) {
2974                 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2975                                  (saveclk | SBSDIO_FORCE_HT), &err);
2976         }
2977         if (err) {
2978                 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2979                            __func__, err));
2980                 goto exit;
2981         }
2982
2983         /* Enable function 2 (frame transfers) */
2984         W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
2985                 &bus->regs->tosbmailboxdata, retries);
2986         enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
2987
2988         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
2989
2990         /* Give the dongle some time to do its thing and set IOR2 */
2991         dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
2992
2993         ready = 0;
2994         while (ready != enable && !dhd_timeout_expired(&tmo))
2995                 ready =
2996                     bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY,
2997                                     NULL);
2998
2999         DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
3000                   __func__, enable, ready, tmo.elapsed));
3001
3002         /* If F2 successfully enabled, set core and enable interrupts */
3003         if (ready == enable) {
3004                 /* Set up the interrupt mask and enable interrupts */
3005                 bus->hostintmask = HOSTINTMASK;
3006                 W_SDREG(bus->hostintmask,
3007                         (unsigned int *)CORE_BUS_REG(bus->ci->buscorebase,
3008                         hostintmask), retries);
3009
3010                 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
3011                                  (u8) watermark, &err);
3012
3013                 /* Set bus state according to enable result */
3014                 dhdp->busstate = DHD_BUS_DATA;
3015
3016                 /* bcmsdh_intr_unmask(bus->sdh); */
3017
3018                 bus->intdis = false;
3019                 if (bus->intr) {
3020                         DHD_INTR(("%s: enable SDIO device interrupts\n",
3021                                   __func__));
3022                         bcmsdh_intr_enable(bus->sdh);
3023                 } else {
3024                         DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
3025                         bcmsdh_intr_disable(bus->sdh);
3026                 }
3027
3028         }
3029
3030         else {
3031                 /* Disable F2 again */
3032                 enable = SDIO_FUNC_ENABLE_1;
3033                 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable,
3034                                  NULL);
3035         }
3036
3037         /* Restore previous clock setting */
3038         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
3039                          saveclk, &err);
3040
3041         /* If we didn't come up, turn off backplane clock */
3042         if (dhdp->busstate != DHD_BUS_DATA)
3043                 dhdsdio_clkctl(bus, CLK_NONE, false);
3044
3045 exit:
3046         if (enforce_mutex)
3047                 dhd_os_sdunlock(bus->dhd);
3048
3049         return ret;
3050 }
3051
3052 static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3053 {
3054         bcmsdh_info_t *sdh = bus->sdh;
3055         sdpcmd_regs_t *regs = bus->regs;
3056         uint retries = 0;
3057         u16 lastrbc;
3058         u8 hi, lo;
3059         int err;
3060
3061         DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3062                    (abort ? "abort command, " : ""),
3063                    (rtx ? ", send NAK" : "")));
3064
3065         if (abort)
3066                 bcmsdh_abort(sdh, SDIO_FUNC_2);
3067
3068         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3069                          &err);
3070         bus->f1regdata++;
3071
3072         /* Wait until the packet has been flushed (device/FIFO stable) */
3073         for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3074                 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3075                                      NULL);
3076                 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3077                                      NULL);
3078                 bus->f1regdata += 2;
3079
3080                 if ((hi == 0) && (lo == 0))
3081                         break;
3082
3083                 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3084                         DHD_ERROR(("%s: count growing: last 0x%04x now "
3085                                 "0x%04x\n",
3086                                 __func__, lastrbc, ((hi << 8) + lo)));
3087                 }
3088                 lastrbc = (hi << 8) + lo;
3089         }
3090
3091         if (!retries) {
3092                 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3093                            __func__, lastrbc));
3094         } else {
3095                 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3096                           (0xffff - retries)));
3097         }
3098
3099         if (rtx) {
3100                 bus->rxrtx++;
3101                 W_SDREG(SMB_NAK, &regs->tosbmailbox, retries);
3102                 bus->f1regdata++;
3103                 if (retries <= retry_limit)
3104                         bus->rxskip = true;
3105         }
3106
3107         /* Clear partial in any case */
3108         bus->nextlen = 0;
3109
3110         /* If we can't reach the device, signal failure */
3111         if (err || bcmsdh_regfail(sdh))
3112                 bus->dhd->busstate = DHD_BUS_DOWN;
3113 }
3114
3115 static void
3116 dhdsdio_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3117 {
3118         bcmsdh_info_t *sdh = bus->sdh;
3119         uint rdlen, pad;
3120
3121         int sdret;
3122
3123         DHD_TRACE(("%s: Enter\n", __func__));
3124
3125         /* Control data already received in aligned rxctl */
3126         if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3127                 goto gotpkt;
3128
3129         ASSERT(bus->rxbuf);
3130         /* Set rxctl for frame (w/optional alignment) */
3131         bus->rxctl = bus->rxbuf;
3132         if (dhd_alignctl) {
3133                 bus->rxctl += firstread;
3134                 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3135                 if (pad)
3136                         bus->rxctl += (DHD_SDALIGN - pad);
3137                 bus->rxctl -= firstread;
3138         }
3139         ASSERT(bus->rxctl >= bus->rxbuf);
3140
3141         /* Copy the already-read portion over */
3142         memcpy(bus->rxctl, hdr, firstread);
3143         if (len <= firstread)
3144                 goto gotpkt;
3145
3146         /* Copy the full data pkt in gSPI case and process ioctl. */
3147         if (bus->bus == SPI_BUS) {
3148                 memcpy(bus->rxctl, hdr, len);
3149                 goto gotpkt;
3150         }
3151
3152         /* Raise rdlen to next SDIO block to avoid tail command */
3153         rdlen = len - firstread;
3154         if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3155                 pad = bus->blocksize - (rdlen % bus->blocksize);
3156                 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3157                     ((len + pad) < bus->dhd->maxctl))
3158                         rdlen += pad;
3159         } else if (rdlen % DHD_SDALIGN) {
3160                 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3161         }
3162
3163         /* Satisfy length-alignment requirements */
3164         if (forcealign && (rdlen & (ALIGNMENT - 1)))
3165                 rdlen = roundup(rdlen, ALIGNMENT);
3166
3167         /* Drop if the read is too big or it exceeds our maximum */
3168         if ((rdlen + firstread) > bus->dhd->maxctl) {
3169                 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3170                            __func__, rdlen, bus->dhd->maxctl));
3171                 bus->dhd->rx_errors++;
3172                 dhdsdio_rxfail(bus, false, false);
3173                 goto done;
3174         }
3175
3176         if ((len - doff) > bus->dhd->maxctl) {
3177                 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3178                         "%d-byte limit\n",
3179                         __func__, len, (len - doff), bus->dhd->maxctl));
3180                 bus->dhd->rx_errors++;
3181                 bus->rx_toolong++;
3182                 dhdsdio_rxfail(bus, false, false);
3183                 goto done;
3184         }
3185
3186         /* Read remainder of frame body into the rxctl buffer */
3187         sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3188                                 F2SYNC, (bus->rxctl + firstread), rdlen,
3189                                 NULL, NULL, NULL);
3190         bus->f2rxdata++;
3191         ASSERT(sdret != -BCME_PENDING);
3192
3193         /* Control frame failures need retransmission */
3194         if (sdret < 0) {
3195                 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3196                            __func__, rdlen, sdret));
3197                 bus->rxc_errors++;      /* dhd.rx_ctlerrs is higher level */
3198                 dhdsdio_rxfail(bus, true, true);
3199                 goto done;
3200         }
3201
3202 gotpkt:
3203
3204 #ifdef DHD_DEBUG
3205         if (DHD_BYTES_ON() && DHD_CTL_ON()) {
3206                 printk(KERN_DEBUG "RxCtrl:\n");
3207                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
3208         }
3209 #endif
3210
3211         /* Point to valid data and indicate its length */
3212         bus->rxctl += doff;
3213         bus->rxlen = len - doff;
3214
3215 done:
3216         /* Awake any waiters */
3217         dhd_os_ioctl_resp_wake(bus->dhd);
3218 }
3219
3220 static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq)
3221 {
3222         u16 dlen, totlen;
3223         u8 *dptr, num = 0;
3224
3225         u16 sublen, check;
3226         struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3227
3228         int errcode;
3229         u8 chan, seq, doff, sfdoff;
3230         u8 txmax;
3231
3232         int ifidx = 0;
3233         bool usechain = bus->use_rxchain;
3234
3235         /* If packets, issue read(s) and send up packet chain */
3236         /* Return sequence numbers consumed? */
3237
3238         DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3239                    bus->glom));
3240
3241         /* If there's a descriptor, generate the packet chain */
3242         if (bus->glomd) {
3243                 dhd_os_sdlock_rxq(bus->dhd);
3244
3245                 pfirst = plast = pnext = NULL;
3246                 dlen = (u16) (bus->glomd->len);
3247                 dptr = bus->glomd->data;
3248                 if (!dlen || (dlen & 1)) {
3249                         DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3250                         __func__, dlen));
3251                         dlen = 0;
3252                 }
3253
3254                 for (totlen = num = 0; dlen; num++) {
3255                         /* Get (and move past) next length */
3256                         sublen = get_unaligned_le16(dptr);
3257                         dlen -= sizeof(u16);
3258                         dptr += sizeof(u16);
3259                         if ((sublen < SDPCM_HDRLEN) ||
3260                             ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3261                                 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3262                                            __func__, num, sublen));
3263                                 pnext = NULL;
3264                                 break;
3265                         }
3266                         if (sublen % DHD_SDALIGN) {
3267                                 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3268                                 __func__, sublen, DHD_SDALIGN));
3269                                 usechain = false;
3270                         }
3271                         totlen += sublen;
3272
3273                         /* For last frame, adjust read len so total
3274                                  is a block multiple */
3275                         if (!dlen) {
3276                                 sublen +=
3277                                     (roundup(totlen, bus->blocksize) - totlen);
3278                                 totlen = roundup(totlen, bus->blocksize);
3279                         }
3280
3281                         /* Allocate/chain packet for next subframe */
3282                         pnext = bcm_pkt_buf_get_skb(sublen + DHD_SDALIGN);
3283                         if (pnext == NULL) {
3284                                 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed, "
3285                                         "num %d len %d\n", __func__,
3286                                         num, sublen));
3287                                 break;
3288                         }
3289                         ASSERT(!(pnext->prev));
3290                         if (!pfirst) {
3291                                 ASSERT(!plast);
3292                                 pfirst = plast = pnext;
3293                         } else {
3294                                 ASSERT(plast);
3295                                 plast->next = pnext;
3296                                 plast = pnext;
3297                         }
3298
3299                         /* Adhere to start alignment requirements */
3300                         PKTALIGN(pnext, sublen, DHD_SDALIGN);
3301                 }
3302
3303                 /* If all allocations succeeded, save packet chain
3304                          in bus structure */
3305                 if (pnext) {
3306                         DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3307                                 "subframes\n", __func__, totlen, num));
3308                         if (DHD_GLOM_ON() && bus->nextlen) {
3309                                 if (totlen != bus->nextlen) {
3310                                         DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3311                                                 __func__, bus->nextlen,
3312                                                 totlen, rxseq));
3313                                 }
3314                         }
3315                         bus->glom = pfirst;
3316                         pfirst = pnext = NULL;
3317                 } else {
3318                         if (pfirst)
3319                                 bcm_pkt_buf_free_skb(pfirst);
3320                         bus->glom = NULL;
3321                         num = 0;
3322                 }
3323
3324                 /* Done with descriptor packet */
3325                 bcm_pkt_buf_free_skb(bus->glomd);
3326                 bus->glomd = NULL;
3327                 bus->nextlen = 0;
3328
3329                 dhd_os_sdunlock_rxq(bus->dhd);
3330         }
3331
3332         /* Ok -- either we just generated a packet chain,
3333                  or had one from before */
3334         if (bus->glom) {
3335                 if (DHD_GLOM_ON()) {
3336                         DHD_GLOM(("%s: try superframe read, packet chain:\n",
3337                                 __func__));
3338                         for (pnext = bus->glom; pnext; pnext = pnext->next) {
3339                                 DHD_GLOM(("    %p: %p len 0x%04x (%d)\n",
3340                                           pnext, (u8 *) (pnext->data),
3341                                           pnext->len, pnext->len));
3342                         }
3343                 }
3344
3345                 pfirst = bus->glom;
3346                 dlen = (u16) bcm_pkttotlen(pfirst);
3347
3348                 /* Do an SDIO read for the superframe.  Configurable iovar to
3349                  * read directly into the chained packet, or allocate a large
3350                  * packet and and copy into the chain.
3351                  */
3352                 if (usechain) {
3353                         errcode = bcmsdh_recv_buf(bus,
3354                                         bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3355                                         F2SYNC, (u8 *) pfirst->data, dlen,
3356                                         pfirst, NULL, NULL);
3357                 } else if (bus->dataptr) {
3358                         errcode = bcmsdh_recv_buf(bus,
3359                                         bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
3360                                         F2SYNC, bus->dataptr, dlen,
3361                                         NULL, NULL, NULL);
3362                         sublen = (u16) bcm_pktfrombuf(pfirst, 0, dlen,
3363                                                 bus->dataptr);
3364                         if (sublen != dlen) {
3365                                 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3366                                         __func__, dlen, sublen));
3367                                 errcode = -1;
3368                         }
3369                         pnext = NULL;
3370                 } else {
3371                         DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3372                                 dlen));
3373                         errcode = -1;
3374                 }
3375                 bus->f2rxdata++;
3376                 ASSERT(errcode != -BCME_PENDING);
3377
3378                 /* On failure, kill the superframe, allow a couple retries */
3379                 if (errcode < 0) {
3380                         DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3381                                    __func__, dlen, errcode));
3382                         bus->dhd->rx_errors++;
3383
3384                         if (bus->glomerr++ < 3) {
3385                                 dhdsdio_rxfail(bus, true, true);
3386                         } else {
3387                                 bus->glomerr = 0;
3388                                 dhdsdio_rxfail(bus, true, false);
3389                                 dhd_os_sdlock_rxq(bus->dhd);
3390                                 bcm_pkt_buf_free_skb(bus->glom);
3391                                 dhd_os_sdunlock_rxq(bus->dhd);
3392                                 bus->rxglomfail++;
3393                                 bus->glom = NULL;
3394                         }
3395                         return 0;
3396                 }
3397 #ifdef DHD_DEBUG
3398                 if (DHD_GLOM_ON()) {
3399                         printk(KERN_DEBUG "SUPERFRAME:\n");
3400                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3401                                 pfirst->data, min_t(int, pfirst->len, 48));
3402                 }
3403 #endif
3404
3405                 /* Validate the superframe header */
3406                 dptr = (u8 *) (pfirst->data);
3407                 sublen = get_unaligned_le16(dptr);
3408                 check = get_unaligned_le16(dptr + sizeof(u16));
3409
3410                 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3411                 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3412                 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3413                 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3414                         DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3415                                 __func__, bus->nextlen, seq));
3416                         bus->nextlen = 0;
3417                 }
3418                 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3419                 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3420
3421                 errcode = 0;
3422                 if ((u16)~(sublen ^ check)) {
3423                         DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3424                                 "0x%04x/0x%04x\n", __func__, sublen, check));
3425                         errcode = -1;
3426                 } else if (roundup(sublen, bus->blocksize) != dlen) {
3427                         DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3428                                 "0x%04x, expect 0x%04x\n",
3429                                 __func__, sublen,
3430                                 roundup(sublen, bus->blocksize), dlen));
3431                         errcode = -1;
3432                 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3433                            SDPCM_GLOM_CHANNEL) {
3434                         DHD_ERROR(("%s (superframe): bad channel %d\n",
3435                                    __func__,
3436                                    SDPCM_PACKET_CHANNEL(&dptr
3437                                                         [SDPCM_FRAMETAG_LEN])));
3438                         errcode = -1;
3439                 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3440                         DHD_ERROR(("%s (superframe): got second descriptor?\n",
3441                                    __func__));
3442                         errcode = -1;
3443                 } else if ((doff < SDPCM_HDRLEN) ||
3444                            (doff > (pfirst->len - SDPCM_HDRLEN))) {
3445                         DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3446                                 "pkt %d min %d\n",
3447                                 __func__, doff, sublen,
3448                                 pfirst->len, SDPCM_HDRLEN));
3449                         errcode = -1;
3450                 }
3451
3452                 /* Check sequence number of superframe SW header */
3453                 if (rxseq != seq) {
3454                         DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3455                                   __func__, seq, rxseq));
3456                         bus->rx_badseq++;
3457                         rxseq = seq;
3458                 }
3459
3460                 /* Check window for sanity */
3461                 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3462                         DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3463                                 __func__, txmax, bus->tx_seq));
3464                         txmax = bus->tx_seq + 2;
3465                 }
3466                 bus->tx_max = txmax;
3467
3468                 /* Remove superframe header, remember offset */
3469                 skb_pull(pfirst, doff);
3470                 sfdoff = doff;
3471
3472                 /* Validate all the subframe headers */
3473                 for (num = 0, pnext = pfirst; pnext && !errcode;
3474                      num++, pnext = pnext->next) {
3475                         dptr = (u8 *) (pnext->data);
3476                         dlen = (u16) (pnext->len);
3477                         sublen = get_unaligned_le16(dptr);
3478                         check = get_unaligned_le16(dptr + sizeof(u16));
3479                         chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3480                         doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3481 #ifdef DHD_DEBUG
3482                         if (DHD_GLOM_ON()) {
3483                                 printk(KERN_DEBUG "subframe:\n");
3484                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3485                                                      dptr, 32);
3486                         }
3487 #endif
3488
3489                         if ((u16)~(sublen ^ check)) {
3490                                 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3491                                            "len/check 0x%04x/0x%04x\n",
3492                                            __func__, num, sublen, check));
3493                                 errcode = -1;
3494                         } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3495                                 DHD_ERROR(("%s (subframe %d): length mismatch: "
3496                                            "len 0x%04x, expect 0x%04x\n",
3497                                            __func__, num, sublen, dlen));
3498                                 errcode = -1;
3499                         } else if ((chan != SDPCM_DATA_CHANNEL) &&
3500                                    (chan != SDPCM_EVENT_CHANNEL)) {
3501                                 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3502                                            __func__, num, chan));
3503                                 errcode = -1;
3504                         } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3505                                 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3506                                         __func__, num, doff, sublen,
3507                                         SDPCM_HDRLEN));
3508                                 errcode = -1;
3509                         }
3510                 }
3511
3512                 if (errcode) {
3513                         /* Terminate frame on error, request
3514                                  a couple retries */
3515                         if (bus->glomerr++ < 3) {
3516                                 /* Restore superframe header space */
3517                                 skb_push(pfirst, sfdoff);
3518                                 dhdsdio_rxfail(bus, true, true);
3519                         } else {
3520                                 bus->glomerr = 0;
3521                                 dhdsdio_rxfail(bus, true, false);
3522                                 dhd_os_sdlock_rxq(bus->dhd);
3523                                 bcm_pkt_buf_free_skb(bus->glom);
3524                                 dhd_os_sdunlock_rxq(bus->dhd);
3525                                 bus->rxglomfail++;
3526                                 bus->glom = NULL;
3527                         }
3528                         bus->nextlen = 0;
3529                         return 0;
3530                 }
3531
3532                 /* Basic SD framing looks ok - process each packet (header) */
3533                 save_pfirst = pfirst;
3534                 bus->glom = NULL;
3535                 plast = NULL;
3536
3537                 dhd_os_sdlock_rxq(bus->dhd);
3538                 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3539                         pnext = pfirst->next;
3540                         pfirst->next = NULL;
3541
3542                         dptr = (u8 *) (pfirst->data);
3543                         sublen = get_unaligned_le16(dptr);
3544                         chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3545                         seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3546                         doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3547
3548                         DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3549                                 "chan %d seq %d\n",
3550                                 __func__, num, pfirst, pfirst->data,
3551                                 pfirst->len, sublen, chan, seq));
3552
3553                         ASSERT((chan == SDPCM_DATA_CHANNEL)
3554                                || (chan == SDPCM_EVENT_CHANNEL));
3555
3556                         if (rxseq != seq) {
3557                                 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3558                                           __func__, seq, rxseq));
3559                                 bus->rx_badseq++;
3560                                 rxseq = seq;
3561                         }
3562 #ifdef DHD_DEBUG
3563                         if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3564                                 printk(KERN_DEBUG "Rx Subframe Data:\n");
3565                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3566                                                      dptr, dlen);
3567                         }
3568 #endif
3569
3570                         __skb_trim(pfirst, sublen);
3571                         skb_pull(pfirst, doff);
3572
3573                         if (pfirst->len == 0) {
3574                                 bcm_pkt_buf_free_skb(pfirst);
3575                                 if (plast) {
3576                                         plast->next = pnext;
3577                                 } else {
3578                                         ASSERT(save_pfirst == pfirst);
3579                                         save_pfirst = pnext;
3580                                 }
3581                                 continue;
3582                         } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3583                                    0) {
3584                                 DHD_ERROR(("%s: rx protocol error\n",
3585                                            __func__));
3586                                 bus->dhd->rx_errors++;
3587                                 bcm_pkt_buf_free_skb(pfirst);
3588                                 if (plast) {
3589                                         plast->next = pnext;
3590                                 } else {
3591                                         ASSERT(save_pfirst == pfirst);
3592                                         save_pfirst = pnext;
3593                                 }
3594                                 continue;
3595                         }
3596
3597                         /* this packet will go up, link back into
3598                                  chain and count it */
3599                         pfirst->next = pnext;
3600                         plast = pfirst;
3601                         num++;
3602
3603 #ifdef DHD_DEBUG
3604                         if (DHD_GLOM_ON()) {
3605                                 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3606                                 "nxt/lnk %p/%p\n",
3607                                 __func__, num, pfirst, pfirst->data,
3608                                 pfirst->len, pfirst->next,
3609                                 pfirst->prev));
3610                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3611                                                 pfirst->data,
3612                                                 min_t(int, pfirst->len, 32));
3613                         }
3614 #endif                          /* DHD_DEBUG */
3615                 }
3616                 dhd_os_sdunlock_rxq(bus->dhd);
3617                 if (num) {
3618                         dhd_os_sdunlock(bus->dhd);
3619                         dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3620                         dhd_os_sdlock(bus->dhd);
3621                 }
3622
3623                 bus->rxglomframes++;
3624                 bus->rxglompkts += num;
3625         }
3626         return num;
3627 }
3628
3629 /* Return true if there may be more frames to read */
3630 static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3631 {
3632         bcmsdh_info_t *sdh = bus->sdh;
3633
3634         u16 len, check; /* Extracted hardware header fields */
3635         u8 chan, seq, doff;     /* Extracted software header fields */
3636         u8 fcbits;              /* Extracted fcbits from software header */
3637
3638         struct sk_buff *pkt;            /* Packet for event or data frames */
3639         u16 pad;                /* Number of pad bytes to read */
3640         u16 rdlen;              /* Total number of bytes to read */
3641         u8 rxseq;               /* Next sequence number to expect */
3642         uint rxleft = 0;        /* Remaining number of frames allowed */
3643         int sdret;              /* Return code from bcmsdh calls */
3644         u8 txmax;               /* Maximum tx sequence offered */
3645         bool len_consistent;    /* Result of comparing readahead len and
3646                                          len from hw-hdr */
3647         u8 *rxbuf;
3648         int ifidx = 0;
3649         uint rxcount = 0;       /* Total frames read */
3650
3651 #if defined(DHD_DEBUG) || defined(SDTEST)
3652         bool sdtest = false;    /* To limit message spew from test mode */
3653 #endif
3654
3655         DHD_TRACE(("%s: Enter\n", __func__));
3656
3657         ASSERT(maxframes);
3658
3659 #ifdef SDTEST
3660         /* Allow pktgen to override maxframes */
3661         if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3662                 maxframes = bus->pktgen_count;
3663                 sdtest = true;
3664         }
3665 #endif
3666
3667         /* Not finished unless we encounter no more frames indication */
3668         *finished = false;
3669
3670         for (rxseq = bus->rx_seq, rxleft = maxframes;
3671              !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3672              rxseq++, rxleft--) {
3673
3674                 /* Handle glomming separately */
3675                 if (bus->glom || bus->glomd) {
3676                         u8 cnt;
3677                         DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3678                                   __func__, bus->glomd, bus->glom));
3679                         cnt = dhdsdio_rxglom(bus, rxseq);
3680                         DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3681                         rxseq += cnt - 1;
3682                         rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3683                         continue;
3684                 }
3685
3686                 /* Try doing single read if we can */
3687                 if (dhd_readahead && bus->nextlen) {
3688                         u16 nextlen = bus->nextlen;
3689                         bus->nextlen = 0;
3690
3691                         if (bus->bus == SPI_BUS) {
3692                                 rdlen = len = nextlen;
3693                         } else {
3694                                 rdlen = len = nextlen << 4;
3695
3696                                 /* Pad read to blocksize for efficiency */
3697                                 if (bus->roundup && bus->blocksize
3698                                     && (rdlen > bus->blocksize)) {
3699                                         pad =
3700                                             bus->blocksize -
3701                                             (rdlen % bus->blocksize);
3702                                         if ((pad <= bus->roundup)
3703                                             && (pad < bus->blocksize)
3704                                             && ((rdlen + pad + firstread) <
3705                                                 MAX_RX_DATASZ))
3706                                                 rdlen += pad;
3707                                 } else if (rdlen % DHD_SDALIGN) {
3708                                         rdlen +=
3709                                             DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3710                                 }
3711                         }
3712
3713                         /* We use bus->rxctl buffer in WinXP for initial
3714                          * control pkt receives.
3715                          * Later we use buffer-poll for data as well
3716                          * as control packets.
3717                          * This is required because dhd receives full
3718                          * frame in gSPI unlike SDIO.
3719                          * After the frame is received we have to
3720                          * distinguish whether it is data
3721                          * or non-data frame.
3722                          */
3723                         /* Allocate a packet buffer */
3724                         dhd_os_sdlock_rxq(bus->dhd);
3725                         pkt = bcm_pkt_buf_get_skb(rdlen + DHD_SDALIGN);
3726                         if (!pkt) {
3727                                 if (bus->bus == SPI_BUS) {
3728                                         bus->usebufpool = false;
3729                                         bus->rxctl = bus->rxbuf;
3730                                         if (dhd_alignctl) {
3731                                                 bus->rxctl += firstread;
3732                                                 pad = ((unsigned long)bus->rxctl %
3733                                                       DHD_SDALIGN);
3734                                                 if (pad)
3735                                                         bus->rxctl +=
3736                                                             (DHD_SDALIGN - pad);
3737                                                 bus->rxctl -= firstread;
3738                                         }
3739                                         ASSERT(bus->rxctl >= bus->rxbuf);
3740                                         rxbuf = bus->rxctl;
3741                                         /* Read the entire frame */
3742                                         sdret = bcmsdh_recv_buf(bus,
3743                                                     bcmsdh_cur_sbwad(sdh),
3744                                                     SDIO_FUNC_2, F2SYNC,
3745                                                     rxbuf, rdlen,
3746                                                     NULL, NULL, NULL);
3747                                         bus->f2rxdata++;
3748                                         ASSERT(sdret != -BCME_PENDING);
3749
3750                                         /* Control frame failures need
3751                                          retransmission */
3752                                         if (sdret < 0) {
3753                                                 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3754                                                         __func__,
3755                                                         rdlen, sdret));
3756                                                 /* dhd.rx_ctlerrs is higher */
3757                                                 bus->rxc_errors++;
3758                                                 dhd_os_sdunlock_rxq(bus->dhd);
3759                                                 dhdsdio_rxfail(bus, true,
3760                                                        (bus->bus ==
3761                                                         SPI_BUS) ? false
3762                                                        : true);
3763                                                 continue;
3764                                         }
3765                                 } else {
3766                                         /* Give up on data,
3767                                         request rtx of events */
3768                                         DHD_ERROR(("%s (nextlen): "
3769                                                    "bcm_pkt_buf_get_skb failed:"
3770                                                    " len %d rdlen %d expected"
3771                                                    " rxseq %d\n", __func__,
3772                                                    len, rdlen, rxseq));
3773                                         /* Just go try again w/normal
3774                                         header read */
3775                                         dhd_os_sdunlock_rxq(bus->dhd);
3776                                         continue;
3777                                 }
3778                         } else {
3779                                 if (bus->bus == SPI_BUS)
3780                                         bus->usebufpool = true;
3781
3782                                 ASSERT(!(pkt->prev));
3783                                 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
3784                                 rxbuf = (u8 *) (pkt->data);
3785                                 /* Read the entire frame */
3786                                 sdret = bcmsdh_recv_buf(bus,
3787                                                 bcmsdh_cur_sbwad(sdh),
3788                                                 SDIO_FUNC_2, F2SYNC,
3789                                                 rxbuf, rdlen,
3790                                                 pkt, NULL, NULL);
3791                                 bus->f2rxdata++;
3792                                 ASSERT(sdret != -BCME_PENDING);
3793
3794                                 if (sdret < 0) {
3795                                         DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3796                                                 __func__, rdlen, sdret));
3797                                         bcm_pkt_buf_free_skb(pkt);
3798                                         bus->dhd->rx_errors++;
3799                                         dhd_os_sdunlock_rxq(bus->dhd);
3800                                         /* Force retry w/normal header read.
3801                                          * Don't attempt NAK for
3802                                          * gSPI
3803                                          */
3804                                         dhdsdio_rxfail(bus, true,
3805                                                        (bus->bus ==
3806                                                         SPI_BUS) ? false :
3807                                                        true);
3808                                         continue;
3809                                 }
3810                         }
3811                         dhd_os_sdunlock_rxq(bus->dhd);
3812
3813                         /* Now check the header */
3814                         memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3815
3816                         /* Extract hardware header fields */
3817                         len = get_unaligned_le16(bus->rxhdr);
3818                         check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3819
3820                         /* All zeros means readahead info was bad */
3821                         if (!(len | check)) {
3822                                 DHD_INFO(("%s (nextlen): read zeros in HW "
3823                                         "header???\n", __func__));
3824                                 dhdsdio_pktfree2(bus, pkt);
3825                                 continue;
3826                         }
3827
3828                         /* Validate check bytes */
3829                         if ((u16)~(len ^ check)) {
3830                                 DHD_ERROR(("%s (nextlen): HW hdr error:"
3831                                         " nextlen/len/check"
3832                                         " 0x%04x/0x%04x/0x%04x\n",
3833                                         __func__, nextlen, len, check));
3834                                 bus->rx_badhdr++;
3835                                 dhdsdio_rxfail(bus, false, false);
3836                                 dhdsdio_pktfree2(bus, pkt);
3837                                 continue;
3838                         }
3839
3840                         /* Validate frame length */
3841                         if (len < SDPCM_HDRLEN) {
3842                                 DHD_ERROR(("%s (nextlen): HW hdr length "
3843                                         "invalid: %d\n", __func__, len));
3844                                 dhdsdio_pktfree2(bus, pkt);
3845                                 continue;
3846                         }
3847
3848                         /* Check for consistency withreadahead info */
3849                         len_consistent = (nextlen != (roundup(len, 16) >> 4));
3850                         if (len_consistent) {
3851                                 /* Mismatch, force retry w/normal
3852                                         header (may be >4K) */
3853                                 DHD_ERROR(("%s (nextlen): mismatch, "
3854                                         "nextlen %d len %d rnd %d; "
3855                                         "expected rxseq %d\n",
3856                                         __func__, nextlen,
3857                                         len, roundup(len, 16), rxseq));
3858                                 dhdsdio_rxfail(bus, true, (bus->bus != SPI_BUS));
3859                                 dhdsdio_pktfree2(bus, pkt);
3860                                 continue;
3861                         }
3862
3863                         /* Extract software header fields */
3864                         chan = SDPCM_PACKET_CHANNEL(
3865                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3866                         seq = SDPCM_PACKET_SEQUENCE(
3867                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3868                         doff = SDPCM_DOFFSET_VALUE(
3869                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3870                         txmax = SDPCM_WINDOW_VALUE(
3871                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3872
3873                         bus->nextlen =
3874                             bus->rxhdr[SDPCM_FRAMETAG_LEN +
3875                                        SDPCM_NEXTLEN_OFFSET];
3876                         if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3877                                 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
3878                                         __func__, bus->nextlen, seq));
3879                                 bus->nextlen = 0;
3880                         }
3881
3882                         bus->dhd->rx_readahead_cnt++;
3883
3884                         /* Handle Flow Control */
3885                         fcbits = SDPCM_FCMASK_VALUE(
3886                                         &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3887
3888                         if (bus->flowcontrol != fcbits) {
3889                                 if (~bus->flowcontrol & fcbits)
3890                                         bus->fc_xoff++;
3891
3892                                 if (bus->flowcontrol & ~fcbits)
3893                                         bus->fc_xon++;
3894
3895                                 bus->fc_rcvd++;
3896                                 bus->flowcontrol = fcbits;
3897                         }
3898
3899                         /* Check and update sequence number */
3900                         if (rxseq != seq) {
3901                                 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
3902                                         "%d\n", __func__, seq, rxseq));
3903                                 bus->rx_badseq++;
3904                                 rxseq = seq;
3905                         }
3906
3907                         /* Check window for sanity */
3908                         if ((u8) (txmax - bus->tx_seq) > 0x40) {
3909                                 DHD_ERROR(("%s: got unlikely tx max %d with "
3910                                         "tx_seq %d\n",
3911                                         __func__, txmax, bus->tx_seq));
3912                                 txmax = bus->tx_seq + 2;
3913                         }
3914                         bus->tx_max = txmax;
3915
3916 #ifdef DHD_DEBUG
3917                         if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3918                                 printk(KERN_DEBUG "Rx Data:\n");
3919                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3920                                                      rxbuf, len);
3921                         } else if (DHD_HDRS_ON()) {
3922                                 printk(KERN_DEBUG "RxHdr:\n");
3923                                 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3924                                                      bus->rxhdr, SDPCM_HDRLEN);
3925                         }
3926 #endif
3927
3928                         if (chan == SDPCM_CONTROL_CHANNEL) {
3929                                 if (bus->bus == SPI_BUS) {
3930                                         dhdsdio_read_control(bus, rxbuf, len,
3931                                                              doff);
3932                                 } else {
3933                                         DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
3934                                                 __func__, seq));
3935                                         /* Force retry w/normal header read */
3936                                         bus->nextlen = 0;
3937                                         dhdsdio_rxfail(bus, false, true);
3938                                 }
3939                                 dhdsdio_pktfree2(bus, pkt);
3940                                 continue;
3941                         }
3942
3943                         if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
3944                                 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
3945                                         len, chan));
3946                                 continue;
3947                         }
3948
3949                         /* Validate data offset */
3950                         if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3951                                 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
3952                                         __func__, doff, len, SDPCM_HDRLEN));
3953                                 dhdsdio_rxfail(bus, false, false);
3954                                 dhdsdio_pktfree2(bus, pkt);
3955                                 continue;
3956                         }
3957
3958                         /* All done with this one -- now deliver the packet */
3959                         goto deliver;
3960                 }
3961                 /* gSPI frames should not be handled in fractions */
3962                 if (bus->bus == SPI_BUS)
3963                         break;
3964
3965                 /* Read frame header (hardware and software) */
3966                 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh),
3967                                 SDIO_FUNC_2, F2SYNC, bus->rxhdr, firstread,
3968                                 NULL, NULL, NULL);
3969                 bus->f2rxhdrs++;
3970                 ASSERT(sdret != -BCME_PENDING);
3971
3972                 if (sdret < 0) {
3973                         DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
3974                                    sdret));
3975                         bus->rx_hdrfail++;
3976                         dhdsdio_rxfail(bus, true, true);
3977                         continue;
3978                 }
3979 #ifdef DHD_DEBUG
3980                 if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
3981                         printk(KERN_DEBUG "RxHdr:\n");
3982                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3983                                              bus->rxhdr, SDPCM_HDRLEN);
3984                 }
3985 #endif
3986
3987                 /* Extract hardware header fields */
3988                 len = get_unaligned_le16(bus->rxhdr);
3989                 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3990
3991                 /* All zeros means no more frames */
3992                 if (!(len | check)) {
3993                         *finished = true;
3994                         break;
3995                 }
3996
3997                 /* Validate check bytes */
3998                 if ((u16) ~(len ^ check)) {
3999                         DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
4000                                 __func__, len, check));
4001                         bus->rx_badhdr++;
4002                         dhdsdio_rxfail(bus, false, false);
4003                         continue;
4004                 }
4005
4006                 /* Validate frame length */
4007                 if (len < SDPCM_HDRLEN) {
4008                         DHD_ERROR(("%s: HW hdr length invalid: %d\n",
4009                                    __func__, len));
4010                         continue;
4011                 }
4012
4013                 /* Extract software header fields */
4014                 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4015                 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4016                 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4017                 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4018
4019                 /* Validate data offset */
4020                 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
4021                         DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
4022                                 "seq %d\n",
4023                                 __func__, doff, len, SDPCM_HDRLEN, seq));
4024                         bus->rx_badhdr++;
4025                         ASSERT(0);
4026                         dhdsdio_rxfail(bus, false, false);
4027                         continue;
4028                 }
4029
4030                 /* Save the readahead length if there is one */
4031                 bus->nextlen =
4032                     bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4033                 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4034                         DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4035                                 "(%d), seq %d\n",
4036                                 __func__, bus->nextlen, seq));
4037                         bus->nextlen = 0;
4038                 }
4039
4040                 /* Handle Flow Control */
4041                 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4042
4043                 if (bus->flowcontrol != fcbits) {
4044                         if (~bus->flowcontrol & fcbits)
4045                                 bus->fc_xoff++;
4046
4047                         if (bus->flowcontrol & ~fcbits)
4048                                 bus->fc_xon++;
4049
4050                         bus->fc_rcvd++;
4051                         bus->flowcontrol = fcbits;
4052                 }
4053
4054                 /* Check and update sequence number */
4055                 if (rxseq != seq) {
4056                         DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4057                                   seq, rxseq));
4058                         bus->rx_badseq++;
4059                         rxseq = seq;
4060                 }
4061
4062                 /* Check window for sanity */
4063                 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4064                         DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4065                                 __func__, txmax, bus->tx_seq));
4066                         txmax = bus->tx_seq + 2;
4067                 }
4068                 bus->tx_max = txmax;
4069
4070                 /* Call a separate function for control frames */
4071                 if (chan == SDPCM_CONTROL_CHANNEL) {
4072                         dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4073                         continue;
4074                 }
4075
4076                 ASSERT((chan == SDPCM_DATA_CHANNEL)
4077                        || (chan == SDPCM_EVENT_CHANNEL)
4078                        || (chan == SDPCM_TEST_CHANNEL)
4079                        || (chan == SDPCM_GLOM_CHANNEL));
4080
4081                 /* Length to read */
4082                 rdlen = (len > firstread) ? (len - firstread) : 0;
4083
4084                 /* May pad read to blocksize for efficiency */
4085                 if (bus->roundup && bus->blocksize &&
4086                         (rdlen > bus->blocksize)) {
4087                         pad = bus->blocksize - (rdlen % bus->blocksize);
4088                         if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4089                             ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4090                                 rdlen += pad;
4091                 } else if (rdlen % DHD_SDALIGN) {
4092                         rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4093                 }
4094
4095                 /* Satisfy length-alignment requirements */
4096                 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4097                         rdlen = roundup(rdlen, ALIGNMENT);
4098
4099                 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4100                         /* Too long -- skip this frame */
4101                         DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4102                                    __func__, len, rdlen));
4103                         bus->dhd->rx_errors++;
4104                         bus->rx_toolong++;
4105                         dhdsdio_rxfail(bus, false, false);
4106                         continue;
4107                 }
4108
4109                 dhd_os_sdlock_rxq(bus->dhd);
4110                 pkt = bcm_pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
4111                 if (!pkt) {
4112                         /* Give up on data, request rtx of events */
4113                         DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed: rdlen %d "
4114                                 "chan %d\n", __func__, rdlen, chan));
4115                         bus->dhd->rx_dropped++;
4116                         dhd_os_sdunlock_rxq(bus->dhd);
4117                         dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
4118                         continue;
4119                 }
4120                 dhd_os_sdunlock_rxq(bus->dhd);
4121
4122                 ASSERT(!(pkt->prev));
4123
4124                 /* Leave room for what we already read, and align remainder */
4125                 ASSERT(firstread < pkt->len);
4126                 skb_pull(pkt, firstread);
4127                 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
4128
4129                 /* Read the remaining frame data */
4130                 sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4131                                         F2SYNC, ((u8 *) (pkt->data)), rdlen,
4132                                         pkt, NULL, NULL);
4133                 bus->f2rxdata++;
4134                 ASSERT(sdret != -BCME_PENDING);
4135
4136                 if (sdret < 0) {
4137                         DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4138                                    __func__, rdlen,
4139                                    ((chan ==
4140                                      SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4141                                         SDPCM_DATA_CHANNEL)
4142                                        ? "data" : "test")),
4143                                    sdret));
4144                         dhd_os_sdlock_rxq(bus->dhd);
4145                         bcm_pkt_buf_free_skb(pkt);
4146                         dhd_os_sdunlock_rxq(bus->dhd);
4147                         bus->dhd->rx_errors++;
4148                         dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
4149                         continue;
4150                 }
4151
4152                 /* Copy the already-read portion */
4153                 skb_push(pkt, firstread);
4154                 memcpy(pkt->data, bus->rxhdr, firstread);
4155
4156 #ifdef DHD_DEBUG
4157                 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4158                         printk(KERN_DEBUG "Rx Data:\n");
4159                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
4160                                              pkt->data, len);
4161                 }
4162 #endif
4163
4164 deliver:
4165                 /* Save superframe descriptor and allocate packet frame */
4166                 if (chan == SDPCM_GLOM_CHANNEL) {
4167                         if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4168                                 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4169                                         __func__, len));
4170 #ifdef DHD_DEBUG
4171                                 if (DHD_GLOM_ON()) {
4172                                         printk(KERN_DEBUG "Glom Data:\n");
4173                                         print_hex_dump_bytes("",
4174                                                              DUMP_PREFIX_OFFSET,
4175                                                              pkt->data, len);
4176                                 }
4177 #endif
4178                                 __skb_trim(pkt, len);
4179                                 ASSERT(doff == SDPCM_HDRLEN);
4180                                 skb_pull(pkt, SDPCM_HDRLEN);
4181                                 bus->glomd = pkt;
4182                         } else {
4183                                 DHD_ERROR(("%s: glom superframe w/o "
4184                                         "descriptor!\n", __func__));
4185                                 dhdsdio_rxfail(bus, false, false);
4186                         }
4187                         continue;
4188                 }
4189
4190                 /* Fill in packet len and prio, deliver upward */
4191                 __skb_trim(pkt, len);
4192                 skb_pull(pkt, doff);
4193
4194 #ifdef SDTEST
4195                 /* Test channel packets are processed separately */
4196                 if (chan == SDPCM_TEST_CHANNEL) {
4197                         dhdsdio_testrcv(bus, pkt, seq);
4198                         continue;
4199                 }
4200 #endif                          /* SDTEST */
4201
4202                 if (pkt->len == 0) {
4203                         dhd_os_sdlock_rxq(bus->dhd);
4204                         bcm_pkt_buf_free_skb(pkt);
4205                         dhd_os_sdunlock_rxq(bus->dhd);
4206                         continue;
4207                 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4208                         DHD_ERROR(("%s: rx protocol error\n", __func__));
4209                         dhd_os_sdlock_rxq(bus->dhd);
4210                         bcm_pkt_buf_free_skb(pkt);
4211                         dhd_os_sdunlock_rxq(bus->dhd);
4212                         bus->dhd->rx_errors++;
4213                         continue;
4214                 }
4215
4216                 /* Unlock during rx call */
4217                 dhd_os_sdunlock(bus->dhd);
4218                 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4219                 dhd_os_sdlock(bus->dhd);
4220         }
4221         rxcount = maxframes - rxleft;
4222 #ifdef DHD_DEBUG
4223         /* Message if we hit the limit */
4224         if (!rxleft && !sdtest)
4225                 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4226                           maxframes));
4227         else
4228 #endif                          /* DHD_DEBUG */
4229                 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4230         /* Back off rxseq if awaiting rtx, update rx_seq */
4231         if (bus->rxskip)
4232                 rxseq--;
4233         bus->rx_seq = rxseq;
4234
4235         return rxcount;
4236 }
4237
4238 static u32 dhdsdio_hostmail(dhd_bus_t *bus)
4239 {
4240         sdpcmd_regs_t *regs = bus->regs;
4241         u32 intstatus = 0;
4242         u32 hmb_data;
4243         u8 fcbits;
4244         uint retries = 0;
4245
4246         DHD_TRACE(("%s: Enter\n", __func__));
4247
4248         /* Read mailbox data and ack that we did so */
4249         R_SDREG(hmb_data, &regs->tohostmailboxdata, retries);
4250         if (retries <= retry_limit)
4251                 W_SDREG(SMB_INT_ACK, &regs->tosbmailbox, retries);
4252         bus->f1regdata += 2;
4253
4254         /* Dongle recomposed rx frames, accept them again */
4255         if (hmb_data & HMB_DATA_NAKHANDLED) {
4256                 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4257                           bus->rx_seq));
4258                 if (!bus->rxskip)
4259                         DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4260
4261                 bus->rxskip = false;
4262                 intstatus |= I_HMB_FRAME_IND;
4263         }
4264
4265         /*
4266          * DEVREADY does not occur with gSPI.
4267          */
4268         if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4269                 bus->sdpcm_ver =
4270                     (hmb_data & HMB_DATA_VERSION_MASK) >>
4271                     HMB_DATA_VERSION_SHIFT;
4272                 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4273                         DHD_ERROR(("Version mismatch, dongle reports %d, "
4274                                 "expecting %d\n",
4275                                 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4276                 else
4277                         DHD_INFO(("Dongle ready, protocol version %d\n",
4278                                   bus->sdpcm_ver));
4279         }
4280
4281         /*
4282          * Flow Control has been moved into the RX headers and this out of band
4283          * method isn't used any more.
4284          * remaining backward compatible with older dongles.
4285          */
4286         if (hmb_data & HMB_DATA_FC) {
4287                 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
4288                                                         HMB_DATA_FCDATA_SHIFT;
4289
4290                 if (fcbits & ~bus->flowcontrol)
4291                         bus->fc_xoff++;
4292
4293                 if (bus->flowcontrol & ~fcbits)
4294                         bus->fc_xon++;
4295
4296                 bus->fc_rcvd++;
4297                 bus->flowcontrol = fcbits;
4298         }
4299
4300         /* Shouldn't be any others */
4301         if (hmb_data & ~(HMB_DATA_DEVREADY |
4302                          HMB_DATA_NAKHANDLED |
4303                          HMB_DATA_FC |
4304                          HMB_DATA_FWREADY |
4305                          HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4306                 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4307         }
4308
4309         return intstatus;
4310 }
4311
4312 bool dhdsdio_dpc(dhd_bus_t *bus)
4313 {
4314         bcmsdh_info_t *sdh = bus->sdh;
4315         sdpcmd_regs_t *regs = bus->regs;
4316         u32 intstatus, newstatus = 0;
4317         uint retries = 0;
4318         uint rxlimit = dhd_rxbound;     /* Rx frames to read before resched */
4319         uint txlimit = dhd_txbound;     /* Tx frames to send before resched */
4320         uint framecnt = 0;      /* Temporary counter of tx/rx frames */
4321         bool rxdone = true;     /* Flag for no more read data */
4322         bool resched = false;   /* Flag indicating resched wanted */
4323
4324         DHD_TRACE(("%s: Enter\n", __func__));
4325
4326         /* Start with leftover status bits */
4327         intstatus = bus->intstatus;
4328
4329         dhd_os_sdlock(bus->dhd);
4330
4331         /* If waiting for HTAVAIL, check status */
4332         if (bus->clkstate == CLK_PENDING) {
4333                 int err;
4334                 u8 clkctl, devctl = 0;
4335
4336 #ifdef DHD_DEBUG
4337                 /* Check for inconsistent device control */
4338                 devctl =
4339                     bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4340                 if (err) {
4341                         DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4342                                    __func__, err));
4343                         bus->dhd->busstate = DHD_BUS_DOWN;
4344                 } else {
4345                         ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4346                 }
4347 #endif                          /* DHD_DEBUG */
4348
4349                 /* Read CSR, if clock on switch to AVAIL, else ignore */
4350                 clkctl =
4351                     bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4352                                     &err);
4353                 if (err) {
4354                         DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4355                                    err));
4356                         bus->dhd->busstate = DHD_BUS_DOWN;
4357                 }
4358
4359                 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4360                           clkctl));
4361
4362                 if (SBSDIO_HTAV(clkctl)) {
4363                         devctl =
4364                             bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4365                                             &err);
4366                         if (err) {
4367                                 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4368                                            __func__, err));
4369                                 bus->dhd->busstate = DHD_BUS_DOWN;
4370                         }
4371                         devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4372                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4373                                          devctl, &err);
4374                         if (err) {
4375                                 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4376                                            __func__, err));
4377                                 bus->dhd->busstate = DHD_BUS_DOWN;
4378                         }
4379                         bus->clkstate = CLK_AVAIL;
4380                 } else {
4381                         goto clkwait;
4382                 }
4383         }
4384
4385         BUS_WAKE(bus);
4386
4387         /* Make sure backplane clock is on */
4388         dhdsdio_clkctl(bus, CLK_AVAIL, true);
4389         if (bus->clkstate == CLK_PENDING)
4390                 goto clkwait;
4391
4392         /* Pending interrupt indicates new device status */
4393         if (bus->ipend) {
4394                 bus->ipend = false;
4395                 R_SDREG(newstatus, &regs->intstatus, retries);
4396                 bus->f1regdata++;
4397                 if (bcmsdh_regfail(bus->sdh))
4398                         newstatus = 0;
4399                 newstatus &= bus->hostintmask;
4400                 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4401                 if (newstatus) {
4402                         W_SDREG(newstatus, &regs->intstatus, retries);
4403                         bus->f1regdata++;
4404                 }
4405         }
4406
4407         /* Merge new bits with previous */
4408         intstatus |= newstatus;
4409         bus->intstatus = 0;
4410
4411         /* Handle flow-control change: read new state in case our ack
4412          * crossed another change interrupt.  If change still set, assume
4413          * FC ON for safety, let next loop through do the debounce.
4414          */
4415         if (intstatus & I_HMB_FC_CHANGE) {
4416                 intstatus &= ~I_HMB_FC_CHANGE;
4417                 W_SDREG(I_HMB_FC_CHANGE, &regs->intstatus, retries);
4418                 R_SDREG(newstatus, &regs->intstatus, retries);
4419                 bus->f1regdata += 2;
4420                 bus->fcstate =
4421                     !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4422                 intstatus |= (newstatus & bus->hostintmask);
4423         }
4424
4425         /* Handle host mailbox indication */
4426         if (intstatus & I_HMB_HOST_INT) {
4427                 intstatus &= ~I_HMB_HOST_INT;
4428                 intstatus |= dhdsdio_hostmail(bus);
4429         }
4430
4431         /* Generally don't ask for these, can get CRC errors... */
4432         if (intstatus & I_WR_OOSYNC) {
4433                 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4434                 intstatus &= ~I_WR_OOSYNC;
4435         }
4436
4437         if (intstatus & I_RD_OOSYNC) {
4438                 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4439                 intstatus &= ~I_RD_OOSYNC;
4440         }
4441
4442         if (intstatus & I_SBINT) {
4443                 DHD_ERROR(("Dongle reports SBINT\n"));
4444                 intstatus &= ~I_SBINT;
4445         }
4446
4447         /* Would be active due to wake-wlan in gSPI */
4448         if (intstatus & I_CHIPACTIVE) {
4449                 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4450                 intstatus &= ~I_CHIPACTIVE;
4451         }
4452
4453         /* Ignore frame indications if rxskip is set */
4454         if (bus->rxskip)
4455                 intstatus &= ~I_HMB_FRAME_IND;
4456
4457         /* On frame indication, read available frames */
4458         if (PKT_AVAILABLE()) {
4459                 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4460                 if (rxdone || bus->rxskip)
4461                         intstatus &= ~I_HMB_FRAME_IND;
4462                 rxlimit -= min(framecnt, rxlimit);
4463         }
4464
4465         /* Keep still-pending events for next scheduling */
4466         bus->intstatus = intstatus;
4467
4468 clkwait:
4469 #if defined(OOB_INTR_ONLY)
4470         bcmsdh_oob_intr_set(1);
4471 #endif                          /* (OOB_INTR_ONLY) */
4472         /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4473          * or clock availability.  (Allows tx loop to check ipend if desired.)
4474          * (Unless register access seems hosed, as we may not be able to ACK...)
4475          */
4476         if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4477                 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4478                           __func__, rxdone, framecnt));
4479                 bus->intdis = false;
4480                 bcmsdh_intr_enable(sdh);
4481         }
4482
4483         if (DATAOK(bus) && bus->ctrl_frame_stat &&
4484                 (bus->clkstate == CLK_AVAIL)) {
4485                 int ret, i;
4486
4487                 ret =
4488                     dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4489                                         F2SYNC, (u8 *) bus->ctrl_frame_buf,
4490                                         (u32) bus->ctrl_frame_len, NULL,
4491                                         NULL, NULL);
4492                 ASSERT(ret != -BCME_PENDING);
4493
4494                 if (ret < 0) {
4495                         /* On failure, abort the command and
4496                                 terminate the frame */
4497                         DHD_INFO(("%s: sdio error %d, abort command and "
4498                                 "terminate frame.\n", __func__, ret));
4499                         bus->tx_sderrs++;
4500
4501                         bcmsdh_abort(sdh, SDIO_FUNC_2);
4502
4503                         bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4504                                          SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4505                                          NULL);
4506                         bus->f1regdata++;
4507
4508                         for (i = 0; i < 3; i++) {
4509                                 u8 hi, lo;
4510                                 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4511                                                      SBSDIO_FUNC1_WFRAMEBCHI,
4512                                                      NULL);
4513                                 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4514                                                      SBSDIO_FUNC1_WFRAMEBCLO,
4515                                                      NULL);
4516                                 bus->f1regdata += 2;
4517                                 if ((hi == 0) && (lo == 0))
4518                                         break;
4519                         }
4520
4521                 }
4522                 if (ret == 0)
4523                         bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4524
4525                 DHD_INFO(("Return_dpc value is : %d\n", ret));
4526                 bus->ctrl_frame_stat = false;
4527                 dhd_wait_event_wakeup(bus->dhd);
4528         }
4529         /* Send queued frames (limit 1 if rx may still be pending) */
4530         else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4531                  bcm_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4532                  && DATAOK(bus)) {
4533                 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4534                 framecnt = dhdsdio_sendfromq(bus, framecnt);
4535                 txlimit -= framecnt;
4536         }
4537
4538         /* Resched if events or tx frames are pending,
4539                  else await next interrupt */
4540         /* On failed register access, all bets are off:
4541                  no resched or interrupts */
4542         if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4543                 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4544                         "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4545                 bus->dhd->busstate = DHD_BUS_DOWN;
4546                 bus->intstatus = 0;
4547         } else if (bus->clkstate == CLK_PENDING) {
4548                 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4549                         "I_CHIPACTIVE interrupt\n", __func__));
4550                 resched = true;
4551         } else if (bus->intstatus || bus->ipend ||
4552                 (!bus->fcstate && bcm_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
4553                         DATAOK(bus)) || PKT_AVAILABLE()) {
4554                 resched = true;
4555         }
4556
4557         bus->dpc_sched = resched;
4558
4559         /* If we're done for now, turn off clock request. */
4560         if ((bus->clkstate != CLK_PENDING)
4561             && bus->idletime == DHD_IDLE_IMMEDIATE) {
4562                 bus->activity = false;
4563                 dhdsdio_clkctl(bus, CLK_NONE, false);
4564         }
4565
4566         dhd_os_sdunlock(bus->dhd);
4567
4568         return resched;
4569 }
4570
4571 bool dhd_bus_dpc(struct dhd_bus *bus)
4572 {
4573         bool resched;
4574
4575         /* Call the DPC directly. */
4576         DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4577         resched = dhdsdio_dpc(bus);
4578
4579         return resched;
4580 }
4581
4582 void dhdsdio_isr(void *arg)
4583 {
4584         dhd_bus_t *bus = (dhd_bus_t *) arg;
4585         bcmsdh_info_t *sdh;
4586
4587         DHD_TRACE(("%s: Enter\n", __func__));
4588
4589         if (!bus) {
4590                 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4591                 return;
4592         }
4593         sdh = bus->sdh;
4594
4595         if (bus->dhd->busstate == DHD_BUS_DOWN) {
4596                 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4597                            __func__));
4598                 return;
4599         }
4600         /* Count the interrupt call */
4601         bus->intrcount++;
4602         bus->ipend = true;
4603
4604         /* Shouldn't get this interrupt if we're sleeping? */
4605         if (bus->sleeping) {
4606                 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4607                 return;
4608         }
4609
4610         /* Disable additional interrupts (is this needed now)? */
4611         if (bus->intr)
4612                 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4613         else
4614                 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4615
4616         bcmsdh_intr_disable(sdh);
4617         bus->intdis = true;
4618
4619 #if defined(SDIO_ISR_THREAD)
4620         DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4621         while (dhdsdio_dpc(bus))
4622                 ;
4623 #else
4624         bus->dpc_sched = true;
4625         dhd_sched_dpc(bus->dhd);
4626 #endif
4627
4628 }
4629
4630 #ifdef SDTEST
4631 static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4632 {
4633         /* Default to specified length, or full range */
4634         if (dhd_pktgen_len) {
4635                 bus->pktgen_maxlen = min(dhd_pktgen_len, MAX_PKTGEN_LEN);
4636                 bus->pktgen_minlen = bus->pktgen_maxlen;
4637         } else {
4638                 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4639                 bus->pktgen_minlen = 0;
4640         }
4641         bus->pktgen_len = (u16) bus->pktgen_minlen;
4642
4643         /* Default to per-watchdog burst with 10s print time */
4644         bus->pktgen_freq = 1;
4645         bus->pktgen_print = 10000 / dhd_watchdog_ms;
4646         bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4647
4648         /* Default to echo mode */
4649         bus->pktgen_mode = DHD_PKTGEN_ECHO;
4650         bus->pktgen_stop = 1;
4651 }
4652
4653 static void dhdsdio_pktgen(dhd_bus_t *bus)
4654 {
4655         struct sk_buff *pkt;
4656         u8 *data;
4657         uint pktcount;
4658         uint fillbyte;
4659         u16 len;
4660
4661         /* Display current count if appropriate */
4662         if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4663                 bus->pktgen_ptick = 0;
4664                 printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4665                        __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4666         }
4667
4668         /* For recv mode, just make sure dongle has started sending */
4669         if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4670                 if (!bus->pktgen_rcvd)
4671                         dhdsdio_sdtest_set(bus, true);
4672                 return;
4673         }
4674
4675         /* Otherwise, generate or request the specified number of packets */
4676         for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4677                 /* Stop if total has been reached */
4678                 if (bus->pktgen_total
4679                     && (bus->pktgen_sent >= bus->pktgen_total)) {
4680                         bus->pktgen_count = 0;
4681                         break;
4682                 }
4683
4684                 /* Allocate an appropriate-sized packet */
4685                 len = bus->pktgen_len;
4686                 pkt = bcm_pkt_buf_get_skb(
4687                         (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4688                         true);
4689                 if (!pkt) {
4690                         DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed!\n",
4691                                 __func__));
4692                         break;
4693                 }
4694                 PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4695                          DHD_SDALIGN);
4696                 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4697
4698                 /* Write test header cmd and extra based on mode */
4699                 switch (bus->pktgen_mode) {
4700                 case DHD_PKTGEN_ECHO:
4701                         *data++ = SDPCM_TEST_ECHOREQ;
4702                         *data++ = (u8) bus->pktgen_sent;
4703                         break;
4704
4705                 case DHD_PKTGEN_SEND:
4706                         *data++ = SDPCM_TEST_DISCARD;
4707                         *data++ = (u8) bus->pktgen_sent;
4708                         break;
4709
4710                 case DHD_PKTGEN_RXBURST:
4711                         *data++ = SDPCM_TEST_BURST;
4712                         *data++ = (u8) bus->pktgen_count;
4713                         break;
4714
4715                 default:
4716                         DHD_ERROR(("Unrecognized pktgen mode %d\n",
4717                                    bus->pktgen_mode));
4718                         bcm_pkt_buf_free_skb(pkt, true);
4719                         bus->pktgen_count = 0;
4720                         return;
4721                 }
4722
4723                 /* Write test header length field */
4724                 *data++ = (len >> 0);
4725                 *data++ = (len >> 8);
4726
4727                 /* Then fill in the remainder -- N/A for burst,
4728                          but who cares... */
4729                 for (fillbyte = 0; fillbyte < len; fillbyte++)
4730                         *data++ =
4731                             SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4732
4733 #ifdef DHD_DEBUG
4734                 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4735                         data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4736                         printk(KERN_DEBUG "dhdsdio_pktgen: Tx Data:\n");
4737                         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, data,
4738                                              pkt->len - SDPCM_HDRLEN);
4739                 }
4740 #endif
4741
4742                 /* Send it */
4743                 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4744                         bus->pktgen_fail++;
4745                         if (bus->pktgen_stop
4746                             && bus->pktgen_stop == bus->pktgen_fail)
4747                                 bus->pktgen_count = 0;
4748                 }
4749                 bus->pktgen_sent++;
4750
4751                 /* Bump length if not fixed, wrap at max */
4752                 if (++bus->pktgen_len > bus->pktgen_maxlen)
4753                         bus->pktgen_len = (u16) bus->pktgen_minlen;
4754
4755                 /* Special case for burst mode: just send one request! */
4756                 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4757                         break;
4758         }
4759 }
4760
4761 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4762 {
4763         struct sk_buff *pkt;
4764         u8 *data;
4765
4766         /* Allocate the packet */
4767         pkt = bcm_pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
4768                 DHD_SDALIGN, true);
4769         if (!pkt) {
4770                 DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed!\n", __func__));
4771                 return;
4772         }
4773         PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4774         data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4775
4776         /* Fill in the test header */
4777         *data++ = SDPCM_TEST_SEND;
4778         *data++ = start;
4779         *data++ = (bus->pktgen_maxlen >> 0);
4780         *data++ = (bus->pktgen_maxlen >> 8);
4781
4782         /* Send it */
4783         if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4784                 bus->pktgen_fail++;
4785 }
4786
4787 static void dhdsdio_testrcv(dhd_bus_t *bus, struct sk_buff *pkt, uint seq)
4788 {
4789         u8 *data;
4790         uint pktlen;
4791
4792         u8 cmd;
4793         u8 extra;
4794         u16 len;
4795         u16 offset;
4796
4797         /* Check for min length */
4798         pktlen = pkt->len;
4799         if (pktlen < SDPCM_TEST_HDRLEN) {
4800                 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4801                            pktlen));
4802                 bcm_pkt_buf_free_skb(pkt, false);
4803                 return;
4804         }
4805
4806         /* Extract header fields */
4807         data = pkt->data;
4808         cmd = *data++;
4809         extra = *data++;
4810         len = *data++;
4811         len += *data++ << 8;
4812
4813         /* Check length for relevant commands */
4814         if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4815             || cmd == SDPCM_TEST_ECHORSP) {
4816                 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4817                         DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4818                                 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4819                                 pktlen, seq, cmd, extra, len));
4820                         bcm_pkt_buf_free_skb(pkt, false);
4821                         return;
4822                 }
4823         }
4824
4825         /* Process as per command */
4826         switch (cmd) {
4827         case SDPCM_TEST_ECHOREQ:
4828                 /* Rx->Tx turnaround ok (even on NDIS w/current
4829                          implementation) */
4830                 *(u8 *) (pkt->data) = SDPCM_TEST_ECHORSP;
4831                 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0) {
4832                         bus->pktgen_sent++;
4833                 } else {
4834                         bus->pktgen_fail++;
4835                         bcm_pkt_buf_free_skb(pkt, false);
4836                 }
4837                 bus->pktgen_rcvd++;
4838                 break;
4839
4840         case SDPCM_TEST_ECHORSP:
4841                 if (bus->ext_loop) {
4842                         bcm_pkt_buf_free_skb(pkt, false);
4843                         bus->pktgen_rcvd++;
4844                         break;
4845                 }
4846
4847                 for (offset = 0; offset < len; offset++, data++) {
4848                         if (*data != SDPCM_TEST_FILL(offset, extra)) {
4849                                 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4850                                         offset, len,
4851                                         SDPCM_TEST_FILL(offset, extra), *data));
4852                                 break;
4853                         }
4854                 }
4855                 bcm_pkt_buf_free_skb(pkt, false);
4856                 bus->pktgen_rcvd++;
4857                 break;
4858
4859         case SDPCM_TEST_DISCARD:
4860                 bcm_pkt_buf_free_skb(pkt, false);
4861                 bus->pktgen_rcvd++;
4862                 break;
4863
4864         case SDPCM_TEST_BURST:
4865         case SDPCM_TEST_SEND:
4866         default:
4867                 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
4868                         "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4869                         pktlen, seq, cmd, extra, len));
4870                 bcm_pkt_buf_free_skb(pkt, false);
4871                 break;
4872         }
4873
4874         /* For recv mode, stop at limie (and tell dongle to stop sending) */
4875         if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4876                 if (bus->pktgen_total
4877                     && (bus->pktgen_rcvd >= bus->pktgen_total)) {
4878                         bus->pktgen_count = 0;
4879                         dhdsdio_sdtest_set(bus, false);
4880                 }
4881         }
4882 }
4883 #endif                          /* SDTEST */
4884
4885 extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
4886 {
4887         dhd_bus_t *bus;
4888
4889         DHD_TIMER(("%s: Enter\n", __func__));
4890
4891         bus = dhdp->bus;
4892
4893         if (bus->dhd->dongle_reset)
4894                 return false;
4895
4896         /* Ignore the timer if simulating bus down */
4897         if (bus->sleeping)
4898                 return false;
4899
4900         dhd_os_sdlock(bus->dhd);
4901
4902         /* Poll period: check device if appropriate. */
4903         if (bus->poll && (++bus->polltick >= bus->pollrate)) {
4904                 u32 intstatus = 0;
4905
4906                 /* Reset poll tick */
4907                 bus->polltick = 0;
4908
4909                 /* Check device if no interrupts */
4910                 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
4911
4912                         if (!bus->dpc_sched) {
4913                                 u8 devpend;
4914                                 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
4915                                                           SDIOD_CCCR_INTPEND,
4916                                                           NULL);
4917                                 intstatus =
4918                                     devpend & (INTR_STATUS_FUNC1 |
4919                                                INTR_STATUS_FUNC2);
4920                         }
4921
4922                         /* If there is something, make like the ISR and
4923                                  schedule the DPC */
4924                         if (intstatus) {
4925                                 bus->pollcnt++;
4926                                 bus->ipend = true;
4927                                 if (bus->intr)
4928                                         bcmsdh_intr_disable(bus->sdh);
4929
4930                                 bus->dpc_sched = true;
4931                                 dhd_sched_dpc(bus->dhd);
4932
4933                         }
4934                 }
4935
4936                 /* Update interrupt tracking */
4937                 bus->lastintrs = bus->intrcount;
4938         }
4939 #ifdef DHD_DEBUG
4940         /* Poll for console output periodically */
4941         if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
4942                 bus->console.count += dhd_watchdog_ms;
4943                 if (bus->console.count >= dhd_console_ms) {
4944                         bus->console.count -= dhd_console_ms;
4945                         /* Make sure backplane clock is on */
4946                         dhdsdio_clkctl(bus, CLK_AVAIL, false);
4947                         if (dhdsdio_readconsole(bus) < 0)
4948                                 dhd_console_ms = 0;     /* On error,
4949                                                          stop trying */
4950                 }
4951         }
4952 #endif                          /* DHD_DEBUG */
4953
4954 #ifdef SDTEST
4955         /* Generate packets if configured */
4956         if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
4957                 /* Make sure backplane clock is on */
4958                 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4959                 bus->pktgen_tick = 0;
4960                 dhdsdio_pktgen(bus);
4961         }
4962 #endif
4963
4964         /* On idle timeout clear activity flag and/or turn off clock */
4965         if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
4966                 if (++bus->idlecount >= bus->idletime) {
4967                         bus->idlecount = 0;
4968                         if (bus->activity) {
4969                                 bus->activity = false;
4970                                 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
4971                         } else {
4972                                 dhdsdio_clkctl(bus, CLK_NONE, false);
4973                         }
4974                 }
4975         }
4976
4977         dhd_os_sdunlock(bus->dhd);
4978
4979         return bus->ipend;
4980 }
4981
4982 #ifdef DHD_DEBUG
4983 extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
4984 {
4985         dhd_bus_t *bus = dhdp->bus;
4986         u32 addr, val;
4987         int rv;
4988         struct sk_buff *pkt;
4989
4990         /* Address could be zero if CONSOLE := 0 in dongle Makefile */
4991         if (bus->console_addr == 0)
4992                 return -ENOTSUPP;
4993
4994         /* Exclusive bus access */
4995         dhd_os_sdlock(bus->dhd);
4996
4997         /* Don't allow input if dongle is in reset */
4998         if (bus->dhd->dongle_reset) {
4999                 dhd_os_sdunlock(bus->dhd);
5000                 return -EPERM;
5001         }
5002
5003         /* Request clock to allow SDIO accesses */
5004         BUS_WAKE(bus);
5005         /* No pend allowed since txpkt is called later, ht clk has to be on */
5006         dhdsdio_clkctl(bus, CLK_AVAIL, false);
5007
5008         /* Zero cbuf_index */
5009         addr = bus->console_addr + offsetof(rte_cons_t, cbuf_idx);
5010         val = cpu_to_le32(0);
5011         rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5012         if (rv < 0)
5013                 goto done;
5014
5015         /* Write message into cbuf */
5016         addr = bus->console_addr + offsetof(rte_cons_t, cbuf);
5017         rv = dhdsdio_membytes(bus, true, addr, (u8 *)msg, msglen);
5018         if (rv < 0)
5019                 goto done;
5020
5021         /* Write length into vcons_in */
5022         addr = bus->console_addr + offsetof(rte_cons_t, vcons_in);
5023         val = cpu_to_le32(msglen);
5024         rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
5025         if (rv < 0)
5026                 goto done;
5027
5028         /* Bump dongle by sending an empty event pkt.
5029          * sdpcm_sendup (RX) checks for virtual console input.
5030          */
5031         pkt = bcm_pkt_buf_get_skb(4 + SDPCM_RESERVE);
5032         if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5033                 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5034
5035 done:
5036         if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5037                 bus->activity = false;
5038                 dhdsdio_clkctl(bus, CLK_NONE, true);
5039         }
5040
5041         dhd_os_sdunlock(bus->dhd);
5042
5043         return rv;
5044 }
5045 #endif                          /* DHD_DEBUG */
5046
5047 #ifdef DHD_DEBUG
5048 static void dhd_dump_cis(uint fn, u8 *cis)
5049 {
5050         uint byte, tag, tdata;
5051         DHD_INFO(("Function %d CIS:\n", fn));
5052
5053         for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) {
5054                 if ((byte % 16) == 0)
5055                         DHD_INFO(("    "));
5056                 DHD_INFO(("%02x ", cis[byte]));
5057                 if ((byte % 16) == 15)
5058                         DHD_INFO(("\n"));
5059                 if (!tdata--) {
5060                         tag = cis[byte];
5061                         if (tag == 0xff)
5062                                 break;
5063                         else if (!tag)
5064                                 tdata = 0;
5065                         else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT)
5066                                 tdata = cis[byte + 1] + 1;
5067                         else
5068                                 DHD_INFO(("]"));
5069                 }
5070         }
5071         if ((byte % 16) != 15)
5072                 DHD_INFO(("\n"));
5073 }
5074 #endif                          /* DHD_DEBUG */
5075
5076 static bool dhdsdio_chipmatch(u16 chipid)
5077 {
5078         if (chipid == BCM4325_CHIP_ID)
5079                 return true;
5080         if (chipid == BCM4329_CHIP_ID)
5081                 return true;
5082         if (chipid == BCM4319_CHIP_ID)
5083                 return true;
5084         return false;
5085 }
5086
5087 static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5088                            u16 slot, u16 func, uint bustype, void *regsva,
5089                            void *sdh)
5090 {
5091         int ret;
5092         dhd_bus_t *bus;
5093
5094         /* Init global variables at run-time, not as part of the declaration.
5095          * This is required to support init/de-init of the driver.
5096          * Initialization
5097          * of globals as part of the declaration results in non-deterministic
5098          * behavior since the value of the globals may be different on the
5099          * first time that the driver is initialized vs subsequent
5100          * initializations.
5101          */
5102         dhd_txbound = DHD_TXBOUND;
5103         dhd_rxbound = DHD_RXBOUND;
5104         dhd_alignctl = true;
5105         sd1idle = true;
5106         dhd_readahead = true;
5107         retrydata = false;
5108         dhd_dongle_memsize = 0;
5109         dhd_txminmax = DHD_TXMINMAX;
5110
5111         forcealign = true;
5112
5113         dhd_common_init();
5114
5115         DHD_TRACE(("%s: Enter\n", __func__));
5116         DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5117
5118         /* We make assumptions about address window mappings */
5119         ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5120
5121         /* BCMSDH passes venid and devid based on CIS parsing -- but
5122          * low-power start
5123          * means early parse could fail, so here we should get either an ID
5124          * we recognize OR (-1) indicating we must request power first.
5125          */
5126         /* Check the Vendor ID */
5127         switch (venid) {
5128         case 0x0000:
5129         case PCI_VENDOR_ID_BROADCOM:
5130                 break;
5131         default:
5132                 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5133                 return NULL;
5134         }
5135
5136         /* Check the Device ID and make sure it's one that we support */
5137         switch (devid) {
5138         case BCM4325_D11DUAL_ID:        /* 4325 802.11a/g id */
5139         case BCM4325_D11G_ID:   /* 4325 802.11g 2.4Ghz band id */
5140         case BCM4325_D11A_ID:   /* 4325 802.11a 5Ghz band id */
5141                 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5142                 break;
5143         case BCM4329_D11NDUAL_ID:       /* 4329 802.11n dualband device */
5144         case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5145         case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5146         case 0x4329:
5147                 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5148                 break;
5149         case BCM4319_D11N_ID:   /* 4319 802.11n id */
5150         case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5151         case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5152                 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5153                 break;
5154         case 0:
5155                 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5156                           __func__));
5157                 break;
5158
5159         default:
5160                 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5161                            __func__, venid, devid));
5162                 return NULL;
5163         }
5164
5165         /* Allocate private bus interface state */
5166         bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5167         if (!bus) {
5168                 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5169                 goto fail;
5170         }
5171         bus->sdh = sdh;
5172         bus->cl_devid = (u16) devid;
5173         bus->bus = DHD_BUS;
5174         bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5175         bus->usebufpool = false;        /* Use bufpool if allocated,
5176                                          else use locally malloced rxbuf */
5177
5178         /* attempt to attach to the dongle */
5179         if (!(dhdsdio_probe_attach(bus, sdh, regsva, devid))) {
5180                 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5181                 goto fail;
5182         }
5183
5184         /* Attach to the dhd/OS/network interface */
5185         bus->dhd = dhd_attach(bus, SDPCM_RESERVE);
5186         if (!bus->dhd) {
5187                 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5188                 goto fail;
5189         }
5190
5191         /* Allocate buffers */
5192         if (!(dhdsdio_probe_malloc(bus, sdh))) {
5193                 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5194                 goto fail;
5195         }
5196
5197         if (!(dhdsdio_probe_init(bus, sdh))) {
5198                 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5199                 goto fail;
5200         }
5201
5202         /* Register interrupt callback, but mask it (not operational yet). */
5203         DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5204                   __func__));
5205         bcmsdh_intr_disable(sdh);
5206         ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5207         if (ret != 0) {
5208                 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5209                            __func__, ret));
5210                 goto fail;
5211         }
5212         DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5213
5214         DHD_INFO(("%s: completed!!\n", __func__));
5215
5216         /* if firmware path present try to download and bring up bus */
5217         ret = dhd_bus_start(bus->dhd);
5218         if (ret != 0) {
5219                 if (ret == -ENOLINK) {
5220                         DHD_ERROR(("%s: dongle is not responding\n", __func__));
5221                         goto fail;
5222                 }
5223         }
5224         /* Ok, have the per-port tell the stack we're open for business */
5225         if (dhd_net_attach(bus->dhd, 0) != 0) {
5226                 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5227                 goto fail;
5228         }
5229
5230         return bus;
5231
5232 fail:
5233         dhdsdio_release(bus);
5234         return NULL;
5235 }
5236
5237 static bool
5238 dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
5239 {
5240         u8 clkctl = 0;
5241         int err = 0;
5242
5243         bus->alp_only = true;
5244
5245         /* Return the window to backplane enumeration space for core access */
5246         if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5247                 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5248
5249 #ifdef DHD_DEBUG
5250         printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5251                bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5252
5253 #endif                          /* DHD_DEBUG */
5254
5255         /*
5256          * Force PLL off until dhdsdio_chip_attach()
5257          * programs PLL control regs
5258          */
5259
5260         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5261                          DHD_INIT_CLKCTL1, &err);
5262         if (!err)
5263                 clkctl =
5264                     bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5265                                     &err);
5266
5267         if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5268                 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5269                         "0x%02x read 0x%02x\n",
5270                         err, DHD_INIT_CLKCTL1, clkctl));
5271                 goto fail;
5272         }
5273 #ifdef DHD_DEBUG
5274         if (DHD_INFO_ON()) {
5275                 uint fn, numfn;
5276                 u8 *cis[SDIOD_MAX_IOFUNCS];
5277                 int err = 0;
5278
5279                 numfn = bcmsdh_query_iofnum(sdh);
5280                 ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
5281
5282                 /* Make sure ALP is available before trying to read CIS */
5283                 SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
5284                                                     SBSDIO_FUNC1_CHIPCLKCSR,
5285                                                     NULL)),
5286                           !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY);
5287
5288                 /* Now request ALP be put on the bus */
5289                 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5290                                  DHD_INIT_CLKCTL2, &err);
5291                 udelay(65);
5292
5293                 for (fn = 0; fn <= numfn; fn++) {
5294                         cis[fn] = kzalloc(SBSDIO_CIS_SIZE_LIMIT, GFP_ATOMIC);
5295                         if (!cis[fn]) {
5296                                 DHD_INFO(("dhdsdio_probe: fn %d cis malloc "
5297                                         "failed\n", fn));
5298                                 break;
5299                         }
5300
5301                         err = bcmsdh_cis_read(sdh, fn, cis[fn],
5302                                                 SBSDIO_CIS_SIZE_LIMIT);
5303                         if (err) {
5304                                 DHD_INFO(("dhdsdio_probe: fn %d cis read "
5305                                         "err %d\n", fn, err));
5306                                 kfree(cis[fn]);
5307                                 break;
5308                         }
5309                         dhd_dump_cis(fn, cis[fn]);
5310                 }
5311
5312                 while (fn-- > 0) {
5313                         ASSERT(cis[fn]);
5314                         kfree(cis[fn]);
5315                 }
5316
5317                 if (err) {
5318                         DHD_ERROR(("dhdsdio_probe: error read/parsing CIS\n"));
5319                         goto fail;
5320                 }
5321         }
5322 #endif                          /* DHD_DEBUG */
5323
5324         if (dhdsdio_chip_attach(bus, regsva)) {
5325                 DHD_ERROR(("%s: dhdsdio_chip_attach failed!\n", __func__));
5326                 goto fail;
5327         }
5328
5329         bcmsdh_chipinfo(sdh, bus->ci->chip, bus->ci->chiprev);
5330
5331         if (!dhdsdio_chipmatch((u16) bus->ci->chip)) {
5332                 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5333                            __func__, bus->ci->chip));
5334                 goto fail;
5335         }
5336
5337         dhdsdio_sdiod_drive_strength_init(bus, dhd_sdiod_drive_strength);
5338
5339         /* Get info on the ARM and SOCRAM cores... */
5340         if (!DHD_NOPMU(bus)) {
5341                 bus->armrev = SBCOREREV(bcmsdh_reg_read(bus->sdh,
5342                         CORE_SB(bus->ci->armcorebase, sbidhigh), 4));
5343                 bus->orig_ramsize = bus->ci->ramsize;
5344                 if (!(bus->orig_ramsize)) {
5345                         DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5346                                    __func__));
5347                         goto fail;
5348                 }
5349                 bus->ramsize = bus->orig_ramsize;
5350                 if (dhd_dongle_memsize)
5351                         dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5352
5353                 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5354                            bus->ramsize, bus->orig_ramsize));
5355         }
5356
5357         bus->regs = (void *)bus->ci->buscorebase;
5358
5359         /* Set core control so an SDIO reset does a backplane reset */
5360         OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
5361
5362         bcm_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
5363
5364         /* Locate an appropriately-aligned portion of hdrbuf */
5365         bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5366
5367         /* Set the poll and/or interrupt flags */
5368         bus->intr = (bool) dhd_intr;
5369         bus->poll = (bool) dhd_poll;
5370         if (bus->poll)
5371                 bus->pollrate = 1;
5372
5373         return true;
5374
5375 fail:
5376         return false;
5377 }
5378
5379 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh)
5380 {
5381         DHD_TRACE(("%s: Enter\n", __func__));
5382
5383         if (bus->dhd->maxctl) {
5384                 bus->rxblen =
5385                     roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5386                             ALIGNMENT) + DHD_SDALIGN;
5387                 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5388                 if (!(bus->rxbuf)) {
5389                         DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5390                                    __func__, bus->rxblen));
5391                         goto fail;
5392                 }
5393         }
5394
5395         /* Allocate buffer to receive glomed packet */
5396         bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5397         if (!(bus->databuf)) {
5398                 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5399                            __func__, MAX_DATA_BUF));
5400                 /* release rxbuf which was already located as above */
5401                 if (!bus->rxblen)
5402                         kfree(bus->rxbuf);
5403                 goto fail;
5404         }
5405
5406         /* Align the buffer */
5407         if ((unsigned long)bus->databuf % DHD_SDALIGN)
5408                 bus->dataptr =
5409                     bus->databuf + (DHD_SDALIGN -
5410                                     ((unsigned long)bus->databuf % DHD_SDALIGN));
5411         else
5412                 bus->dataptr = bus->databuf;
5413
5414         return true;
5415
5416 fail:
5417         return false;
5418 }
5419
5420 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh)
5421 {
5422         s32 fnum;
5423
5424         DHD_TRACE(("%s: Enter\n", __func__));
5425
5426 #ifdef SDTEST
5427         dhdsdio_pktgen_init(bus);
5428 #endif                          /* SDTEST */
5429
5430         /* Disable F2 to clear any intermediate frame state on the dongle */
5431         bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1,
5432                          NULL);
5433
5434         bus->dhd->busstate = DHD_BUS_DOWN;
5435         bus->sleeping = false;
5436         bus->rxflow = false;
5437         bus->prev_rxlim_hit = 0;
5438
5439         /* Done with backplane-dependent accesses, can drop clock... */
5440         bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5441
5442         /* ...and initialize clock/power states */
5443         bus->clkstate = CLK_SDONLY;
5444         bus->idletime = (s32) dhd_idletime;
5445         bus->idleclock = DHD_IDLE_ACTIVE;
5446
5447         /* Query the F2 block size, set roundup accordingly */
5448         fnum = 2;
5449         if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5450                             &bus->blocksize, sizeof(s32), false) != 0) {
5451                 bus->blocksize = 0;
5452                 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5453         } else {
5454                 DHD_INFO(("%s: Initial value for %s is %d\n",
5455                           __func__, "sd_blocksize", bus->blocksize));
5456         }
5457         bus->roundup = min(max_roundup, bus->blocksize);
5458
5459         /* Query if bus module supports packet chaining,
5460                  default to use if supported */
5461         if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5462                             &bus->sd_rxchain, sizeof(s32),
5463                             false) != 0) {
5464                 bus->sd_rxchain = false;
5465         } else {
5466                 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5467                           __func__,
5468                           (bus->sd_rxchain ? "supports" : "does not support")));
5469         }
5470         bus->use_rxchain = (bool) bus->sd_rxchain;
5471
5472         return true;
5473 }
5474
5475 bool
5476 dhd_bus_download_firmware(struct dhd_bus *bus, char *fw_path, char *nv_path)
5477 {
5478         bool ret;
5479         bus->fw_path = fw_path;
5480         bus->nv_path = nv_path;
5481
5482         ret = dhdsdio_download_firmware(bus, bus->sdh);
5483
5484         return ret;
5485 }
5486
5487 static bool
5488 dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh)
5489 {
5490         bool ret;
5491
5492         /* Download the firmware */
5493         dhdsdio_clkctl(bus, CLK_AVAIL, false);
5494
5495         ret = _dhdsdio_download_firmware(bus) == 0;
5496
5497         dhdsdio_clkctl(bus, CLK_SDONLY, false);
5498
5499         return ret;
5500 }
5501
5502 /* Detach and free everything */
5503 static void dhdsdio_release(dhd_bus_t *bus)
5504 {
5505         DHD_TRACE(("%s: Enter\n", __func__));
5506
5507         if (bus) {
5508                 /* De-register interrupt handler */
5509                 bcmsdh_intr_disable(bus->sdh);
5510                 bcmsdh_intr_dereg(bus->sdh);
5511
5512                 if (bus->dhd) {
5513                         dhd_detach(bus->dhd);
5514                         dhdsdio_release_dongle(bus);
5515                         bus->dhd = NULL;
5516                 }
5517
5518                 dhdsdio_release_malloc(bus);
5519
5520                 kfree(bus);
5521         }
5522
5523         DHD_TRACE(("%s: Disconnected\n", __func__));
5524 }
5525
5526 static void dhdsdio_release_malloc(dhd_bus_t *bus)
5527 {
5528         DHD_TRACE(("%s: Enter\n", __func__));
5529
5530         if (bus->dhd && bus->dhd->dongle_reset)
5531                 return;
5532
5533         if (bus->rxbuf) {
5534                 kfree(bus->rxbuf);
5535                 bus->rxctl = bus->rxbuf = NULL;
5536                 bus->rxlen = 0;
5537         }
5538
5539         kfree(bus->databuf);
5540         bus->databuf = NULL;
5541 }
5542
5543 static void dhdsdio_release_dongle(dhd_bus_t *bus)
5544 {
5545         DHD_TRACE(("%s: Enter\n", __func__));
5546
5547         if (bus->dhd && bus->dhd->dongle_reset)
5548                 return;
5549
5550         if (bus->ci) {
5551                 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5552                 dhdsdio_clkctl(bus, CLK_NONE, false);
5553                 dhdsdio_chip_detach(bus);
5554                 if (bus->vars && bus->varsz)
5555                         kfree(bus->vars);
5556                 bus->vars = NULL;
5557         }
5558
5559         DHD_TRACE(("%s: Disconnected\n", __func__));
5560 }
5561
5562 static void dhdsdio_disconnect(void *ptr)
5563 {
5564         dhd_bus_t *bus = (dhd_bus_t *)ptr;
5565
5566         DHD_TRACE(("%s: Enter\n", __func__));
5567
5568         if (bus) {
5569                 ASSERT(bus->dhd);
5570                 dhdsdio_release(bus);
5571         }
5572
5573         DHD_TRACE(("%s: Disconnected\n", __func__));
5574 }
5575
5576 /* Register/Unregister functions are called by the main DHD entry
5577  * point (e.g. module insertion) to link with the bus driver, in
5578  * order to look for or await the device.
5579  */
5580
5581 static bcmsdh_driver_t dhd_sdio = {
5582         dhdsdio_probe,
5583         dhdsdio_disconnect
5584 };
5585
5586 int dhd_bus_register(void)
5587 {
5588         DHD_TRACE(("%s: Enter\n", __func__));
5589
5590         return bcmsdh_register(&dhd_sdio);
5591 }
5592
5593 void dhd_bus_unregister(void)
5594 {
5595         DHD_TRACE(("%s: Enter\n", __func__));
5596
5597         bcmsdh_unregister();
5598 }
5599
5600 #ifdef BCMEMBEDIMAGE
5601 static int dhdsdio_download_code_array(struct dhd_bus *bus)
5602 {
5603         int bcmerror = -1;
5604         int offset = 0;
5605
5606         DHD_INFO(("%s: download embedded firmware...\n", __func__));
5607
5608         /* Download image */
5609         while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5610                 bcmerror =
5611                     dhdsdio_membytes(bus, true, offset, dlarray + offset,
5612                                      MEMBLOCK);
5613                 if (bcmerror) {
5614                         DHD_ERROR(("%s: error %d on writing %d membytes at "
5615                                 "0x%08x\n",
5616                                 __func__, bcmerror, MEMBLOCK, offset));
5617                         goto err;
5618                 }
5619
5620                 offset += MEMBLOCK;
5621         }
5622
5623         if (offset < sizeof(dlarray)) {
5624                 bcmerror = dhdsdio_membytes(bus, true, offset,
5625                                             dlarray + offset,
5626                                             sizeof(dlarray) - offset);
5627                 if (bcmerror) {
5628                         DHD_ERROR(("%s: error %d on writing %d membytes at "
5629                                 "0x%08x\n", __func__, bcmerror,
5630                                 sizeof(dlarray) - offset, offset));
5631                         goto err;
5632                 }
5633         }
5634 #ifdef DHD_DEBUG
5635         /* Upload and compare the downloaded code */
5636         {
5637                 unsigned char *ularray;
5638
5639                 ularray = kmalloc(bus->ramsize, GFP_ATOMIC);
5640                 if (!ularray) {
5641                         bcmerror = -ENOMEM;
5642                         goto err;
5643                 }
5644                 /* Upload image to verify downloaded contents. */
5645                 offset = 0;
5646                 memset(ularray, 0xaa, bus->ramsize);
5647                 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5648                         bcmerror =
5649                             dhdsdio_membytes(bus, false, offset,
5650                                              ularray + offset, MEMBLOCK);
5651                         if (bcmerror) {
5652                                 DHD_ERROR(("%s: error %d on reading %d membytes"
5653                                         " at 0x%08x\n",
5654                                         __func__, bcmerror, MEMBLOCK, offset));
5655                                 goto free;
5656                         }
5657
5658                         offset += MEMBLOCK;
5659                 }
5660
5661                 if (offset < sizeof(dlarray)) {
5662                         bcmerror = dhdsdio_membytes(bus, false, offset,
5663                                                     ularray + offset,
5664                                                     sizeof(dlarray) - offset);
5665                         if (bcmerror) {
5666                                 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
5667                                 __func__, bcmerror,
5668                                 sizeof(dlarray) - offset, offset));
5669                                 goto free;
5670                         }
5671                 }
5672
5673                 if (memcmp(dlarray, ularray, sizeof(dlarray))) {
5674                         DHD_ERROR(("%s: Downloaded image is corrupted.\n",
5675                                    __func__));
5676                         ASSERT(0);
5677                         goto free;
5678                 } else
5679                         DHD_ERROR(("%s: Download/Upload/Compare succeeded.\n",
5680                                 __func__));
5681 free:
5682                 kfree(ularray);
5683         }
5684 #endif                          /* DHD_DEBUG */
5685
5686 err:
5687         return bcmerror;
5688 }
5689 #endif                          /* BCMEMBEDIMAGE */
5690
5691 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5692 {
5693         int bcmerror = -1;
5694         int offset = 0;
5695         uint len;
5696         void *image = NULL;
5697         u8 *memblock = NULL, *memptr;
5698
5699         DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5700
5701         image = dhd_os_open_image(fw_path);
5702         if (image == NULL)
5703                 goto err;
5704
5705         memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5706         if (memblock == NULL) {
5707                 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5708                            __func__, MEMBLOCK));
5709                 goto err;
5710         }
5711         if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5712                 memptr +=
5713                     (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5714
5715         /* Download image */
5716         while ((len =
5717                 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5718                 bcmerror = dhdsdio_membytes(bus, true, offset, memptr, len);
5719                 if (bcmerror) {
5720                         DHD_ERROR(("%s: error %d on writing %d membytes at "
5721                         "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5722                         goto err;
5723                 }
5724
5725                 offset += MEMBLOCK;
5726         }
5727
5728 err:
5729         kfree(memblock);
5730
5731         if (image)
5732                 dhd_os_close_image(image);
5733
5734         return bcmerror;
5735 }
5736
5737 /*
5738  * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5739  * and ending in a NUL.
5740  * Removes carriage returns, empty lines, comment lines, and converts
5741  * newlines to NULs.
5742  * Shortens buffer as needed and pads with NULs.  End of buffer is marked
5743  * by two NULs.
5744 */
5745
5746 static uint process_nvram_vars(char *varbuf, uint len)
5747 {
5748         char *dp;
5749         bool findNewline;
5750         int column;
5751         uint buf_len, n;
5752
5753         dp = varbuf;
5754
5755         findNewline = false;
5756         column = 0;
5757
5758         for (n = 0; n < len; n++) {
5759                 if (varbuf[n] == 0)
5760                         break;
5761                 if (varbuf[n] == '\r')
5762                         continue;
5763                 if (findNewline && varbuf[n] != '\n')
5764                         continue;
5765                 findNewline = false;
5766                 if (varbuf[n] == '#') {
5767                         findNewline = true;
5768                         continue;
5769                 }
5770                 if (varbuf[n] == '\n') {
5771                         if (column == 0)
5772                                 continue;
5773                         *dp++ = 0;
5774                         column = 0;
5775                         continue;
5776                 }
5777                 *dp++ = varbuf[n];
5778                 column++;
5779         }
5780         buf_len = dp - varbuf;
5781
5782         while (dp < varbuf + n)
5783                 *dp++ = 0;
5784
5785         return buf_len;
5786 }
5787
5788 /*
5789         EXAMPLE: nvram_array
5790         nvram_arry format:
5791         name=value
5792         Use carriage return at the end of each assignment,
5793          and an empty string with
5794         carriage return at the end of array.
5795
5796         For example:
5797         unsigned char  nvram_array[] = {"name1=value1\n",
5798         "name2=value2\n", "\n"};
5799         Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5800
5801         Search "EXAMPLE: nvram_array" to see how the array is activated.
5802 */
5803
5804 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5805 {
5806         bus->nvram_params = nvram_params;
5807 }
5808
5809 static int dhdsdio_download_nvram(struct dhd_bus *bus)
5810 {
5811         int bcmerror = -1;
5812         uint len;
5813         void *image = NULL;
5814         char *memblock = NULL;
5815         char *bufp;
5816         char *nv_path;
5817         bool nvram_file_exists;
5818
5819         nv_path = bus->nv_path;
5820
5821         nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5822         if (!nvram_file_exists && (bus->nvram_params == NULL))
5823                 return 0;
5824
5825         if (nvram_file_exists) {
5826                 image = dhd_os_open_image(nv_path);
5827                 if (image == NULL)
5828                         goto err;
5829         }
5830
5831         memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5832         if (memblock == NULL) {
5833                 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5834                            __func__, MEMBLOCK));
5835                 goto err;
5836         }
5837
5838         /* Download variables */
5839         if (nvram_file_exists) {
5840                 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5841         } else {
5842                 len = strlen(bus->nvram_params);
5843                 ASSERT(len <= MEMBLOCK);
5844                 if (len > MEMBLOCK)
5845                         len = MEMBLOCK;
5846                 memcpy(memblock, bus->nvram_params, len);
5847         }
5848
5849         if (len > 0 && len < MEMBLOCK) {
5850                 bufp = (char *)memblock;
5851                 bufp[len] = 0;
5852                 len = process_nvram_vars(bufp, len);
5853                 bufp += len;
5854                 *bufp++ = 0;
5855                 if (len)
5856                         bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5857                 if (bcmerror) {
5858                         DHD_ERROR(("%s: error downloading vars: %d\n",
5859                                    __func__, bcmerror));
5860                 }
5861         } else {
5862                 DHD_ERROR(("%s: error reading nvram file: %d\n",
5863                            __func__, len));
5864                 bcmerror = -EIO;
5865         }
5866
5867 err:
5868         kfree(memblock);
5869
5870         if (image)
5871                 dhd_os_close_image(image);
5872
5873         return bcmerror;
5874 }
5875
5876 static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5877 {
5878         int bcmerror = -1;
5879
5880         bool embed = false;     /* download embedded firmware */
5881         bool dlok = false;      /* download firmware succeeded */
5882
5883         /* Out immediately if no image to download */
5884         if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
5885 #ifdef BCMEMBEDIMAGE
5886                 embed = true;
5887 #else
5888                 return bcmerror;
5889 #endif
5890         }
5891
5892         /* Keep arm in reset */
5893         if (dhdsdio_download_state(bus, true)) {
5894                 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5895                 goto err;
5896         }
5897
5898         /* External image takes precedence if specified */
5899         if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5900                 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5901                         DHD_ERROR(("%s: dongle image file download failed\n",
5902                                    __func__));
5903 #ifdef BCMEMBEDIMAGE
5904                         embed = true;
5905 #else
5906                         goto err;
5907 #endif
5908                 } else {
5909                         embed = false;
5910                         dlok = true;
5911                 }
5912         }
5913 #ifdef BCMEMBEDIMAGE
5914         if (embed) {
5915                 if (dhdsdio_download_code_array(bus)) {
5916                         DHD_ERROR(("%s: dongle image array download failed\n",
5917                                    __func__));
5918                         goto err;
5919                 } else {
5920                         dlok = true;
5921                 }
5922         }
5923 #endif
5924         if (!dlok) {
5925                 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5926                 goto err;
5927         }
5928
5929         /* EXAMPLE: nvram_array */
5930         /* If a valid nvram_arry is specified as above, it can be passed
5931                  down to dongle */
5932         /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5933
5934         /* External nvram takes precedence if specified */
5935         if (dhdsdio_download_nvram(bus)) {
5936                 DHD_ERROR(("%s: dongle nvram file download failed\n",
5937                            __func__));
5938         }
5939
5940         /* Take arm out of reset */
5941         if (dhdsdio_download_state(bus, false)) {
5942                 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5943                            __func__));
5944                 goto err;
5945         }
5946
5947         bcmerror = 0;
5948
5949 err:
5950         return bcmerror;
5951 }
5952
5953
5954 static int
5955 dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5956                     u8 *buf, uint nbytes, struct sk_buff *pkt,
5957                     bcmsdh_cmplt_fn_t complete, void *handle)
5958 {
5959         return bcmsdh_send_buf
5960                 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
5961                  handle);
5962 }
5963
5964 uint dhd_bus_chip(struct dhd_bus *bus)
5965 {
5966         ASSERT(bus->ci != NULL);
5967         return bus->ci->chip;
5968 }
5969
5970 void *dhd_bus_pub(struct dhd_bus *bus)
5971 {
5972         return bus->dhd;
5973 }
5974
5975 void *dhd_bus_txq(struct dhd_bus *bus)
5976 {
5977         return &bus->txq;
5978 }
5979
5980 uint dhd_bus_hdrlen(struct dhd_bus *bus)
5981 {
5982         return SDPCM_HDRLEN;
5983 }
5984
5985 int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
5986 {
5987         int bcmerror = 0;
5988         dhd_bus_t *bus;
5989
5990         bus = dhdp->bus;
5991
5992         if (flag == true) {
5993                 if (!bus->dhd->dongle_reset) {
5994                         /* Expect app to have torn down any
5995                          connection before calling */
5996                         /* Stop the bus, disable F2 */
5997                         dhd_bus_stop(bus, false);
5998
5999                         /* Clean tx/rx buffer pointers,
6000                          detach from the dongle */
6001                         dhdsdio_release_dongle(bus);
6002
6003                         bus->dhd->dongle_reset = true;
6004                         bus->dhd->up = false;
6005
6006                         DHD_TRACE(("%s:  WLAN OFF DONE\n", __func__));
6007                         /* App can now remove power from device */
6008                 } else
6009                         bcmerror = -EIO;
6010         } else {
6011                 /* App must have restored power to device before calling */
6012
6013                 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
6014
6015                 if (bus->dhd->dongle_reset) {
6016                         /* Turn on WLAN */
6017                         /* Reset SD client */
6018                         bcmsdh_reset(bus->sdh);
6019
6020                         /* Attempt to re-attach & download */
6021                         if (dhdsdio_probe_attach(bus, bus->sdh,
6022                                                  (u32 *) SI_ENUM_BASE,
6023                                                  bus->cl_devid)) {
6024                                 /* Attempt to download binary to the dongle */
6025                                 if (dhdsdio_probe_init
6026                                     (bus, bus->sdh)
6027                                     && dhdsdio_download_firmware(bus,
6028                                                                  bus->sdh)) {
6029
6030                                         /* Re-init bus, enable F2 transfer */
6031                                         dhd_bus_init((dhd_pub_t *) bus->dhd,
6032                                                      false);
6033
6034 #if defined(OOB_INTR_ONLY)
6035                                         dhd_enable_oob_intr(bus, true);
6036 #endif                          /* defined(OOB_INTR_ONLY) */
6037
6038                                         bus->dhd->dongle_reset = false;
6039                                         bus->dhd->up = true;
6040
6041                                         DHD_TRACE(("%s: WLAN ON DONE\n",
6042                                                    __func__));
6043                                 } else
6044                                         bcmerror = -EIO;
6045                         } else
6046                                 bcmerror = -EIO;
6047                 } else {
6048                         bcmerror = -EISCONN;
6049                         DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
6050                                 "is on\n", __func__));
6051                         bcmerror = -EIO;
6052                 }
6053         }
6054         return bcmerror;
6055 }
6056
6057 static int
6058 dhdsdio_chip_recognition(bcmsdh_info_t *sdh, struct chip_info *ci, void *regs)
6059 {
6060         u32 regdata;
6061
6062         /*
6063          * Get CC core rev
6064          * Chipid is assume to be at offset 0 from regs arg
6065          * For different chiptypes or old sdio hosts w/o chipcommon,
6066          * other ways of recognition should be added here.
6067          */
6068         ci->cccorebase = (u32)regs;
6069         regdata = bcmsdh_reg_read(sdh, CORE_CC_REG(ci->cccorebase, chipid), 4);
6070         ci->chip = regdata & CID_ID_MASK;
6071         ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
6072
6073         DHD_INFO(("%s: chipid=0x%x chiprev=%d\n",
6074                 __func__, ci->chip, ci->chiprev));
6075
6076         /* Address of cores for new chips should be added here */
6077         switch (ci->chip) {
6078         case BCM4329_CHIP_ID:
6079                 ci->buscorebase = BCM4329_CORE_BUS_BASE;
6080                 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
6081                 ci->armcorebase = BCM4329_CORE_ARM_BASE;
6082                 ci->ramsize = BCM4329_RAMSIZE;
6083                 break;
6084         default:
6085                 DHD_ERROR(("%s: chipid 0x%x is not supported\n",
6086                         __func__, ci->chip));
6087                 return -ENODEV;
6088         }
6089
6090         regdata = bcmsdh_reg_read(sdh,
6091                 CORE_SB(ci->cccorebase, sbidhigh), 4);
6092         ci->ccrev = SBCOREREV(regdata);
6093
6094         regdata = bcmsdh_reg_read(sdh,
6095                 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
6096         ci->pmurev = regdata & PCAP_REV_MASK;
6097
6098         regdata = bcmsdh_reg_read(sdh, CORE_SB(ci->buscorebase, sbidhigh), 4);
6099         ci->buscorerev = SBCOREREV(regdata);
6100         ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
6101
6102         DHD_INFO(("%s: ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
6103                 __func__, ci->ccrev, ci->pmurev,
6104                 ci->buscorerev, ci->buscoretype));
6105
6106         /* get chipcommon capabilites */
6107         ci->cccaps = bcmsdh_reg_read(sdh,
6108                 CORE_CC_REG(ci->cccorebase, capabilities), 4);
6109
6110         return 0;
6111 }
6112
6113 static void
6114 dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase)
6115 {
6116         u32 regdata;
6117
6118         regdata = bcmsdh_reg_read(sdh,
6119                 CORE_SB(corebase, sbtmstatelow), 4);
6120         if (regdata & SBTML_RESET)
6121                 return;
6122
6123         regdata = bcmsdh_reg_read(sdh,
6124                 CORE_SB(corebase, sbtmstatelow), 4);
6125         if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
6126                 /*
6127                  * set target reject and spin until busy is clear
6128                  * (preserve core-specific bits)
6129                  */
6130                 regdata = bcmsdh_reg_read(sdh,
6131                         CORE_SB(corebase, sbtmstatelow), 4);
6132                 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6133                         regdata | SBTML_REJ);
6134
6135                 regdata = bcmsdh_reg_read(sdh,
6136                         CORE_SB(corebase, sbtmstatelow), 4);
6137                 udelay(1);
6138                 SPINWAIT((bcmsdh_reg_read(sdh,
6139                         CORE_SB(corebase, sbtmstatehigh), 4) &
6140                         SBTMH_BUSY), 100000);
6141
6142                 regdata = bcmsdh_reg_read(sdh,
6143                         CORE_SB(corebase, sbtmstatehigh), 4);
6144                 if (regdata & SBTMH_BUSY)
6145                         DHD_ERROR(("%s: ARM core still busy\n", __func__));
6146
6147                 regdata = bcmsdh_reg_read(sdh,
6148                         CORE_SB(corebase, sbidlow), 4);
6149                 if (regdata & SBIDL_INIT) {
6150                         regdata = bcmsdh_reg_read(sdh,
6151                                 CORE_SB(corebase, sbimstate), 4) |
6152                                 SBIM_RJ;
6153                         bcmsdh_reg_write(sdh,
6154                                 CORE_SB(corebase, sbimstate), 4,
6155                                 regdata);
6156                         regdata = bcmsdh_reg_read(sdh,
6157                                 CORE_SB(corebase, sbimstate), 4);
6158                         udelay(1);
6159                         SPINWAIT((bcmsdh_reg_read(sdh,
6160                                 CORE_SB(corebase, sbimstate), 4) &
6161                                 SBIM_BY), 100000);
6162                 }
6163
6164                 /* set reset and reject while enabling the clocks */
6165                 bcmsdh_reg_write(sdh,
6166                         CORE_SB(corebase, sbtmstatelow), 4,
6167                         (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6168                         SBTML_REJ | SBTML_RESET));
6169                 regdata = bcmsdh_reg_read(sdh,
6170                         CORE_SB(corebase, sbtmstatelow), 4);
6171                 udelay(10);
6172
6173                 /* clear the initiator reject bit */
6174                 regdata = bcmsdh_reg_read(sdh,
6175                         CORE_SB(corebase, sbidlow), 4);
6176                 if (regdata & SBIDL_INIT) {
6177                         regdata = bcmsdh_reg_read(sdh,
6178                                 CORE_SB(corebase, sbimstate), 4) &
6179                                 ~SBIM_RJ;
6180                         bcmsdh_reg_write(sdh,
6181                                 CORE_SB(corebase, sbimstate), 4,
6182                                 regdata);
6183                 }
6184         }
6185
6186         /* leave reset and reject asserted */
6187         bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6188                 (SBTML_REJ | SBTML_RESET));
6189         udelay(1);
6190 }
6191
6192 static int
6193 dhdsdio_chip_attach(struct dhd_bus *bus, void *regs)
6194 {
6195         struct chip_info *ci;
6196         int err;
6197         u8 clkval, clkset;
6198
6199         DHD_TRACE(("%s: Enter\n", __func__));
6200
6201         /* alloc chip_info_t */
6202         ci = kmalloc(sizeof(struct chip_info), GFP_ATOMIC);
6203         if (NULL == ci) {
6204                 DHD_ERROR(("%s: malloc failed!\n", __func__));
6205                 return -ENOMEM;
6206         }
6207
6208         memset((unsigned char *)ci, 0, sizeof(struct chip_info));
6209
6210         /* bus/core/clk setup for register access */
6211         /* Try forcing SDIO core to do ALPAvail request only */
6212         clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
6213         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
6214                         clkset, &err);
6215         if (err) {
6216                 DHD_ERROR(("%s: error writing for HT off\n", __func__));
6217                 goto fail;
6218         }
6219
6220         /* If register supported, wait for ALPAvail and then force ALP */
6221         /* This may take up to 15 milliseconds */
6222         clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6223                         SBSDIO_FUNC1_CHIPCLKCSR, NULL);
6224         if ((clkval & ~SBSDIO_AVBITS) == clkset) {
6225                 SPINWAIT(((clkval =
6226                                 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6227                                                 SBSDIO_FUNC1_CHIPCLKCSR,
6228                                                 NULL)),
6229                                 !SBSDIO_ALPAV(clkval)),
6230                                 PMU_MAX_TRANSITION_DLY);
6231                 if (!SBSDIO_ALPAV(clkval)) {
6232                         DHD_ERROR(("%s: timeout on ALPAV wait, clkval 0x%02x\n",
6233                                 __func__, clkval));
6234                         err = -EBUSY;
6235                         goto fail;
6236                 }
6237                 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
6238                                 SBSDIO_FORCE_ALP;
6239                 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
6240                                 SBSDIO_FUNC1_CHIPCLKCSR,
6241                                 clkset, &err);
6242                 udelay(65);
6243         } else {
6244                 DHD_ERROR(("%s: ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
6245                         __func__, clkset, clkval));
6246                 err = -EACCES;
6247                 goto fail;
6248         }
6249
6250         /* Also, disable the extra SDIO pull-ups */
6251         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0,
6252                          NULL);
6253
6254         err = dhdsdio_chip_recognition(bus->sdh, ci, regs);
6255         if (err)
6256                 goto fail;
6257
6258         /*
6259          * Make sure any on-chip ARM is off (in case strapping is wrong),
6260          * or downloaded code was already running.
6261          */
6262         dhdsdio_chip_disablecore(bus->sdh, ci->armcorebase);
6263
6264         bcmsdh_reg_write(bus->sdh,
6265                 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
6266         bcmsdh_reg_write(bus->sdh,
6267                 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
6268
6269         /* Disable F2 to clear any intermediate frame state on the dongle */
6270         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
6271                 SDIO_FUNC_ENABLE_1, NULL);
6272
6273         /* WAR: cmd52 backplane read so core HW will drop ALPReq */
6274         clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
6275                         0, NULL);
6276
6277         /* Done with backplane-dependent accesses, can drop clock... */
6278         bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0,
6279                          NULL);
6280
6281         bus->ci = ci;
6282         return 0;
6283 fail:
6284         bus->ci = NULL;
6285         kfree(ci);
6286         return err;
6287 }
6288
6289 static void
6290 dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase)
6291 {
6292         u32 regdata;
6293
6294         /*
6295          * Must do the disable sequence first to work for
6296          * arbitrary current core state.
6297          */
6298         dhdsdio_chip_disablecore(sdh, corebase);
6299
6300         /*
6301          * Now do the initialization sequence.
6302          * set reset while enabling the clock and
6303          * forcing them on throughout the core
6304          */
6305         bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6306                 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
6307                 SBTML_RESET);
6308         udelay(1);
6309
6310         regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbtmstatehigh), 4);
6311         if (regdata & SBTMH_SERR)
6312                 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatehigh), 4, 0);
6313
6314         regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbimstate), 4);
6315         if (regdata & (SBIM_IBE | SBIM_TO))
6316                 bcmsdh_reg_write(sdh, CORE_SB(corebase, sbimstate), 4,
6317                         regdata & ~(SBIM_IBE | SBIM_TO));
6318
6319         /* clear reset and allow it to propagate throughout the core */
6320         bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6321                 (SICF_FGC << SBTML_SICF_SHIFT) |
6322                 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6323         udelay(1);
6324
6325         /* leave clock enabled */
6326         bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
6327                 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
6328         udelay(1);
6329 }
6330
6331 /* SDIO Pad drive strength to select value mappings */
6332 struct sdiod_drive_str {
6333         u8 strength;    /* Pad Drive Strength in mA */
6334         u8 sel;         /* Chip-specific select value */
6335 };
6336
6337 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
6338 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
6339         {
6340         4, 0x2}, {
6341         2, 0x3}, {
6342         1, 0x0}, {
6343         0, 0x0}
6344         };
6345
6346 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
6347 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
6348         {
6349         12, 0x7}, {
6350         10, 0x6}, {
6351         8, 0x5}, {
6352         6, 0x4}, {
6353         4, 0x2}, {
6354         2, 0x1}, {
6355         0, 0x0}
6356         };
6357
6358 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
6359 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
6360         {
6361         32, 0x7}, {
6362         26, 0x6}, {
6363         22, 0x5}, {
6364         16, 0x4}, {
6365         12, 0x3}, {
6366         8, 0x2}, {
6367         4, 0x1}, {
6368         0, 0x0}
6369         };
6370
6371 #define SDIOD_DRVSTR_KEY(chip, pmu)     (((chip) << 16) | (pmu))
6372
6373 static void
6374 dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus, u32 drivestrength) {
6375         struct sdiod_drive_str *str_tab = NULL;
6376         u32 str_mask = 0;
6377         u32 str_shift = 0;
6378         char chn[8];
6379
6380         if (!(bus->ci->cccaps & CC_CAP_PMU))
6381                 return;
6382
6383         switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
6384         case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
6385                 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
6386                 str_mask = 0x30000000;
6387                 str_shift = 28;
6388                 break;
6389         case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
6390         case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
6391                 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
6392                 str_mask = 0x00003800;
6393                 str_shift = 11;
6394                 break;
6395         case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
6396                 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
6397                 str_mask = 0x00003800;
6398                 str_shift = 11;
6399                 break;
6400         default:
6401                 DHD_ERROR(("No SDIO Drive strength init"
6402                         "done for chip %s rev %d pmurev %d\n",
6403                         bcm_chipname(bus->ci->chip, chn, 8),
6404                         bus->ci->chiprev, bus->ci->pmurev));
6405                 break;
6406         }
6407
6408         if (str_tab != NULL) {
6409                 u32 drivestrength_sel = 0;
6410                 u32 cc_data_temp;
6411                 int i;
6412
6413                 for (i = 0; str_tab[i].strength != 0; i++) {
6414                         if (drivestrength >= str_tab[i].strength) {
6415                                 drivestrength_sel = str_tab[i].sel;
6416                                 break;
6417                         }
6418                 }
6419
6420                 bcmsdh_reg_write(bus->sdh,
6421                         CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6422                         4, 1);
6423                 cc_data_temp = bcmsdh_reg_read(bus->sdh,
6424                         CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
6425                 cc_data_temp &= ~str_mask;
6426                 drivestrength_sel <<= str_shift;
6427                 cc_data_temp |= drivestrength_sel;
6428                 bcmsdh_reg_write(bus->sdh,
6429                         CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
6430                         4, cc_data_temp);
6431
6432                 DHD_INFO(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
6433                         drivestrength, cc_data_temp));
6434         }
6435 }
6436
6437 static void
6438 dhdsdio_chip_detach(struct dhd_bus *bus)
6439 {
6440         DHD_TRACE(("%s: Enter\n", __func__));
6441
6442         kfree(bus->ci);
6443         bus->ci = NULL;
6444 }