drivers/staging/bcm/DDRInit.c

   1 #include "headers.h"
   2
   3
   4
   5 #define DDR_DUMP_INTERNAL_DEVICE_MEMORY 0xBFC02B00
   6 #define MIPS_CLOCK_REG  0x0f000820
   7
   8     //DDR INIT-133Mhz
   9 #define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12  //index for 0x0F007000
  10 static DDR_SET_NODE asT3_DDRSetting133MHz[]= {//      # DPLL Clock Setting
  11                                         {0x0F000800,0x00007212},
  12                                         {0x0f000820,0x07F13FFF},
  13                                         {0x0f000810,0x00000F95},
  14                                         {0x0f000860,0x00000000},
  15                                         {0x0f000880,0x000003DD},
  16                                         // Changed source for X-bar and MIPS clock to APLL
  17                                         {0x0f000840,0x0FFF1B00},
  18                                         {0x0f000870,0x00000002},
  19                                         {0x0F00a044,0x1fffffff},
  20                                         {0x0F00a040,0x1f000000},
  21                                         {0x0F00a084,0x1Cffffff},
  22                                         {0x0F00a080,0x1C000000},
  23                                         {0x0F00a04C,0x0000000C},
  24                                         //Memcontroller Default values
  25                                         {0x0F007000,0x00010001},
  26                                         {0x0F007004,0x01010100},
  27                                         {0x0F007008,0x01000001},
  28                                         {0x0F00700c,0x00000000},
  29                                         {0x0F007010,0x01000000},
  30                                         {0x0F007014,0x01000100},
  31                                         {0x0F007018,0x01000000},
  32                                         {0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
  33                                         {0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
  34                                         {0x0F007024,0x02000007},
  35                                         {0x0F007028,0x02020202},
  36                                         {0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
  37                                         {0x0F007030,0x05000000},
  38                                         {0x0F007034,0x00000003},
  39                                         {0x0F007038,0x110a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
  40                                         {0x0F00703C,0x02101010},//ROB - 0x02101010,//0x02101018},
  41                                         {0x0F007040,0x45751200},//ROB - 0x45751200,//0x450f1200},
  42                                         {0x0F007044,0x110a0d00},//ROB - 0x110a0d00//0x111f0d00
  43                                         {0x0F007048,0x081b0306},
  44                                         {0x0F00704c,0x00000000},
  45                                         {0x0F007050,0x0000001c},
  46                                         {0x0F007054,0x00000000},
  47                                         {0x0F007058,0x00000000},
  48                                         {0x0F00705c,0x00000000},
  49                                         {0x0F007060,0x0010246c},
  50                                         {0x0F007064,0x00000010},
  51                                         {0x0F007068,0x00000000},
  52                                         {0x0F00706c,0x00000001},
  53                                         {0x0F007070,0x00007000},
  54                                         {0x0F007074,0x00000000},
  55                                         {0x0F007078,0x00000000},
  56                                         {0x0F00707C,0x00000000},
  57                                         {0x0F007080,0x00000000},
  58                                         {0x0F007084,0x00000000},
  59                                         //# Enable BW improvement within memory controller
  60                                         {0x0F007094,0x00000104},
  61                                         //# Enable 2 ports within X-bar
  62                                         {0x0F00A000,0x00000016},
  63                                         //# Enable start bit within memory controller
  64                                         {0x0F007018,0x01010000}
  65                                         };
  66 //80Mhz
  67 #define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10  //index for 0x0F007000
  68 static DDR_SET_NODE asT3_DDRSetting80MHz[]= {//   # DPLL Clock Setting
  69                                         {0x0f000810,0x00000F95},
  70                                         {0x0f000820,0x07f1ffff},
  71                                         {0x0f000860,0x00000000},
  72                                         {0x0f000880,0x000003DD},
  73                                         {0x0F00a044,0x1fffffff},
  74                                         {0x0F00a040,0x1f000000},
  75                                         {0x0F00a084,0x1Cffffff},
  76                                         {0x0F00a080,0x1C000000},
  77                                         {0x0F00a000,0x00000016},
  78                                         {0x0F00a04C,0x0000000C},
  79                                 //Memcontroller Default values
  80                                         {0x0F007000,0x00010001},
  81                                         {0x0F007004,0x01000000},
  82                                         {0x0F007008,0x01000001},
  83                                         {0x0F00700c,0x00000000},
  84                                         {0x0F007010,0x01000000},
  85                                         {0x0F007014,0x01000100},
  86                                         {0x0F007018,0x01000000},
  87                                         {0x0F00701c,0x01020000},
  88                                         {0x0F007020,0x04020107},
  89                                         {0x0F007024,0x00000007},
  90                                         {0x0F007028,0x02020201},
  91                                         {0x0F00702c,0x0204040a},
  92                                         {0x0F007030,0x04000000},
  93                                         {0x0F007034,0x00000002},
  94                                         {0x0F007038,0x1F060200},
  95                                         {0x0F00703C,0x1C22221F},
  96                                         {0x0F007040,0x8A006600},
  97                                         {0x0F007044,0x221a0800},
  98                                         {0x0F007048,0x02690204},
  99                                         {0x0F00704c,0x00000000},
 100                                         {0x0F007050,0x0000001c},
 101                                         {0x0F007054,0x00000000},
 102                                         {0x0F007058,0x00000000},
 103                                         {0x0F00705c,0x00000000},
 104                                         {0x0F007060,0x000A15D6},
 105                                         {0x0F007064,0x0000000A},
 106                                         {0x0F007068,0x00000000},
 107                                         {0x0F00706c,0x00000001},
 108                                         {0x0F007070,0x00004000},
 109                                         {0x0F007074,0x00000000},
 110                                         {0x0F007078,0x00000000},
 111                                         {0x0F00707C,0x00000000},
 112                                         {0x0F007080,0x00000000},
 113                                         {0x0F007084,0x00000000},
 114                                         {0x0F007094,0x00000104},
 115                                         //# Enable start bit within memory controller
 116                                                                                 {0x0F007018,0x01010000}
 117                                 };
 118 //100Mhz
 119 #define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13  //index for 0x0F007000
 120 static DDR_SET_NODE asT3_DDRSetting100MHz[]= {//  # DPLL Clock Setting
 121                                         {0x0F000800,0x00007008},
 122                                         {0x0f000810,0x00000F95},
 123                                         {0x0f000820,0x07F13E3F},
 124                                         {0x0f000860,0x00000000},
 125                                         {0x0f000880,0x000003DD},
 126                                 // Changed source for X-bar and MIPS clock to APLL
 127                                 //0x0f000840,0x0FFF1800,
 128                                         {0x0f000840,0x0FFF1B00},
 129                                         {0x0f000870,0x00000002},
 130                                         {0x0F00a044,0x1fffffff},
 131                                         {0x0F00a040,0x1f000000},
 132                                         {0x0F00a084,0x1Cffffff},
 133                                         {0x0F00a080,0x1C000000},
 134                                         {0x0F00a04C,0x0000000C},
 135                                 //# Enable 2 ports within X-bar
 136                                         {0x0F00A000,0x00000016},
 137                                 //Memcontroller Default values
 138                                         {0x0F007000,0x00010001},
 139                                         {0x0F007004,0x01010100},
 140                                         {0x0F007008,0x01000001},
 141                                         {0x0F00700c,0x00000000},
 142                                         {0x0F007010,0x01000000},
 143                                         {0x0F007014,0x01000100},
 144                                         {0x0F007018,0x01000000},
 145                                         {0x0F00701c,0x01020001}, // POP - 0x00020000 Normal 0x01020000
 146                                         {0x0F007020,0x04020107},//Normal - 0x04030107 POP - 0x05030107
 147                                         {0x0F007024,0x00000007},
 148                                         {0x0F007028,0x01020201},
 149                                         {0x0F00702c,0x0204040A},
 150                                         {0x0F007030,0x06000000},
 151                                         {0x0F007034,0x00000004},
 152                                         {0x0F007038,0x20080200},
 153                                         {0x0F00703C,0x02030320},
 154                                         {0x0F007040,0x6E7F1200},
 155                                         {0x0F007044,0x01190A00},
 156                                         {0x0F007048,0x06120305},//0x02690204 // 0x06120305
 157                                         {0x0F00704c,0x00000000},
 158                                         {0x0F007050,0x0000001C},
 159                                         {0x0F007054,0x00000000},
 160                                         {0x0F007058,0x00000000},
 161                                         {0x0F00705c,0x00000000},
 162                                         {0x0F007060,0x00082ED6},
 163                                         {0x0F007064,0x0000000A},
 164                                         {0x0F007068,0x00000000},
 165                                         {0x0F00706c,0x00000001},
 166                                         {0x0F007070,0x00005000},
 167                                         {0x0F007074,0x00000000},
 168                                         {0x0F007078,0x00000000},
 169                                         {0x0F00707C,0x00000000},
 170                                         {0x0F007080,0x00000000},
 171                                         {0x0F007084,0x00000000},
 172                                 //# Enable BW improvement within memory controller
 173                                         {0x0F007094,0x00000104},
 174                                 //# Enable start bit within memory controller
 175                                         {0x0F007018,0x01010000}
 176                                 };
 177
 178 //Net T3B DDR Settings
 179 //DDR INIT-133Mhz
 180 static DDR_SET_NODE asDPLL_266MHZ[] = {
 181                                         {0x0F000800,0x00007212},
 182                                         {0x0f000820,0x07F13FFF},
 183                                         {0x0f000810,0x00000F95},
 184                                         {0x0f000860,0x00000000},
 185                                         {0x0f000880,0x000003DD},
 186                                         // Changed source for X-bar and MIPS clock to APLL
 187                                         {0x0f000840,0x0FFF1B00},
 188                                         {0x0f000870,0x00000002}
 189                                                                           };
 190 #if 0
 191 static DDR_SET_NODE asDPLL_800MHZ[] = {
 192                                                                                 {0x0f000810,0x00000F95},
 193                                                                                 {0x0f000810,0x00000F95},
 194                                         {0x0f000810,0x00000F95},
 195                                         {0x0f000820,0x03F1365B},
 196                                         {0x0f000840,0x0FFF0000},
 197                                         {0x0f000880,0x000003DD},
 198                                         {0x0f000860,0x00000000}
 199                                                                           };
 200 #endif
 201
 202 #define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11  //index for 0x0F007000
 203 static DDR_SET_NODE asT3B_DDRSetting133MHz[] = {//      # DPLL Clock Setting
 204                                         {0x0f000810,0x00000F95},
 205                                         {0x0f000810,0x00000F95},
 206                                         {0x0f000810,0x00000F95},
 207                                         {0x0f000820,0x07F13652},
 208                                         {0x0f000840,0x0FFF0800},
 209                                         // Changed source for X-bar and MIPS clock to APLL
 210                                         {0x0f000880,0x000003DD},
 211                                         {0x0f000860,0x00000000},
 212                                         // Changed source for X-bar and MIPS clock to APLL
 213                                         {0x0F00a044,0x1fffffff},
 214                                         {0x0F00a040,0x1f000000},
 215                                         {0x0F00a084,0x1Cffffff},
 216                                         {0x0F00a080,0x1C000000},
 217                                         //# Enable 2 ports within X-bar
 218                                         {0x0F00A000,0x00000016},
 219                                         //Memcontroller Default values
 220                                         {0x0F007000,0x00010001},
 221                                         {0x0F007004,0x01010100},
 222                                         {0x0F007008,0x01000001},
 223                                         {0x0F00700c,0x00000000},
 224                                         {0x0F007010,0x01000000},
 225                                         {0x0F007014,0x01000100},
 226                                         {0x0F007018,0x01000000},
 227                                         {0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
 228                                         {0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
 229                                         {0x0F007024,0x02000007},
 230                                         {0x0F007028,0x02020202},
 231                                         {0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
 232                                         {0x0F007030,0x05000000},
 233                                         {0x0F007034,0x00000003},
 234                                         {0x0F007038,0x130a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
 235                                         {0x0F00703C,0x02101012},//ROB - 0x02101010,//0x02101018},
 236                                         {0x0F007040,0x457D1200},//ROB - 0x45751200,//0x450f1200},
 237                                         {0x0F007044,0x11130d00},//ROB - 0x110a0d00//0x111f0d00
 238                                         {0x0F007048,0x040D0306},
 239                                         {0x0F00704c,0x00000000},
 240                                         {0x0F007050,0x0000001c},
 241                                         {0x0F007054,0x00000000},
 242                                         {0x0F007058,0x00000000},
 243                                         {0x0F00705c,0x00000000},
 244                                         {0x0F007060,0x0010246c},
 245                                         {0x0F007064,0x00000012},
 246                                         {0x0F007068,0x00000000},
 247                                         {0x0F00706c,0x00000001},
 248                                         {0x0F007070,0x00007000},
 249                                         {0x0F007074,0x00000000},
 250                                         {0x0F007078,0x00000000},
 251                                         {0x0F00707C,0x00000000},
 252                                         {0x0F007080,0x00000000},
 253                                         {0x0F007084,0x00000000},
 254                                         //# Enable BW improvement within memory controller
 255                                         {0x0F007094,0x00000104},
 256                                         //# Enable start bit within memory controller
 257                                         {0x0F007018,0x01010000},
 258                                         };
 259
 260 #define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9  //index for 0x0F007000
 261 static DDR_SET_NODE asT3B_DDRSetting80MHz[] = {//       # DPLL Clock Setting
 262                                                                                 {0x0f000810,0x00000F95},
 263                                                                                 {0x0f000820,0x07F13FFF},
 264                                                                                 {0x0f000840,0x0FFF1F00},
 265                                                                                 {0x0f000880,0x000003DD},
 266                                                                                 {0x0f000860,0x00000000},
 267
 268                                                                                 {0x0F00a044,0x1fffffff},
 269                                                                                 {0x0F00a040,0x1f000000},
 270                                                                                 {0x0F00a084,0x1Cffffff},
 271                                                                                 {0x0F00a080,0x1C000000},
 272                                                                                 {0x0F00a000,0x00000016},
 273                                                                                 //Memcontroller Default values
 274                                                                                 {0x0F007000,0x00010001},
 275                                                                                 {0x0F007004,0x01000000},
 276                                                                                 {0x0F007008,0x01000001},
 277                                                                                 {0x0F00700c,0x00000000},
 278                                                                                 {0x0F007010,0x01000000},
 279                                                                                 {0x0F007014,0x01000100},
 280                                                                                 {0x0F007018,0x01000000},
 281                                                                                 {0x0F00701c,0x01020000},
 282                                                                                 {0x0F007020,0x04020107},
 283                                                                                 {0x0F007024,0x00000007},
 284                                                                                 {0x0F007028,0x02020201},
 285                                                                                 {0x0F00702c,0x0204040a},
 286                                                                                 {0x0F007030,0x04000000},
 287                                                                                 {0x0F007034,0x02000002},
 288                                                                                 {0x0F007038,0x1F060202},
 289                                                                                 {0x0F00703C,0x1C22221F},
 290                                                                                 {0x0F007040,0x8A006600},
 291                                                                                 {0x0F007044,0x221a0800},
 292                                                                                 {0x0F007048,0x02690204},
 293                                                                                 {0x0F00704c,0x00000000},
 294                                                                                 {0x0F007050,0x0100001c},
 295                                                                                 {0x0F007054,0x00000000},
 296                                                                                 {0x0F007058,0x00000000},
 297                                                                                 {0x0F00705c,0x00000000},
 298                                                                                 {0x0F007060,0x000A15D6},
 299                                                                                 {0x0F007064,0x0000000A},
 300                                                                                 {0x0F007068,0x00000000},
 301                                                                                 {0x0F00706c,0x00000001},
 302                                                                                 {0x0F007070,0x00004000},
 303                                                                                 {0x0F007074,0x00000000},
 304                                                                                 {0x0F007078,0x00000000},
 305                                                                                 {0x0F00707C,0x00000000},
 306                                                                                 {0x0F007080,0x00000000},
 307                                                                                 {0x0F007084,0x00000000},
 308                                                                                 {0x0F007094,0x00000104},
 309                                                                                 //# Enable start bit within memory controller
 310                                                                                 {0x0F007018,0x01010000}
 311                                                                 };
 312
 313 //100Mhz
 314 #define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9  //index for 0x0F007000
 315 static DDR_SET_NODE asT3B_DDRSetting100MHz[] = {//      # DPLL Clock Setting
 316                                                                                 {0x0f000810,0x00000F95},
 317                                                                                 {0x0f000820,0x07F1369B},
 318                                                                                 {0x0f000840,0x0FFF0800},
 319                                                                                 {0x0f000880,0x000003DD},
 320                                                                                 {0x0f000860,0x00000000},
 321                                                                                 {0x0F00a044,0x1fffffff},
 322                                                                                 {0x0F00a040,0x1f000000},
 323                                                                                 {0x0F00a084,0x1Cffffff},
 324                                                                                 {0x0F00a080,0x1C000000},
 325                                                                                 //# Enable 2 ports within X-bar
 326                                                                                 {0x0F00A000,0x00000016},
 327                                                                 //Memcontroller Default values
 328                                                                                 {0x0F007000,0x00010001},
 329                                                                                 {0x0F007004,0x01010100},
 330                                                                                 {0x0F007008,0x01000001},
 331                                                                                 {0x0F00700c,0x00000000},
 332                                                                                 {0x0F007010,0x01000000},
 333                                                                                 {0x0F007014,0x01000100},
 334                                                                                 {0x0F007018,0x01000000},
 335                                                                                 {0x0F00701c,0x01020000}, // POP - 0x00020000 Normal 0x01020000
 336                                                                                 {0x0F007020,0x04020107},//Normal - 0x04030107 POP - 0x05030107
 337                                                                                 {0x0F007024,0x00000007},
 338                                                                                 {0x0F007028,0x01020201},
 339                                                                                 {0x0F00702c,0x0204040A},
 340                                                                                 {0x0F007030,0x06000000},
 341                                                                                 {0x0F007034,0x02000004},
 342                                                                                 {0x0F007038,0x20080200},
 343                                                                                 {0x0F00703C,0x02030320},
 344                                                                                 {0x0F007040,0x6E7F1200},
 345                                                                                 {0x0F007044,0x01190A00},
 346                                                                                 {0x0F007048,0x06120305},//0x02690204 // 0x06120305
 347                                                                                 {0x0F00704c,0x00000000},
 348                                                                                 {0x0F007050,0x0100001C},
 349                                                                                 {0x0F007054,0x00000000},
 350                                                                                 {0x0F007058,0x00000000},
 351                                                                                 {0x0F00705c,0x00000000},
 352                                                                                 {0x0F007060,0x00082ED6},
 353                                                                                 {0x0F007064,0x0000000A},
 354                                                                                 {0x0F007068,0x00000000},
 355                                                                                 {0x0F00706c,0x00000001},
 356                                                                                 {0x0F007070,0x00005000},
 357                                                                                 {0x0F007074,0x00000000},
 358                                                                                 {0x0F007078,0x00000000},
 359                                                                                 {0x0F00707C,0x00000000},
 360                                                                                 {0x0F007080,0x00000000},
 361                                                                                 {0x0F007084,0x00000000},
 362                                                                 //# Enable BW improvement within memory controller
 363                                                                                 {0x0F007094,0x00000104},
 364                                                                 //# Enable start bit within memory controller
 365                                                                                 {0x0F007018,0x01010000}
 366                                                         };
 367
 368
 369 #define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9  //index for 0x0F007000
 370 static DDR_SET_NODE asT3LP_DDRSetting133MHz[]= {//      # DPLL Clock Setting
 371                                                                 {0x0f000820,0x03F1365B},
 372                                                                 {0x0f000810,0x00002F95},
 373                                                                 {0x0f000880,0x000003DD},
 374                                                                 // Changed source for X-bar and MIPS clock to APLL
 375                                                                 {0x0f000840,0x0FFF0000},
 376                                                                 {0x0f000860,0x00000000},
 377                                                                 {0x0F00a044,0x1fffffff},
 378                                                                 {0x0F00a040,0x1f000000},
 379                                                                 {0x0F00a084,0x1Cffffff},
 380                                                                 {0x0F00a080,0x1C000000},
 381                                                                 {0x0F00A000,0x00000016},
 382                                                                 //Memcontroller Default values
 383                                                                 {0x0F007000,0x00010001},
 384                                                                 {0x0F007004,0x01010100},
 385                                                                 {0x0F007008,0x01000001},
 386                                                                 {0x0F00700c,0x00000000},
 387                                                                 {0x0F007010,0x01000000},
 388                                                                 {0x0F007014,0x01000100},
 389                                                                 {0x0F007018,0x01000000},
 390                                                                 {0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
 391                                                                 {0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
 392                                                                 {0x0F007024,0x02000007},
 393                                                                 {0x0F007028,0x02020200},
 394                                                                 {0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
 395                                                                 {0x0F007030,0x05000000},
 396                                                                 {0x0F007034,0x00000003},
 397                                                                 {0x0F007038,0x200a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
 398                                                                 {0x0F00703C,0x02101020},//ROB - 0x02101010,//0x02101018,
 399                                                                 {0x0F007040,0x45711200},//ROB - 0x45751200,//0x450f1200,
 400                                                                 {0x0F007044,0x110D0D00},//ROB - 0x110a0d00//0x111f0d00
 401                                                                 {0x0F007048,0x04080306},
 402                                                                 {0x0F00704c,0x00000000},
 403                                                                 {0x0F007050,0x0100001c},
 404                                                                 {0x0F007054,0x00000000},
 405                                                                 {0x0F007058,0x00000000},
 406                                                                 {0x0F00705c,0x00000000},
 407                                                                 {0x0F007060,0x0010245F},
 408                                                                 {0x0F007064,0x00000010},
 409                                                                 {0x0F007068,0x00000000},
 410                                                                 {0x0F00706c,0x00000001},
 411                                                                 {0x0F007070,0x00007000},
 412                                                                 {0x0F007074,0x00000000},
 413                                                                 {0x0F007078,0x00000000},
 414                                                                 {0x0F00707C,0x00000000},
 415                                                                 {0x0F007080,0x00000000},
 416                                                                 {0x0F007084,0x00000000},
 417                                                                 {0x0F007088,0x01000001},
 418                                                                 {0x0F00708c,0x00000101},
 419                                                                 {0x0F007090,0x00000000},
 420                                                                 //# Enable BW improvement within memory controller
 421                                                                 {0x0F007094,0x00040000},
 422                                                                 {0x0F007098,0x00000000},
 423                                                                 {0x0F0070c8,0x00000104},
 424                                                                 //# Enable 2 ports within X-bar
 425                                                                 //# Enable start bit within memory controller
 426                                                                 {0x0F007018,0x01010000}
 427 };
 428
 429 #define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11  //index for 0x0F007000
 430 static DDR_SET_NODE asT3LP_DDRSetting100MHz[]= {//      # DPLL Clock Setting
 431                                                                 {0x0f000810,0x00002F95},
 432                                                                 {0x0f000820,0x03F1369B},
 433                                                                 {0x0f000840,0x0fff0000},
 434                                                                 {0x0f000860,0x00000000},
 435                                                                 {0x0f000880,0x000003DD},
 436                                                                 // Changed source for X-bar and MIPS clock to APLL
 437                                                                 {0x0f000840,0x0FFF0000},
 438                                                                 {0x0F00a044,0x1fffffff},
 439                                                                 {0x0F00a040,0x1f000000},
 440                                                                 {0x0F00a084,0x1Cffffff},
 441                                                                 {0x0F00a080,0x1C000000},
 442                                                                 //Memcontroller Default values
 443                                                                 {0x0F007000,0x00010001},
 444                                                                 {0x0F007004,0x01010100},
 445                                                                 {0x0F007008,0x01000001},
 446                                                                 {0x0F00700c,0x00000000},
 447                                                                 {0x0F007010,0x01000000},
 448                                                                 {0x0F007014,0x01000100},
 449                                                                 {0x0F007018,0x01000000},
 450                                                                 {0x0F00701c,0x01020000},// POP - 0x00020001 Normal 0x01020001
 451                                                                 {0x0F007020,0x04020107}, //Normal - 0x04030107 POP - 0x05030107
 452                                                                 {0x0F007024,0x00000007},
 453                                                                 {0x0F007028,0x01020200},
 454                                                                 {0x0F00702c,0x0204040a},//ROB- 0x0205050a,//0x0206060a
 455                                                                 {0x0F007030,0x06000000},
 456                                                                 {0x0F007034,0x00000004},
 457                                                                 {0x0F007038,0x1F080200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
 458                                                                 {0x0F00703C,0x0203031F},//ROB - 0x02101010,//0x02101018,
 459                                                                 {0x0F007040,0x6e001200},//ROB - 0x45751200,//0x450f1200,
 460                                                                 {0x0F007044,0x011a0a00},//ROB - 0x110a0d00//0x111f0d00
 461                                                                 {0x0F007048,0x03000305},
 462                                                                 {0x0F00704c,0x00000000},
 463                                                                 {0x0F007050,0x0100001c},
 464                                                                 {0x0F007054,0x00000000},
 465                                                                 {0x0F007058,0x00000000},
 466                                                                 {0x0F00705c,0x00000000},
 467                                                                 {0x0F007060,0x00082ED6},
 468                                                                 {0x0F007064,0x0000000A},
 469                                                                 {0x0F007068,0x00000000},
 470                                                                 {0x0F00706c,0x00000001},
 471                                                                 {0x0F007070,0x00005000},
 472                                                                 {0x0F007074,0x00000000},
 473                                                                 {0x0F007078,0x00000000},
 474                                                                 {0x0F00707C,0x00000000},
 475                                                                 {0x0F007080,0x00000000},
 476                                                                 {0x0F007084,0x00000000},
 477                                                                 {0x0F007088,0x01000001},
 478                                                                 {0x0F00708c,0x00000101},
 479                                                                 {0x0F007090,0x00000000},
 480                                                                 {0x0F007094,0x00010000},
 481                                                                 {0x0F007098,0x00000000},
 482                                                                 {0x0F0070C8,0x00000104},
 483                                                                 //# Enable 2 ports within X-bar
 484                                                                 {0x0F00A000,0x00000016},
 485                                                                 //# Enable start bit within memory controller
 486                                                                 {0x0F007018,0x01010000}
 487 };
 488
 489 #define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9  //index for 0x0F007000
 490 static DDR_SET_NODE asT3LP_DDRSetting80MHz[]= {//       # DPLL Clock Setting
 491                                                                 {0x0f000820,0x07F13FFF},
 492                                                                 {0x0f000810,0x00002F95},
 493                                                                 {0x0f000860,0x00000000},
 494                                                                 {0x0f000880,0x000003DD},
 495                                                                 {0x0f000840,0x0FFF1F00},
 496                                                                 {0x0F00a044,0x1fffffff},
 497                                                                 {0x0F00a040,0x1f000000},
 498                                                                 {0x0F00a084,0x1Cffffff},
 499                                                                 {0x0F00a080,0x1C000000},
 500                                                                 {0x0F00A000,0x00000016},
 501                                                                 {0x0f007000,0x00010001},
 502                                                                 {0x0f007004,0x01000000},
 503                                                                 {0x0f007008,0x01000001},
 504                                                                 {0x0f00700c,0x00000000},
 505                                                                 {0x0f007010,0x01000000},
 506                                                                 {0x0f007014,0x01000100},
 507                                                                 {0x0f007018,0x01000000},
 508                                                                 {0x0f00701c,0x01020000},
 509                                                                 {0x0f007020,0x04020107},
 510                                                                 {0x0f007024,0x00000007},
 511                                                                 {0x0f007028,0x02020200},
 512                                                                 {0x0f00702c,0x0204040a},
 513                                                                 {0x0f007030,0x04000000},
 514                                                                 {0x0f007034,0x00000002},
 515                                                                 {0x0f007038,0x1d060200},
 516                                                                 {0x0f00703c,0x1c22221d},
 517                                                                 {0x0f007040,0x8A116600},
 518                                                                 {0x0f007044,0x222d0800},
 519                                                                 {0x0f007048,0x02690204},
 520                                                                 {0x0f00704c,0x00000000},
 521                                                                 {0x0f007050,0x0100001c},
 522                                                                 {0x0f007054,0x00000000},
 523                                                                 {0x0f007058,0x00000000},
 524                                                                 {0x0f00705c,0x00000000},
 525                                                                 {0x0f007060,0x000A15D6},
 526                                                                 {0x0f007064,0x0000000A},
 527                                                                 {0x0f007068,0x00000000},
 528                                                                 {0x0f00706c,0x00000001},
 529                                                                 {0x0f007070,0x00004000},
 530                                                                 {0x0f007074,0x00000000},
 531                                                                 {0x0f007078,0x00000000},
 532                                                                 {0x0f00707c,0x00000000},
 533                                                                 {0x0f007080,0x00000000},
 534                                                                 {0x0f007084,0x00000000},
 535                                                                 {0x0f007088,0x01000001},
 536                                                                 {0x0f00708c,0x00000101},
 537                                                                 {0x0f007090,0x00000000},
 538                                                                 {0x0f007094,0x00010000},
 539                                                                 {0x0f007098,0x00000000},
 540                                                                 {0x0F0070C8,0x00000104},
 541                                                                 {0x0F007018,0x01010000}
 542 };
 543
 544
 545
 546
 547 ///T3 LP-B (UMA-B)
 548
 549 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7  //index for 0x0F007000
 550 static DDR_SET_NODE asT3LPB_DDRSetting160MHz[]= {//     # DPLL Clock Setting
 551
 552                                                                 {0x0f000820,0x03F137DB},
 553                                                                 {0x0f000810,0x01842795},
 554                                                                 {0x0f000860,0x00000000},
 555                                                                 {0x0f000880,0x000003DD},
 556                                                                 {0x0f000840,0x0FFF0400},
 557                                                                 {0x0F00a044,0x1fffffff},
 558                                                                 {0x0F00a040,0x1f000000},
 559                                                                 {0x0f003050,0x00000021},//this is flash/eeprom clock divisor which set the flash clock to 20 MHz
 560                                                                 {0x0F00a084,0x1Cffffff},//Now dump from her in internal memory
 561                                                                 {0x0F00a080,0x1C000000},
 562                                                                 {0x0F00A000,0x00000016},
 563                                                                 {0x0f007000,0x00010001},
 564                                                                 {0x0f007004,0x01000001},
 565                                                                 {0x0f007008,0x01000101},
 566                                                                 {0x0f00700c,0x00000000},
 567                                                                 {0x0f007010,0x01000100},
 568                                                                 {0x0f007014,0x01000100},
 569                                                                 {0x0f007018,0x01000000},
 570                                                                 {0x0f00701c,0x01020000},
 571                                                                 {0x0f007020,0x04030107},
 572                                                                 {0x0f007024,0x02000007},
 573                                                                 {0x0f007028,0x02020200},
 574                                                                 {0x0f00702c,0x0206060a},
 575                                                                 {0x0f007030,0x050d0d00},
 576                                                                 {0x0f007034,0x00000003},
 577                                                                 {0x0f007038,0x170a0200},
 578                                                                 {0x0f00703c,0x02101012},
 579                                                                 {0x0f007040,0x45161200},
 580                                                                 {0x0f007044,0x11250c00},
 581                                                                 {0x0f007048,0x04da0307},
 582                                                                 {0x0f00704c,0x00000000},
 583                                                                 {0x0f007050,0x0000001c},
 584                                                                 {0x0f007054,0x00000000},
 585                                                                 {0x0f007058,0x00000000},
 586                                                                 {0x0f00705c,0x00000000},
 587                                                                 {0x0f007060,0x00142bb6},
 588                                                                 {0x0f007064,0x20430014},
 589                                                                 {0x0f007068,0x00000000},
 590                                                                 {0x0f00706c,0x00000001},
 591                                                                 {0x0f007070,0x00009000},
 592                                                                 {0x0f007074,0x00000000},
 593                                                                 {0x0f007078,0x00000000},
 594                                                                 {0x0f00707c,0x00000000},
 595                                                                 {0x0f007080,0x00000000},
 596                                                                 {0x0f007084,0x00000000},
 597                                                                 {0x0f007088,0x01000001},
 598                                                                 {0x0f00708c,0x00000101},
 599                                                                 {0x0f007090,0x00000000},
 600                                                                 {0x0f007094,0x00040000},
 601                                                                 {0x0f007098,0x00000000},
 602                                                                 {0x0F0070C8,0x00000104},
 603                                                                 {0x0F007018,0x01010000}
 604 };
 605
 606
 607 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 7  //index for 0x0F007000
 608 static DDR_SET_NODE asT3LPB_DDRSetting133MHz[]= {//     # DPLL Clock Setting
 609                                                                 {0x0f000820,0x03F1365B},
 610                                                                 {0x0f000810,0x00002F95},
 611                                                                 {0x0f000880,0x000003DD},
 612                                                                 // Changed source for X-bar and MIPS clock to APLL
 613                                                                 {0x0f000840,0x0FFF0000},
 614                                                                 {0x0f000860,0x00000000},
 615                                                                 {0x0F00a044,0x1fffffff},
 616                                                                 {0x0F00a040,0x1f000000},
 617                                                                 {0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
 618                                                                 {0x0F00a084,0x1Cffffff},//dump from here in internal memory
 619                                                                 {0x0F00a080,0x1C000000},
 620                                                                 {0x0F00A000,0x00000016},
 621                                                                 //Memcontroller Default values
 622                                                                 {0x0F007000,0x00010001},
 623                                                                 {0x0F007004,0x01010100},
 624                                                                 {0x0F007008,0x01000001},
 625                                                                 {0x0F00700c,0x00000000},
 626                                                                 {0x0F007010,0x01000000},
 627                                                                 {0x0F007014,0x01000100},
 628                                                                 {0x0F007018,0x01000000},
 629                                                                 {0x0F00701c,0x01020001},// POP - 0x00020001 Normal 0x01020001
 630                                                                 {0x0F007020,0x04030107}, //Normal - 0x04030107 POP - 0x05030107
 631                                                                 {0x0F007024,0x02000007},
 632                                                                 {0x0F007028,0x02020200},
 633                                                                 {0x0F00702c,0x0206060a},//ROB- 0x0205050a,//0x0206060a
 634                                                                 {0x0F007030,0x05000000},
 635                                                                 {0x0F007034,0x00000003},
 636                                                                 {0x0F007038,0x190a0200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
 637                                                                 {0x0F00703C,0x02101017},//ROB - 0x02101010,//0x02101018,
 638                                                                 {0x0F007040,0x45171200},//ROB - 0x45751200,//0x450f1200,
 639                                                                 {0x0F007044,0x11290D00},//ROB - 0x110a0d00//0x111f0d00
 640                                                                 {0x0F007048,0x04080306},
 641                                                                 {0x0F00704c,0x00000000},
 642                                                                 {0x0F007050,0x0100001c},
 643                                                                 {0x0F007054,0x00000000},
 644                                                                 {0x0F007058,0x00000000},
 645                                                                 {0x0F00705c,0x00000000},
 646                                                                 {0x0F007060,0x0010245F},
 647                                                                 {0x0F007064,0x00000010},
 648                                                                 {0x0F007068,0x00000000},
 649                                                                 {0x0F00706c,0x00000001},
 650                                                                 {0x0F007070,0x00007000},
 651                                                                 {0x0F007074,0x00000000},
 652                                                                 {0x0F007078,0x00000000},
 653                                                                 {0x0F00707C,0x00000000},
 654                                                                 {0x0F007080,0x00000000},
 655                                                                 {0x0F007084,0x00000000},
 656                                                                 {0x0F007088,0x01000001},
 657                                                                 {0x0F00708c,0x00000101},
 658                                                                 {0x0F007090,0x00000000},
 659                                                                 //# Enable BW improvement within memory controller
 660                                                                 {0x0F007094,0x00040000},
 661                                                                 {0x0F007098,0x00000000},
 662                                                                 {0x0F0070c8,0x00000104},
 663                                                                 //# Enable 2 ports within X-bar
 664                                                                 //# Enable start bit within memory controller
 665                                                                 {0x0F007018,0x01010000}
 666 };
 667
 668 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 8  //index for 0x0F007000
 669 static DDR_SET_NODE asT3LPB_DDRSetting100MHz[]= {//     # DPLL Clock Setting
 670                                                                 {0x0f000810,0x00002F95},
 671                                                                 {0x0f000820,0x03F1369B},
 672                                                                 {0x0f000840,0x0fff0000},
 673                                                                 {0x0f000860,0x00000000},
 674                                                                 {0x0f000880,0x000003DD},
 675                                                                 // Changed source for X-bar and MIPS clock to APLL
 676                                                                 {0x0f000840,0x0FFF0000},
 677                                                                 {0x0F00a044,0x1fffffff},
 678                                                                 {0x0F00a040,0x1f000000},
 679                                                                 {0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
 680                                                                 {0x0F00a084,0x1Cffffff}, //dump from here in internal memory
 681                                                                 {0x0F00a080,0x1C000000},
 682                                                                 //Memcontroller Default values
 683                                                                 {0x0F007000,0x00010001},
 684                                                                 {0x0F007004,0x01010100},
 685                                                                 {0x0F007008,0x01000001},
 686                                                                 {0x0F00700c,0x00000000},
 687                                                                 {0x0F007010,0x01000000},
 688                                                                 {0x0F007014,0x01000100},
 689                                                                 {0x0F007018,0x01000000},
 690                                                                 {0x0F00701c,0x01020000},// POP - 0x00020001 Normal 0x01020001
 691                                                                 {0x0F007020,0x04020107}, //Normal - 0x04030107 POP - 0x05030107
 692                                                                 {0x0F007024,0x00000007},
 693                                                                 {0x0F007028,0x01020200},
 694                                                                 {0x0F00702c,0x0204040a},//ROB- 0x0205050a,//0x0206060a
 695                                                                 {0x0F007030,0x06000000},
 696                                                                 {0x0F007034,0x00000004},
 697                                                                 {0x0F007038,0x1F080200},//ROB - 0x110a0200,//0x180a0200,// 0x1f0a0200
 698                                                                 {0x0F00703C,0x0203031F},//ROB - 0x02101010,//0x02101018,
 699                                                                 {0x0F007040,0x6e001200},//ROB - 0x45751200,//0x450f1200,
 700                                                                 {0x0F007044,0x011a0a00},//ROB - 0x110a0d00//0x111f0d00
 701                                                                 {0x0F007048,0x03000305},
 702                                                                 {0x0F00704c,0x00000000},
 703                                                                 {0x0F007050,0x0100001c},
 704                                                                 {0x0F007054,0x00000000},
 705                                                                 {0x0F007058,0x00000000},
 706                                                                 {0x0F00705c,0x00000000},
 707                                                                 {0x0F007060,0x00082ED6},
 708                                                                 {0x0F007064,0x0000000A},
 709                                                                 {0x0F007068,0x00000000},
 710                                                                 {0x0F00706c,0x00000001},
 711                                                                 {0x0F007070,0x00005000},
 712                                                                 {0x0F007074,0x00000000},
 713                                                                 {0x0F007078,0x00000000},
 714                                                                 {0x0F00707C,0x00000000},
 715                                                                 {0x0F007080,0x00000000},
 716                                                                 {0x0F007084,0x00000000},
 717                                                                 {0x0F007088,0x01000001},
 718                                                                 {0x0F00708c,0x00000101},
 719                                                                 {0x0F007090,0x00000000},
 720                                                                 {0x0F007094,0x00010000},
 721                                                                 {0x0F007098,0x00000000},
 722                                                                 {0x0F0070C8,0x00000104},
 723                                                                 //# Enable 2 ports within X-bar
 724                                                                 {0x0F00A000,0x00000016},
 725                                                                 //# Enable start bit within memory controller
 726                                                                 {0x0F007018,0x01010000}
 727 };
 728
 729 #define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 7  //index for 0x0F007000
 730 static DDR_SET_NODE asT3LPB_DDRSetting80MHz[]= {//      # DPLL Clock Setting
 731                                                                 {0x0f000820,0x07F13FFF},
 732                                                                 {0x0f000810,0x00002F95},
 733                                                                 {0x0f000860,0x00000000},
 734                                                                 {0x0f000880,0x000003DD},
 735                                                                 {0x0f000840,0x0FFF1F00},
 736                                                                 {0x0F00a044,0x1fffffff},
 737                                                                 {0x0F00a040,0x1f000000},
 738                                                                 {0x0f003050,0x00000021},//flash/eeprom clock divisor which set the flash clock to 20 MHz
 739                                                                 {0x0F00a084,0x1Cffffff},// dump from here in internal memory
 740                                                                 {0x0F00a080,0x1C000000},
 741                                                                 {0x0F00A000,0x00000016},
 742                                                                 {0x0f007000,0x00010001},
 743                                                                 {0x0f007004,0x01000000},
 744                                                                 {0x0f007008,0x01000001},
 745                                                                 {0x0f00700c,0x00000000},
 746                                                                 {0x0f007010,0x01000000},
 747                                                                 {0x0f007014,0x01000100},
 748                                                                 {0x0f007018,0x01000000},
 749                                                                 {0x0f00701c,0x01020000},
 750                                                                 {0x0f007020,0x04020107},
 751                                                                 {0x0f007024,0x00000007},
 752                                                                 {0x0f007028,0x02020200},
 753                                                                 {0x0f00702c,0x0204040a},
 754                                                                 {0x0f007030,0x04000000},
 755                                                                 {0x0f007034,0x00000002},
 756                                                                 {0x0f007038,0x1d060200},
 757                                                                 {0x0f00703c,0x1c22221d},
 758                                                                 {0x0f007040,0x8A116600},
 759                                                                 {0x0f007044,0x222d0800},
 760                                                                 {0x0f007048,0x02690204},
 761                                                                 {0x0f00704c,0x00000000},
 762                                                                 {0x0f007050,0x0100001c},
 763                                                                 {0x0f007054,0x00000000},
 764                                                                 {0x0f007058,0x00000000},
 765                                                                 {0x0f00705c,0x00000000},
 766                                                                 {0x0f007060,0x000A15D6},
 767                                                                 {0x0f007064,0x0000000A},
 768                                                                 {0x0f007068,0x00000000},
 769                                                                 {0x0f00706c,0x00000001},
 770                                                                 {0x0f007070,0x00004000},
 771                                                                 {0x0f007074,0x00000000},
 772                                                                 {0x0f007078,0x00000000},
 773                                                                 {0x0f00707c,0x00000000},
 774                                                                 {0x0f007080,0x00000000},
 775                                                                 {0x0f007084,0x00000000},
 776                                                                 {0x0f007088,0x01000001},
 777                                                                 {0x0f00708c,0x00000101},
 778                                                                 {0x0f007090,0x00000000},
 779                                                                 {0x0f007094,0x00010000},
 780                                                                 {0x0f007098,0x00000000},
 781                                                                 {0x0F0070C8,0x00000104},
 782                                                                 {0x0F007018,0x01010000}
 783 };
 784
 785
 786 int ddr_init(MINI_ADAPTER *Adapter)
 787 {
 788         PDDR_SETTING psDDRSetting=NULL;
 789         ULONG RegCount=0;
 790         ULONG value = 0;
 791         UINT  uiResetValue = 0;
 792         UINT uiClockSetting = 0;
 793         int retval = STATUS_SUCCESS;
 794
 795     switch (Adapter->chip_id)
 796         {
 797         case 0xbece3200:
 798             switch (Adapter->DDRSetting)
 799             {
 800                 case DDR_80_MHZ:
 801                                 psDDRSetting=asT3LP_DDRSetting80MHz;
 802                             RegCount=(sizeof(asT3LP_DDRSetting80MHz)/
 803                                 sizeof(DDR_SETTING));
 804                             break;
 805                     case DDR_100_MHZ:
 806                                 psDDRSetting=asT3LP_DDRSetting100MHz;
 807                             RegCount=(sizeof(asT3LP_DDRSetting100MHz)/
 808                                 sizeof(DDR_SETTING));
 809                             break;
 810                     case DDR_133_MHZ:
 811                                 psDDRSetting=asT3LP_DDRSetting133MHz;
 812                             RegCount=(sizeof(asT3LP_DDRSetting133MHz)/
 813                                         sizeof(DDR_SETTING));
 814                                 if(Adapter->bMipsConfig == MIPS_200_MHZ)
 815                                 {
 816                                         uiClockSetting = 0x03F13652;
 817                                 }
 818                                 else
 819                                 {
 820                                         uiClockSetting = 0x03F1365B;
 821                                 }
 822                                 break;
 823                     default:
 824                             return -EINVAL;
 825         }
 826
 827                 break;
 828         case T3LPB:
 829         case BCS220_2:
 830         case BCS220_2BC:
 831         case BCS250_BC:
 832         case BCS220_3 :
 833                 /* Set bit 2 and bit 6 to 1 for BBIC 2mA drive
 834                  * (please check current value and additionally set these bits)
 835                  */
 836                 if( (Adapter->chip_id !=  BCS220_2) &&
 837                         (Adapter->chip_id !=  BCS220_2BC) &&
 838                         (Adapter->chip_id != BCS220_3) )
 839                 {
 840                                 retval= rdmalt(Adapter,(UINT)0x0f000830, &uiResetValue, sizeof(uiResetValue));
 841                                 if(retval < 0) {
 842                                         BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
 843                                         return retval;
 844                                 }
 845                                 uiResetValue |= 0x44;
 846                                 retval = wrmalt(Adapter,(UINT)0x0f000830, &uiResetValue, sizeof(uiResetValue));
 847                                 if(retval < 0) {
 848                                         BCM_DEBUG_PRINT(Adapter,CMHOST, WRM, DBG_LVL_ALL, "%s:%d WRM failed\n", __FUNCTION__, __LINE__);
 849                                         return retval;
 850                                 }
 851                 }
 852                 switch(Adapter->DDRSetting)
 853                 {
 854
 855
 856
 857                         case DDR_80_MHZ:
 858                                 psDDRSetting = asT3LPB_DDRSetting80MHz;
 859                         RegCount=(sizeof(asT3B_DDRSetting80MHz)/
 860                                   sizeof(DDR_SETTING));
 861                         break;
 862             case DDR_100_MHZ:
 863                                 psDDRSetting=asT3LPB_DDRSetting100MHz;
 864                         RegCount=(sizeof(asT3B_DDRSetting100MHz)/
 865                                  sizeof(DDR_SETTING));
 866                         break;
 867             case DDR_133_MHZ:
 868                                 psDDRSetting = asT3LPB_DDRSetting133MHz;
 869                                 RegCount=(sizeof(asT3B_DDRSetting133MHz)/
 870                                                  sizeof(DDR_SETTING));
 871
 872                                 if(Adapter->bMipsConfig == MIPS_200_MHZ)
 873                                 {
 874                                         uiClockSetting = 0x03F13652;
 875                                 }
 876                                 else
 877                                 {
 878                                         uiClockSetting = 0x03F1365B;
 879                                 }
 880                         break;
 881
 882                         case DDR_160_MHZ:
 883                                 psDDRSetting = asT3LPB_DDRSetting160MHz;
 884                                 RegCount = sizeof(asT3LPB_DDRSetting160MHz)/sizeof(DDR_SETTING);
 885
 886                                 if(Adapter->bMipsConfig == MIPS_200_MHZ)
 887                                 {
 888                                         uiClockSetting = 0x03F137D2;
 889                                 }
 890                                 else
 891                                 {
 892                                         uiClockSetting = 0x03F137DB;
 893                                 }
 894                         }
 895                         break;
 896
 897         case 0xbece0110:
 898         case 0xbece0120:
 899         case 0xbece0121:
 900         case 0xbece0130:
 901         case 0xbece0300:
 902                 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_INITEXIT, DRV_ENTRY, DBG_LVL_ALL, "DDR Setting: %x\n", Adapter->DDRSetting);
 903             switch (Adapter->DDRSetting)
 904             {
 905                 case DDR_80_MHZ:
 906                                 psDDRSetting = asT3_DDRSetting80MHz;
 907                             RegCount = (sizeof(asT3_DDRSetting80MHz)/
 908                                 sizeof(DDR_SETTING));
 909                             break;
 910                     case DDR_100_MHZ:
 911                                 psDDRSetting = asT3_DDRSetting100MHz;
 912                             RegCount = (sizeof(asT3_DDRSetting100MHz)/
 913                                 sizeof(DDR_SETTING));
 914                             break;
 915                     case DDR_133_MHZ:
 916                                 psDDRSetting = asT3_DDRSetting133MHz;
 917                             RegCount = (sizeof(asT3_DDRSetting133MHz)/
 918                                 sizeof(DDR_SETTING));
 919                                 break;
 920                     default:
 921                             return -EINVAL;
 922         }
 923         case 0xbece0310:
 924         {
 925             switch (Adapter->DDRSetting)
 926             {
 927                 case DDR_80_MHZ:
 928                                 psDDRSetting = asT3B_DDRSetting80MHz;
 929                         RegCount=(sizeof(asT3B_DDRSetting80MHz)/
 930                                   sizeof(DDR_SETTING));
 931                     break;
 932             case DDR_100_MHZ:
 933                                 psDDRSetting=asT3B_DDRSetting100MHz;
 934                         RegCount=(sizeof(asT3B_DDRSetting100MHz)/
 935                                  sizeof(DDR_SETTING));
 936                         break;
 937             case DDR_133_MHZ:
 938
 939                                 if(Adapter->bDPLLConfig == PLL_266_MHZ)//266Mhz PLL selected.
 940                                 {
 941                                         memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ,
 942                                                                          sizeof(asDPLL_266MHZ));
 943                                         psDDRSetting = asT3B_DDRSetting133MHz;
 944                                         RegCount=(sizeof(asT3B_DDRSetting133MHz)/
 945                                                                         sizeof(DDR_SETTING));
 946                                 }
 947                                 else
 948                                 {
 949                                         psDDRSetting = asT3B_DDRSetting133MHz;
 950                                         RegCount=(sizeof(asT3B_DDRSetting133MHz)/
 951                                                                         sizeof(DDR_SETTING));
 952                                         if(Adapter->bMipsConfig == MIPS_200_MHZ)
 953                                         {
 954                                                 uiClockSetting = 0x07F13652;
 955                                         }
 956                                         else
 957                                         {
 958                                                 uiClockSetting = 0x07F1365B;
 959                                         }
 960                                 }
 961                                 break;
 962                     default:
 963                             return -EINVAL;
 964                 }
 965                 break;
 966
 967         }
 968         default:
 969                 return -EINVAL;
 970         }
 971
 972         value=0;
 973         BCM_DEBUG_PRINT(Adapter,DBG_TYPE_INITEXIT, DRV_ENTRY, DBG_LVL_ALL, "Register Count is =%lu\n", RegCount);
 974         while(RegCount && !retval)
 975         {
 976                 if(uiClockSetting && psDDRSetting->ulRegAddress == MIPS_CLOCK_REG)
 977                 {
 978                         value = uiClockSetting;
 979                 }
 980                 else
 981                 {
 982                         value = psDDRSetting->ulRegValue;
 983                 }
 984                 retval = wrmalt(Adapter, psDDRSetting->ulRegAddress, (PUINT)&value, sizeof(value));
 985                 if(STATUS_SUCCESS != retval) {
 986                         BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
 987                         break;
 988                 }
 989
 990                 RegCount--;
 991                 psDDRSetting++;
 992         }
 993
 994         if(Adapter->chip_id >= 0xbece3300  )
 995         {
 996
 997                 mdelay(3);
 998                 if( (Adapter->chip_id != BCS220_2)&&
 999                         (Adapter->chip_id != BCS220_2BC)&&
1000                         (Adapter->chip_id != BCS220_3))
1001                 {
1002                         /* drive MDDR to half in case of UMA-B: */
1003                         uiResetValue = 0x01010001;
1004                         retval = wrmalt(Adapter, (UINT)0x0F007018, &uiResetValue, sizeof(uiResetValue));
1005                         if(retval < 0) {
1006                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1007                                 return retval;
1008                         }
1009                         uiResetValue = 0x00040020;
1010                         retval = wrmalt(Adapter, (UINT)0x0F007094, &uiResetValue, sizeof(uiResetValue));
1011                         if(retval < 0) {
1012                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1013                                 return retval;
1014                         }
1015                         uiResetValue = 0x01020101;
1016                         retval = wrmalt(Adapter, (UINT)0x0F00701c, &uiResetValue, sizeof(uiResetValue));
1017                         if(retval < 0) {
1018                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1019                                 return retval;
1020                         }
1021                         uiResetValue = 0x01010000;
1022                         retval = wrmalt(Adapter, (UINT)0x0F007018, &uiResetValue, sizeof(uiResetValue));
1023                         if(retval < 0) {
1024                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1025                                 return retval;
1026                         }
1027                 }
1028                 mdelay(3);
1029
1030                 /* DC/DC standby change...
1031                  * This is to be done only for Hybrid PMU mode.
1032                  * with the current h/w there is no way to detect this.
1033                  * and since we dont have internal PMU lets do it under UMA-B chip id.
1034              * we will change this when we will have internal PMU.
1035              */
1036                 if(Adapter->PmuMode == HYBRID_MODE_7C)
1037                 {
1038                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1039                         if(retval < 0) {
1040                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1041                                 return retval;
1042                         }
1043                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1044                         if(retval < 0) {
1045                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1046                                 return retval;
1047                         }
1048                         uiResetValue = 0x1322a8;
1049                         retval = wrmalt(Adapter, (UINT)0x0f000d1c, &uiResetValue, sizeof(uiResetValue));
1050                         if(retval < 0) {
1051                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1052                                 return retval;
1053                         }
1054                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1055                         if(retval < 0) {
1056                                 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1057                                 return retval;
1058                         }
1059                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1060                         if(retval < 0) {
1061                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1062                                 return retval;
1063                         }
1064                         uiResetValue = 0x132296;
1065                         retval = wrmalt(Adapter, (UINT)0x0f000d14, &uiResetValue, sizeof(uiResetValue));
1066                         if(retval < 0) {
1067                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1068                                 return retval;
1069                         }
1070                 }
1071                 else if(Adapter->PmuMode == HYBRID_MODE_6 )
1072                 {
1073
1074                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1075                         if(retval < 0) {
1076                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1077                                 return retval;
1078                         }
1079                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1080                         if(retval < 0) {
1081                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1082                                 return retval;
1083                         }
1084                         uiResetValue = 0x6003229a;
1085                         retval = wrmalt(Adapter, (UINT)0x0f000d14, &uiResetValue, sizeof(uiResetValue));
1086                         if(retval < 0) {
1087                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1088                                 return retval;
1089                         }
1090                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1091                         if(retval < 0) {
1092                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1093                                 return retval;
1094                         }
1095                         retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue));
1096                         if(retval < 0) {
1097                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1098                                 return retval;
1099                         }
1100                         uiResetValue = 0x1322a8;
1101                         retval = wrmalt(Adapter, (UINT)0x0f000d1c, &uiResetValue, sizeof(uiResetValue));
1102                         if(retval < 0) {
1103                                 BCM_DEBUG_PRINT(Adapter,CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __FUNCTION__, __LINE__);
1104                                 return retval;
1105                         }
1106                 }
1107
1108         }
1109         Adapter->bDDRInitDone = TRUE;
1110         return retval;
1111 }
1112
1113 int download_ddr_settings(PMINI_ADAPTER Adapter)
1114 {
1115         PDDR_SET_NODE psDDRSetting=NULL;
1116         ULONG RegCount=0;
1117         unsigned long ul_ddr_setting_load_addr = DDR_DUMP_INTERNAL_DEVICE_MEMORY;
1118         UINT  value = 0;
1119         int retval = STATUS_SUCCESS;
1120         BOOLEAN bOverrideSelfRefresh = FALSE;
1121
1122         switch (Adapter->chip_id)
1123         {
1124         case 0xbece3200:
1125             switch (Adapter->DDRSetting)
1126             {
1127                 case DDR_80_MHZ:
1128                                 psDDRSetting = asT3LP_DDRSetting80MHz;
1129                 RegCount = (sizeof(asT3LP_DDRSetting80MHz)/sizeof(DDR_SET_NODE));
1130                                 RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
1131                 psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1132                         break;
1133                     case DDR_100_MHZ:
1134                                 psDDRSetting = asT3LP_DDRSetting100MHz;
1135                             RegCount = (sizeof(asT3LP_DDRSetting100MHz)/sizeof(DDR_SET_NODE));
1136                                 RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
1137                 psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1138                             break;
1139                      case DDR_133_MHZ:
1140                                 bOverrideSelfRefresh = TRUE;
1141                                 psDDRSetting = asT3LP_DDRSetting133MHz;
1142                             RegCount = (sizeof(asT3LP_DDRSetting133MHz)/sizeof(DDR_SET_NODE));
1143                                 RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1144                         psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1145                                 break;
1146                         default:
1147                             return -EINVAL;
1148         }
1149                 break;
1150
1151         case T3LPB:
1152         case BCS220_2:
1153         case BCS220_2BC:
1154         case BCS250_BC:
1155         case BCS220_3 :
1156             switch (Adapter->DDRSetting)
1157             {
1158                 case DDR_80_MHZ:
1159                                 psDDRSetting = asT3LPB_DDRSetting80MHz;
1160                 RegCount=(sizeof(asT3LPB_DDRSetting80MHz)/sizeof(DDR_SET_NODE));
1161                                 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
1162                 psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1163                         break;
1164                     case DDR_100_MHZ:
1165                                 psDDRSetting = asT3LPB_DDRSetting100MHz;
1166                             RegCount = (sizeof(asT3LPB_DDRSetting100MHz)/sizeof(DDR_SET_NODE));
1167                                 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
1168                 psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1169                             break;
1170                      case DDR_133_MHZ:
1171                                 bOverrideSelfRefresh = TRUE;
1172                                 psDDRSetting = asT3LPB_DDRSetting133MHz;
1173                             RegCount = (sizeof(asT3LPB_DDRSetting133MHz)/sizeof(DDR_SET_NODE));
1174                                 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1175                         psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1176                                 break;
1177
1178                         case DDR_160_MHZ:
1179                                         bOverrideSelfRefresh = TRUE;
1180                                         psDDRSetting = asT3LPB_DDRSetting160MHz;
1181                                         RegCount = sizeof(asT3LPB_DDRSetting160MHz)/sizeof(DDR_SET_NODE);
1182                                         RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ;
1183                                         psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ;
1184
1185                                         break;
1186                         default:
1187                             return -EINVAL;
1188         }
1189                 break;
1190         case 0xbece0300:
1191             switch (Adapter->DDRSetting)
1192             {
1193                 case DDR_80_MHZ:
1194                                 psDDRSetting = asT3_DDRSetting80MHz;
1195                 RegCount = (sizeof(asT3_DDRSetting80MHz)/sizeof(DDR_SET_NODE));
1196                                 RegCount-=T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
1197                 psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1198                         break;
1199                     case DDR_100_MHZ:
1200                                 psDDRSetting = asT3_DDRSetting100MHz;
1201                             RegCount = (sizeof(asT3_DDRSetting100MHz)/sizeof(DDR_SET_NODE));
1202                                 RegCount-=T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
1203                 psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1204                             break;
1205                      case DDR_133_MHZ:
1206                                 psDDRSetting = asT3_DDRSetting133MHz;
1207                             RegCount = (sizeof(asT3_DDRSetting133MHz)/sizeof(DDR_SET_NODE));
1208                                 RegCount-=T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1209                         psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1210                                 break;
1211                         default:
1212                             return -EINVAL;
1213         }
1214         break;
1215         case 0xbece0310:
1216             {
1217                     switch (Adapter->DDRSetting)
1218                     {
1219                         case DDR_80_MHZ:
1220                                         psDDRSetting = asT3B_DDRSetting80MHz;
1221                     RegCount = (sizeof(asT3B_DDRSetting80MHz)/sizeof(DDR_SET_NODE));
1222                     RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ ;
1223                     psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1224                                 break;
1225                         case DDR_100_MHZ:
1226                                         psDDRSetting = asT3B_DDRSetting100MHz;
1227                                 RegCount = (sizeof(asT3B_DDRSetting100MHz)/sizeof(DDR_SET_NODE));
1228                     RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ ;
1229                     psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1230                                 break;
1231                         case DDR_133_MHZ:
1232                                         bOverrideSelfRefresh = TRUE;
1233                                         psDDRSetting = asT3B_DDRSetting133MHz;
1234                                 RegCount = (sizeof(asT3B_DDRSetting133MHz)/sizeof(DDR_SET_NODE));
1235                         RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ ;
1236                             psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1237                                         break;
1238                       }
1239                       break;
1240              }
1241         default:
1242                 return -EINVAL;
1243         }
1244         //total number of Register that has to be dumped
1245         value =RegCount  ;
1246         retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
1247         if(retval)
1248         {
1249                 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
1250
1251                 return retval;
1252         }
1253         ul_ddr_setting_load_addr+=sizeof(ULONG);
1254         /*signature */
1255         value =(0x1d1e0dd0);
1256         retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
1257         if(retval)
1258         {
1259                 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
1260                 return retval;
1261         }
1262
1263         ul_ddr_setting_load_addr+=sizeof(ULONG);
1264         RegCount*=(sizeof(DDR_SETTING)/sizeof(ULONG));
1265
1266         while(RegCount && !retval)
1267         {
1268                 value = psDDRSetting->ulRegAddress ;
1269                 retval = wrmalt( Adapter, ul_ddr_setting_load_addr, &value, sizeof(value));
1270                 ul_ddr_setting_load_addr+=sizeof(ULONG);
1271                 if(!retval)
1272                 {
1273                         if(bOverrideSelfRefresh && (psDDRSetting->ulRegAddress == 0x0F007018))
1274                         {
1275                                 value = (psDDRSetting->ulRegValue |(1<<8));
1276                                 if(STATUS_SUCCESS != wrmalt(Adapter, ul_ddr_setting_load_addr,
1277                                                 &value, sizeof(value))){
1278                                         BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
1279                                         break;
1280                                 }
1281                         }
1282                         else
1283                         {
1284                                 value =  psDDRSetting->ulRegValue;
1285
1286                                 if(STATUS_SUCCESS != wrmalt(Adapter, ul_ddr_setting_load_addr ,
1287                                                         &value, sizeof(value))){
1288                                         BCM_DEBUG_PRINT(Adapter,DBG_TYPE_PRINTK, 0, 0,"%s:%d\n", __FUNCTION__, __LINE__);
1289                                         break;
1290                                 }
1291                         }
1292                 }
1293                 ul_ddr_setting_load_addr+=sizeof(ULONG);
1294                 RegCount--;
1295                 psDDRSetting++;
1296         }
1297         return retval;
1298 }
1299
1300