1 //------------------------------------------------------------------------------
2 // <copyright file="target_reg_table.h" company="Atheros">
3 // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
6 // Permission to use, copy, modify, and/or distribute this software for any
7 // purpose with or without fee is hereby granted, provided that the above
8 // copyright notice and this permission notice appear in all copies.
10 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 //------------------------------------------------------------------------------
20 //==============================================================================
21 // Target register table macros and structure definitions
23 // Author(s): ="Atheros"
24 //==============================================================================
26 #ifndef TARGET_REG_TABLE_H_
27 #define TARGET_REG_TABLE_H_
29 #include "targaddrs.h"
31 /*** WARNING : Add to the end of the TABLE! do not change the order ****/
32 typedef struct targetdef_s {
33 u32 d_RTC_BASE_ADDRESS;
34 u32 d_SYSTEM_SLEEP_OFFSET;
35 u32 d_SYSTEM_SLEEP_DISABLE_LSB;
36 u32 d_SYSTEM_SLEEP_DISABLE_MASK;
37 u32 d_CLOCK_CONTROL_OFFSET;
38 u32 d_CLOCK_CONTROL_SI0_CLK_MASK;
39 u32 d_RESET_CONTROL_OFFSET;
40 u32 d_RESET_CONTROL_SI0_RST_MASK;
41 u32 d_GPIO_BASE_ADDRESS;
42 u32 d_GPIO_PIN0_OFFSET;
43 u32 d_GPIO_PIN1_OFFSET;
44 u32 d_GPIO_PIN0_CONFIG_MASK;
45 u32 d_GPIO_PIN1_CONFIG_MASK;
46 u32 d_SI_CONFIG_BIDIR_OD_DATA_LSB;
47 u32 d_SI_CONFIG_BIDIR_OD_DATA_MASK;
48 u32 d_SI_CONFIG_I2C_LSB;
49 u32 d_SI_CONFIG_I2C_MASK;
50 u32 d_SI_CONFIG_POS_SAMPLE_LSB;
51 u32 d_SI_CONFIG_POS_SAMPLE_MASK;
52 u32 d_SI_CONFIG_INACTIVE_CLK_LSB;
53 u32 d_SI_CONFIG_INACTIVE_CLK_MASK;
54 u32 d_SI_CONFIG_INACTIVE_DATA_LSB;
55 u32 d_SI_CONFIG_INACTIVE_DATA_MASK;
56 u32 d_SI_CONFIG_DIVIDER_LSB;
57 u32 d_SI_CONFIG_DIVIDER_MASK;
58 u32 d_SI_BASE_ADDRESS;
59 u32 d_SI_CONFIG_OFFSET;
60 u32 d_SI_TX_DATA0_OFFSET;
61 u32 d_SI_TX_DATA1_OFFSET;
62 u32 d_SI_RX_DATA0_OFFSET;
63 u32 d_SI_RX_DATA1_OFFSET;
65 u32 d_SI_CS_DONE_ERR_MASK;
66 u32 d_SI_CS_DONE_INT_MASK;
67 u32 d_SI_CS_START_LSB;
68 u32 d_SI_CS_START_MASK;
69 u32 d_SI_CS_RX_CNT_LSB;
70 u32 d_SI_CS_RX_CNT_MASK;
71 u32 d_SI_CS_TX_CNT_LSB;
72 u32 d_SI_CS_TX_CNT_MASK;
74 u32 d_BOARD_EXT_DATA_SZ;
75 } TARGET_REGISTER_TABLE;
77 #define BOARD_DATA_SZ_MAX 2048
79 #if defined(MY_TARGET_DEF) /* { */
81 #ifdef ATH_REG_TABLE_DIRECT_ASSIGN
83 static struct targetdef_s my_target_def = {
86 SYSTEM_SLEEP_DISABLE_LSB,
87 SYSTEM_SLEEP_DISABLE_MASK,
89 CLOCK_CONTROL_SI0_CLK_MASK,
91 RESET_CONTROL_SI0_RST_MASK,
94 GPIO_PIN0_CONFIG_MASK,
96 GPIO_PIN1_CONFIG_MASK,
97 SI_CONFIG_BIDIR_OD_DATA_LSB,
98 SI_CONFIG_BIDIR_OD_DATA_MASK,
101 SI_CONFIG_POS_SAMPLE_LSB,
102 SI_CONFIG_POS_SAMPLE_MASK,
103 SI_CONFIG_INACTIVE_CLK_LSB,
104 SI_CONFIG_INACTIVE_CLK_MASK,
105 SI_CONFIG_INACTIVE_DATA_LSB,
106 SI_CONFIG_INACTIVE_DATA_MASK,
107 SI_CONFIG_DIVIDER_LSB,
108 SI_CONFIG_DIVIDER_MASK,
124 MY_TARGET_BOARD_DATA_SZ,
125 MY_TARGET_BOARD_EXT_DATA_SZ,
130 static struct targetdef_s my_target_def = {
131 .d_RTC_BASE_ADDRESS = RTC_BASE_ADDRESS,
132 .d_SYSTEM_SLEEP_OFFSET = SYSTEM_SLEEP_OFFSET,
133 .d_SYSTEM_SLEEP_DISABLE_LSB = SYSTEM_SLEEP_DISABLE_LSB,
134 .d_SYSTEM_SLEEP_DISABLE_MASK = SYSTEM_SLEEP_DISABLE_MASK,
135 .d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET,
136 .d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK,
137 .d_RESET_CONTROL_OFFSET = RESET_CONTROL_OFFSET,
138 .d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK,
139 .d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS,
140 .d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET,
141 .d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK,
142 .d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET,
143 .d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK,
144 .d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB,
145 .d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK,
146 .d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB,
147 .d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK,
148 .d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB,
149 .d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK,
150 .d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB,
151 .d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK,
152 .d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB,
153 .d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK,
154 .d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB,
155 .d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK,
156 .d_SI_BASE_ADDRESS = SI_BASE_ADDRESS,
157 .d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET,
158 .d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET,
159 .d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET,
160 .d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET,
161 .d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET,
162 .d_SI_CS_OFFSET = SI_CS_OFFSET,
163 .d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK,
164 .d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK,
165 .d_SI_CS_START_LSB = SI_CS_START_LSB,
166 .d_SI_CS_START_MASK = SI_CS_START_MASK,
167 .d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB,
168 .d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK,
169 .d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB,
170 .d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK,
171 .d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ,
172 .d_BOARD_EXT_DATA_SZ = MY_TARGET_BOARD_EXT_DATA_SZ,
177 #if MY_TARGET_BOARD_DATA_SZ > BOARD_DATA_SZ_MAX
178 #error "BOARD_DATA_SZ_MAX is too small"
181 struct targetdef_s *MY_TARGET_DEF = &my_target_def;
185 #define RTC_BASE_ADDRESS (targetdef->d_RTC_BASE_ADDRESS)
186 #define SYSTEM_SLEEP_OFFSET (targetdef->d_SYSTEM_SLEEP_OFFSET)
187 #define SYSTEM_SLEEP_DISABLE_LSB (targetdef->d_SYSTEM_SLEEP_DISABLE_LSB)
188 #define SYSTEM_SLEEP_DISABLE_MASK (targetdef->d_SYSTEM_SLEEP_DISABLE_MASK)
189 #define CLOCK_CONTROL_OFFSET (targetdef->d_CLOCK_CONTROL_OFFSET)
190 #define CLOCK_CONTROL_SI0_CLK_MASK (targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
191 #define RESET_CONTROL_OFFSET (targetdef->d_RESET_CONTROL_OFFSET)
192 #define RESET_CONTROL_SI0_RST_MASK (targetdef->d_RESET_CONTROL_SI0_RST_MASK)
193 #define GPIO_BASE_ADDRESS (targetdef->d_GPIO_BASE_ADDRESS)
194 #define GPIO_PIN0_OFFSET (targetdef->d_GPIO_PIN0_OFFSET)
195 #define GPIO_PIN0_CONFIG_MASK (targetdef->d_GPIO_PIN0_CONFIG_MASK)
196 #define GPIO_PIN1_OFFSET (targetdef->d_GPIO_PIN1_OFFSET)
197 #define GPIO_PIN1_CONFIG_MASK (targetdef->d_GPIO_PIN1_CONFIG_MASK)
198 #define SI_CONFIG_BIDIR_OD_DATA_LSB (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
199 #define SI_CONFIG_BIDIR_OD_DATA_MASK (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
200 #define SI_CONFIG_I2C_LSB (targetdef->d_SI_CONFIG_I2C_LSB)
201 #define SI_CONFIG_I2C_MASK (targetdef->d_SI_CONFIG_I2C_MASK)
202 #define SI_CONFIG_POS_SAMPLE_LSB (targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
203 #define SI_CONFIG_POS_SAMPLE_MASK (targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
204 #define SI_CONFIG_INACTIVE_CLK_LSB (targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
205 #define SI_CONFIG_INACTIVE_CLK_MASK (targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
206 #define SI_CONFIG_INACTIVE_DATA_LSB (targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
207 #define SI_CONFIG_INACTIVE_DATA_MASK (targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
208 #define SI_CONFIG_DIVIDER_LSB (targetdef->d_SI_CONFIG_DIVIDER_LSB)
209 #define SI_CONFIG_DIVIDER_MASK (targetdef->d_SI_CONFIG_DIVIDER_MASK)
210 #define SI_BASE_ADDRESS (targetdef->d_SI_BASE_ADDRESS)
211 #define SI_CONFIG_OFFSET (targetdef->d_SI_CONFIG_OFFSET)
212 #define SI_TX_DATA0_OFFSET (targetdef->d_SI_TX_DATA0_OFFSET)
213 #define SI_TX_DATA1_OFFSET (targetdef->d_SI_TX_DATA1_OFFSET)
214 #define SI_RX_DATA0_OFFSET (targetdef->d_SI_RX_DATA0_OFFSET)
215 #define SI_RX_DATA1_OFFSET (targetdef->d_SI_RX_DATA1_OFFSET)
216 #define SI_CS_OFFSET (targetdef->d_SI_CS_OFFSET)
217 #define SI_CS_DONE_ERR_MASK (targetdef->d_SI_CS_DONE_ERR_MASK)
218 #define SI_CS_DONE_INT_MASK (targetdef->d_SI_CS_DONE_INT_MASK)
219 #define SI_CS_START_LSB (targetdef->d_SI_CS_START_LSB)
220 #define SI_CS_START_MASK (targetdef->d_SI_CS_START_MASK)
221 #define SI_CS_RX_CNT_LSB (targetdef->d_SI_CS_RX_CNT_LSB)
222 #define SI_CS_RX_CNT_MASK (targetdef->d_SI_CS_RX_CNT_MASK)
223 #define SI_CS_TX_CNT_LSB (targetdef->d_SI_CS_TX_CNT_LSB)
224 #define SI_CS_TX_CNT_MASK (targetdef->d_SI_CS_TX_CNT_MASK)
225 #define EEPROM_SZ (targetdef->d_BOARD_DATA_SZ)
226 #define EEPROM_EXT_SZ (targetdef->d_BOARD_EXT_DATA_SZ)
229 #define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
230 #define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
231 #define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
232 #define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
233 #define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
234 #define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
235 #define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
236 #define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
237 #define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
238 #define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
242 #endif /*TARGET_REG_TABLE_H_*/