1 //------------------------------------------------------------------------------
2 // Copyright (c) 2010 Atheros Corporation. All rights reserved.
5 // Permission to use, copy, modify, and/or distribute this software for any
6 // purpose with or without fee is hereby granted, provided that the above
7 // copyright notice and this permission notice appear in all copies.
9 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 // Author(s): ="Atheros"
20 //------------------------------------------------------------------------------
22 #ifndef __TARGADDRS_H__
23 #define __TARGADDRS_H__
26 #include "AR6002/addrs.h"
30 * AR6K option bits, to enable/disable various features.
31 * By default, all option bits are 0.
32 * These bits can be set in LOCAL_SCRATCH register 0.
34 #define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */
35 #define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */
36 #define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */
37 #define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */
38 #define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */
39 #define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */
40 #define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */
41 #define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */
44 * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
45 * host_interest structure. It must match the address of the _host_interest
46 * symbol (see linker script).
48 * Host Interest is shared between Host and Target in order to coordinate
49 * between the two, and is intended to remain constant (with additions only
50 * at the end) across software releases.
52 * All addresses are available here so that it's possible to
53 * write a single binary that works with all Target Types.
54 * May be used in assembler code as well as C.
56 #define AR6002_HOST_INTEREST_ADDRESS 0x00500400
57 #define AR6003_HOST_INTEREST_ADDRESS 0x00540600
60 #define HOST_INTEREST_MAX_SIZE 0x100
62 #if !defined(__ASSEMBLER__)
63 struct register_dump_s;
67 * These are items that the Host may need to access
68 * via BMI or via the Diagnostic Window. The position
69 * of items in this structure must remain constant
70 * across firmware revisions!
72 * Types for each item must be fixed size across
73 * target and host platforms.
75 * More items may be added at the end.
77 PREPACK struct host_interest_s {
79 * Pointer to application-defined area, if any.
80 * Set by Target application during startup.
82 u32 hi_app_host_interest; /* 0x00 */
84 /* Pointer to register dump area, valid after Target crash. */
85 u32 hi_failure_state; /* 0x04 */
87 /* Pointer to debug logging header */
88 u32 hi_dbglog_hdr; /* 0x08 */
90 u32 hi_unused1; /* 0x0c */
93 * General-purpose flag bits, similar to AR6000_OPTION_* flags.
94 * Can be used by application rather than by OS.
96 u32 hi_option_flag; /* 0x10 */
99 * Boolean that determines whether or not to
100 * display messages on the serial port.
102 u32 hi_serial_enable; /* 0x14 */
104 /* Start address of DataSet index, if any */
105 u32 hi_dset_list_head; /* 0x18 */
107 /* Override Target application start address */
108 u32 hi_app_start; /* 0x1c */
110 /* Clock and voltage tuning */
111 u32 hi_skip_clock_init; /* 0x20 */
112 u32 hi_core_clock_setting; /* 0x24 */
113 u32 hi_cpu_clock_setting; /* 0x28 */
114 u32 hi_system_sleep_setting; /* 0x2c */
115 u32 hi_xtal_control_setting; /* 0x30 */
116 u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
117 u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
118 u32 hi_ref_voltage_trim_setting; /* 0x3c */
119 u32 hi_clock_info; /* 0x40 */
122 * Flash configuration overrides, used only
123 * when firmware is not executing from flash.
124 * (When using flash, modify the global variables
125 * with equivalent names.)
127 u32 hi_bank0_addr_value; /* 0x44 */
128 u32 hi_bank0_read_value; /* 0x48 */
129 u32 hi_bank0_write_value; /* 0x4c */
130 u32 hi_bank0_config_value; /* 0x50 */
132 /* Pointer to Board Data */
133 u32 hi_board_data; /* 0x54 */
134 u32 hi_board_data_initialized; /* 0x58 */
136 u32 hi_dset_RAM_index_table; /* 0x5c */
138 u32 hi_desired_baud_rate; /* 0x60 */
139 u32 hi_dbglog_config; /* 0x64 */
140 u32 hi_end_RAM_reserve_sz; /* 0x68 */
141 u32 hi_mbox_io_block_sz; /* 0x6c */
143 u32 hi_num_bpatch_streams; /* 0x70 -- unused */
144 u32 hi_mbox_isr_yield_limit; /* 0x74 */
146 u32 hi_refclk_hz; /* 0x78 */
147 u32 hi_ext_clk_detected; /* 0x7c */
148 u32 hi_dbg_uart_txpin; /* 0x80 */
149 u32 hi_dbg_uart_rxpin; /* 0x84 */
150 u32 hi_hci_uart_baud; /* 0x88 */
151 u32 hi_hci_uart_pin_assignments; /* 0x8C */
152 /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
153 u32 hi_hci_uart_baud_scale_val; /* 0x90 */
154 u32 hi_hci_uart_baud_step_val; /* 0x94 */
156 u32 hi_allocram_start; /* 0x98 */
157 u32 hi_allocram_sz; /* 0x9c */
158 u32 hi_hci_bridge_flags; /* 0xa0 */
159 u32 hi_hci_uart_support_pins; /* 0xa4 */
160 /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
161 u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
163 * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
164 * [31:16]: wakeup timeout in ms
167 /* Pointer to extended board data */
168 u32 hi_board_ext_data; /* 0xac */
169 u32 hi_board_ext_data_config; /* 0xb0 */
176 * hi_reset_flag is used to do some stuff when target reset.
177 * such as restore app_start after warm reset or
178 * preserve host Interest area, or preserve ROM data, literals etc.
180 u32 hi_reset_flag; /* 0xb4 */
181 /* indicate hi_reset_flag is valid */
182 u32 hi_reset_flag_valid; /* 0xb8 */
183 u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
185 * 0xbc - [31:0]: idle timeout in ms
188 u32 hi_acs_flags; /* 0xc0 */
189 u32 hi_console_flags; /* 0xc4 */
190 u32 hi_nvram_state; /* 0xc8 */
191 u32 hi_option_flag2; /* 0xcc */
193 /* If non-zero, override values sent to Host in WMI_READY event. */
194 u32 hi_sw_version_override; /* 0xd0 */
195 u32 hi_abi_version_override; /* 0xd4 */
198 * Percentage of high priority RX traffic to total expected RX traffic -
199 * applicable only to ar6004
201 u32 hi_hp_rx_traffic_ratio; /* 0xd8 */
203 /* test applications flags */
204 u32 hi_test_apps_related ; /* 0xdc */
205 /* location of test script */
206 u32 hi_ota_testscript; /* 0xe0 */
207 /* location of CAL data */
208 u32 hi_cal_data; /* 0xe4 */
209 /* Number of packet log buffers */
210 u32 hi_pktlog_num_buffers; /* 0xe8 */
214 /* Bits defined in hi_option_flag */
215 #define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */
216 #define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */
217 #define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
218 /* MAC addr method 0-locally administred 1-globally unique addrs */
219 #define HI_OPTION_MAC_ADDR_METHOD 0x08
220 #define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */
221 #define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
222 #define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
223 #define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
224 #define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
225 #define HI_OPTION_NUM_DEV_LSB 0x200
226 #define HI_OPTION_NUM_DEV_MSB 0x800
227 #define HI_OPTION_DEV_MODE_LSB 0x1000
228 #define HI_OPTION_DEV_MODE_MSB 0x8000000
229 /* Disable LowFreq Timer Stabilization */
230 #define HI_OPTION_NO_LFT_STBL 0x10000000
231 #define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */
232 /* Do regulatory scan during init beforesending WMI ready event to host */
233 #define HI_OPTION_INIT_REG_SCAN 0x40000000
234 #define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory
237 /* hi_option_flag2 options */
238 #define HI_OPTION_OFFLOAD_AMSDU 0x01
239 #define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
241 #define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
243 /* 2 bits of hi_option_flag are used to represent 3 modes */
244 #define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
245 #define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
246 #define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
248 /* 2 bits of hi_option flag are usedto represent 4 submodes */
249 #define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
250 #define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
251 #define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
252 #define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
255 #define HI_OPTION_NUM_DEV_MASK 0x7
256 #define HI_OPTION_NUM_DEV_SHIFT 0x9
258 /* firmware bridging */
259 #define HI_OPTION_FW_BRIDGE_SHIFT 0x04
261 /* Fw Mode/SubMode Mask
262 |------------------------------------------------------------------------------|
263 | SUB | SUB | SUB | SUB | | | |
264 | MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0|
265 | (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2)
266 |------------------------------------------------------------------------------|
268 #define HI_OPTION_FW_MODE_BITS 0x2
269 #define HI_OPTION_FW_MODE_MASK 0x3
270 #define HI_OPTION_FW_MODE_SHIFT 0xC
271 #define HI_OPTION_ALL_FW_MODE_MASK 0xFF
273 #define HI_OPTION_FW_SUBMODE_BITS 0x2
274 #define HI_OPTION_FW_SUBMODE_MASK 0x3
275 #define HI_OPTION_FW_SUBMODE_SHIFT 0x14
276 #define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00
277 #define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
281 /* preserve App Start address */
282 #define HI_RESET_FLAG_PRESERVE_APP_START 0x01
283 /* preserve host interest */
284 #define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02
285 #define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */
286 #define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08
287 #define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10
289 #define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is
292 #define ON_RESET_FLAGS_VALID() \
293 (HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID)
295 #define RESET_FLAGS_VALIDATE() \
296 (HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID)
298 #define RESET_FLAGS_INVALIDATE() \
299 (HOST_INTEREST->hi_reset_flag_valid = 0)
301 #define ON_RESET_PRESERVE_APP_START() \
302 (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START)
304 #define ON_RESET_PRESERVE_NVRAM_STATE() \
305 (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE)
307 #define ON_RESET_PRESERVE_HOST_INTEREST() \
308 (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST)
310 #define ON_RESET_PRESERVE_ROMDATA() \
311 (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA)
313 #define ON_RESET_PRESERVE_BOOT_INFO() \
314 (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO)
316 #define HI_ACS_FLAGS_ENABLED (1 << 0) /* ACS is enabled */
317 #define HI_ACS_FLAGS_USE_WWAN (1 << 1) /* Use physical WWAN device */
318 #define HI_ACS_FLAGS_TEST_VAP (1 << 2) /* Use test VAP */
323 * --------- --------------------------------
324 * 2..0 UART ID (0 = Default)
325 * 3 Baud Select (0 = 9600, 1 = 115200)
331 #define HI_CONSOLE_FLAGS_ENABLE (1 << 31)
332 #define HI_CONSOLE_FLAGS_UART_MASK (0x7)
333 #define HI_CONSOLE_FLAGS_UART_SHIFT 0
334 #define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3)
337 * Intended for use by Host software, this macro returns the Target RAM
338 * address of any item in the host_interest structure.
339 * Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
341 #define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
342 (u32)((unsigned long)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
344 #define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
345 (u32)((unsigned long)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
347 #define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \
348 ((u32)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item)))
351 #define HOST_INTEREST_DBGLOG_IS_ENABLED() \
352 (!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
354 #define HOST_INTEREST_PKTLOG_IS_ENABLED() \
355 ((HOST_INTEREST->hi_pktlog_num_buffers))
358 #define HOST_INTEREST_PROFILE_IS_ENABLED() \
359 (HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
361 #define LF_TIMER_STABILIZATION_IS_ENABLED() \
362 (!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL))
364 #define IS_AMSDU_OFFLAOD_ENABLED() \
365 ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU))
367 #define HOST_INTEREST_DFS_IS_ENABLED() \
368 ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT))
370 /* Convert a Target virtual address into a Target physical address */
371 #define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
372 #define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
373 #define TARG_VTOP(TargetType, vaddr) \
374 (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr))
376 #define AR6003_REV2_APP_START_OVERRIDE 0x944C00
377 #define AR6003_REV2_APP_LOAD_ADDRESS 0x543180
378 #define AR6003_REV2_BOARD_EXT_DATA_ADDRESS 0x57E500
379 #define AR6003_REV2_DATASET_PATCH_ADDRESS 0x57e884
380 #define AR6003_REV2_RAM_RESERVE_SIZE 6912
382 #define AR6003_REV3_APP_START_OVERRIDE 0x945d00
383 #define AR6003_REV3_APP_LOAD_ADDRESS 0x545000
384 #define AR6003_REV3_BOARD_EXT_DATA_ADDRESS 0x542330
385 #define AR6003_REV3_DATASET_PATCH_ADDRESS 0x57FF74
386 #define AR6003_REV3_RAM_RESERVE_SIZE 512
388 #define AR6003_BOARD_EXT_DATA_ADDRESS 0x57E600
390 /* # of u32 entries in targregs, used by DIAG_FETCH_TARG_REGS */
391 #define AR6003_FETCH_TARG_REGS_COUNT 64
393 #endif /* !__ASSEMBLER__ */
395 #endif /* __TARGADDRS_H__ */