2 * Sonics Silicon Backplane
3 * Broadcom ChipCommon core driver
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/ssb/ssb.h>
12 #include <linux/ssb/ssb_regs.h>
13 #include <linux/pci.h>
15 #include "ssb_private.h"
21 SSB_CHIPCO_CLKSRC_PCI,
22 /* Crystal slow clock oscillator */
23 SSB_CHIPCO_CLKSRC_XTALOS,
24 /* Low power oscillator */
25 SSB_CHIPCO_CLKSRC_LOPWROS,
29 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
33 value |= chipco_read32(cc, offset) & ~mask;
34 chipco_write32(cc, offset, value);
39 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
40 enum ssb_clkmode mode)
42 struct ssb_device *ccdev = cc->dev;
49 /* chipcommon cores prior to rev6 don't support dynamic clock control */
50 if (ccdev->id.revision < 6)
52 /* chipcommon cores rev10 are a whole new ball game */
53 if (ccdev->id.revision >= 10)
55 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
59 case SSB_CLKMODE_SLOW:
60 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
61 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
62 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
64 case SSB_CLKMODE_FAST:
65 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
66 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
67 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
68 tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
69 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
71 case SSB_CLKMODE_DYNAMIC:
72 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
73 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
74 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
75 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
76 if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
77 tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
78 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
80 /* for dynamic control, we have to release our xtal_pu "force on" */
81 if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
82 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
89 /* Get the Slow Clock Source */
90 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
92 struct ssb_bus *bus = cc->dev->bus;
93 u32 uninitialized_var(tmp);
95 if (cc->dev->id.revision < 6) {
96 if (bus->bustype == SSB_BUSTYPE_SSB ||
97 bus->bustype == SSB_BUSTYPE_PCMCIA)
98 return SSB_CHIPCO_CLKSRC_XTALOS;
99 if (bus->bustype == SSB_BUSTYPE_PCI) {
100 pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
102 return SSB_CHIPCO_CLKSRC_PCI;
103 return SSB_CHIPCO_CLKSRC_XTALOS;
106 if (cc->dev->id.revision < 10) {
107 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
110 return SSB_CHIPCO_CLKSRC_LOPWROS;
112 return SSB_CHIPCO_CLKSRC_XTALOS;
114 return SSB_CHIPCO_CLKSRC_PCI;
117 return SSB_CHIPCO_CLKSRC_XTALOS;
120 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
121 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
123 int uninitialized_var(limit);
124 enum ssb_clksrc clocksrc;
128 clocksrc = chipco_pctl_get_slowclksrc(cc);
129 if (cc->dev->id.revision < 6) {
131 case SSB_CHIPCO_CLKSRC_PCI:
134 case SSB_CHIPCO_CLKSRC_XTALOS:
140 } else if (cc->dev->id.revision < 10) {
142 case SSB_CHIPCO_CLKSRC_LOPWROS:
144 case SSB_CHIPCO_CLKSRC_XTALOS:
145 case SSB_CHIPCO_CLKSRC_PCI:
146 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
147 divisor = (tmp >> 16) + 1;
152 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
153 divisor = (tmp >> 16) + 1;
158 case SSB_CHIPCO_CLKSRC_LOPWROS:
164 case SSB_CHIPCO_CLKSRC_XTALOS:
170 case SSB_CHIPCO_CLKSRC_PCI:
182 static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
184 struct ssb_bus *bus = cc->dev->bus;
186 if (bus->chip_id == 0x4321) {
187 if (bus->chip_rev == 0)
188 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
189 else if (bus->chip_rev == 1)
190 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
193 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
196 if (cc->dev->id.revision >= 10) {
197 /* Set Idle Power clock rate to 1Mhz */
198 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
199 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
200 0x0000FFFF) | 0x00040000);
204 maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
205 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
206 (maxfreq * 150 + 999999) / 1000000);
207 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
208 (maxfreq * 15 + 999999) / 1000000);
212 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
214 struct ssb_bus *bus = cc->dev->bus;
219 if (bus->bustype != SSB_BUSTYPE_PCI)
221 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
224 minfreq = chipco_pctl_clockfreqlimit(cc, 0);
225 pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
226 tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
227 SSB_WARN_ON(tmp & ~0xFFFF);
229 cc->fast_pwrup_delay = tmp;
232 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
235 return; /* We don't have a ChipCommon */
237 chipco_powercontrol_init(cc);
238 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
239 calc_fast_powerup_delay(cc);
242 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
246 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
249 void ssb_chipco_resume(struct ssb_chipcommon *cc)
253 chipco_powercontrol_init(cc);
254 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
257 /* Get the processor clock */
258 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
259 u32 *plltype, u32 *n, u32 *m)
261 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
262 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
268 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
271 /* 5350 uses m2 to control mips */
272 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
275 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
280 /* Get the bus clock */
281 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
282 u32 *plltype, u32 *n, u32 *m)
284 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
285 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
287 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
288 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
290 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
291 if (cc->dev->bus->chip_id != 0x5365) {
292 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
297 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
301 void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
304 struct ssb_device *dev = cc->dev;
305 struct ssb_bus *bus = dev->bus;
308 /* set register for external IO to control LED. */
309 chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
310 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
311 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */
312 tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */
313 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
315 /* Set timing for the flash */
316 tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */
317 tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */
318 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */
319 if ((bus->chip_id == 0x5365) ||
320 (dev->id.revision < 9))
321 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
322 if ((bus->chip_id == 0x5365) ||
323 (dev->id.revision < 9) ||
324 ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
325 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
327 if (bus->chip_id == 0x5350) {
329 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
330 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */
331 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
332 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */
333 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
337 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
338 void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
341 chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
344 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
346 chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
349 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
351 return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
354 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
356 return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
359 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
361 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
364 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
366 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
369 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
371 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
374 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
376 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
379 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
381 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
384 #ifdef CONFIG_SSB_SERIAL
385 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
386 struct ssb_serial_port *ports)
388 struct ssb_bus *bus = cc->dev->bus;
394 unsigned int ccrev = cc->dev->id.revision;
396 plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
397 irq = ssb_mips_irq(cc->dev);
399 if (plltype == SSB_PLLTYPE_1) {
401 baud_base = ssb_calc_clock_rate(plltype,
402 chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
403 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
407 /* BCM5354 uses constant 25MHz clock */
408 baud_base = 25000000;
410 /* Set the override bit so we don't divide it */
411 chipco_write32(cc, SSB_CHIPCO_CORECTL,
412 chipco_read32(cc, SSB_CHIPCO_CORECTL)
413 | SSB_CHIPCO_CORECTL_UARTCLK0);
414 } else if ((ccrev >= 11) && (ccrev != 15)) {
415 /* Fixed ALP clock */
416 baud_base = 20000000;
417 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
418 /* FIXME: baud_base is different for devices with a PMU */
423 /* Turn off UART clock before switching clocksource. */
424 chipco_write32(cc, SSB_CHIPCO_CORECTL,
425 chipco_read32(cc, SSB_CHIPCO_CORECTL)
426 & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
428 /* Set the override bit so we don't divide it */
429 chipco_write32(cc, SSB_CHIPCO_CORECTL,
430 chipco_read32(cc, SSB_CHIPCO_CORECTL)
431 | SSB_CHIPCO_CORECTL_UARTCLK0);
433 /* Re-enable the UART clock. */
434 chipco_write32(cc, SSB_CHIPCO_CORECTL,
435 chipco_read32(cc, SSB_CHIPCO_CORECTL)
436 | SSB_CHIPCO_CORECTL_UARTCLKEN);
438 } else if (ccrev >= 3) {
439 /* Internal backplane clock */
440 baud_base = ssb_clockspeed(bus);
441 div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
442 & SSB_CHIPCO_CLKDIV_UART;
444 /* Fixed internal backplane clock */
445 baud_base = 88000000;
449 /* Clock source depends on strapping if UartClkOverride is unset */
451 !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
452 if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
453 SSB_CHIPCO_CAP_UARTCLK_INT) {
454 /* Internal divided backplane clock */
457 /* Assume external clock of 1.8432 MHz */
463 /* Determine the registers of the UARTs */
464 n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
465 for (i = 0; i < n; i++) {
466 void __iomem *cc_mmio;
467 void __iomem *uart_regs;
469 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
470 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
471 /* Offset changed at after rev 0 */
473 uart_regs += (i * 8);
475 uart_regs += (i * 256);
478 ports[i].regs = uart_regs;
480 ports[i].baud_base = baud_base;
481 ports[i].reg_shift = 0;
486 #endif /* CONFIG_SSB_SERIAL */