2 * Driver for Nvidia TEGRA spi controller.
4 * Copyright (C) 2010 Google, Inc.
7 * Erik Gilling <konkers@android.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/err.h>
23 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/dmapool.h>
27 #include <linux/clk.h>
28 #include <linux/interrupt.h>
29 #include <linux/delay.h>
31 #include <linux/spi/spi.h>
35 #define SLINK_COMMAND 0x000
36 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
37 #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
38 #define SLINK_BOTH_EN (1 << 10)
39 #define SLINK_CS_SW (1 << 11)
40 #define SLINK_CS_VALUE (1 << 12)
41 #define SLINK_CS_POLARITY (1 << 13)
42 #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
43 #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
44 #define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
45 #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
46 #define SLINK_IDLE_SDA_MASK (3 << 16)
47 #define SLINK_CS_POLARITY1 (1 << 20)
48 #define SLINK_CK_SDA (1 << 21)
49 #define SLINK_CS_POLARITY2 (1 << 22)
50 #define SLINK_CS_POLARITY3 (1 << 23)
51 #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
52 #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
53 #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
54 #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
55 #define SLINK_IDLE_SCLK_MASK (3 << 24)
56 #define SLINK_M_S (1 << 28)
57 #define SLINK_WAIT (1 << 29)
58 #define SLINK_GO (1 << 30)
59 #define SLINK_ENB (1 << 31)
61 #define SLINK_COMMAND2 0x004
62 #define SLINK_LSBFE (1 << 0)
63 #define SLINK_SSOE (1 << 1)
64 #define SLINK_SPIE (1 << 4)
65 #define SLINK_BIDIROE (1 << 6)
66 #define SLINK_MODFEN (1 << 7)
67 #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
68 #define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
69 #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
70 #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
71 #define SLINK_FIFO_REFILLS_0 (0 << 22)
72 #define SLINK_FIFO_REFILLS_1 (1 << 22)
73 #define SLINK_FIFO_REFILLS_2 (2 << 22)
74 #define SLINK_FIFO_REFILLS_3 (3 << 22)
75 #define SLINK_FIFO_REFILLS_MASK (3 << 22)
76 #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
77 #define SLINK_SPC0 (1 << 29)
78 #define SLINK_TXEN (1 << 30)
79 #define SLINK_RXEN (1 << 31)
81 #define SLINK_STATUS 0x008
82 #define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
83 #define SLINK_WORD(val) (((val) >> 5) & 0x1f)
84 #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
85 #define SLINK_MODF (1 << 16)
86 #define SLINK_RX_UNF (1 << 18)
87 #define SLINK_TX_OVF (1 << 19)
88 #define SLINK_TX_FULL (1 << 20)
89 #define SLINK_TX_EMPTY (1 << 21)
90 #define SLINK_RX_FULL (1 << 22)
91 #define SLINK_RX_EMPTY (1 << 23)
92 #define SLINK_TX_UNF (1 << 24)
93 #define SLINK_RX_OVF (1 << 25)
94 #define SLINK_TX_FLUSH (1 << 26)
95 #define SLINK_RX_FLUSH (1 << 27)
96 #define SLINK_SCLK (1 << 28)
97 #define SLINK_ERR (1 << 29)
98 #define SLINK_RDY (1 << 30)
99 #define SLINK_BSY (1 << 31)
101 #define SLINK_MAS_DATA 0x010
102 #define SLINK_SLAVE_DATA 0x014
104 #define SLINK_DMA_CTL 0x018
105 #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
106 #define SLINK_TX_TRIG_1 (0 << 16)
107 #define SLINK_TX_TRIG_4 (1 << 16)
108 #define SLINK_TX_TRIG_8 (2 << 16)
109 #define SLINK_TX_TRIG_16 (3 << 16)
110 #define SLINK_TX_TRIG_MASK (3 << 16)
111 #define SLINK_RX_TRIG_1 (0 << 18)
112 #define SLINK_RX_TRIG_4 (1 << 18)
113 #define SLINK_RX_TRIG_8 (2 << 18)
114 #define SLINK_RX_TRIG_16 (3 << 18)
115 #define SLINK_RX_TRIG_MASK (3 << 18)
116 #define SLINK_PACKED (1 << 20)
117 #define SLINK_PACK_SIZE_4 (0 << 21)
118 #define SLINK_PACK_SIZE_8 (1 << 21)
119 #define SLINK_PACK_SIZE_16 (2 << 21)
120 #define SLINK_PACK_SIZE_32 (3 << 21)
121 #define SLINK_PACK_SIZE_MASK (3 << 21)
122 #define SLINK_IE_TXC (1 << 26)
123 #define SLINK_IE_RXC (1 << 27)
124 #define SLINK_DMA_EN (1 << 31)
126 #define SLINK_STATUS2 0x01c
127 #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
128 #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f) >> 16)
130 #define SLINK_TX_FIFO 0x100
131 #define SLINK_RX_FIFO 0x180
133 static const unsigned long spi_tegra_req_sels[] = {
134 TEGRA_DMA_REQ_SEL_SL2B1,
135 TEGRA_DMA_REQ_SEL_SL2B2,
136 TEGRA_DMA_REQ_SEL_SL2B3,
137 TEGRA_DMA_REQ_SEL_SL2B4,
142 struct spi_tegra_data {
143 struct spi_master *master;
144 struct platform_device *pdev;
153 struct list_head queue;
154 struct spi_transfer *cur;
157 unsigned cur_bytes_per_word;
159 /* The tegra spi controller has a bug which causes the first word
160 * in PIO transactions to be garbage. Since packed DMA transactions
161 * require transfers to be 4 byte aligned we need a bounce buffer
162 * for the generic case.
164 struct tegra_dma_req rx_dma_req;
165 struct tegra_dma_channel *rx_dma;
167 dma_addr_t rx_bb_phys;
171 static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
174 return readl(tspi->base + reg);
177 static inline void spi_tegra_writel(struct spi_tegra_data *tspi,
181 writel(val, tspi->base + reg);
184 static void spi_tegra_go(struct spi_tegra_data *tspi)
190 val = spi_tegra_readl(tspi, SLINK_DMA_CTL);
191 val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;
192 val |= SLINK_DMA_BLOCK_SIZE(tspi->rx_dma_req.size / 4 - 1);
193 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
195 tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);
198 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
201 static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data *tspi,
202 struct spi_transfer *t)
204 unsigned len = min(t->len - tspi->cur_pos, BB_LEN *
205 tspi->cur_bytes_per_word);
206 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_pos;
210 val = spi_tegra_readl(tspi, SLINK_COMMAND);
211 val &= ~SLINK_WORD_SIZE(~0);
212 val |= SLINK_WORD_SIZE(len / tspi->cur_bytes_per_word - 1);
213 spi_tegra_writel(tspi, val, SLINK_COMMAND);
215 for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
217 for (j = 0; j < tspi->cur_bytes_per_word; j++)
218 val |= tx_buf[i + j] << j * 8;
220 spi_tegra_writel(tspi, val, SLINK_TX_FIFO);
223 tspi->rx_dma_req.size = len / tspi->cur_bytes_per_word * 4;
228 static unsigned spi_tegra_drain_rx_fifo(struct spi_tegra_data *tspi,
229 struct spi_transfer *t)
231 unsigned len = tspi->cur_len;
232 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_pos;
236 for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
237 val = tspi->rx_bb[i / tspi->cur_bytes_per_word];
238 for (j = 0; j < tspi->cur_bytes_per_word; j++)
239 rx_buf[i + j] = (val >> (j * 8)) & 0xff;
245 static void spi_tegra_start_transfer(struct spi_device *spi,
246 struct spi_transfer *t)
248 struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
253 speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
254 bits_per_word = t->bits_per_word ? t->bits_per_word :
257 tspi->cur_bytes_per_word = (bits_per_word - 1) / 8 + 1;
259 if (speed != tspi->cur_speed)
260 clk_set_rate(tspi->clk, speed);
262 if (tspi->cur_speed == 0)
263 clk_enable(tspi->clk);
265 tspi->cur_speed = speed;
267 val = spi_tegra_readl(tspi, SLINK_COMMAND2);
268 val &= ~SLINK_SS_EN_CS(~0) | SLINK_RXEN | SLINK_TXEN;
273 val |= SLINK_SS_EN_CS(spi->chip_select);
275 spi_tegra_writel(tspi, val, SLINK_COMMAND2);
277 val = spi_tegra_readl(tspi, SLINK_COMMAND);
278 val &= ~SLINK_BIT_LENGTH(~0);
279 val |= SLINK_BIT_LENGTH(bits_per_word - 1);
281 /* FIXME: should probably control CS manually so that we can be sure
282 * it does not go low between transfer and to support delay_usecs
285 val &= ~SLINK_IDLE_SCLK_MASK & ~SLINK_CK_SDA & ~SLINK_CS_SW;
287 if (spi->mode & SPI_CPHA)
290 if (spi->mode & SPI_CPOL)
291 val |= SLINK_IDLE_SCLK_DRIVE_HIGH;
293 val |= SLINK_IDLE_SCLK_DRIVE_LOW;
297 spi_tegra_writel(tspi, val, SLINK_COMMAND);
299 spi_tegra_writel(tspi, SLINK_RX_FLUSH | SLINK_TX_FLUSH, SLINK_STATUS);
303 tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, t);
308 static void spi_tegra_start_message(struct spi_device *spi,
309 struct spi_message *m)
311 struct spi_transfer *t;
313 m->actual_length = 0;
316 t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
317 spi_tegra_start_transfer(spi, t);
320 static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
322 struct spi_tegra_data *tspi = req->dev;
324 struct spi_message *m;
325 struct spi_device *spi;
329 /* the SPI controller may come back with both the BSY and RDY bits
330 * set. In this case we need to wait for the BSY bit to clear so
331 * that we are sure the DMA is finished. 1000 reads was empirically
332 * determined to be long enough.
334 while (timeout++ < 1000) {
335 if (!(spi_tegra_readl(tspi, SLINK_STATUS) & SLINK_BSY))
339 spin_lock_irqsave(&tspi->lock, flags);
341 val = spi_tegra_readl(tspi, SLINK_STATUS);
343 spi_tegra_writel(tspi, val, SLINK_STATUS);
345 m = list_first_entry(&tspi->queue, struct spi_message, queue);
352 tspi->cur_pos += spi_tegra_drain_rx_fifo(tspi, tspi->cur);
353 m->actual_length += tspi->cur_pos;
355 if (tspi->cur_pos < tspi->cur->len) {
356 tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, tspi->cur);
358 } else if (!list_is_last(&tspi->cur->transfer_list,
360 tspi->cur = list_first_entry(&tspi->cur->transfer_list,
363 spi_tegra_start_transfer(spi, tspi->cur);
367 m->complete(m->context);
369 if (!list_empty(&tspi->queue)) {
370 m = list_first_entry(&tspi->queue, struct spi_message,
373 spi_tegra_start_message(spi, m);
375 clk_disable(tspi->clk);
380 spin_unlock_irqrestore(&tspi->lock, flags);
383 static int spi_tegra_setup(struct spi_device *spi)
385 struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
386 unsigned long cs_bit;
390 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
392 spi->mode & SPI_CPOL ? "" : "~",
393 spi->mode & SPI_CPHA ? "" : "~",
397 switch (spi->chip_select) {
399 cs_bit = SLINK_CS_POLARITY;
403 cs_bit = SLINK_CS_POLARITY1;
407 cs_bit = SLINK_CS_POLARITY2;
411 cs_bit = SLINK_CS_POLARITY3;
418 spin_lock_irqsave(&tspi->lock, flags);
420 val = spi_tegra_readl(tspi, SLINK_COMMAND);
421 if (spi->mode & SPI_CS_HIGH)
425 spi_tegra_writel(tspi, val, SLINK_COMMAND);
427 spin_unlock_irqrestore(&tspi->lock, flags);
432 static int spi_tegra_transfer(struct spi_device *spi, struct spi_message *m)
434 struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
435 struct spi_transfer *t;
439 if (list_empty(&m->transfers) || !m->complete)
442 list_for_each_entry(t, &m->transfers, transfer_list) {
443 if (t->bits_per_word < 0 || t->bits_per_word > 32)
449 if (!t->rx_buf && !t->tx_buf)
455 spin_lock_irqsave(&tspi->lock, flags);
456 was_empty = list_empty(&tspi->queue);
457 list_add_tail(&m->queue, &tspi->queue);
460 spi_tegra_start_message(spi, m);
462 spin_unlock_irqrestore(&tspi->lock, flags);
467 static int __init spi_tegra_probe(struct platform_device *pdev)
469 struct spi_master *master;
470 struct spi_tegra_data *tspi;
474 master = spi_alloc_master(&pdev->dev, sizeof *tspi);
475 if (master == NULL) {
476 dev_err(&pdev->dev, "master allocation failed\n");
480 /* the spi->mode bits understood by this driver: */
481 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
483 master->bus_num = pdev->id;
485 master->setup = spi_tegra_setup;
486 master->transfer = spi_tegra_transfer;
487 master->num_chipselect = 4;
489 dev_set_drvdata(&pdev->dev, master);
490 tspi = spi_master_get_devdata(master);
491 tspi->master = master;
493 spin_lock_init(&tspi->lock);
495 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
501 if (!request_mem_region(r->start, (r->end - r->start) + 1,
502 dev_name(&pdev->dev))) {
507 tspi->phys = r->start;
508 tspi->base = ioremap(r->start, r->end - r->start + 1);
510 dev_err(&pdev->dev, "can't ioremap iomem\n");
515 tspi->clk = clk_get(&pdev->dev, NULL);
516 if (IS_ERR_OR_NULL(tspi->clk)) {
517 dev_err(&pdev->dev, "can not get clock\n");
518 ret = PTR_ERR(tspi->clk);
522 INIT_LIST_HEAD(&tspi->queue);
524 tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
526 dev_err(&pdev->dev, "can not allocate rx dma channel\n");
531 tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
532 &tspi->rx_bb_phys, GFP_KERNEL);
534 dev_err(&pdev->dev, "can not allocate rx bounce buffer\n");
539 tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
540 tspi->rx_dma_req.to_memory = 1;
541 tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys;
542 tspi->rx_dma_req.dest_bus_width = 32;
543 tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;
544 tspi->rx_dma_req.source_bus_width = 32;
545 tspi->rx_dma_req.source_wrap = 4;
546 tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
547 tspi->rx_dma_req.dev = tspi;
549 ret = spi_register_master(master);
557 dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
558 tspi->rx_bb, tspi->rx_bb_phys);
560 tegra_dma_free_channel(tspi->rx_dma);
566 release_mem_region(r->start, (r->end - r->start) + 1);
568 spi_master_put(master);
572 static int __devexit spi_tegra_remove(struct platform_device *pdev)
574 struct spi_master *master;
575 struct spi_tegra_data *tspi;
578 master = dev_get_drvdata(&pdev->dev);
579 tspi = spi_master_get_devdata(master);
581 tegra_dma_free_channel(tspi->rx_dma);
583 dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
584 tspi->rx_bb, tspi->rx_bb_phys);
589 spi_master_put(master);
590 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
591 release_mem_region(r->start, (r->end - r->start) + 1);
596 MODULE_ALIAS("platform:spi_tegra");
598 static struct platform_driver spi_tegra_driver = {
601 .owner = THIS_MODULE,
603 .remove = __devexit_p(spi_tegra_remove),
606 static int __init spi_tegra_init(void)
608 return platform_driver_probe(&spi_tegra_driver, spi_tegra_probe);
610 module_init(spi_tegra_init);
612 static void __exit spi_tegra_exit(void)
614 platform_driver_unregister(&spi_tegra_driver);
616 module_exit(spi_tegra_exit);
618 MODULE_LICENSE("GPL");