2 * MPC83xx SPI controller driver.
4 * Maintainer: Kumar Gala
6 * Copyright (C) 2006 Polycom, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/completion.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
20 #include <linux/irq.h>
21 #include <linux/device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/spi_bitbang.h>
24 #include <linux/platform_device.h>
25 #include <linux/fsl_devices.h>
30 /* SPI Controller registers */
31 struct mpc83xx_spi_reg {
41 /* SPI Controller mode register definitions */
42 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
43 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
44 #define SPMODE_DIV16 (1 << 27)
45 #define SPMODE_REV (1 << 26)
46 #define SPMODE_MS (1 << 25)
47 #define SPMODE_ENABLE (1 << 24)
48 #define SPMODE_LEN(x) ((x) << 20)
49 #define SPMODE_PM(x) ((x) << 16)
52 * Default for SPI Mode:
53 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
55 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
56 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
58 /* SPIE register values */
59 #define SPIE_NE 0x00000200 /* Not empty */
60 #define SPIE_NF 0x00000100 /* Not full */
62 /* SPIM register values */
63 #define SPIM_NE 0x00000200 /* Not empty */
64 #define SPIM_NF 0x00000100 /* Not full */
66 /* SPI Controller driver's private data. */
68 /* bitbang has to be first */
69 struct spi_bitbang bitbang;
70 struct completion done;
72 struct mpc83xx_spi_reg __iomem *base;
74 /* rx & tx bufs from the spi_transfer */
78 /* functions to deal with different sized buffers */
79 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
80 u32(*get_tx) (struct mpc83xx_spi *);
85 unsigned nsecs; /* (clock cycle time)/2 */
88 void (*activate_cs) (u8 cs, u8 polarity);
89 void (*deactivate_cs) (u8 cs, u8 polarity);
92 static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
97 static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
102 #define MPC83XX_SPI_RX_BUF(type) \
103 void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
105 type * rx = mpc83xx_spi->rx; \
106 *rx++ = (type)data; \
107 mpc83xx_spi->rx = rx; \
110 #define MPC83XX_SPI_TX_BUF(type) \
111 u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
114 const type * tx = mpc83xx_spi->tx; \
118 mpc83xx_spi->tx = tx; \
122 MPC83XX_SPI_RX_BUF(u8)
123 MPC83XX_SPI_RX_BUF(u16)
124 MPC83XX_SPI_RX_BUF(u32)
125 MPC83XX_SPI_TX_BUF(u8)
126 MPC83XX_SPI_TX_BUF(u16)
127 MPC83XX_SPI_TX_BUF(u32)
129 static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
131 struct mpc83xx_spi *mpc83xx_spi;
132 u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
134 mpc83xx_spi = spi_master_get_devdata(spi->master);
136 if (value == BITBANG_CS_INACTIVE) {
137 if (mpc83xx_spi->deactivate_cs)
138 mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
141 if (value == BITBANG_CS_ACTIVE) {
142 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
143 u32 len = spi->bits_per_word;
149 /* mask out bits we are going to set */
150 regval &= ~0x38ff0000;
152 if (spi->mode & SPI_CPHA)
153 regval |= SPMODE_CP_BEGIN_EDGECLK;
154 if (spi->mode & SPI_CPOL)
155 regval |= SPMODE_CI_INACTIVEHIGH;
157 regval |= SPMODE_LEN(len);
159 if ((mpc83xx_spi->sysclk / spi->max_speed_hz) >= 64) {
160 u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 64);
162 printk(KERN_WARNING "MPC83xx SPI: SPICLK can't be less then a SYSCLK/1024!\n"
163 "Requested SPICLK is %d Hz. Will use %d Hz instead.\n",
164 spi->max_speed_hz, mpc83xx_spi->sysclk / 1024);
167 regval |= SPMODE_PM(pm) | SPMODE_DIV16;
169 u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 4);
170 regval |= SPMODE_PM(pm);
173 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
174 if (mpc83xx_spi->activate_cs)
175 mpc83xx_spi->activate_cs(spi->chip_select, pol);
180 int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
182 struct mpc83xx_spi *mpc83xx_spi;
187 mpc83xx_spi = spi_master_get_devdata(spi->master);
190 bits_per_word = t->bits_per_word;
197 /* spi_transfer level calls that work per-word */
199 bits_per_word = spi->bits_per_word;
201 /* Make sure its a bit width we support [4..16, 32] */
202 if ((bits_per_word < 4)
203 || ((bits_per_word > 16) && (bits_per_word != 32)))
206 if (bits_per_word <= 8) {
207 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
208 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
209 } else if (bits_per_word <= 16) {
210 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16;
211 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16;
212 } else if (bits_per_word <= 32) {
213 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32;
214 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32;
218 /* nsecs = (clock period)/2 */
220 hz = spi->max_speed_hz;
221 mpc83xx_spi->nsecs = (1000000000 / 2) / hz;
222 if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000)
225 if (bits_per_word == 32)
228 bits_per_word = bits_per_word - 1;
230 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
232 /* Mask out bits_per_wordgth */
233 regval &= 0xff0fffff;
234 regval |= SPMODE_LEN(bits_per_word);
236 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
241 /* the spi->mode bits understood by this driver: */
242 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
244 static int mpc83xx_spi_setup(struct spi_device *spi)
246 struct spi_bitbang *bitbang;
247 struct mpc83xx_spi *mpc83xx_spi;
250 if (spi->mode & ~MODEBITS) {
251 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
252 spi->mode & ~MODEBITS);
256 if (!spi->max_speed_hz)
259 bitbang = spi_master_get_devdata(spi->master);
260 mpc83xx_spi = spi_master_get_devdata(spi->master);
262 if (!spi->bits_per_word)
263 spi->bits_per_word = 8;
265 retval = mpc83xx_spi_setup_transfer(spi, NULL);
269 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n",
270 __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA),
271 spi->bits_per_word, 2 * mpc83xx_spi->nsecs);
273 /* NOTE we _need_ to call chipselect() early, ideally with adapter
274 * setup, unless the hardware defaults cooperate to avoid confusion
275 * between normal (active low) and inverted chipselects.
278 /* deselect chip (low or high) */
279 spin_lock(&bitbang->lock);
280 if (!bitbang->busy) {
281 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
282 ndelay(mpc83xx_spi->nsecs);
284 spin_unlock(&bitbang->lock);
289 static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
291 struct mpc83xx_spi *mpc83xx_spi;
294 mpc83xx_spi = spi_master_get_devdata(spi->master);
296 mpc83xx_spi->tx = t->tx_buf;
297 mpc83xx_spi->rx = t->rx_buf;
298 mpc83xx_spi->count = t->len;
299 INIT_COMPLETION(mpc83xx_spi->done);
302 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
305 word = mpc83xx_spi->get_tx(mpc83xx_spi);
306 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
308 wait_for_completion(&mpc83xx_spi->done);
310 /* disable rx ints */
311 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
313 return t->len - mpc83xx_spi->count;
316 irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
318 struct mpc83xx_spi *mpc83xx_spi = context_data;
320 irqreturn_t ret = IRQ_NONE;
322 /* Get interrupt events(tx/rx) */
323 event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
325 /* We need handle RX first */
326 if (event & SPIE_NE) {
327 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
330 mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
335 if ((event & SPIE_NF) == 0)
336 /* spin until TX is done */
338 mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
342 mpc83xx_spi->count -= 1;
343 if (mpc83xx_spi->count) {
344 if (mpc83xx_spi->tx) {
345 u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
346 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit,
350 complete(&mpc83xx_spi->done);
353 /* Clear the events */
354 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
359 static int __init mpc83xx_spi_probe(struct platform_device *dev)
361 struct spi_master *master;
362 struct mpc83xx_spi *mpc83xx_spi;
363 struct fsl_spi_platform_data *pdata;
368 /* Get resources(memory, IRQ) associated with the device */
369 master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
371 if (master == NULL) {
376 platform_set_drvdata(dev, master);
377 pdata = dev->dev.platform_data;
384 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
390 mpc83xx_spi = spi_master_get_devdata(master);
391 mpc83xx_spi->bitbang.master = spi_master_get(master);
392 mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect;
393 mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer;
394 mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs;
395 mpc83xx_spi->sysclk = pdata->sysclk;
396 mpc83xx_spi->activate_cs = pdata->activate_cs;
397 mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
398 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
399 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
401 mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup;
402 init_completion(&mpc83xx_spi->done);
404 mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
405 if (mpc83xx_spi->base == NULL) {
410 mpc83xx_spi->irq = platform_get_irq(dev, 0);
412 if (mpc83xx_spi->irq < 0) {
417 /* Register for SPI Interrupt */
418 ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
419 0, "mpc83xx_spi", mpc83xx_spi);
424 master->bus_num = pdata->bus_num;
425 master->num_chipselect = pdata->max_chipselect;
427 /* SPI controller initializations */
428 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
429 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
430 mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
431 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
433 /* Enable SPI interface */
434 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
435 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
437 ret = spi_bitbang_start(&mpc83xx_spi->bitbang);
443 "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
444 dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
449 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
451 iounmap(mpc83xx_spi->base);
453 spi_master_put(master);
460 static int __devexit mpc83xx_spi_remove(struct platform_device *dev)
462 struct mpc83xx_spi *mpc83xx_spi;
463 struct spi_master *master;
465 master = platform_get_drvdata(dev);
466 mpc83xx_spi = spi_master_get_devdata(master);
468 spi_bitbang_stop(&mpc83xx_spi->bitbang);
469 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
470 iounmap(mpc83xx_spi->base);
471 spi_master_put(mpc83xx_spi->bitbang.master);
476 static struct platform_driver mpc83xx_spi_driver = {
477 .probe = mpc83xx_spi_probe,
478 .remove = __devexit_p(mpc83xx_spi_remove),
480 .name = "mpc83xx_spi",
484 static int __init mpc83xx_spi_init(void)
486 return platform_driver_register(&mpc83xx_spi_driver);
489 static void __exit mpc83xx_spi_exit(void)
491 platform_driver_unregister(&mpc83xx_spi_driver);
494 module_init(mpc83xx_spi_init);
495 module_exit(mpc83xx_spi_exit);
497 MODULE_AUTHOR("Kumar Gala");
498 MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
499 MODULE_LICENSE("GPL");