drivers/spi/spi_imx.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright (C) 2008 Juergen Beisert
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the
  16  * Free Software Foundation
  17  * 51 Franklin Street, Fifth Floor
  18  * Boston, MA  02110-1301, USA.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/completion.h>
  23 #include <linux/delay.h>
  24 #include <linux/err.h>
  25 #include <linux/gpio.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/irq.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/slab.h>
  34 #include <linux/spi/spi.h>
  35 #include <linux/spi/spi_bitbang.h>
  36 #include <linux/types.h>
  37
  38 #include <mach/spi.h>
  39
  40 #define DRIVER_NAME "spi_imx"
  41
  42 #define MXC_CSPIRXDATA          0x00
  43 #define MXC_CSPITXDATA          0x04
  44 #define MXC_CSPICTRL            0x08
  45 #define MXC_CSPIINT             0x0c
  46 #define MXC_RESET               0x1c
  47
  48 #define MX3_CSPISTAT            0x14
  49 #define MX3_CSPISTAT_RR         (1 << 3)
  50
  51 /* generic defines to abstract from the different register layouts */
  52 #define MXC_INT_RR      (1 << 0) /* Receive data ready interrupt */
  53 #define MXC_INT_TE      (1 << 1) /* Transmit FIFO empty interrupt */
  54
  55 struct spi_imx_config {
  56         unsigned int speed_hz;
  57         unsigned int bpw;
  58         unsigned int mode;
  59         u8 cs;
  60 };
  61
  62 enum spi_imx_devtype {
  63         SPI_IMX_VER_IMX1,
  64         SPI_IMX_VER_0_0,
  65         SPI_IMX_VER_0_4,
  66         SPI_IMX_VER_0_5,
  67         SPI_IMX_VER_0_7,
  68         SPI_IMX_VER_AUTODETECT,
  69 };
  70
  71 struct spi_imx_data;
  72
  73 struct spi_imx_devtype_data {
  74         void (*intctrl)(struct spi_imx_data *, int);
  75         int (*config)(struct spi_imx_data *, struct spi_imx_config *);
  76         void (*trigger)(struct spi_imx_data *);
  77         int (*rx_available)(struct spi_imx_data *);
  78         void (*reset)(struct spi_imx_data *);
  79 };
  80
  81 struct spi_imx_data {
  82         struct spi_bitbang bitbang;
  83
  84         struct completion xfer_done;
  85         void *base;
  86         int irq;
  87         struct clk *clk;
  88         unsigned long spi_clk;
  89         int *chipselect;
  90
  91         unsigned int count;
  92         void (*tx)(struct spi_imx_data *);
  93         void (*rx)(struct spi_imx_data *);
  94         void *rx_buf;
  95         const void *tx_buf;
  96         unsigned int txfifo; /* number of words pushed in tx FIFO */
  97
  98         struct spi_imx_devtype_data devtype_data;
  99 };
 100
 101 #define MXC_SPI_BUF_RX(type)                                            \
 102 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)         \
 103 {                                                                       \
 104         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);       \
 105                                                                         \
 106         if (spi_imx->rx_buf) {                                          \
 107                 *(type *)spi_imx->rx_buf = val;                         \
 108                 spi_imx->rx_buf += sizeof(type);                        \
 109         }                                                               \
 110 }
 111
 112 #define MXC_SPI_BUF_TX(type)                                            \
 113 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)         \
 114 {                                                                       \
 115         type val = 0;                                                   \
 116                                                                         \
 117         if (spi_imx->tx_buf) {                                          \
 118                 val = *(type *)spi_imx->tx_buf;                         \
 119                 spi_imx->tx_buf += sizeof(type);                        \
 120         }                                                               \
 121                                                                         \
 122         spi_imx->count -= sizeof(type);                                 \
 123                                                                         \
 124         writel(val, spi_imx->base + MXC_CSPITXDATA);                    \
 125 }
 126
 127 MXC_SPI_BUF_RX(u8)
 128 MXC_SPI_BUF_TX(u8)
 129 MXC_SPI_BUF_RX(u16)
 130 MXC_SPI_BUF_TX(u16)
 131 MXC_SPI_BUF_RX(u32)
 132 MXC_SPI_BUF_TX(u32)
 133
 134 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
 135  * (which is currently not the case in this driver)
 136  */
 137 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
 138         256, 384, 512, 768, 1024};
 139
 140 /* MX21, MX27 */
 141 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
 142                 unsigned int fspi)
 143 {
 144         int i, max;
 145
 146         if (cpu_is_mx21())
 147                 max = 18;
 148         else
 149                 max = 16;
 150
 151         for (i = 2; i < max; i++)
 152                 if (fspi * mxc_clkdivs[i] >= fin)
 153                         return i;
 154
 155         return max;
 156 }
 157
 158 /* MX1, MX31, MX35 */
 159 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 160                 unsigned int fspi)
 161 {
 162         int i, div = 4;
 163
 164         for (i = 0; i < 7; i++) {
 165                 if (fspi * div >= fin)
 166                         return i;
 167                 div <<= 1;
 168         }
 169
 170         return 7;
 171 }
 172
 173 #define MX31_INTREG_TEEN        (1 << 0)
 174 #define MX31_INTREG_RREN        (1 << 3)
 175
 176 #define MX31_CSPICTRL_ENABLE    (1 << 0)
 177 #define MX31_CSPICTRL_MASTER    (1 << 1)
 178 #define MX31_CSPICTRL_XCH       (1 << 2)
 179 #define MX31_CSPICTRL_POL       (1 << 4)
 180 #define MX31_CSPICTRL_PHA       (1 << 5)
 181 #define MX31_CSPICTRL_SSCTL     (1 << 6)
 182 #define MX31_CSPICTRL_SSPOL     (1 << 7)
 183 #define MX31_CSPICTRL_BC_SHIFT  8
 184 #define MX35_CSPICTRL_BL_SHIFT  20
 185 #define MX31_CSPICTRL_CS_SHIFT  24
 186 #define MX35_CSPICTRL_CS_SHIFT  12
 187 #define MX31_CSPICTRL_DR_SHIFT  16
 188
 189 #define MX31_CSPISTATUS         0x14
 190 #define MX31_STATUS_RR          (1 << 3)
 191
 192 /* These functions also work for the i.MX35, but be aware that
 193  * the i.MX35 has a slightly different register layout for bits
 194  * we do not use here.
 195  */
 196 static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
 197 {
 198         unsigned int val = 0;
 199
 200         if (enable & MXC_INT_TE)
 201                 val |= MX31_INTREG_TEEN;
 202         if (enable & MXC_INT_RR)
 203                 val |= MX31_INTREG_RREN;
 204
 205         writel(val, spi_imx->base + MXC_CSPIINT);
 206 }
 207
 208 static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
 209 {
 210         unsigned int reg;
 211
 212         reg = readl(spi_imx->base + MXC_CSPICTRL);
 213         reg |= MX31_CSPICTRL_XCH;
 214         writel(reg, spi_imx->base + MXC_CSPICTRL);
 215 }
 216
 217 static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
 218                 struct spi_imx_config *config)
 219 {
 220         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
 221         int cs = spi_imx->chipselect[config->cs];
 222
 223         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
 224                 MX31_CSPICTRL_DR_SHIFT;
 225
 226         reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
 227
 228         if (config->mode & SPI_CPHA)
 229                 reg |= MX31_CSPICTRL_PHA;
 230         if (config->mode & SPI_CPOL)
 231                 reg |= MX31_CSPICTRL_POL;
 232         if (config->mode & SPI_CS_HIGH)
 233                 reg |= MX31_CSPICTRL_SSPOL;
 234         if (cs < 0)
 235                 reg |= (cs + 32) << MX31_CSPICTRL_CS_SHIFT;
 236
 237         writel(reg, spi_imx->base + MXC_CSPICTRL);
 238
 239         return 0;
 240 }
 241
 242 static int __maybe_unused spi_imx0_7_config(struct spi_imx_data *spi_imx,
 243                 struct spi_imx_config *config)
 244 {
 245         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
 246         int cs = spi_imx->chipselect[config->cs];
 247
 248         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
 249                 MX31_CSPICTRL_DR_SHIFT;
 250
 251         reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
 252         reg |= MX31_CSPICTRL_SSCTL;
 253
 254         if (config->mode & SPI_CPHA)
 255                 reg |= MX31_CSPICTRL_PHA;
 256         if (config->mode & SPI_CPOL)
 257                 reg |= MX31_CSPICTRL_POL;
 258         if (config->mode & SPI_CS_HIGH)
 259                 reg |= MX31_CSPICTRL_SSPOL;
 260         if (cs < 0)
 261                 reg |= (cs + 32) << MX35_CSPICTRL_CS_SHIFT;
 262
 263         writel(reg, spi_imx->base + MXC_CSPICTRL);
 264
 265         return 0;
 266 }
 267
 268 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
 269 {
 270         return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
 271 }
 272
 273 static void __maybe_unused spi_imx0_4_reset(struct spi_imx_data *spi_imx)
 274 {
 275         /* drain receive buffer */
 276         while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
 277                 readl(spi_imx->base + MXC_CSPIRXDATA);
 278 }
 279
 280 #define MX27_INTREG_RR          (1 << 4)
 281 #define MX27_INTREG_TEEN        (1 << 9)
 282 #define MX27_INTREG_RREN        (1 << 13)
 283
 284 #define MX27_CSPICTRL_POL       (1 << 5)
 285 #define MX27_CSPICTRL_PHA       (1 << 6)
 286 #define MX27_CSPICTRL_SSPOL     (1 << 8)
 287 #define MX27_CSPICTRL_XCH       (1 << 9)
 288 #define MX27_CSPICTRL_ENABLE    (1 << 10)
 289 #define MX27_CSPICTRL_MASTER    (1 << 11)
 290 #define MX27_CSPICTRL_DR_SHIFT  14
 291 #define MX27_CSPICTRL_CS_SHIFT  19
 292
 293 static void __maybe_unused mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
 294 {
 295         unsigned int val = 0;
 296
 297         if (enable & MXC_INT_TE)
 298                 val |= MX27_INTREG_TEEN;
 299         if (enable & MXC_INT_RR)
 300                 val |= MX27_INTREG_RREN;
 301
 302         writel(val, spi_imx->base + MXC_CSPIINT);
 303 }
 304
 305 static void __maybe_unused mx27_trigger(struct spi_imx_data *spi_imx)
 306 {
 307         unsigned int reg;
 308
 309         reg = readl(spi_imx->base + MXC_CSPICTRL);
 310         reg |= MX27_CSPICTRL_XCH;
 311         writel(reg, spi_imx->base + MXC_CSPICTRL);
 312 }
 313
 314 static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx,
 315                 struct spi_imx_config *config)
 316 {
 317         unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
 318         int cs = spi_imx->chipselect[config->cs];
 319
 320         reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) <<
 321                 MX27_CSPICTRL_DR_SHIFT;
 322         reg |= config->bpw - 1;
 323
 324         if (config->mode & SPI_CPHA)
 325                 reg |= MX27_CSPICTRL_PHA;
 326         if (config->mode & SPI_CPOL)
 327                 reg |= MX27_CSPICTRL_POL;
 328         if (config->mode & SPI_CS_HIGH)
 329                 reg |= MX27_CSPICTRL_SSPOL;
 330         if (cs < 0)
 331                 reg |= (cs + 32) << MX27_CSPICTRL_CS_SHIFT;
 332
 333         writel(reg, spi_imx->base + MXC_CSPICTRL);
 334
 335         return 0;
 336 }
 337
 338 static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx)
 339 {
 340         return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
 341 }
 342
 343 static void __maybe_unused spi_imx0_0_reset(struct spi_imx_data *spi_imx)
 344 {
 345         writel(1, spi_imx->base + MXC_RESET);
 346 }
 347
 348 #define MX1_INTREG_RR           (1 << 3)
 349 #define MX1_INTREG_TEEN         (1 << 8)
 350 #define MX1_INTREG_RREN         (1 << 11)
 351
 352 #define MX1_CSPICTRL_POL        (1 << 4)
 353 #define MX1_CSPICTRL_PHA        (1 << 5)
 354 #define MX1_CSPICTRL_XCH        (1 << 8)
 355 #define MX1_CSPICTRL_ENABLE     (1 << 9)
 356 #define MX1_CSPICTRL_MASTER     (1 << 10)
 357 #define MX1_CSPICTRL_DR_SHIFT   13
 358
 359 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
 360 {
 361         unsigned int val = 0;
 362
 363         if (enable & MXC_INT_TE)
 364                 val |= MX1_INTREG_TEEN;
 365         if (enable & MXC_INT_RR)
 366                 val |= MX1_INTREG_RREN;
 367
 368         writel(val, spi_imx->base + MXC_CSPIINT);
 369 }
 370
 371 static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
 372 {
 373         unsigned int reg;
 374
 375         reg = readl(spi_imx->base + MXC_CSPICTRL);
 376         reg |= MX1_CSPICTRL_XCH;
 377         writel(reg, spi_imx->base + MXC_CSPICTRL);
 378 }
 379
 380 static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
 381                 struct spi_imx_config *config)
 382 {
 383         unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
 384
 385         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
 386                 MX1_CSPICTRL_DR_SHIFT;
 387         reg |= config->bpw - 1;
 388
 389         if (config->mode & SPI_CPHA)
 390                 reg |= MX1_CSPICTRL_PHA;
 391         if (config->mode & SPI_CPOL)
 392                 reg |= MX1_CSPICTRL_POL;
 393
 394         writel(reg, spi_imx->base + MXC_CSPICTRL);
 395
 396         return 0;
 397 }
 398
 399 static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
 400 {
 401         return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
 402 }
 403
 404 static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
 405 {
 406         writel(1, spi_imx->base + MXC_RESET);
 407 }
 408
 409 /*
 410  * These version numbers are taken from the Freescale driver.  Unfortunately it
 411  * doesn't support i.MX1, so this entry doesn't match the scheme. :-(
 412  */
 413 static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
 414 #ifdef CONFIG_SPI_IMX_VER_IMX1
 415         [SPI_IMX_VER_IMX1] = {
 416                 .intctrl = mx1_intctrl,
 417                 .config = mx1_config,
 418                 .trigger = mx1_trigger,
 419                 .rx_available = mx1_rx_available,
 420                 .reset = mx1_reset,
 421         },
 422 #endif
 423 #ifdef CONFIG_SPI_IMX_VER_0_0
 424         [SPI_IMX_VER_0_0] = {
 425                 .intctrl = mx27_intctrl,
 426                 .config = mx27_config,
 427                 .trigger = mx27_trigger,
 428                 .rx_available = mx27_rx_available,
 429                 .reset = spi_imx0_0_reset,
 430         },
 431 #endif
 432 #ifdef CONFIG_SPI_IMX_VER_0_4
 433         [SPI_IMX_VER_0_4] = {
 434                 .intctrl = mx31_intctrl,
 435                 .config = spi_imx0_4_config,
 436                 .trigger = mx31_trigger,
 437                 .rx_available = mx31_rx_available,
 438                 .reset = spi_imx0_4_reset,
 439         },
 440 #endif
 441 #ifdef CONFIG_SPI_IMX_VER_0_7
 442         [SPI_IMX_VER_0_7] = {
 443                 .intctrl = mx31_intctrl,
 444                 .config = spi_imx0_7_config,
 445                 .trigger = mx31_trigger,
 446                 .rx_available = mx31_rx_available,
 447                 .reset = spi_imx0_4_reset,
 448         },
 449 #endif
 450 };
 451
 452 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
 453 {
 454         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 455         int gpio = spi_imx->chipselect[spi->chip_select];
 456         int active = is_active != BITBANG_CS_INACTIVE;
 457         int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
 458
 459         if (gpio < 0)
 460                 return;
 461
 462         gpio_set_value(gpio, dev_is_lowactive ^ active);
 463 }
 464
 465 static void spi_imx_push(struct spi_imx_data *spi_imx)
 466 {
 467         while (spi_imx->txfifo < 8) {
 468                 if (!spi_imx->count)
 469                         break;
 470                 spi_imx->tx(spi_imx);
 471                 spi_imx->txfifo++;
 472         }
 473
 474         spi_imx->devtype_data.trigger(spi_imx);
 475 }
 476
 477 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
 478 {
 479         struct spi_imx_data *spi_imx = dev_id;
 480
 481         while (spi_imx->devtype_data.rx_available(spi_imx)) {
 482                 spi_imx->rx(spi_imx);
 483                 spi_imx->txfifo--;
 484         }
 485
 486         if (spi_imx->count) {
 487                 spi_imx_push(spi_imx);
 488                 return IRQ_HANDLED;
 489         }
 490
 491         if (spi_imx->txfifo) {
 492                 /* No data left to push, but still waiting for rx data,
 493                  * enable receive data available interrupt.
 494                  */
 495                 spi_imx->devtype_data.intctrl(
 496                                 spi_imx, MXC_INT_RR);
 497                 return IRQ_HANDLED;
 498         }
 499
 500         spi_imx->devtype_data.intctrl(spi_imx, 0);
 501         complete(&spi_imx->xfer_done);
 502
 503         return IRQ_HANDLED;
 504 }
 505
 506 static int spi_imx_setupxfer(struct spi_device *spi,
 507                                  struct spi_transfer *t)
 508 {
 509         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 510         struct spi_imx_config config;
 511
 512         config.bpw = t ? t->bits_per_word : spi->bits_per_word;
 513         config.speed_hz  = t ? t->speed_hz : spi->max_speed_hz;
 514         config.mode = spi->mode;
 515         config.cs = spi->chip_select;
 516
 517         if (!config.speed_hz)
 518                 config.speed_hz = spi->max_speed_hz;
 519         if (!config.bpw)
 520                 config.bpw = spi->bits_per_word;
 521         if (!config.speed_hz)
 522                 config.speed_hz = spi->max_speed_hz;
 523
 524         /* Initialize the functions for transfer */
 525         if (config.bpw <= 8) {
 526                 spi_imx->rx = spi_imx_buf_rx_u8;
 527                 spi_imx->tx = spi_imx_buf_tx_u8;
 528         } else if (config.bpw <= 16) {
 529                 spi_imx->rx = spi_imx_buf_rx_u16;
 530                 spi_imx->tx = spi_imx_buf_tx_u16;
 531         } else if (config.bpw <= 32) {
 532                 spi_imx->rx = spi_imx_buf_rx_u32;
 533                 spi_imx->tx = spi_imx_buf_tx_u32;
 534         } else
 535                 BUG();
 536
 537         spi_imx->devtype_data.config(spi_imx, &config);
 538
 539         return 0;
 540 }
 541
 542 static int spi_imx_transfer(struct spi_device *spi,
 543                                 struct spi_transfer *transfer)
 544 {
 545         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 546
 547         spi_imx->tx_buf = transfer->tx_buf;
 548         spi_imx->rx_buf = transfer->rx_buf;
 549         spi_imx->count = transfer->len;
 550         spi_imx->txfifo = 0;
 551
 552         init_completion(&spi_imx->xfer_done);
 553
 554         spi_imx_push(spi_imx);
 555
 556         spi_imx->devtype_data.intctrl(spi_imx, MXC_INT_TE);
 557
 558         wait_for_completion(&spi_imx->xfer_done);
 559
 560         return transfer->len;
 561 }
 562
 563 static int spi_imx_setup(struct spi_device *spi)
 564 {
 565         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 566         int gpio = spi_imx->chipselect[spi->chip_select];
 567
 568         dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
 569                  spi->mode, spi->bits_per_word, spi->max_speed_hz);
 570
 571         if (gpio >= 0)
 572                 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
 573
 574         spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
 575
 576         return 0;
 577 }
 578
 579 static void spi_imx_cleanup(struct spi_device *spi)
 580 {
 581 }
 582
 583 static struct platform_device_id spi_imx_devtype[] = {
 584         {
 585                 .name = DRIVER_NAME,
 586                 .driver_data = SPI_IMX_VER_AUTODETECT,
 587         }, {
 588                 .name = "imx1-cspi",
 589                 .driver_data = SPI_IMX_VER_IMX1,
 590         }, {
 591                 .name = "imx21-cspi",
 592                 .driver_data = SPI_IMX_VER_0_0,
 593         }, {
 594                 .name = "imx25-cspi",
 595                 .driver_data = SPI_IMX_VER_0_7,
 596         }, {
 597                 .name = "imx27-cspi",
 598                 .driver_data = SPI_IMX_VER_0_0,
 599         }, {
 600                 .name = "imx31-cspi",
 601                 .driver_data = SPI_IMX_VER_0_4,
 602         }, {
 603                 .name = "imx35-cspi",
 604                 .driver_data = SPI_IMX_VER_0_7,
 605         }, {
 606                 /* sentinel */
 607         }
 608 };
 609
 610 static int __devinit spi_imx_probe(struct platform_device *pdev)
 611 {
 612         struct spi_imx_master *mxc_platform_info;
 613         struct spi_master *master;
 614         struct spi_imx_data *spi_imx;
 615         struct resource *res;
 616         int i, ret;
 617
 618         mxc_platform_info = dev_get_platdata(&pdev->dev);
 619         if (!mxc_platform_info) {
 620                 dev_err(&pdev->dev, "can't get the platform data\n");
 621                 return -EINVAL;
 622         }
 623
 624         master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
 625         if (!master)
 626                 return -ENOMEM;
 627
 628         platform_set_drvdata(pdev, master);
 629
 630         master->bus_num = pdev->id;
 631         master->num_chipselect = mxc_platform_info->num_chipselect;
 632
 633         spi_imx = spi_master_get_devdata(master);
 634         spi_imx->bitbang.master = spi_master_get(master);
 635         spi_imx->chipselect = mxc_platform_info->chipselect;
 636
 637         for (i = 0; i < master->num_chipselect; i++) {
 638                 if (spi_imx->chipselect[i] < 0)
 639                         continue;
 640                 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
 641                 if (ret) {
 642                         while (i > 0) {
 643                                 i--;
 644                                 if (spi_imx->chipselect[i] >= 0)
 645                                         gpio_free(spi_imx->chipselect[i]);
 646                         }
 647                         dev_err(&pdev->dev, "can't get cs gpios\n");
 648                         goto out_master_put;
 649                 }
 650         }
 651
 652         spi_imx->bitbang.chipselect = spi_imx_chipselect;
 653         spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
 654         spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
 655         spi_imx->bitbang.master->setup = spi_imx_setup;
 656         spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
 657         spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 658
 659         init_completion(&spi_imx->xfer_done);
 660
 661         if (pdev->id_entry->driver_data == SPI_IMX_VER_AUTODETECT) {
 662                 if (cpu_is_mx25() || cpu_is_mx35())
 663                         spi_imx->devtype_data =
 664                                 spi_imx_devtype_data[SPI_IMX_VER_0_7];
 665                 else if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
 666                         spi_imx->devtype_data =
 667                                 spi_imx_devtype_data[SPI_IMX_VER_0_4];
 668                 else if (cpu_is_mx27() || cpu_is_mx21())
 669                         spi_imx->devtype_data =
 670                                 spi_imx_devtype_data[SPI_IMX_VER_0_0];
 671                 else if (cpu_is_mx1())
 672                         spi_imx->devtype_data =
 673                                 spi_imx_devtype_data[SPI_IMX_VER_IMX1];
 674                 else
 675                         BUG();
 676         } else
 677                 spi_imx->devtype_data =
 678                         spi_imx_devtype_data[pdev->id_entry->driver_data];
 679
 680         if (!spi_imx->devtype_data.intctrl) {
 681                 dev_err(&pdev->dev, "no support for this device compiled in\n");
 682                 ret = -ENODEV;
 683                 goto out_gpio_free;
 684         }
 685
 686         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 687         if (!res) {
 688                 dev_err(&pdev->dev, "can't get platform resource\n");
 689                 ret = -ENOMEM;
 690                 goto out_gpio_free;
 691         }
 692
 693         if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
 694                 dev_err(&pdev->dev, "request_mem_region failed\n");
 695                 ret = -EBUSY;
 696                 goto out_gpio_free;
 697         }
 698
 699         spi_imx->base = ioremap(res->start, resource_size(res));
 700         if (!spi_imx->base) {
 701                 ret = -EINVAL;
 702                 goto out_release_mem;
 703         }
 704
 705         spi_imx->irq = platform_get_irq(pdev, 0);
 706         if (spi_imx->irq <= 0) {
 707                 ret = -EINVAL;
 708                 goto out_iounmap;
 709         }
 710
 711         ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
 712         if (ret) {
 713                 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
 714                 goto out_iounmap;
 715         }
 716
 717         spi_imx->clk = clk_get(&pdev->dev, NULL);
 718         if (IS_ERR(spi_imx->clk)) {
 719                 dev_err(&pdev->dev, "unable to get clock\n");
 720                 ret = PTR_ERR(spi_imx->clk);
 721                 goto out_free_irq;
 722         }
 723
 724         clk_enable(spi_imx->clk);
 725         spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
 726
 727         spi_imx->devtype_data.reset(spi_imx);
 728
 729         spi_imx->devtype_data.intctrl(spi_imx, 0);
 730
 731         ret = spi_bitbang_start(&spi_imx->bitbang);
 732         if (ret) {
 733                 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
 734                 goto out_clk_put;
 735         }
 736
 737         dev_info(&pdev->dev, "probed\n");
 738
 739         return ret;
 740
 741 out_clk_put:
 742         clk_disable(spi_imx->clk);
 743         clk_put(spi_imx->clk);
 744 out_free_irq:
 745         free_irq(spi_imx->irq, spi_imx);
 746 out_iounmap:
 747         iounmap(spi_imx->base);
 748 out_release_mem:
 749         release_mem_region(res->start, resource_size(res));
 750 out_gpio_free:
 751         for (i = 0; i < master->num_chipselect; i++)
 752                 if (spi_imx->chipselect[i] >= 0)
 753                         gpio_free(spi_imx->chipselect[i]);
 754 out_master_put:
 755         spi_master_put(master);
 756         kfree(master);
 757         platform_set_drvdata(pdev, NULL);
 758         return ret;
 759 }
 760
 761 static int __devexit spi_imx_remove(struct platform_device *pdev)
 762 {
 763         struct spi_master *master = platform_get_drvdata(pdev);
 764         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 765         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
 766         int i;
 767
 768         spi_bitbang_stop(&spi_imx->bitbang);
 769
 770         writel(0, spi_imx->base + MXC_CSPICTRL);
 771         clk_disable(spi_imx->clk);
 772         clk_put(spi_imx->clk);
 773         free_irq(spi_imx->irq, spi_imx);
 774         iounmap(spi_imx->base);
 775
 776         for (i = 0; i < master->num_chipselect; i++)
 777                 if (spi_imx->chipselect[i] >= 0)
 778                         gpio_free(spi_imx->chipselect[i]);
 779
 780         spi_master_put(master);
 781
 782         release_mem_region(res->start, resource_size(res));
 783
 784         platform_set_drvdata(pdev, NULL);
 785
 786         return 0;
 787 }
 788
 789 static struct platform_driver spi_imx_driver = {
 790         .driver = {
 791                    .name = DRIVER_NAME,
 792                    .owner = THIS_MODULE,
 793                    },
 794         .id_table = spi_imx_devtype,
 795         .probe = spi_imx_probe,
 796         .remove = __devexit_p(spi_imx_remove),
 797 };
 798
 799 static int __init spi_imx_init(void)
 800 {
 801         return platform_driver_register(&spi_imx_driver);
 802 }
 803
 804 static void __exit spi_imx_exit(void)
 805 {
 806         platform_driver_unregister(&spi_imx_driver);
 807 }
 808
 809 module_init(spi_imx_init);
 810 module_exit(spi_imx_exit);
 811
 812 MODULE_DESCRIPTION("SPI Master Controller driver");
 813 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
 814 MODULE_LICENSE("GPL");