drivers/spi/spi_bfin5xx.c

   1 /*
   2  * File:         drivers/spi/bfin5xx_spi.c
   3  * Based on:     N/A
   4  * Author:       Luke Yang (Analog Devices Inc.)
   5  *
   6  * Created:      March. 10th 2006
   7  * Description:  SPI controller driver for Blackfin 5xx
   8  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
   9  *
  10  * Modified:
  11  *      March 10, 2006  bfin5xx_spi.c Created. (Luke Yang)
  12  *      August 7, 2006  added full duplex mode (Axel Weiss & Luke Yang)
  13  *
  14  * Copyright 2004-2006 Analog Devices Inc.
  15  *
  16  * This program is free software ;  you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation ;  either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY ;  without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program ;  see the file COPYING.
  28  * If not, write to the Free Software Foundation,
  29  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 #include <linux/init.h>
  33 #include <linux/module.h>
  34 #include <linux/device.h>
  35 #include <linux/ioport.h>
  36 #include <linux/errno.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/platform_device.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/spi/spi.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/errno.h>
  43 #include <linux/delay.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/irq.h>
  47 #include <asm/delay.h>
  48 #include <asm/dma.h>
  49
  50 #include <asm/bfin5xx_spi.h>
  51
  52 MODULE_AUTHOR("Luke Yang");
  53 MODULE_DESCRIPTION("Blackfin 5xx SPI Contoller");
  54 MODULE_LICENSE("GPL");
  55
  56 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
  57
  58 #define DEFINE_SPI_REG(reg, off) \
  59 static inline u16 read_##reg(void) \
  60             { return *(volatile unsigned short*)(SPI0_REGBASE + off); } \
  61 static inline void write_##reg(u16 v) \
  62             {*(volatile unsigned short*)(SPI0_REGBASE + off) = v;\
  63              SSYNC();}
  64
  65 DEFINE_SPI_REG(CTRL, 0x00)
  66 DEFINE_SPI_REG(FLAG, 0x04)
  67 DEFINE_SPI_REG(STAT, 0x08)
  68 DEFINE_SPI_REG(TDBR, 0x0C)
  69 DEFINE_SPI_REG(RDBR, 0x10)
  70 DEFINE_SPI_REG(BAUD, 0x14)
  71 DEFINE_SPI_REG(SHAW, 0x18)
  72 #define START_STATE ((void*)0)
  73 #define RUNNING_STATE ((void*)1)
  74 #define DONE_STATE ((void*)2)
  75 #define ERROR_STATE ((void*)-1)
  76 #define QUEUE_RUNNING 0
  77 #define QUEUE_STOPPED 1
  78 int dma_requested;
  79
  80 struct driver_data {
  81         /* Driver model hookup */
  82         struct platform_device *pdev;
  83
  84         /* SPI framework hookup */
  85         struct spi_master *master;
  86
  87         /* BFIN hookup */
  88         struct bfin5xx_spi_master *master_info;
  89
  90         /* Driver message queue */
  91         struct workqueue_struct *workqueue;
  92         struct work_struct pump_messages;
  93         spinlock_t lock;
  94         struct list_head queue;
  95         int busy;
  96         int run;
  97
  98         /* Message Transfer pump */
  99         struct tasklet_struct pump_transfers;
 100
 101         /* Current message transfer state info */
 102         struct spi_message *cur_msg;
 103         struct spi_transfer *cur_transfer;
 104         struct chip_data *cur_chip;
 105         size_t len_in_bytes;
 106         size_t len;
 107         void *tx;
 108         void *tx_end;
 109         void *rx;
 110         void *rx_end;
 111         int dma_mapped;
 112         dma_addr_t rx_dma;
 113         dma_addr_t tx_dma;
 114         size_t rx_map_len;
 115         size_t tx_map_len;
 116         u8 n_bytes;
 117         void (*write) (struct driver_data *);
 118         void (*read) (struct driver_data *);
 119         void (*duplex) (struct driver_data *);
 120 };
 121
 122 struct chip_data {
 123         u16 ctl_reg;
 124         u16 baud;
 125         u16 flag;
 126
 127         u8 chip_select_num;
 128         u8 n_bytes;
 129         u32 width;              /* 0 or 1 */
 130         u8 enable_dma;
 131         u8 bits_per_word;       /* 8 or 16 */
 132         u8 cs_change_per_word;
 133         u8 cs_chg_udelay;
 134         void (*write) (struct driver_data *);
 135         void (*read) (struct driver_data *);
 136         void (*duplex) (struct driver_data *);
 137 };
 138
 139 void bfin_spi_enable(struct driver_data *drv_data)
 140 {
 141         u16 cr;
 142
 143         cr = read_CTRL();
 144         write_CTRL(cr | BIT_CTL_ENABLE);
 145         SSYNC();
 146 }
 147
 148 void bfin_spi_disable(struct driver_data *drv_data)
 149 {
 150         u16 cr;
 151
 152         cr = read_CTRL();
 153         write_CTRL(cr & (~BIT_CTL_ENABLE));
 154         SSYNC();
 155 }
 156
 157 /* Caculate the SPI_BAUD register value based on input HZ */
 158 static u16 hz_to_spi_baud(u32 speed_hz)
 159 {
 160         u_long sclk = get_sclk();
 161         u16 spi_baud = (sclk / (2 * speed_hz));
 162
 163         if ((sclk % (2 * speed_hz)) > 0)
 164                 spi_baud++;
 165
 166         pr_debug("sclk = %ld, speed_hz = %d, spi_baud = %d\n", sclk, speed_hz,
 167                  spi_baud);
 168
 169         return spi_baud;
 170 }
 171
 172 static int flush(struct driver_data *drv_data)
 173 {
 174         unsigned long limit = loops_per_jiffy << 1;
 175
 176         /* wait for stop and clear stat */
 177         while (!(read_STAT() & BIT_STAT_SPIF) && limit--)
 178                 continue;
 179
 180         write_STAT(BIT_STAT_CLR);
 181
 182         return limit;
 183 }
 184
 185 /* stop controller and re-config current chip*/
 186 static void restore_state(struct driver_data *drv_data)
 187 {
 188         struct chip_data *chip = drv_data->cur_chip;
 189
 190         /* Clear status and disable clock */
 191         write_STAT(BIT_STAT_CLR);
 192         bfin_spi_disable(drv_data);
 193         pr_debug("restoring spi ctl state\n");
 194
 195 #if defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
 196         pr_debug("chip select number is %d\n", chip->chip_select_num);
 197
 198         switch (chip->chip_select_num) {
 199         case 1:
 200                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3c00);
 201                 SSYNC();
 202                 break;
 203
 204         case 2:
 205         case 3:
 206                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJSE_SPI);
 207                 SSYNC();
 208                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
 209                 SSYNC();
 210                 break;
 211
 212         case 4:
 213                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS4E_SPI);
 214                 SSYNC();
 215                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3840);
 216                 SSYNC();
 217                 break;
 218
 219         case 5:
 220                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS5E_SPI);
 221                 SSYNC();
 222                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3820);
 223                 SSYNC();
 224                 break;
 225
 226         case 6:
 227                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS6E_SPI);
 228                 SSYNC();
 229                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3810);
 230                 SSYNC();
 231                 break;
 232
 233         case 7:
 234                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJCE_SPI);
 235                 SSYNC();
 236                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
 237                 SSYNC();
 238                 break;
 239         }
 240 #endif
 241
 242         /* Load the registers */
 243         write_CTRL(chip->ctl_reg);
 244         write_BAUD(chip->baud);
 245         write_FLAG(chip->flag);
 246 }
 247
 248 /* used to kick off transfer in rx mode */
 249 static unsigned short dummy_read(void)
 250 {
 251         unsigned short tmp;
 252         tmp = read_RDBR();
 253         return tmp;
 254 }
 255
 256 static void null_writer(struct driver_data *drv_data)
 257 {
 258         u8 n_bytes = drv_data->n_bytes;
 259
 260         while (drv_data->tx < drv_data->tx_end) {
 261                 write_TDBR(0);
 262                 while ((read_STAT() & BIT_STAT_TXS))
 263                         continue;
 264                 drv_data->tx += n_bytes;
 265         }
 266 }
 267
 268 static void null_reader(struct driver_data *drv_data)
 269 {
 270         u8 n_bytes = drv_data->n_bytes;
 271         dummy_read();
 272
 273         while (drv_data->rx < drv_data->rx_end) {
 274                 while (!(read_STAT() & BIT_STAT_RXS))
 275                         continue;
 276                 dummy_read();
 277                 drv_data->rx += n_bytes;
 278         }
 279 }
 280
 281 static void u8_writer(struct driver_data *drv_data)
 282 {
 283         pr_debug("cr8-s is 0x%x\n", read_STAT());
 284         while (drv_data->tx < drv_data->tx_end) {
 285                 write_TDBR(*(u8 *) (drv_data->tx));
 286                 while (read_STAT() & BIT_STAT_TXS)
 287                         continue;
 288                 ++drv_data->tx;
 289         }
 290
 291         /* poll for SPI completion before returning */
 292         while (!(read_STAT() & BIT_STAT_SPIF))
 293                 continue;
 294 }
 295
 296 static void u8_cs_chg_writer(struct driver_data *drv_data)
 297 {
 298         struct chip_data *chip = drv_data->cur_chip;
 299
 300         while (drv_data->tx < drv_data->tx_end) {
 301                 write_FLAG(chip->flag);
 302                 SSYNC();
 303
 304                 write_TDBR(*(u8 *) (drv_data->tx));
 305                 while (read_STAT() & BIT_STAT_TXS)
 306                         continue;
 307                 while (!(read_STAT() & BIT_STAT_SPIF))
 308                         continue;
 309                 write_FLAG(0xFF00 | chip->flag);
 310                 SSYNC();
 311                 if (chip->cs_chg_udelay)
 312                         udelay(chip->cs_chg_udelay);
 313                 ++drv_data->tx;
 314         }
 315         write_FLAG(0xFF00);
 316         SSYNC();
 317 }
 318
 319 static void u8_reader(struct driver_data *drv_data)
 320 {
 321         pr_debug("cr-8 is 0x%x\n", read_STAT());
 322
 323         /* clear TDBR buffer before read(else it will be shifted out) */
 324         write_TDBR(0xFFFF);
 325
 326         dummy_read();
 327
 328         while (drv_data->rx < drv_data->rx_end - 1) {
 329                 while (!(read_STAT() & BIT_STAT_RXS))
 330                         continue;
 331                 *(u8 *) (drv_data->rx) = read_RDBR();
 332                 ++drv_data->rx;
 333         }
 334
 335         while (!(read_STAT() & BIT_STAT_RXS))
 336                 continue;
 337         *(u8 *) (drv_data->rx) = read_SHAW();
 338         ++drv_data->rx;
 339 }
 340
 341 static void u8_cs_chg_reader(struct driver_data *drv_data)
 342 {
 343         struct chip_data *chip = drv_data->cur_chip;
 344
 345         while (drv_data->rx < drv_data->rx_end) {
 346                 write_FLAG(chip->flag);
 347                 SSYNC();
 348
 349                 read_RDBR();    /* kick off */
 350                 while (!(read_STAT() & BIT_STAT_RXS))
 351                         continue;
 352                 while (!(read_STAT() & BIT_STAT_SPIF))
 353                         continue;
 354                 *(u8 *) (drv_data->rx) = read_SHAW();
 355                 write_FLAG(0xFF00 | chip->flag);
 356                 SSYNC();
 357                 if (chip->cs_chg_udelay)
 358                         udelay(chip->cs_chg_udelay);
 359                 ++drv_data->rx;
 360         }
 361         write_FLAG(0xFF00);
 362         SSYNC();
 363 }
 364
 365 static void u8_duplex(struct driver_data *drv_data)
 366 {
 367         /* in duplex mode, clk is triggered by writing of TDBR */
 368         while (drv_data->rx < drv_data->rx_end) {
 369                 write_TDBR(*(u8 *) (drv_data->tx));
 370                 while (!(read_STAT() & BIT_STAT_SPIF))
 371                         continue;
 372                 while (!(read_STAT() & BIT_STAT_RXS))
 373                         continue;
 374                 *(u8 *) (drv_data->rx) = read_RDBR();
 375                 ++drv_data->rx;
 376                 ++drv_data->tx;
 377         }
 378 }
 379
 380 static void u8_cs_chg_duplex(struct driver_data *drv_data)
 381 {
 382         struct chip_data *chip = drv_data->cur_chip;
 383
 384         while (drv_data->rx < drv_data->rx_end) {
 385                 write_FLAG(chip->flag);
 386                 SSYNC();
 387
 388                 write_TDBR(*(u8 *) (drv_data->tx));
 389                 while (!(read_STAT() & BIT_STAT_SPIF))
 390                         continue;
 391                 while (!(read_STAT() & BIT_STAT_RXS))
 392                         continue;
 393                 *(u8 *) (drv_data->rx) = read_RDBR();
 394                 write_FLAG(0xFF00 | chip->flag);
 395                 SSYNC();
 396                 if (chip->cs_chg_udelay)
 397                         udelay(chip->cs_chg_udelay);
 398                 ++drv_data->rx;
 399                 ++drv_data->tx;
 400         }
 401         write_FLAG(0xFF00);
 402         SSYNC();
 403 }
 404
 405 static void u16_writer(struct driver_data *drv_data)
 406 {
 407         pr_debug("cr16 is 0x%x\n", read_STAT());
 408         while (drv_data->tx < drv_data->tx_end) {
 409                 write_TDBR(*(u16 *) (drv_data->tx));
 410                 while ((read_STAT() & BIT_STAT_TXS))
 411                         continue;
 412                 drv_data->tx += 2;
 413         }
 414
 415         /* poll for SPI completion before returning */
 416         while (!(read_STAT() & BIT_STAT_SPIF))
 417                 continue;
 418 }
 419
 420 static void u16_cs_chg_writer(struct driver_data *drv_data)
 421 {
 422         struct chip_data *chip = drv_data->cur_chip;
 423
 424         while (drv_data->tx < drv_data->tx_end) {
 425                 write_FLAG(chip->flag);
 426                 SSYNC();
 427
 428                 write_TDBR(*(u16 *) (drv_data->tx));
 429                 while ((read_STAT() & BIT_STAT_TXS))
 430                         continue;
 431                 while (!(read_STAT() & BIT_STAT_SPIF))
 432                         continue;
 433                 write_FLAG(0xFF00 | chip->flag);
 434                 SSYNC();
 435                 if (chip->cs_chg_udelay)
 436                         udelay(chip->cs_chg_udelay);
 437                 drv_data->tx += 2;
 438         }
 439         write_FLAG(0xFF00);
 440         SSYNC();
 441 }
 442
 443 static void u16_reader(struct driver_data *drv_data)
 444 {
 445         pr_debug("cr-16 is 0x%x\n", read_STAT());
 446         dummy_read();
 447
 448         while (drv_data->rx < (drv_data->rx_end - 2)) {
 449                 while (!(read_STAT() & BIT_STAT_RXS))
 450                         continue;
 451                 *(u16 *) (drv_data->rx) = read_RDBR();
 452                 drv_data->rx += 2;
 453         }
 454
 455         while (!(read_STAT() & BIT_STAT_RXS))
 456                 continue;
 457         *(u16 *) (drv_data->rx) = read_SHAW();
 458         drv_data->rx += 2;
 459 }
 460
 461 static void u16_cs_chg_reader(struct driver_data *drv_data)
 462 {
 463         struct chip_data *chip = drv_data->cur_chip;
 464
 465         while (drv_data->rx < drv_data->rx_end) {
 466                 write_FLAG(chip->flag);
 467                 SSYNC();
 468
 469                 read_RDBR();    /* kick off */
 470                 while (!(read_STAT() & BIT_STAT_RXS))
 471                         continue;
 472                 while (!(read_STAT() & BIT_STAT_SPIF))
 473                         continue;
 474                 *(u16 *) (drv_data->rx) = read_SHAW();
 475                 write_FLAG(0xFF00 | chip->flag);
 476                 SSYNC();
 477                 if (chip->cs_chg_udelay)
 478                         udelay(chip->cs_chg_udelay);
 479                 drv_data->rx += 2;
 480         }
 481         write_FLAG(0xFF00);
 482         SSYNC();
 483 }
 484
 485 static void u16_duplex(struct driver_data *drv_data)
 486 {
 487         /* in duplex mode, clk is triggered by writing of TDBR */
 488         while (drv_data->tx < drv_data->tx_end) {
 489                 write_TDBR(*(u16 *) (drv_data->tx));
 490                 while (!(read_STAT() & BIT_STAT_SPIF))
 491                         continue;
 492                 while (!(read_STAT() & BIT_STAT_RXS))
 493                         continue;
 494                 *(u16 *) (drv_data->rx) = read_RDBR();
 495                 drv_data->rx += 2;
 496                 drv_data->tx += 2;
 497         }
 498 }
 499
 500 static void u16_cs_chg_duplex(struct driver_data *drv_data)
 501 {
 502         struct chip_data *chip = drv_data->cur_chip;
 503
 504         while (drv_data->tx < drv_data->tx_end) {
 505                 write_FLAG(chip->flag);
 506                 SSYNC();
 507
 508                 write_TDBR(*(u16 *) (drv_data->tx));
 509                 while (!(read_STAT() & BIT_STAT_SPIF))
 510                         continue;
 511                 while (!(read_STAT() & BIT_STAT_RXS))
 512                         continue;
 513                 *(u16 *) (drv_data->rx) = read_RDBR();
 514                 write_FLAG(0xFF00 | chip->flag);
 515                 SSYNC();
 516                 if (chip->cs_chg_udelay)
 517                         udelay(chip->cs_chg_udelay);
 518                 drv_data->rx += 2;
 519                 drv_data->tx += 2;
 520         }
 521         write_FLAG(0xFF00);
 522         SSYNC();
 523 }
 524
 525 /* test if ther is more transfer to be done */
 526 static void *next_transfer(struct driver_data *drv_data)
 527 {
 528         struct spi_message *msg = drv_data->cur_msg;
 529         struct spi_transfer *trans = drv_data->cur_transfer;
 530
 531         /* Move to next transfer */
 532         if (trans->transfer_list.next != &msg->transfers) {
 533                 drv_data->cur_transfer =
 534                     list_entry(trans->transfer_list.next,
 535                                struct spi_transfer, transfer_list);
 536                 return RUNNING_STATE;
 537         } else
 538                 return DONE_STATE;
 539 }
 540
 541 /*
 542  * caller already set message->status;
 543  * dma and pio irqs are blocked give finished message back
 544  */
 545 static void giveback(struct driver_data *drv_data)
 546 {
 547         struct spi_transfer *last_transfer;
 548         unsigned long flags;
 549         struct spi_message *msg;
 550
 551         spin_lock_irqsave(&drv_data->lock, flags);
 552         msg = drv_data->cur_msg;
 553         drv_data->cur_msg = NULL;
 554         drv_data->cur_transfer = NULL;
 555         drv_data->cur_chip = NULL;
 556         queue_work(drv_data->workqueue, &drv_data->pump_messages);
 557         spin_unlock_irqrestore(&drv_data->lock, flags);
 558
 559         last_transfer = list_entry(msg->transfers.prev,
 560                                    struct spi_transfer, transfer_list);
 561
 562         msg->state = NULL;
 563
 564         /* disable chip select signal. And not stop spi in autobuffer mode */
 565         if (drv_data->tx_dma != 0xFFFF) {
 566                 write_FLAG(0xFF00);
 567                 bfin_spi_disable(drv_data);
 568         }
 569
 570         if (msg->complete)
 571                 msg->complete(msg->context);
 572 }
 573
 574 static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
 575 {
 576         struct driver_data *drv_data = (struct driver_data *)dev_id;
 577         struct spi_message *msg = drv_data->cur_msg;
 578
 579         pr_debug("in dma_irq_handler\n");
 580         clear_dma_irqstat(CH_SPI);
 581
 582         /*
 583          * wait for the last transaction shifted out.  yes, these two
 584          * while loops are supposed to be the same (see the HRM).
 585          */
 586         if (drv_data->tx != NULL) {
 587                 while (bfin_read_SPI_STAT() & TXS)
 588                         continue;
 589                 while (bfin_read_SPI_STAT() & TXS)
 590                         continue;
 591         }
 592
 593         while (!(bfin_read_SPI_STAT() & SPIF))
 594                 continue;
 595
 596         bfin_spi_disable(drv_data);
 597
 598         msg->actual_length += drv_data->len_in_bytes;
 599
 600         /* Move to next transfer */
 601         msg->state = next_transfer(drv_data);
 602
 603         /* Schedule transfer tasklet */
 604         tasklet_schedule(&drv_data->pump_transfers);
 605
 606         /* free the irq handler before next transfer */
 607         pr_debug("disable dma channel irq%d\n", CH_SPI);
 608         dma_disable_irq(CH_SPI);
 609
 610         return IRQ_HANDLED;
 611 }
 612
 613 static void pump_transfers(unsigned long data)
 614 {
 615         struct driver_data *drv_data = (struct driver_data *)data;
 616         struct spi_message *message = NULL;
 617         struct spi_transfer *transfer = NULL;
 618         struct spi_transfer *previous = NULL;
 619         struct chip_data *chip = NULL;
 620         u16 cr, width, dma_width, dma_config;
 621         u32 tranf_success = 1;
 622
 623         /* Get current state information */
 624         message = drv_data->cur_msg;
 625         transfer = drv_data->cur_transfer;
 626         chip = drv_data->cur_chip;
 627
 628         /*
 629          * if msg is error or done, report it back using complete() callback
 630          */
 631
 632          /* Handle for abort */
 633         if (message->state == ERROR_STATE) {
 634                 message->status = -EIO;
 635                 giveback(drv_data);
 636                 return;
 637         }
 638
 639         /* Handle end of message */
 640         if (message->state == DONE_STATE) {
 641                 message->status = 0;
 642                 giveback(drv_data);
 643                 return;
 644         }
 645
 646         /* Delay if requested at end of transfer */
 647         if (message->state == RUNNING_STATE) {
 648                 previous = list_entry(transfer->transfer_list.prev,
 649                                       struct spi_transfer, transfer_list);
 650                 if (previous->delay_usecs)
 651                         udelay(previous->delay_usecs);
 652         }
 653
 654         /* Setup the transfer state based on the type of transfer */
 655         if (flush(drv_data) == 0) {
 656                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
 657                 message->status = -EIO;
 658                 giveback(drv_data);
 659                 return;
 660         }
 661
 662         if (transfer->tx_buf != NULL) {
 663                 drv_data->tx = (void *)transfer->tx_buf;
 664                 drv_data->tx_end = drv_data->tx + transfer->len;
 665                 pr_debug("tx_buf is %p, tx_end is %p\n", transfer->tx_buf,
 666                          drv_data->tx_end);
 667         } else {
 668                 drv_data->tx = NULL;
 669         }
 670
 671         if (transfer->rx_buf != NULL) {
 672                 drv_data->rx = transfer->rx_buf;
 673                 drv_data->rx_end = drv_data->rx + transfer->len;
 674                 pr_debug("rx_buf is %p, rx_end is %p\n", transfer->rx_buf,
 675                          drv_data->rx_end);
 676         } else {
 677                 drv_data->rx = NULL;
 678         }
 679
 680         drv_data->rx_dma = transfer->rx_dma;
 681         drv_data->tx_dma = transfer->tx_dma;
 682         drv_data->len_in_bytes = transfer->len;
 683
 684         width = chip->width;
 685         if (width == CFG_SPI_WORDSIZE16) {
 686                 drv_data->len = (transfer->len) >> 1;
 687         } else {
 688                 drv_data->len = transfer->len;
 689         }
 690         drv_data->write = drv_data->tx ? chip->write : null_writer;
 691         drv_data->read = drv_data->rx ? chip->read : null_reader;
 692         drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
 693         pr_debug
 694             ("transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
 695              drv_data->write, chip->write, null_writer);
 696
 697         /* speed and width has been set on per message */
 698         message->state = RUNNING_STATE;
 699         dma_config = 0;
 700
 701         /* restore spi status for each spi transfer */
 702         if (transfer->speed_hz) {
 703                 write_BAUD(hz_to_spi_baud(transfer->speed_hz));
 704         } else {
 705                 write_BAUD(chip->baud);
 706         }
 707         write_FLAG(chip->flag);
 708
 709         pr_debug("now pumping a transfer: width is %d, len is %d\n", width,
 710                  transfer->len);
 711
 712         /*
 713          * Try to map dma buffer and do a dma transfer if
 714          * successful use different way to r/w according to
 715          * drv_data->cur_chip->enable_dma
 716          */
 717         if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
 718
 719                 write_STAT(BIT_STAT_CLR);
 720                 disable_dma(CH_SPI);
 721                 clear_dma_irqstat(CH_SPI);
 722                 bfin_spi_disable(drv_data);
 723
 724                 /* config dma channel */
 725                 pr_debug("doing dma transfer\n");
 726                 if (width == CFG_SPI_WORDSIZE16) {
 727                         set_dma_x_count(CH_SPI, drv_data->len);
 728                         set_dma_x_modify(CH_SPI, 2);
 729                         dma_width = WDSIZE_16;
 730                 } else {
 731                         set_dma_x_count(CH_SPI, drv_data->len);
 732                         set_dma_x_modify(CH_SPI, 1);
 733                         dma_width = WDSIZE_8;
 734                 }
 735
 736                 /* set transfer width,direction. And enable spi */
 737                 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 738
 739                 /* dirty hack for autobuffer DMA mode */
 740                 if (drv_data->tx_dma == 0xFFFF) {
 741                         pr_debug("doing autobuffer DMA out.\n");
 742
 743                         /* no irq in autobuffer mode */
 744                         dma_config =
 745                             (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
 746                         set_dma_config(CH_SPI, dma_config);
 747                         set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx);
 748                         enable_dma(CH_SPI);
 749                         write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
 750                                    (CFG_SPI_ENABLE << 14));
 751
 752                         /* just return here, there can only be one transfer in this mode */
 753                         message->status = 0;
 754                         giveback(drv_data);
 755                         return;
 756                 }
 757
 758                 /* In dma mode, rx or tx must be NULL in one transfer */
 759                 if (drv_data->rx != NULL) {
 760                         /* set transfer mode, and enable SPI */
 761                         pr_debug("doing DMA in.\n");
 762
 763                         /* disable SPI before write to TDBR */
 764                         write_CTRL(cr & ~BIT_CTL_ENABLE);
 765
 766                         /* clear tx reg soformer data is not shifted out */
 767                         write_TDBR(0xFF);
 768
 769                         set_dma_x_count(CH_SPI, drv_data->len);
 770
 771                         /* start dma */
 772                         dma_enable_irq(CH_SPI);
 773                         dma_config = (WNR | RESTART | dma_width | DI_EN);
 774                         set_dma_config(CH_SPI, dma_config);
 775                         set_dma_start_addr(CH_SPI, (unsigned long)drv_data->rx);
 776                         enable_dma(CH_SPI);
 777
 778                         cr |=
 779                             CFG_SPI_DMAREAD | (width << 8) | (CFG_SPI_ENABLE <<
 780                                                               14);
 781                         /* set transfer mode, and enable SPI */
 782                         write_CTRL(cr);
 783                 } else if (drv_data->tx != NULL) {
 784                         pr_debug("doing DMA out.\n");
 785
 786                         /* start dma */
 787                         dma_enable_irq(CH_SPI);
 788                         dma_config = (RESTART | dma_width | DI_EN);
 789                         set_dma_config(CH_SPI, dma_config);
 790                         set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx);
 791                         enable_dma(CH_SPI);
 792
 793                         write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
 794                                    (CFG_SPI_ENABLE << 14));
 795
 796                 }
 797         } else {
 798                 /* IO mode write then read */
 799                 pr_debug("doing IO transfer\n");
 800
 801                 write_STAT(BIT_STAT_CLR);
 802
 803                 if (drv_data->tx != NULL && drv_data->rx != NULL) {
 804                         /* full duplex mode */
 805                         BUG_ON((drv_data->tx_end - drv_data->tx) !=
 806                                (drv_data->rx_end - drv_data->rx));
 807                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));  /* clear the TIMOD bits */
 808                         cr |=
 809                             CFG_SPI_WRITE | (width << 8) | (CFG_SPI_ENABLE <<
 810                                                             14);
 811                         pr_debug("IO duplex: cr is 0x%x\n", cr);
 812
 813                         write_CTRL(cr);
 814                         SSYNC();
 815
 816                         drv_data->duplex(drv_data);
 817
 818                         if (drv_data->tx != drv_data->tx_end)
 819                                 tranf_success = 0;
 820                 } else if (drv_data->tx != NULL) {
 821                         /* write only half duplex */
 822                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));  /* clear the TIMOD bits */
 823                         cr |=
 824                             CFG_SPI_WRITE | (width << 8) | (CFG_SPI_ENABLE <<
 825                                                             14);
 826                         pr_debug("IO write: cr is 0x%x\n", cr);
 827
 828                         write_CTRL(cr);
 829                         SSYNC();
 830
 831                         drv_data->write(drv_data);
 832
 833                         if (drv_data->tx != drv_data->tx_end)
 834                                 tranf_success = 0;
 835                 } else if (drv_data->rx != NULL) {
 836                         /* read only half duplex */
 837                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));  /* cleare the TIMOD bits */
 838                         cr |=
 839                             CFG_SPI_READ | (width << 8) | (CFG_SPI_ENABLE <<
 840                                                            14);
 841                         pr_debug("IO read: cr is 0x%x\n", cr);
 842
 843                         write_CTRL(cr);
 844                         SSYNC();
 845
 846                         drv_data->read(drv_data);
 847                         if (drv_data->rx != drv_data->rx_end)
 848                                 tranf_success = 0;
 849                 }
 850
 851                 if (!tranf_success) {
 852                         pr_debug("IO write error!\n");
 853                         message->state = ERROR_STATE;
 854                 } else {
 855                         /* Update total byte transfered */
 856                         message->actual_length += drv_data->len;
 857
 858                         /* Move to next transfer of this msg */
 859                         message->state = next_transfer(drv_data);
 860                 }
 861
 862                 /* Schedule next transfer tasklet */
 863                 tasklet_schedule(&drv_data->pump_transfers);
 864
 865         }
 866 }
 867
 868 /* pop a msg from queue and kick off real transfer */
 869 static void pump_messages(struct work_struct *work)
 870 {
 871         struct driver_data *drv_data = container_of(work, struct driver_data, pump_messages);
 872         unsigned long flags;
 873
 874         /* Lock queue and check for queue work */
 875         spin_lock_irqsave(&drv_data->lock, flags);
 876         if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
 877                 /* pumper kicked off but no work to do */
 878                 drv_data->busy = 0;
 879                 spin_unlock_irqrestore(&drv_data->lock, flags);
 880                 return;
 881         }
 882
 883         /* Make sure we are not already running a message */
 884         if (drv_data->cur_msg) {
 885                 spin_unlock_irqrestore(&drv_data->lock, flags);
 886                 return;
 887         }
 888
 889         /* Extract head of queue */
 890         drv_data->cur_msg = list_entry(drv_data->queue.next,
 891                                        struct spi_message, queue);
 892         list_del_init(&drv_data->cur_msg->queue);
 893
 894         /* Initial message state */
 895         drv_data->cur_msg->state = START_STATE;
 896         drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
 897                                             struct spi_transfer, transfer_list);
 898
 899         /* Setup the SSP using the per chip configuration */
 900         drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
 901         restore_state(drv_data);
 902         pr_debug
 903             ("got a message to pump, state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
 904              drv_data->cur_chip->baud, drv_data->cur_chip->flag,
 905              drv_data->cur_chip->ctl_reg);
 906         pr_debug("the first transfer len is %d\n", drv_data->cur_transfer->len);
 907
 908         /* Mark as busy and launch transfers */
 909         tasklet_schedule(&drv_data->pump_transfers);
 910
 911         drv_data->busy = 1;
 912         spin_unlock_irqrestore(&drv_data->lock, flags);
 913 }
 914
 915 /*
 916  * got a msg to transfer, queue it in drv_data->queue.
 917  * And kick off message pumper
 918  */
 919 static int transfer(struct spi_device *spi, struct spi_message *msg)
 920 {
 921         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 922         unsigned long flags;
 923
 924         spin_lock_irqsave(&drv_data->lock, flags);
 925
 926         if (drv_data->run == QUEUE_STOPPED) {
 927                 spin_unlock_irqrestore(&drv_data->lock, flags);
 928                 return -ESHUTDOWN;
 929         }
 930
 931         msg->actual_length = 0;
 932         msg->status = -EINPROGRESS;
 933         msg->state = START_STATE;
 934
 935         pr_debug("adding an msg in transfer() \n");
 936         list_add_tail(&msg->queue, &drv_data->queue);
 937
 938         if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
 939                 queue_work(drv_data->workqueue, &drv_data->pump_messages);
 940
 941         spin_unlock_irqrestore(&drv_data->lock, flags);
 942
 943         return 0;
 944 }
 945
 946 /* first setup for new devices */
 947 static int setup(struct spi_device *spi)
 948 {
 949         struct bfin5xx_spi_chip *chip_info = NULL;
 950         struct chip_data *chip;
 951         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 952         u8 spi_flg;
 953
 954         /* Abort device setup if requested features are not supported */
 955         if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
 956                 dev_err(&spi->dev, "requested mode not fully supported\n");
 957                 return -EINVAL;
 958         }
 959
 960         /* Zero (the default) here means 8 bits */
 961         if (!spi->bits_per_word)
 962                 spi->bits_per_word = 8;
 963
 964         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 965                 return -EINVAL;
 966
 967         /* Only alloc (or use chip_info) on first setup */
 968         chip = spi_get_ctldata(spi);
 969         if (chip == NULL) {
 970                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 971                 if (!chip)
 972                         return -ENOMEM;
 973
 974                 chip->enable_dma = 0;
 975                 chip_info = spi->controller_data;
 976         }
 977
 978         /* chip_info isn't always needed */
 979         if (chip_info) {
 980                 chip->enable_dma = chip_info->enable_dma != 0
 981                     && drv_data->master_info->enable_dma;
 982                 chip->ctl_reg = chip_info->ctl_reg;
 983                 chip->bits_per_word = chip_info->bits_per_word;
 984                 chip->cs_change_per_word = chip_info->cs_change_per_word;
 985                 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
 986         }
 987
 988         /* translate common spi framework into our register */
 989         if (spi->mode & SPI_CPOL)
 990                 chip->ctl_reg |= CPOL;
 991         if (spi->mode & SPI_CPHA)
 992                 chip->ctl_reg |= CPHA;
 993         if (spi->mode & SPI_LSB_FIRST)
 994                 chip->ctl_reg |= LSBF;
 995         /* we dont support running in slave mode (yet?) */
 996         chip->ctl_reg |= MSTR;
 997
 998         /*
 999          * if any one SPI chip is registered and wants DMA, request the
1000          * DMA channel for it
1001          */
1002         if (chip->enable_dma && !dma_requested) {
1003                 /* register dma irq handler */
1004                 if (request_dma(CH_SPI, "BF53x_SPI_DMA") < 0) {
1005                         pr_debug
1006                             ("Unable to request BlackFin SPI DMA channel\n");
1007                         return -ENODEV;
1008                 }
1009                 if (set_dma_callback(CH_SPI, (void *)dma_irq_handler, drv_data)
1010                     < 0) {
1011                         pr_debug("Unable to set dma callback\n");
1012                         return -EPERM;
1013                 }
1014                 dma_disable_irq(CH_SPI);
1015                 dma_requested = 1;
1016         }
1017
1018         /*
1019          * Notice: for blackfin, the speed_hz is the value of register
1020          * SPI_BAUD, not the real baudrate
1021          */
1022         chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1023         spi_flg = ~(1 << (spi->chip_select));
1024         chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1025         chip->chip_select_num = spi->chip_select;
1026
1027         switch (chip->bits_per_word) {
1028         case 8:
1029                 chip->n_bytes = 1;
1030                 chip->width = CFG_SPI_WORDSIZE8;
1031                 chip->read = chip->cs_change_per_word ?
1032                         u8_cs_chg_reader : u8_reader;
1033                 chip->write = chip->cs_change_per_word ?
1034                         u8_cs_chg_writer : u8_writer;
1035                 chip->duplex = chip->cs_change_per_word ?
1036                         u8_cs_chg_duplex : u8_duplex;
1037                 break;
1038
1039         case 16:
1040                 chip->n_bytes = 2;
1041                 chip->width = CFG_SPI_WORDSIZE16;
1042                 chip->read = chip->cs_change_per_word ?
1043                         u16_cs_chg_reader : u16_reader;
1044                 chip->write = chip->cs_change_per_word ?
1045                         u16_cs_chg_writer : u16_writer;
1046                 chip->duplex = chip->cs_change_per_word ?
1047                         u16_cs_chg_duplex : u16_duplex;
1048                 break;
1049
1050         default:
1051                 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1052                                 chip->bits_per_word);
1053                 kfree(chip);
1054                 return -ENODEV;
1055         }
1056
1057         pr_debug("setup spi chip %s, width is %d, dma is %d,",
1058                         spi->modalias, chip->width, chip->enable_dma);
1059         pr_debug("ctl_reg is 0x%x, flag_reg is 0x%x\n",
1060                         chip->ctl_reg, chip->flag);
1061
1062         spi_set_ctldata(spi, chip);
1063
1064         return 0;
1065 }
1066
1067 /*
1068  * callback for spi framework.
1069  * clean driver specific data
1070  */
1071 static void cleanup(const struct spi_device *spi)
1072 {
1073         struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
1074
1075         kfree(chip);
1076 }
1077
1078 static inline int init_queue(struct driver_data *drv_data)
1079 {
1080         INIT_LIST_HEAD(&drv_data->queue);
1081         spin_lock_init(&drv_data->lock);
1082
1083         drv_data->run = QUEUE_STOPPED;
1084         drv_data->busy = 0;
1085
1086         /* init transfer tasklet */
1087         tasklet_init(&drv_data->pump_transfers,
1088                      pump_transfers, (unsigned long)drv_data);
1089
1090         /* init messages workqueue */
1091         INIT_WORK(&drv_data->pump_messages, pump_messages);
1092         drv_data->workqueue =
1093             create_singlethread_workqueue(drv_data->master->cdev.dev->bus_id);
1094         if (drv_data->workqueue == NULL)
1095                 return -EBUSY;
1096
1097         return 0;
1098 }
1099
1100 static inline int start_queue(struct driver_data *drv_data)
1101 {
1102         unsigned long flags;
1103
1104         spin_lock_irqsave(&drv_data->lock, flags);
1105
1106         if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1107                 spin_unlock_irqrestore(&drv_data->lock, flags);
1108                 return -EBUSY;
1109         }
1110
1111         drv_data->run = QUEUE_RUNNING;
1112         drv_data->cur_msg = NULL;
1113         drv_data->cur_transfer = NULL;
1114         drv_data->cur_chip = NULL;
1115         spin_unlock_irqrestore(&drv_data->lock, flags);
1116
1117         queue_work(drv_data->workqueue, &drv_data->pump_messages);
1118
1119         return 0;
1120 }
1121
1122 static inline int stop_queue(struct driver_data *drv_data)
1123 {
1124         unsigned long flags;
1125         unsigned limit = 500;
1126         int status = 0;
1127
1128         spin_lock_irqsave(&drv_data->lock, flags);
1129
1130         /*
1131          * This is a bit lame, but is optimized for the common execution path.
1132          * A wait_queue on the drv_data->busy could be used, but then the common
1133          * execution path (pump_messages) would be required to call wake_up or
1134          * friends on every SPI message. Do this instead
1135          */
1136         drv_data->run = QUEUE_STOPPED;
1137         while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1138                 spin_unlock_irqrestore(&drv_data->lock, flags);
1139                 msleep(10);
1140                 spin_lock_irqsave(&drv_data->lock, flags);
1141         }
1142
1143         if (!list_empty(&drv_data->queue) || drv_data->busy)
1144                 status = -EBUSY;
1145
1146         spin_unlock_irqrestore(&drv_data->lock, flags);
1147
1148         return status;
1149 }
1150
1151 static inline int destroy_queue(struct driver_data *drv_data)
1152 {
1153         int status;
1154
1155         status = stop_queue(drv_data);
1156         if (status != 0)
1157                 return status;
1158
1159         destroy_workqueue(drv_data->workqueue);
1160
1161         return 0;
1162 }
1163
1164 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1165 {
1166         struct device *dev = &pdev->dev;
1167         struct bfin5xx_spi_master *platform_info;
1168         struct spi_master *master;
1169         struct driver_data *drv_data = 0;
1170         int status = 0;
1171
1172         platform_info = dev->platform_data;
1173
1174         /* Allocate master with space for drv_data */
1175         master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1176         if (!master) {
1177                 dev_err(&pdev->dev, "can not alloc spi_master\n");
1178                 return -ENOMEM;
1179         }
1180         drv_data = spi_master_get_devdata(master);
1181         drv_data->master = master;
1182         drv_data->master_info = platform_info;
1183         drv_data->pdev = pdev;
1184
1185         master->bus_num = pdev->id;
1186         master->num_chipselect = platform_info->num_chipselect;
1187         master->cleanup = cleanup;
1188         master->setup = setup;
1189         master->transfer = transfer;
1190
1191         /* Initial and start queue */
1192         status = init_queue(drv_data);
1193         if (status != 0) {
1194                 dev_err(&pdev->dev, "problem initializing queue\n");
1195                 goto out_error_queue_alloc;
1196         }
1197         status = start_queue(drv_data);
1198         if (status != 0) {
1199                 dev_err(&pdev->dev, "problem starting queue\n");
1200                 goto out_error_queue_alloc;
1201         }
1202
1203         /* Register with the SPI framework */
1204         platform_set_drvdata(pdev, drv_data);
1205         status = spi_register_master(master);
1206         if (status != 0) {
1207                 dev_err(&pdev->dev, "problem registering spi master\n");
1208                 goto out_error_queue_alloc;
1209         }
1210         pr_debug("controller probe successfully\n");
1211         return status;
1212
1213       out_error_queue_alloc:
1214         destroy_queue(drv_data);
1215         spi_master_put(master);
1216         return status;
1217 }
1218
1219 /* stop hardware and remove the driver */
1220 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1221 {
1222         struct driver_data *drv_data = platform_get_drvdata(pdev);
1223         int status = 0;
1224
1225         if (!drv_data)
1226                 return 0;
1227
1228         /* Remove the queue */
1229         status = destroy_queue(drv_data);
1230         if (status != 0)
1231                 return status;
1232
1233         /* Disable the SSP at the peripheral and SOC level */
1234         bfin_spi_disable(drv_data);
1235
1236         /* Release DMA */
1237         if (drv_data->master_info->enable_dma) {
1238                 if (dma_channel_active(CH_SPI))
1239                         free_dma(CH_SPI);
1240         }
1241
1242         /* Disconnect from the SPI framework */
1243         spi_unregister_master(drv_data->master);
1244
1245         /* Prevent double remove */
1246         platform_set_drvdata(pdev, NULL);
1247
1248         return 0;
1249 }
1250
1251 #ifdef CONFIG_PM
1252 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1253 {
1254         struct driver_data *drv_data = platform_get_drvdata(pdev);
1255         int status = 0;
1256
1257         status = stop_queue(drv_data);
1258         if (status != 0)
1259                 return status;
1260
1261         /* stop hardware */
1262         bfin_spi_disable(drv_data);
1263
1264         return 0;
1265 }
1266
1267 static int bfin5xx_spi_resume(struct platform_device *pdev)
1268 {
1269         struct driver_data *drv_data = platform_get_drvdata(pdev);
1270         int status = 0;
1271
1272         /* Enable the SPI interface */
1273         bfin_spi_enable(drv_data);
1274
1275         /* Start the queue running */
1276         status = start_queue(drv_data);
1277         if (status != 0) {
1278                 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1279                 return status;
1280         }
1281
1282         return 0;
1283 }
1284 #else
1285 #define bfin5xx_spi_suspend NULL
1286 #define bfin5xx_spi_resume NULL
1287 #endif                          /* CONFIG_PM */
1288
1289 static struct platform_driver bfin5xx_spi_driver = {
1290         .driver = {
1291                    .name = "bfin-spi-master",
1292                    .bus = &platform_bus_type,
1293                    .owner = THIS_MODULE,
1294                    },
1295         .probe = bfin5xx_spi_probe,
1296         .remove = __devexit_p(bfin5xx_spi_remove),
1297         .suspend = bfin5xx_spi_suspend,
1298         .resume = bfin5xx_spi_resume,
1299 };
1300
1301 static int __init bfin5xx_spi_init(void)
1302 {
1303         return platform_driver_register(&bfin5xx_spi_driver);
1304 }
1305
1306 module_init(bfin5xx_spi_init);
1307
1308 static void __exit bfin5xx_spi_exit(void)
1309 {
1310         platform_driver_unregister(&bfin5xx_spi_driver);
1311 }
1312
1313 module_exit(bfin5xx_spi_exit);