2 * Blackfin On-Chip SPI Driver
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
24 #include <linux/workqueue.h>
27 #include <asm/portmux.h>
28 #include <asm/bfin5xx_spi.h>
29 #include <asm/cacheflush.h>
31 #define DRV_NAME "bfin-spi"
32 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
33 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
34 #define DRV_VERSION "1.0"
36 MODULE_AUTHOR(DRV_AUTHOR);
37 MODULE_DESCRIPTION(DRV_DESC);
38 MODULE_LICENSE("GPL");
40 #define START_STATE ((void *)0)
41 #define RUNNING_STATE ((void *)1)
42 #define DONE_STATE ((void *)2)
43 #define ERROR_STATE ((void *)-1)
48 void (*write) (struct master_data *);
49 void (*read) (struct master_data *);
50 void (*duplex) (struct master_data *);
54 /* Driver model hookup */
55 struct platform_device *pdev;
57 /* SPI framework hookup */
58 struct spi_master *master;
60 /* Regs base of SPI controller */
61 void __iomem *regs_base;
63 /* Pin request list */
67 struct bfin5xx_spi_master *master_info;
69 /* Driver message queue */
70 struct workqueue_struct *workqueue;
71 struct work_struct pump_messages;
73 struct list_head queue;
77 /* Message Transfer pump */
78 struct tasklet_struct pump_transfers;
80 /* Current message transfer state info */
81 struct spi_message *cur_msg;
82 struct spi_transfer *cur_transfer;
83 struct slave_data *cur_chip;
105 const struct transfer_ops *ops;
115 u8 width; /* 0 or 1 */
117 u8 bits_per_word; /* 8 or 16 */
118 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
121 u8 pio_interrupt; /* use spi data irq */
122 const struct transfer_ops *ops;
125 #define DEFINE_SPI_REG(reg, off) \
126 static inline u16 read_##reg(struct master_data *drv_data) \
127 { return bfin_read16(drv_data->regs_base + off); } \
128 static inline void write_##reg(struct master_data *drv_data, u16 v) \
129 { bfin_write16(drv_data->regs_base + off, v); }
131 DEFINE_SPI_REG(CTRL, 0x00)
132 DEFINE_SPI_REG(FLAG, 0x04)
133 DEFINE_SPI_REG(STAT, 0x08)
134 DEFINE_SPI_REG(TDBR, 0x0C)
135 DEFINE_SPI_REG(RDBR, 0x10)
136 DEFINE_SPI_REG(BAUD, 0x14)
137 DEFINE_SPI_REG(SHAW, 0x18)
139 static void bfin_spi_enable(struct master_data *drv_data)
143 cr = read_CTRL(drv_data);
144 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
147 static void bfin_spi_disable(struct master_data *drv_data)
151 cr = read_CTRL(drv_data);
152 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
155 /* Caculate the SPI_BAUD register value based on input HZ */
156 static u16 hz_to_spi_baud(u32 speed_hz)
158 u_long sclk = get_sclk();
159 u16 spi_baud = (sclk / (2 * speed_hz));
161 if ((sclk % (2 * speed_hz)) > 0)
164 if (spi_baud < MIN_SPI_BAUD_VAL)
165 spi_baud = MIN_SPI_BAUD_VAL;
170 static int bfin_spi_flush(struct master_data *drv_data)
172 unsigned long limit = loops_per_jiffy << 1;
174 /* wait for stop and clear stat */
175 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit)
178 write_STAT(drv_data, BIT_STAT_CLR);
183 /* Chip select operation functions for cs_change flag */
184 static void bfin_spi_cs_active(struct master_data *drv_data, struct slave_data *chip)
186 if (likely(chip->chip_select_num)) {
187 u16 flag = read_FLAG(drv_data);
191 write_FLAG(drv_data, flag);
193 gpio_set_value(chip->cs_gpio, 0);
197 static void bfin_spi_cs_deactive(struct master_data *drv_data, struct slave_data *chip)
199 if (likely(chip->chip_select_num)) {
200 u16 flag = read_FLAG(drv_data);
204 write_FLAG(drv_data, flag);
206 gpio_set_value(chip->cs_gpio, 1);
209 /* Move delay here for consistency */
210 if (chip->cs_chg_udelay)
211 udelay(chip->cs_chg_udelay);
214 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
215 static inline void bfin_spi_cs_enable(struct master_data *drv_data, struct slave_data *chip)
217 u16 flag = read_FLAG(drv_data);
219 flag |= (chip->flag >> 8);
221 write_FLAG(drv_data, flag);
224 static inline void bfin_spi_cs_disable(struct master_data *drv_data, struct slave_data *chip)
226 u16 flag = read_FLAG(drv_data);
228 flag &= ~(chip->flag >> 8);
230 write_FLAG(drv_data, flag);
233 /* stop controller and re-config current chip*/
234 static void bfin_spi_restore_state(struct master_data *drv_data)
236 struct slave_data *chip = drv_data->cur_chip;
238 /* Clear status and disable clock */
239 write_STAT(drv_data, BIT_STAT_CLR);
240 bfin_spi_disable(drv_data);
241 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
243 /* Load the registers */
244 write_CTRL(drv_data, chip->ctl_reg);
245 write_BAUD(drv_data, chip->baud);
247 bfin_spi_enable(drv_data);
248 bfin_spi_cs_active(drv_data, chip);
251 /* used to kick off transfer in rx mode and read unwanted RX data */
252 static inline void bfin_spi_dummy_read(struct master_data *drv_data)
254 (void) read_RDBR(drv_data);
257 static void bfin_spi_u8_writer(struct master_data *drv_data)
259 /* clear RXS (we check for RXS inside the loop) */
260 bfin_spi_dummy_read(drv_data);
262 while (drv_data->tx < drv_data->tx_end) {
263 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
264 /* wait until transfer finished.
265 checking SPIF or TXS may not guarantee transfer completion */
266 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
268 /* discard RX data and clear RXS */
269 bfin_spi_dummy_read(drv_data);
273 static void bfin_spi_u8_reader(struct master_data *drv_data)
275 u16 tx_val = drv_data->cur_chip->idle_tx_val;
277 /* discard old RX data and clear RXS */
278 bfin_spi_dummy_read(drv_data);
280 while (drv_data->rx < drv_data->rx_end) {
281 write_TDBR(drv_data, tx_val);
282 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
284 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
288 static void bfin_spi_u8_duplex(struct master_data *drv_data)
290 /* discard old RX data and clear RXS */
291 bfin_spi_dummy_read(drv_data);
293 while (drv_data->rx < drv_data->rx_end) {
294 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
295 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
297 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
301 static const struct transfer_ops bfin_transfer_ops_u8 = {
302 .write = bfin_spi_u8_writer,
303 .read = bfin_spi_u8_reader,
304 .duplex = bfin_spi_u8_duplex,
307 static void bfin_spi_u16_writer(struct master_data *drv_data)
309 /* clear RXS (we check for RXS inside the loop) */
310 bfin_spi_dummy_read(drv_data);
312 while (drv_data->tx < drv_data->tx_end) {
313 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
315 /* wait until transfer finished.
316 checking SPIF or TXS may not guarantee transfer completion */
317 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
319 /* discard RX data and clear RXS */
320 bfin_spi_dummy_read(drv_data);
324 static void bfin_spi_u16_reader(struct master_data *drv_data)
326 u16 tx_val = drv_data->cur_chip->idle_tx_val;
328 /* discard old RX data and clear RXS */
329 bfin_spi_dummy_read(drv_data);
331 while (drv_data->rx < drv_data->rx_end) {
332 write_TDBR(drv_data, tx_val);
333 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
335 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
340 static void bfin_spi_u16_duplex(struct master_data *drv_data)
342 /* discard old RX data and clear RXS */
343 bfin_spi_dummy_read(drv_data);
345 while (drv_data->rx < drv_data->rx_end) {
346 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
348 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
350 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
355 static const struct transfer_ops bfin_transfer_ops_u16 = {
356 .write = bfin_spi_u16_writer,
357 .read = bfin_spi_u16_reader,
358 .duplex = bfin_spi_u16_duplex,
361 /* test if ther is more transfer to be done */
362 static void *bfin_spi_next_transfer(struct master_data *drv_data)
364 struct spi_message *msg = drv_data->cur_msg;
365 struct spi_transfer *trans = drv_data->cur_transfer;
367 /* Move to next transfer */
368 if (trans->transfer_list.next != &msg->transfers) {
369 drv_data->cur_transfer =
370 list_entry(trans->transfer_list.next,
371 struct spi_transfer, transfer_list);
372 return RUNNING_STATE;
378 * caller already set message->status;
379 * dma and pio irqs are blocked give finished message back
381 static void bfin_spi_giveback(struct master_data *drv_data)
383 struct slave_data *chip = drv_data->cur_chip;
384 struct spi_transfer *last_transfer;
386 struct spi_message *msg;
388 spin_lock_irqsave(&drv_data->lock, flags);
389 msg = drv_data->cur_msg;
390 drv_data->cur_msg = NULL;
391 drv_data->cur_transfer = NULL;
392 drv_data->cur_chip = NULL;
393 queue_work(drv_data->workqueue, &drv_data->pump_messages);
394 spin_unlock_irqrestore(&drv_data->lock, flags);
396 last_transfer = list_entry(msg->transfers.prev,
397 struct spi_transfer, transfer_list);
401 if (!drv_data->cs_change)
402 bfin_spi_cs_deactive(drv_data, chip);
404 /* Not stop spi in autobuffer mode */
405 if (drv_data->tx_dma != 0xFFFF)
406 bfin_spi_disable(drv_data);
409 msg->complete(msg->context);
412 /* spi data irq handler */
413 static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
415 struct master_data *drv_data = dev_id;
416 struct slave_data *chip = drv_data->cur_chip;
417 struct spi_message *msg = drv_data->cur_msg;
418 int n_bytes = drv_data->n_bytes;
420 /* wait until transfer finished. */
421 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
424 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
425 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
428 dev_dbg(&drv_data->pdev->dev, "last read\n");
430 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
431 else if (n_bytes == 1)
432 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
433 drv_data->rx += n_bytes;
436 msg->actual_length += drv_data->len_in_bytes;
437 if (drv_data->cs_change)
438 bfin_spi_cs_deactive(drv_data, chip);
439 /* Move to next transfer */
440 msg->state = bfin_spi_next_transfer(drv_data);
442 disable_irq(drv_data->spi_irq);
444 /* Schedule transfer tasklet */
445 tasklet_schedule(&drv_data->pump_transfers);
449 if (drv_data->rx && drv_data->tx) {
451 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
452 if (drv_data->n_bytes == 2) {
453 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
454 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
455 } else if (drv_data->n_bytes == 1) {
456 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
457 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
459 } else if (drv_data->rx) {
461 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
462 if (drv_data->n_bytes == 2)
463 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
464 else if (drv_data->n_bytes == 1)
465 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
466 write_TDBR(drv_data, chip->idle_tx_val);
467 } else if (drv_data->tx) {
469 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
470 bfin_spi_dummy_read(drv_data);
471 if (drv_data->n_bytes == 2)
472 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
473 else if (drv_data->n_bytes == 1)
474 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
478 drv_data->tx += n_bytes;
480 drv_data->rx += n_bytes;
485 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
487 struct master_data *drv_data = dev_id;
488 struct slave_data *chip = drv_data->cur_chip;
489 struct spi_message *msg = drv_data->cur_msg;
490 unsigned long timeout;
491 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
492 u16 spistat = read_STAT(drv_data);
494 dev_dbg(&drv_data->pdev->dev,
495 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
498 clear_dma_irqstat(drv_data->dma_channel);
501 * wait for the last transaction shifted out. HRM states:
502 * at this point there may still be data in the SPI DMA FIFO waiting
503 * to be transmitted ... software needs to poll TXS in the SPI_STAT
504 * register until it goes low for 2 successive reads
506 if (drv_data->tx != NULL) {
507 while ((read_STAT(drv_data) & TXS) ||
508 (read_STAT(drv_data) & TXS))
512 dev_dbg(&drv_data->pdev->dev,
513 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
514 dmastat, read_STAT(drv_data));
516 timeout = jiffies + HZ;
517 while (!(read_STAT(drv_data) & SPIF))
518 if (!time_before(jiffies, timeout)) {
519 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
524 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
525 msg->state = ERROR_STATE;
526 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
528 msg->actual_length += drv_data->len_in_bytes;
530 if (drv_data->cs_change)
531 bfin_spi_cs_deactive(drv_data, chip);
533 /* Move to next transfer */
534 msg->state = bfin_spi_next_transfer(drv_data);
537 /* Schedule transfer tasklet */
538 tasklet_schedule(&drv_data->pump_transfers);
540 /* free the irq handler before next transfer */
541 dev_dbg(&drv_data->pdev->dev,
542 "disable dma channel irq%d\n",
543 drv_data->dma_channel);
544 dma_disable_irq(drv_data->dma_channel);
549 static void bfin_spi_pump_transfers(unsigned long data)
551 struct master_data *drv_data = (struct master_data *)data;
552 struct spi_message *message = NULL;
553 struct spi_transfer *transfer = NULL;
554 struct spi_transfer *previous = NULL;
555 struct slave_data *chip = NULL;
557 u16 cr, dma_width, dma_config;
558 u32 tranf_success = 1;
561 /* Get current state information */
562 message = drv_data->cur_msg;
563 transfer = drv_data->cur_transfer;
564 chip = drv_data->cur_chip;
567 * if msg is error or done, report it back using complete() callback
570 /* Handle for abort */
571 if (message->state == ERROR_STATE) {
572 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
573 message->status = -EIO;
574 bfin_spi_giveback(drv_data);
578 /* Handle end of message */
579 if (message->state == DONE_STATE) {
580 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
582 bfin_spi_giveback(drv_data);
586 /* Delay if requested at end of transfer */
587 if (message->state == RUNNING_STATE) {
588 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
589 previous = list_entry(transfer->transfer_list.prev,
590 struct spi_transfer, transfer_list);
591 if (previous->delay_usecs)
592 udelay(previous->delay_usecs);
595 /* Flush any existing transfers that may be sitting in the hardware */
596 if (bfin_spi_flush(drv_data) == 0) {
597 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
598 message->status = -EIO;
599 bfin_spi_giveback(drv_data);
603 if (transfer->len == 0) {
604 /* Move to next transfer of this msg */
605 message->state = bfin_spi_next_transfer(drv_data);
606 /* Schedule next transfer tasklet */
607 tasklet_schedule(&drv_data->pump_transfers);
610 if (transfer->tx_buf != NULL) {
611 drv_data->tx = (void *)transfer->tx_buf;
612 drv_data->tx_end = drv_data->tx + transfer->len;
613 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
614 transfer->tx_buf, drv_data->tx_end);
619 if (transfer->rx_buf != NULL) {
620 full_duplex = transfer->tx_buf != NULL;
621 drv_data->rx = transfer->rx_buf;
622 drv_data->rx_end = drv_data->rx + transfer->len;
623 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
624 transfer->rx_buf, drv_data->rx_end);
629 drv_data->rx_dma = transfer->rx_dma;
630 drv_data->tx_dma = transfer->tx_dma;
631 drv_data->len_in_bytes = transfer->len;
632 drv_data->cs_change = transfer->cs_change;
634 /* Bits per word setup */
635 switch (transfer->bits_per_word) {
637 drv_data->n_bytes = 1;
638 width = CFG_SPI_WORDSIZE8;
639 drv_data->ops = &bfin_transfer_ops_u8;
643 drv_data->n_bytes = 2;
644 width = CFG_SPI_WORDSIZE16;
645 drv_data->ops = &bfin_transfer_ops_u16;
649 /* No change, the same as default setting */
650 transfer->bits_per_word = chip->bits_per_word;
651 drv_data->n_bytes = chip->n_bytes;
653 drv_data->ops = chip->ops;
656 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
658 write_CTRL(drv_data, cr);
660 if (width == CFG_SPI_WORDSIZE16) {
661 drv_data->len = (transfer->len) >> 1;
663 drv_data->len = transfer->len;
665 dev_dbg(&drv_data->pdev->dev,
666 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
667 drv_data->ops, chip->ops, &bfin_transfer_ops_u8);
669 message->state = RUNNING_STATE;
672 /* Speed setup (surely valid because already checked) */
673 if (transfer->speed_hz)
674 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
676 write_BAUD(drv_data, chip->baud);
678 write_STAT(drv_data, BIT_STAT_CLR);
679 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
680 if (drv_data->cs_change)
681 bfin_spi_cs_active(drv_data, chip);
683 dev_dbg(&drv_data->pdev->dev,
684 "now pumping a transfer: width is %d, len is %d\n",
685 width, transfer->len);
688 * Try to map dma buffer and do a dma transfer. If successful use,
689 * different way to r/w according to the enable_dma settings and if
690 * we are not doing a full duplex transfer (since the hardware does
691 * not support full duplex DMA transfers).
693 if (!full_duplex && drv_data->cur_chip->enable_dma
694 && drv_data->len > 6) {
696 unsigned long dma_start_addr, flags;
698 disable_dma(drv_data->dma_channel);
699 clear_dma_irqstat(drv_data->dma_channel);
701 /* config dma channel */
702 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
703 set_dma_x_count(drv_data->dma_channel, drv_data->len);
704 if (width == CFG_SPI_WORDSIZE16) {
705 set_dma_x_modify(drv_data->dma_channel, 2);
706 dma_width = WDSIZE_16;
708 set_dma_x_modify(drv_data->dma_channel, 1);
709 dma_width = WDSIZE_8;
712 /* poll for SPI completion before start */
713 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
716 /* dirty hack for autobuffer DMA mode */
717 if (drv_data->tx_dma == 0xFFFF) {
718 dev_dbg(&drv_data->pdev->dev,
719 "doing autobuffer DMA out.\n");
721 /* no irq in autobuffer mode */
723 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
724 set_dma_config(drv_data->dma_channel, dma_config);
725 set_dma_start_addr(drv_data->dma_channel,
726 (unsigned long)drv_data->tx);
727 enable_dma(drv_data->dma_channel);
729 /* start SPI transfer */
730 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
732 /* just return here, there can only be one transfer
736 bfin_spi_giveback(drv_data);
740 /* In dma mode, rx or tx must be NULL in one transfer */
741 dma_config = (RESTART | dma_width | DI_EN);
742 if (drv_data->rx != NULL) {
743 /* set transfer mode, and enable SPI */
744 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
745 drv_data->rx, drv_data->len_in_bytes);
747 /* invalidate caches, if needed */
748 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
749 invalidate_dcache_range((unsigned long) drv_data->rx,
750 (unsigned long) (drv_data->rx +
751 drv_data->len_in_bytes));
754 dma_start_addr = (unsigned long)drv_data->rx;
755 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
757 } else if (drv_data->tx != NULL) {
758 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
760 /* flush caches, if needed */
761 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
762 flush_dcache_range((unsigned long) drv_data->tx,
763 (unsigned long) (drv_data->tx +
764 drv_data->len_in_bytes));
766 dma_start_addr = (unsigned long)drv_data->tx;
767 cr |= BIT_CTL_TIMOD_DMA_TX;
772 /* oh man, here there be monsters ... and i dont mean the
773 * fluffy cute ones from pixar, i mean the kind that'll eat
774 * your data, kick your dog, and love it all. do *not* try
775 * and change these lines unless you (1) heavily test DMA
776 * with SPI flashes on a loaded system (e.g. ping floods),
777 * (2) know just how broken the DMA engine interaction with
778 * the SPI peripheral is, and (3) have someone else to blame
779 * when you screw it all up anyways.
781 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
782 set_dma_config(drv_data->dma_channel, dma_config);
783 local_irq_save(flags);
785 write_CTRL(drv_data, cr);
786 enable_dma(drv_data->dma_channel);
787 dma_enable_irq(drv_data->dma_channel);
788 local_irq_restore(flags);
793 if (chip->pio_interrupt) {
794 /* use write mode. spi irq should have been disabled */
795 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
796 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
798 /* discard old RX data and clear RXS */
799 bfin_spi_dummy_read(drv_data);
802 if (drv_data->tx == NULL)
803 write_TDBR(drv_data, chip->idle_tx_val);
805 if (transfer->bits_per_word == 8)
806 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
807 else if (transfer->bits_per_word == 16)
808 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
809 drv_data->tx += drv_data->n_bytes;
812 /* once TDBR is empty, interrupt is triggered */
813 enable_irq(drv_data->spi_irq);
818 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
820 /* we always use SPI_WRITE mode. SPI_READ mode
821 seems to have problems with setting up the
822 output value in TDBR prior to the transfer. */
823 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
826 /* full duplex mode */
827 BUG_ON((drv_data->tx_end - drv_data->tx) !=
828 (drv_data->rx_end - drv_data->rx));
829 dev_dbg(&drv_data->pdev->dev,
830 "IO duplex: cr is 0x%x\n", cr);
832 drv_data->ops->duplex(drv_data);
834 if (drv_data->tx != drv_data->tx_end)
836 } else if (drv_data->tx != NULL) {
837 /* write only half duplex */
838 dev_dbg(&drv_data->pdev->dev,
839 "IO write: cr is 0x%x\n", cr);
841 drv_data->ops->write(drv_data);
843 if (drv_data->tx != drv_data->tx_end)
845 } else if (drv_data->rx != NULL) {
846 /* read only half duplex */
847 dev_dbg(&drv_data->pdev->dev,
848 "IO read: cr is 0x%x\n", cr);
850 drv_data->ops->read(drv_data);
851 if (drv_data->rx != drv_data->rx_end)
855 if (!tranf_success) {
856 dev_dbg(&drv_data->pdev->dev,
857 "IO write error!\n");
858 message->state = ERROR_STATE;
860 /* Update total byte transfered */
861 message->actual_length += drv_data->len_in_bytes;
862 /* Move to next transfer of this msg */
863 message->state = bfin_spi_next_transfer(drv_data);
864 if (drv_data->cs_change)
865 bfin_spi_cs_deactive(drv_data, chip);
868 /* Schedule next transfer tasklet */
869 tasklet_schedule(&drv_data->pump_transfers);
872 /* pop a msg from queue and kick off real transfer */
873 static void bfin_spi_pump_messages(struct work_struct *work)
875 struct master_data *drv_data;
878 drv_data = container_of(work, struct master_data, pump_messages);
880 /* Lock queue and check for queue work */
881 spin_lock_irqsave(&drv_data->lock, flags);
882 if (list_empty(&drv_data->queue) || !drv_data->running) {
883 /* pumper kicked off but no work to do */
885 spin_unlock_irqrestore(&drv_data->lock, flags);
889 /* Make sure we are not already running a message */
890 if (drv_data->cur_msg) {
891 spin_unlock_irqrestore(&drv_data->lock, flags);
895 /* Extract head of queue */
896 drv_data->cur_msg = list_entry(drv_data->queue.next,
897 struct spi_message, queue);
899 /* Setup the SSP using the per chip configuration */
900 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
901 bfin_spi_restore_state(drv_data);
903 list_del_init(&drv_data->cur_msg->queue);
905 /* Initial message state */
906 drv_data->cur_msg->state = START_STATE;
907 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
908 struct spi_transfer, transfer_list);
910 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
911 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
912 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
913 drv_data->cur_chip->ctl_reg);
915 dev_dbg(&drv_data->pdev->dev,
916 "the first transfer len is %d\n",
917 drv_data->cur_transfer->len);
919 /* Mark as busy and launch transfers */
920 tasklet_schedule(&drv_data->pump_transfers);
923 spin_unlock_irqrestore(&drv_data->lock, flags);
927 * got a msg to transfer, queue it in drv_data->queue.
928 * And kick off message pumper
930 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
932 struct master_data *drv_data = spi_master_get_devdata(spi->master);
935 spin_lock_irqsave(&drv_data->lock, flags);
937 if (!drv_data->running) {
938 spin_unlock_irqrestore(&drv_data->lock, flags);
942 msg->actual_length = 0;
943 msg->status = -EINPROGRESS;
944 msg->state = START_STATE;
946 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
947 list_add_tail(&msg->queue, &drv_data->queue);
949 if (drv_data->running && !drv_data->busy)
950 queue_work(drv_data->workqueue, &drv_data->pump_messages);
952 spin_unlock_irqrestore(&drv_data->lock, flags);
957 #define MAX_SPI_SSEL 7
959 static u16 ssel[][MAX_SPI_SSEL] = {
960 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
961 P_SPI0_SSEL4, P_SPI0_SSEL5,
962 P_SPI0_SSEL6, P_SPI0_SSEL7},
964 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
965 P_SPI1_SSEL4, P_SPI1_SSEL5,
966 P_SPI1_SSEL6, P_SPI1_SSEL7},
968 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
969 P_SPI2_SSEL4, P_SPI2_SSEL5,
970 P_SPI2_SSEL6, P_SPI2_SSEL7},
973 /* setup for devices (may be called multiple times -- not just first setup) */
974 static int bfin_spi_setup(struct spi_device *spi)
976 struct bfin5xx_spi_chip *chip_info;
977 struct slave_data *chip = NULL;
978 struct master_data *drv_data = spi_master_get_devdata(spi->master);
981 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
984 /* Only alloc (or use chip_info) on first setup */
986 chip = spi_get_ctldata(spi);
988 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
990 dev_err(&spi->dev, "cannot allocate chip data\n");
995 chip->enable_dma = 0;
996 chip_info = spi->controller_data;
999 /* chip_info isn't always needed */
1001 /* Make sure people stop trying to set fields via ctl_reg
1002 * when they should actually be using common SPI framework.
1003 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1004 * Not sure if a user actually needs/uses any of these,
1005 * but let's assume (for now) they do.
1007 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1008 dev_err(&spi->dev, "do not set bits in ctl_reg "
1009 "that the SPI framework manages\n");
1013 chip->enable_dma = chip_info->enable_dma != 0
1014 && drv_data->master_info->enable_dma;
1015 chip->ctl_reg = chip_info->ctl_reg;
1016 chip->bits_per_word = chip_info->bits_per_word;
1017 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1018 chip->cs_gpio = chip_info->cs_gpio;
1019 chip->idle_tx_val = chip_info->idle_tx_val;
1020 chip->pio_interrupt = chip_info->pio_interrupt;
1023 /* translate common spi framework into our register */
1024 if (spi->mode & SPI_CPOL)
1025 chip->ctl_reg |= CPOL;
1026 if (spi->mode & SPI_CPHA)
1027 chip->ctl_reg |= CPHA;
1028 if (spi->mode & SPI_LSB_FIRST)
1029 chip->ctl_reg |= LSBF;
1030 /* we dont support running in slave mode (yet?) */
1031 chip->ctl_reg |= MSTR;
1034 * Notice: for blackfin, the speed_hz is the value of register
1035 * SPI_BAUD, not the real baudrate
1037 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1038 chip->flag = (1 << (spi->chip_select)) << 8;
1039 chip->chip_select_num = spi->chip_select;
1041 switch (chip->bits_per_word) {
1044 chip->width = CFG_SPI_WORDSIZE8;
1045 chip->ops = &bfin_transfer_ops_u8;
1050 chip->width = CFG_SPI_WORDSIZE16;
1051 chip->ops = &bfin_transfer_ops_u16;
1055 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1056 chip->bits_per_word);
1060 if (chip->enable_dma && chip->pio_interrupt) {
1061 dev_err(&spi->dev, "enable_dma is set, "
1062 "do not set pio_interrupt\n");
1066 * if any one SPI chip is registered and wants DMA, request the
1067 * DMA channel for it
1069 if (chip->enable_dma && !drv_data->dma_requested) {
1070 /* register dma irq handler */
1071 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1074 "Unable to request BlackFin SPI DMA channel\n");
1077 drv_data->dma_requested = 1;
1079 ret = set_dma_callback(drv_data->dma_channel,
1080 bfin_spi_dma_irq_handler, drv_data);
1082 dev_err(&spi->dev, "Unable to set dma callback\n");
1085 dma_disable_irq(drv_data->dma_channel);
1088 if (chip->pio_interrupt && !drv_data->irq_requested) {
1089 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1090 IRQF_DISABLED, "BFIN_SPI", drv_data);
1092 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1095 drv_data->irq_requested = 1;
1096 /* we use write mode, spi irq has to be disabled here */
1097 disable_irq(drv_data->spi_irq);
1100 if (chip->chip_select_num == 0) {
1101 ret = gpio_request(chip->cs_gpio, spi->modalias);
1103 dev_err(&spi->dev, "gpio_request() error\n");
1106 gpio_direction_output(chip->cs_gpio, 1);
1109 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1110 spi->modalias, chip->width, chip->enable_dma);
1111 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1112 chip->ctl_reg, chip->flag);
1114 spi_set_ctldata(spi, chip);
1116 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1117 if (chip->chip_select_num > 0 &&
1118 chip->chip_select_num <= spi->master->num_chipselect) {
1119 ret = peripheral_request(ssel[spi->master->bus_num]
1120 [chip->chip_select_num-1], spi->modalias);
1122 dev_err(&spi->dev, "peripheral_request() error\n");
1127 bfin_spi_cs_enable(drv_data, chip);
1128 bfin_spi_cs_deactive(drv_data, chip);
1133 if (chip->chip_select_num == 0)
1134 gpio_free(chip->cs_gpio);
1136 peripheral_free(ssel[spi->master->bus_num]
1137 [chip->chip_select_num - 1]);
1140 if (drv_data->dma_requested)
1141 free_dma(drv_data->dma_channel);
1142 drv_data->dma_requested = 0;
1145 /* prevent free 'chip' twice */
1146 spi_set_ctldata(spi, NULL);
1153 * callback for spi framework.
1154 * clean driver specific data
1156 static void bfin_spi_cleanup(struct spi_device *spi)
1158 struct slave_data *chip = spi_get_ctldata(spi);
1159 struct master_data *drv_data = spi_master_get_devdata(spi->master);
1164 if ((chip->chip_select_num > 0)
1165 && (chip->chip_select_num <= spi->master->num_chipselect)) {
1166 peripheral_free(ssel[spi->master->bus_num]
1167 [chip->chip_select_num-1]);
1168 bfin_spi_cs_disable(drv_data, chip);
1171 if (chip->chip_select_num == 0)
1172 gpio_free(chip->cs_gpio);
1175 /* prevent free 'chip' twice */
1176 spi_set_ctldata(spi, NULL);
1179 static inline int bfin_spi_init_queue(struct master_data *drv_data)
1181 INIT_LIST_HEAD(&drv_data->queue);
1182 spin_lock_init(&drv_data->lock);
1184 drv_data->running = false;
1187 /* init transfer tasklet */
1188 tasklet_init(&drv_data->pump_transfers,
1189 bfin_spi_pump_transfers, (unsigned long)drv_data);
1191 /* init messages workqueue */
1192 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1193 drv_data->workqueue = create_singlethread_workqueue(
1194 dev_name(drv_data->master->dev.parent));
1195 if (drv_data->workqueue == NULL)
1201 static inline int bfin_spi_start_queue(struct master_data *drv_data)
1203 unsigned long flags;
1205 spin_lock_irqsave(&drv_data->lock, flags);
1207 if (drv_data->running || drv_data->busy) {
1208 spin_unlock_irqrestore(&drv_data->lock, flags);
1212 drv_data->running = true;
1213 drv_data->cur_msg = NULL;
1214 drv_data->cur_transfer = NULL;
1215 drv_data->cur_chip = NULL;
1216 spin_unlock_irqrestore(&drv_data->lock, flags);
1218 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1223 static inline int bfin_spi_stop_queue(struct master_data *drv_data)
1225 unsigned long flags;
1226 unsigned limit = 500;
1229 spin_lock_irqsave(&drv_data->lock, flags);
1232 * This is a bit lame, but is optimized for the common execution path.
1233 * A wait_queue on the drv_data->busy could be used, but then the common
1234 * execution path (pump_messages) would be required to call wake_up or
1235 * friends on every SPI message. Do this instead
1237 drv_data->running = false;
1238 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1239 spin_unlock_irqrestore(&drv_data->lock, flags);
1241 spin_lock_irqsave(&drv_data->lock, flags);
1244 if (!list_empty(&drv_data->queue) || drv_data->busy)
1247 spin_unlock_irqrestore(&drv_data->lock, flags);
1252 static inline int bfin_spi_destroy_queue(struct master_data *drv_data)
1256 status = bfin_spi_stop_queue(drv_data);
1260 destroy_workqueue(drv_data->workqueue);
1265 static int __init bfin_spi_probe(struct platform_device *pdev)
1267 struct device *dev = &pdev->dev;
1268 struct bfin5xx_spi_master *platform_info;
1269 struct spi_master *master;
1270 struct master_data *drv_data;
1271 struct resource *res;
1274 platform_info = dev->platform_data;
1276 /* Allocate master with space for drv_data */
1277 master = spi_alloc_master(dev, sizeof(*drv_data));
1279 dev_err(&pdev->dev, "can not alloc spi_master\n");
1283 drv_data = spi_master_get_devdata(master);
1284 drv_data->master = master;
1285 drv_data->master_info = platform_info;
1286 drv_data->pdev = pdev;
1287 drv_data->pin_req = platform_info->pin_req;
1289 /* the spi->mode bits supported by this driver: */
1290 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1292 master->bus_num = pdev->id;
1293 master->num_chipselect = platform_info->num_chipselect;
1294 master->cleanup = bfin_spi_cleanup;
1295 master->setup = bfin_spi_setup;
1296 master->transfer = bfin_spi_transfer;
1298 /* Find and map our resources */
1299 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1301 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1303 goto out_error_get_res;
1306 drv_data->regs_base = ioremap(res->start, resource_size(res));
1307 if (drv_data->regs_base == NULL) {
1308 dev_err(dev, "Cannot map IO\n");
1310 goto out_error_ioremap;
1313 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1315 dev_err(dev, "No DMA channel specified\n");
1317 goto out_error_free_io;
1319 drv_data->dma_channel = res->start;
1321 drv_data->spi_irq = platform_get_irq(pdev, 0);
1322 if (drv_data->spi_irq < 0) {
1323 dev_err(dev, "No spi pio irq specified\n");
1325 goto out_error_free_io;
1328 /* Initial and start queue */
1329 status = bfin_spi_init_queue(drv_data);
1331 dev_err(dev, "problem initializing queue\n");
1332 goto out_error_queue_alloc;
1335 status = bfin_spi_start_queue(drv_data);
1337 dev_err(dev, "problem starting queue\n");
1338 goto out_error_queue_alloc;
1341 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1343 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1344 goto out_error_queue_alloc;
1347 /* Reset SPI registers. If these registers were used by the boot loader,
1348 * the sky may fall on your head if you enable the dma controller.
1350 write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1351 write_FLAG(drv_data, 0xFF00);
1353 /* Register with the SPI framework */
1354 platform_set_drvdata(pdev, drv_data);
1355 status = spi_register_master(master);
1357 dev_err(dev, "problem registering spi master\n");
1358 goto out_error_queue_alloc;
1361 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1362 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1363 drv_data->dma_channel);
1366 out_error_queue_alloc:
1367 bfin_spi_destroy_queue(drv_data);
1369 iounmap((void *) drv_data->regs_base);
1372 spi_master_put(master);
1377 /* stop hardware and remove the driver */
1378 static int __devexit bfin_spi_remove(struct platform_device *pdev)
1380 struct master_data *drv_data = platform_get_drvdata(pdev);
1386 /* Remove the queue */
1387 status = bfin_spi_destroy_queue(drv_data);
1391 /* Disable the SSP at the peripheral and SOC level */
1392 bfin_spi_disable(drv_data);
1395 if (drv_data->master_info->enable_dma) {
1396 if (dma_channel_active(drv_data->dma_channel))
1397 free_dma(drv_data->dma_channel);
1400 if (drv_data->irq_requested) {
1401 free_irq(drv_data->spi_irq, drv_data);
1402 drv_data->irq_requested = 0;
1405 /* Disconnect from the SPI framework */
1406 spi_unregister_master(drv_data->master);
1408 peripheral_free_list(drv_data->pin_req);
1410 /* Prevent double remove */
1411 platform_set_drvdata(pdev, NULL);
1417 static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1419 struct master_data *drv_data = platform_get_drvdata(pdev);
1422 status = bfin_spi_stop_queue(drv_data);
1427 bfin_spi_disable(drv_data);
1432 static int bfin_spi_resume(struct platform_device *pdev)
1434 struct master_data *drv_data = platform_get_drvdata(pdev);
1437 /* Enable the SPI interface */
1438 bfin_spi_enable(drv_data);
1440 /* Start the queue running */
1441 status = bfin_spi_start_queue(drv_data);
1443 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1450 #define bfin_spi_suspend NULL
1451 #define bfin_spi_resume NULL
1452 #endif /* CONFIG_PM */
1454 MODULE_ALIAS("platform:bfin-spi");
1455 static struct platform_driver bfin_spi_driver = {
1458 .owner = THIS_MODULE,
1460 .suspend = bfin_spi_suspend,
1461 .resume = bfin_spi_resume,
1462 .remove = __devexit_p(bfin_spi_remove),
1465 static int __init bfin_spi_init(void)
1467 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1469 module_init(bfin_spi_init);
1471 static void __exit bfin_spi_exit(void)
1473 platform_driver_unregister(&bfin_spi_driver);
1475 module_exit(bfin_spi_exit);