2 * Blackfin On-Chip SPI Driver
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
24 #include <linux/workqueue.h>
27 #include <asm/portmux.h>
28 #include <asm/bfin5xx_spi.h>
29 #include <asm/cacheflush.h>
31 #define DRV_NAME "bfin-spi"
32 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
33 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
34 #define DRV_VERSION "1.0"
36 MODULE_AUTHOR(DRV_AUTHOR);
37 MODULE_DESCRIPTION(DRV_DESC);
38 MODULE_LICENSE("GPL");
40 #define START_STATE ((void *)0)
41 #define RUNNING_STATE ((void *)1)
42 #define DONE_STATE ((void *)2)
43 #define ERROR_STATE ((void *)-1)
44 #define QUEUE_RUNNING 0
45 #define QUEUE_STOPPED 1
48 /* Driver model hookup */
49 struct platform_device *pdev;
51 /* SPI framework hookup */
52 struct spi_master *master;
54 /* Regs base of SPI controller */
55 void __iomem *regs_base;
57 /* Pin request list */
61 struct bfin5xx_spi_master *master_info;
63 /* Driver message queue */
64 struct workqueue_struct *workqueue;
65 struct work_struct pump_messages;
67 struct list_head queue;
71 /* Message Transfer pump */
72 struct tasklet_struct pump_transfers;
74 /* Current message transfer state info */
75 struct spi_message *cur_msg;
76 struct spi_transfer *cur_transfer;
77 struct chip_data *cur_chip;
99 void (*write) (struct driver_data *);
100 void (*read) (struct driver_data *);
101 void (*duplex) (struct driver_data *);
111 u8 width; /* 0 or 1 */
113 u8 bits_per_word; /* 8 or 16 */
114 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
117 u8 pio_interrupt; /* use spi data irq */
118 void (*write) (struct driver_data *);
119 void (*read) (struct driver_data *);
120 void (*duplex) (struct driver_data *);
123 #define DEFINE_SPI_REG(reg, off) \
124 static inline u16 read_##reg(struct driver_data *drv_data) \
125 { return bfin_read16(drv_data->regs_base + off); } \
126 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
127 { bfin_write16(drv_data->regs_base + off, v); }
129 DEFINE_SPI_REG(CTRL, 0x00)
130 DEFINE_SPI_REG(FLAG, 0x04)
131 DEFINE_SPI_REG(STAT, 0x08)
132 DEFINE_SPI_REG(TDBR, 0x0C)
133 DEFINE_SPI_REG(RDBR, 0x10)
134 DEFINE_SPI_REG(BAUD, 0x14)
135 DEFINE_SPI_REG(SHAW, 0x18)
137 static void bfin_spi_enable(struct driver_data *drv_data)
141 cr = read_CTRL(drv_data);
142 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
145 static void bfin_spi_disable(struct driver_data *drv_data)
149 cr = read_CTRL(drv_data);
150 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
153 /* Caculate the SPI_BAUD register value based on input HZ */
154 static u16 hz_to_spi_baud(u32 speed_hz)
156 u_long sclk = get_sclk();
157 u16 spi_baud = (sclk / (2 * speed_hz));
159 if ((sclk % (2 * speed_hz)) > 0)
162 if (spi_baud < MIN_SPI_BAUD_VAL)
163 spi_baud = MIN_SPI_BAUD_VAL;
168 static int bfin_spi_flush(struct driver_data *drv_data)
170 unsigned long limit = loops_per_jiffy << 1;
172 /* wait for stop and clear stat */
173 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit)
176 write_STAT(drv_data, BIT_STAT_CLR);
181 /* Chip select operation functions for cs_change flag */
182 static void bfin_spi_cs_active(struct driver_data *drv_data, struct chip_data *chip)
184 if (likely(chip->chip_select_num)) {
185 u16 flag = read_FLAG(drv_data);
189 write_FLAG(drv_data, flag);
191 gpio_set_value(chip->cs_gpio, 0);
195 static void bfin_spi_cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
197 if (likely(chip->chip_select_num)) {
198 u16 flag = read_FLAG(drv_data);
202 write_FLAG(drv_data, flag);
204 gpio_set_value(chip->cs_gpio, 1);
207 /* Move delay here for consistency */
208 if (chip->cs_chg_udelay)
209 udelay(chip->cs_chg_udelay);
212 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
213 static inline void bfin_spi_cs_enable(struct driver_data *drv_data, struct chip_data *chip)
215 u16 flag = read_FLAG(drv_data);
217 flag |= (chip->flag >> 8);
219 write_FLAG(drv_data, flag);
222 static inline void bfin_spi_cs_disable(struct driver_data *drv_data, struct chip_data *chip)
224 u16 flag = read_FLAG(drv_data);
226 flag &= ~(chip->flag >> 8);
228 write_FLAG(drv_data, flag);
231 /* stop controller and re-config current chip*/
232 static void bfin_spi_restore_state(struct driver_data *drv_data)
234 struct chip_data *chip = drv_data->cur_chip;
236 /* Clear status and disable clock */
237 write_STAT(drv_data, BIT_STAT_CLR);
238 bfin_spi_disable(drv_data);
239 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
241 /* Load the registers */
242 write_CTRL(drv_data, chip->ctl_reg);
243 write_BAUD(drv_data, chip->baud);
245 bfin_spi_enable(drv_data);
246 bfin_spi_cs_active(drv_data, chip);
249 /* used to kick off transfer in rx mode and read unwanted RX data */
250 static inline void bfin_spi_dummy_read(struct driver_data *drv_data)
252 (void) read_RDBR(drv_data);
255 static void bfin_spi_u8_writer(struct driver_data *drv_data)
257 /* clear RXS (we check for RXS inside the loop) */
258 bfin_spi_dummy_read(drv_data);
260 while (drv_data->tx < drv_data->tx_end) {
261 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
262 /* wait until transfer finished.
263 checking SPIF or TXS may not guarantee transfer completion */
264 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
266 /* discard RX data and clear RXS */
267 bfin_spi_dummy_read(drv_data);
271 static void bfin_spi_u8_reader(struct driver_data *drv_data)
273 u16 tx_val = drv_data->cur_chip->idle_tx_val;
275 /* discard old RX data and clear RXS */
276 bfin_spi_dummy_read(drv_data);
278 while (drv_data->rx < drv_data->rx_end) {
279 write_TDBR(drv_data, tx_val);
280 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
282 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
286 static void bfin_spi_u8_duplex(struct driver_data *drv_data)
288 /* discard old RX data and clear RXS */
289 bfin_spi_dummy_read(drv_data);
291 while (drv_data->rx < drv_data->rx_end) {
292 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
293 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
295 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
299 static void bfin_spi_u16_writer(struct driver_data *drv_data)
301 /* clear RXS (we check for RXS inside the loop) */
302 bfin_spi_dummy_read(drv_data);
304 while (drv_data->tx < drv_data->tx_end) {
305 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
307 /* wait until transfer finished.
308 checking SPIF or TXS may not guarantee transfer completion */
309 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
311 /* discard RX data and clear RXS */
312 bfin_spi_dummy_read(drv_data);
316 static void bfin_spi_u16_reader(struct driver_data *drv_data)
318 u16 tx_val = drv_data->cur_chip->idle_tx_val;
320 /* discard old RX data and clear RXS */
321 bfin_spi_dummy_read(drv_data);
323 while (drv_data->rx < drv_data->rx_end) {
324 write_TDBR(drv_data, tx_val);
325 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
327 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
332 static void bfin_spi_u16_duplex(struct driver_data *drv_data)
334 /* discard old RX data and clear RXS */
335 bfin_spi_dummy_read(drv_data);
337 while (drv_data->rx < drv_data->rx_end) {
338 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
340 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
342 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
347 /* test if ther is more transfer to be done */
348 static void *bfin_spi_next_transfer(struct driver_data *drv_data)
350 struct spi_message *msg = drv_data->cur_msg;
351 struct spi_transfer *trans = drv_data->cur_transfer;
353 /* Move to next transfer */
354 if (trans->transfer_list.next != &msg->transfers) {
355 drv_data->cur_transfer =
356 list_entry(trans->transfer_list.next,
357 struct spi_transfer, transfer_list);
358 return RUNNING_STATE;
364 * caller already set message->status;
365 * dma and pio irqs are blocked give finished message back
367 static void bfin_spi_giveback(struct driver_data *drv_data)
369 struct chip_data *chip = drv_data->cur_chip;
370 struct spi_transfer *last_transfer;
372 struct spi_message *msg;
374 spin_lock_irqsave(&drv_data->lock, flags);
375 msg = drv_data->cur_msg;
376 drv_data->cur_msg = NULL;
377 drv_data->cur_transfer = NULL;
378 drv_data->cur_chip = NULL;
379 queue_work(drv_data->workqueue, &drv_data->pump_messages);
380 spin_unlock_irqrestore(&drv_data->lock, flags);
382 last_transfer = list_entry(msg->transfers.prev,
383 struct spi_transfer, transfer_list);
387 if (!drv_data->cs_change)
388 bfin_spi_cs_deactive(drv_data, chip);
390 /* Not stop spi in autobuffer mode */
391 if (drv_data->tx_dma != 0xFFFF)
392 bfin_spi_disable(drv_data);
395 msg->complete(msg->context);
398 /* spi data irq handler */
399 static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
401 struct driver_data *drv_data = dev_id;
402 struct chip_data *chip = drv_data->cur_chip;
403 struct spi_message *msg = drv_data->cur_msg;
404 int n_bytes = drv_data->n_bytes;
406 /* wait until transfer finished. */
407 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
410 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
411 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
414 dev_dbg(&drv_data->pdev->dev, "last read\n");
416 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
417 else if (n_bytes == 1)
418 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
419 drv_data->rx += n_bytes;
422 msg->actual_length += drv_data->len_in_bytes;
423 if (drv_data->cs_change)
424 bfin_spi_cs_deactive(drv_data, chip);
425 /* Move to next transfer */
426 msg->state = bfin_spi_next_transfer(drv_data);
428 disable_irq(drv_data->spi_irq);
430 /* Schedule transfer tasklet */
431 tasklet_schedule(&drv_data->pump_transfers);
435 if (drv_data->rx && drv_data->tx) {
437 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
438 if (drv_data->n_bytes == 2) {
439 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
440 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
441 } else if (drv_data->n_bytes == 1) {
442 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
443 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
445 } else if (drv_data->rx) {
447 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
448 if (drv_data->n_bytes == 2)
449 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
450 else if (drv_data->n_bytes == 1)
451 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
452 write_TDBR(drv_data, chip->idle_tx_val);
453 } else if (drv_data->tx) {
455 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
456 bfin_spi_dummy_read(drv_data);
457 if (drv_data->n_bytes == 2)
458 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
459 else if (drv_data->n_bytes == 1)
460 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
464 drv_data->tx += n_bytes;
466 drv_data->rx += n_bytes;
471 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
473 struct driver_data *drv_data = dev_id;
474 struct chip_data *chip = drv_data->cur_chip;
475 struct spi_message *msg = drv_data->cur_msg;
476 unsigned long timeout;
477 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
478 u16 spistat = read_STAT(drv_data);
480 dev_dbg(&drv_data->pdev->dev,
481 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
484 clear_dma_irqstat(drv_data->dma_channel);
487 * wait for the last transaction shifted out. HRM states:
488 * at this point there may still be data in the SPI DMA FIFO waiting
489 * to be transmitted ... software needs to poll TXS in the SPI_STAT
490 * register until it goes low for 2 successive reads
492 if (drv_data->tx != NULL) {
493 while ((read_STAT(drv_data) & TXS) ||
494 (read_STAT(drv_data) & TXS))
498 dev_dbg(&drv_data->pdev->dev,
499 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
500 dmastat, read_STAT(drv_data));
502 timeout = jiffies + HZ;
503 while (!(read_STAT(drv_data) & SPIF))
504 if (!time_before(jiffies, timeout)) {
505 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
510 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
511 msg->state = ERROR_STATE;
512 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
514 msg->actual_length += drv_data->len_in_bytes;
516 if (drv_data->cs_change)
517 bfin_spi_cs_deactive(drv_data, chip);
519 /* Move to next transfer */
520 msg->state = bfin_spi_next_transfer(drv_data);
523 /* Schedule transfer tasklet */
524 tasklet_schedule(&drv_data->pump_transfers);
526 /* free the irq handler before next transfer */
527 dev_dbg(&drv_data->pdev->dev,
528 "disable dma channel irq%d\n",
529 drv_data->dma_channel);
530 dma_disable_irq(drv_data->dma_channel);
535 static void bfin_spi_pump_transfers(unsigned long data)
537 struct driver_data *drv_data = (struct driver_data *)data;
538 struct spi_message *message = NULL;
539 struct spi_transfer *transfer = NULL;
540 struct spi_transfer *previous = NULL;
541 struct chip_data *chip = NULL;
543 u16 cr, dma_width, dma_config;
544 u32 tranf_success = 1;
547 /* Get current state information */
548 message = drv_data->cur_msg;
549 transfer = drv_data->cur_transfer;
550 chip = drv_data->cur_chip;
553 * if msg is error or done, report it back using complete() callback
556 /* Handle for abort */
557 if (message->state == ERROR_STATE) {
558 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
559 message->status = -EIO;
560 bfin_spi_giveback(drv_data);
564 /* Handle end of message */
565 if (message->state == DONE_STATE) {
566 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
568 bfin_spi_giveback(drv_data);
572 /* Delay if requested at end of transfer */
573 if (message->state == RUNNING_STATE) {
574 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
575 previous = list_entry(transfer->transfer_list.prev,
576 struct spi_transfer, transfer_list);
577 if (previous->delay_usecs)
578 udelay(previous->delay_usecs);
581 /* Flush any existing transfers that may be sitting in the hardware */
582 if (bfin_spi_flush(drv_data) == 0) {
583 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
584 message->status = -EIO;
585 bfin_spi_giveback(drv_data);
589 if (transfer->len == 0) {
590 /* Move to next transfer of this msg */
591 message->state = bfin_spi_next_transfer(drv_data);
592 /* Schedule next transfer tasklet */
593 tasklet_schedule(&drv_data->pump_transfers);
596 if (transfer->tx_buf != NULL) {
597 drv_data->tx = (void *)transfer->tx_buf;
598 drv_data->tx_end = drv_data->tx + transfer->len;
599 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
600 transfer->tx_buf, drv_data->tx_end);
605 if (transfer->rx_buf != NULL) {
606 full_duplex = transfer->tx_buf != NULL;
607 drv_data->rx = transfer->rx_buf;
608 drv_data->rx_end = drv_data->rx + transfer->len;
609 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
610 transfer->rx_buf, drv_data->rx_end);
615 drv_data->rx_dma = transfer->rx_dma;
616 drv_data->tx_dma = transfer->tx_dma;
617 drv_data->len_in_bytes = transfer->len;
618 drv_data->cs_change = transfer->cs_change;
620 /* Bits per word setup */
621 switch (transfer->bits_per_word) {
623 drv_data->n_bytes = 1;
624 width = CFG_SPI_WORDSIZE8;
625 drv_data->read = bfin_spi_u8_reader;
626 drv_data->write = bfin_spi_u8_writer;
627 drv_data->duplex = bfin_spi_u8_duplex;
631 drv_data->n_bytes = 2;
632 width = CFG_SPI_WORDSIZE16;
633 drv_data->read = bfin_spi_u16_reader;
634 drv_data->write = bfin_spi_u16_writer;
635 drv_data->duplex = bfin_spi_u16_duplex;
639 /* No change, the same as default setting */
640 transfer->bits_per_word = chip->bits_per_word;
641 drv_data->n_bytes = chip->n_bytes;
643 drv_data->write = chip->write;
644 drv_data->read = chip->read;
645 drv_data->duplex = chip->duplex;
648 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
650 write_CTRL(drv_data, cr);
652 if (width == CFG_SPI_WORDSIZE16) {
653 drv_data->len = (transfer->len) >> 1;
655 drv_data->len = transfer->len;
657 dev_dbg(&drv_data->pdev->dev,
658 "transfer: drv_data->write is %p, chip->write is %p\n",
659 drv_data->write, chip->write);
661 message->state = RUNNING_STATE;
664 /* Speed setup (surely valid because already checked) */
665 if (transfer->speed_hz)
666 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
668 write_BAUD(drv_data, chip->baud);
670 write_STAT(drv_data, BIT_STAT_CLR);
671 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
672 if (drv_data->cs_change)
673 bfin_spi_cs_active(drv_data, chip);
675 dev_dbg(&drv_data->pdev->dev,
676 "now pumping a transfer: width is %d, len is %d\n",
677 width, transfer->len);
680 * Try to map dma buffer and do a dma transfer. If successful use,
681 * different way to r/w according to the enable_dma settings and if
682 * we are not doing a full duplex transfer (since the hardware does
683 * not support full duplex DMA transfers).
685 if (!full_duplex && drv_data->cur_chip->enable_dma
686 && drv_data->len > 6) {
688 unsigned long dma_start_addr, flags;
690 disable_dma(drv_data->dma_channel);
691 clear_dma_irqstat(drv_data->dma_channel);
693 /* config dma channel */
694 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
695 set_dma_x_count(drv_data->dma_channel, drv_data->len);
696 if (width == CFG_SPI_WORDSIZE16) {
697 set_dma_x_modify(drv_data->dma_channel, 2);
698 dma_width = WDSIZE_16;
700 set_dma_x_modify(drv_data->dma_channel, 1);
701 dma_width = WDSIZE_8;
704 /* poll for SPI completion before start */
705 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
708 /* dirty hack for autobuffer DMA mode */
709 if (drv_data->tx_dma == 0xFFFF) {
710 dev_dbg(&drv_data->pdev->dev,
711 "doing autobuffer DMA out.\n");
713 /* no irq in autobuffer mode */
715 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
716 set_dma_config(drv_data->dma_channel, dma_config);
717 set_dma_start_addr(drv_data->dma_channel,
718 (unsigned long)drv_data->tx);
719 enable_dma(drv_data->dma_channel);
721 /* start SPI transfer */
722 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
724 /* just return here, there can only be one transfer
728 bfin_spi_giveback(drv_data);
732 /* In dma mode, rx or tx must be NULL in one transfer */
733 dma_config = (RESTART | dma_width | DI_EN);
734 if (drv_data->rx != NULL) {
735 /* set transfer mode, and enable SPI */
736 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
737 drv_data->rx, drv_data->len_in_bytes);
739 /* invalidate caches, if needed */
740 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
741 invalidate_dcache_range((unsigned long) drv_data->rx,
742 (unsigned long) (drv_data->rx +
743 drv_data->len_in_bytes));
746 dma_start_addr = (unsigned long)drv_data->rx;
747 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
749 } else if (drv_data->tx != NULL) {
750 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
752 /* flush caches, if needed */
753 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
754 flush_dcache_range((unsigned long) drv_data->tx,
755 (unsigned long) (drv_data->tx +
756 drv_data->len_in_bytes));
758 dma_start_addr = (unsigned long)drv_data->tx;
759 cr |= BIT_CTL_TIMOD_DMA_TX;
764 /* oh man, here there be monsters ... and i dont mean the
765 * fluffy cute ones from pixar, i mean the kind that'll eat
766 * your data, kick your dog, and love it all. do *not* try
767 * and change these lines unless you (1) heavily test DMA
768 * with SPI flashes on a loaded system (e.g. ping floods),
769 * (2) know just how broken the DMA engine interaction with
770 * the SPI peripheral is, and (3) have someone else to blame
771 * when you screw it all up anyways.
773 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
774 set_dma_config(drv_data->dma_channel, dma_config);
775 local_irq_save(flags);
777 write_CTRL(drv_data, cr);
778 enable_dma(drv_data->dma_channel);
779 dma_enable_irq(drv_data->dma_channel);
780 local_irq_restore(flags);
785 if (chip->pio_interrupt) {
786 /* use write mode. spi irq should have been disabled */
787 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
788 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
790 /* discard old RX data and clear RXS */
791 bfin_spi_dummy_read(drv_data);
794 if (drv_data->tx == NULL)
795 write_TDBR(drv_data, chip->idle_tx_val);
797 if (transfer->bits_per_word == 8)
798 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
799 else if (transfer->bits_per_word == 16)
800 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
801 drv_data->tx += drv_data->n_bytes;
804 /* once TDBR is empty, interrupt is triggered */
805 enable_irq(drv_data->spi_irq);
810 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
812 /* we always use SPI_WRITE mode. SPI_READ mode
813 seems to have problems with setting up the
814 output value in TDBR prior to the transfer. */
815 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
818 /* full duplex mode */
819 BUG_ON((drv_data->tx_end - drv_data->tx) !=
820 (drv_data->rx_end - drv_data->rx));
821 dev_dbg(&drv_data->pdev->dev,
822 "IO duplex: cr is 0x%x\n", cr);
824 drv_data->duplex(drv_data);
826 if (drv_data->tx != drv_data->tx_end)
828 } else if (drv_data->tx != NULL) {
829 /* write only half duplex */
830 dev_dbg(&drv_data->pdev->dev,
831 "IO write: cr is 0x%x\n", cr);
833 drv_data->write(drv_data);
835 if (drv_data->tx != drv_data->tx_end)
837 } else if (drv_data->rx != NULL) {
838 /* read only half duplex */
839 dev_dbg(&drv_data->pdev->dev,
840 "IO read: cr is 0x%x\n", cr);
842 drv_data->read(drv_data);
843 if (drv_data->rx != drv_data->rx_end)
847 if (!tranf_success) {
848 dev_dbg(&drv_data->pdev->dev,
849 "IO write error!\n");
850 message->state = ERROR_STATE;
852 /* Update total byte transfered */
853 message->actual_length += drv_data->len_in_bytes;
854 /* Move to next transfer of this msg */
855 message->state = bfin_spi_next_transfer(drv_data);
856 if (drv_data->cs_change)
857 bfin_spi_cs_deactive(drv_data, chip);
860 /* Schedule next transfer tasklet */
861 tasklet_schedule(&drv_data->pump_transfers);
864 /* pop a msg from queue and kick off real transfer */
865 static void bfin_spi_pump_messages(struct work_struct *work)
867 struct driver_data *drv_data;
870 drv_data = container_of(work, struct driver_data, pump_messages);
872 /* Lock queue and check for queue work */
873 spin_lock_irqsave(&drv_data->lock, flags);
874 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
875 /* pumper kicked off but no work to do */
877 spin_unlock_irqrestore(&drv_data->lock, flags);
881 /* Make sure we are not already running a message */
882 if (drv_data->cur_msg) {
883 spin_unlock_irqrestore(&drv_data->lock, flags);
887 /* Extract head of queue */
888 drv_data->cur_msg = list_entry(drv_data->queue.next,
889 struct spi_message, queue);
891 /* Setup the SSP using the per chip configuration */
892 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
893 bfin_spi_restore_state(drv_data);
895 list_del_init(&drv_data->cur_msg->queue);
897 /* Initial message state */
898 drv_data->cur_msg->state = START_STATE;
899 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
900 struct spi_transfer, transfer_list);
902 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
903 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
904 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
905 drv_data->cur_chip->ctl_reg);
907 dev_dbg(&drv_data->pdev->dev,
908 "the first transfer len is %d\n",
909 drv_data->cur_transfer->len);
911 /* Mark as busy and launch transfers */
912 tasklet_schedule(&drv_data->pump_transfers);
915 spin_unlock_irqrestore(&drv_data->lock, flags);
919 * got a msg to transfer, queue it in drv_data->queue.
920 * And kick off message pumper
922 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
924 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
927 spin_lock_irqsave(&drv_data->lock, flags);
929 if (drv_data->run == QUEUE_STOPPED) {
930 spin_unlock_irqrestore(&drv_data->lock, flags);
934 msg->actual_length = 0;
935 msg->status = -EINPROGRESS;
936 msg->state = START_STATE;
938 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
939 list_add_tail(&msg->queue, &drv_data->queue);
941 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
942 queue_work(drv_data->workqueue, &drv_data->pump_messages);
944 spin_unlock_irqrestore(&drv_data->lock, flags);
949 #define MAX_SPI_SSEL 7
951 static u16 ssel[][MAX_SPI_SSEL] = {
952 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
953 P_SPI0_SSEL4, P_SPI0_SSEL5,
954 P_SPI0_SSEL6, P_SPI0_SSEL7},
956 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
957 P_SPI1_SSEL4, P_SPI1_SSEL5,
958 P_SPI1_SSEL6, P_SPI1_SSEL7},
960 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
961 P_SPI2_SSEL4, P_SPI2_SSEL5,
962 P_SPI2_SSEL6, P_SPI2_SSEL7},
965 /* setup for devices (may be called multiple times -- not just first setup) */
966 static int bfin_spi_setup(struct spi_device *spi)
968 struct bfin5xx_spi_chip *chip_info;
969 struct chip_data *chip = NULL;
970 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
973 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
976 /* Only alloc (or use chip_info) on first setup */
978 chip = spi_get_ctldata(spi);
980 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
982 dev_err(&spi->dev, "cannot allocate chip data\n");
987 chip->enable_dma = 0;
988 chip_info = spi->controller_data;
991 /* chip_info isn't always needed */
993 /* Make sure people stop trying to set fields via ctl_reg
994 * when they should actually be using common SPI framework.
995 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
996 * Not sure if a user actually needs/uses any of these,
997 * but let's assume (for now) they do.
999 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1000 dev_err(&spi->dev, "do not set bits in ctl_reg "
1001 "that the SPI framework manages\n");
1005 chip->enable_dma = chip_info->enable_dma != 0
1006 && drv_data->master_info->enable_dma;
1007 chip->ctl_reg = chip_info->ctl_reg;
1008 chip->bits_per_word = chip_info->bits_per_word;
1009 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1010 chip->cs_gpio = chip_info->cs_gpio;
1011 chip->idle_tx_val = chip_info->idle_tx_val;
1012 chip->pio_interrupt = chip_info->pio_interrupt;
1015 /* translate common spi framework into our register */
1016 if (spi->mode & SPI_CPOL)
1017 chip->ctl_reg |= CPOL;
1018 if (spi->mode & SPI_CPHA)
1019 chip->ctl_reg |= CPHA;
1020 if (spi->mode & SPI_LSB_FIRST)
1021 chip->ctl_reg |= LSBF;
1022 /* we dont support running in slave mode (yet?) */
1023 chip->ctl_reg |= MSTR;
1026 * Notice: for blackfin, the speed_hz is the value of register
1027 * SPI_BAUD, not the real baudrate
1029 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1030 chip->flag = (1 << (spi->chip_select)) << 8;
1031 chip->chip_select_num = spi->chip_select;
1033 switch (chip->bits_per_word) {
1036 chip->width = CFG_SPI_WORDSIZE8;
1037 chip->read = bfin_spi_u8_reader;
1038 chip->write = bfin_spi_u8_writer;
1039 chip->duplex = bfin_spi_u8_duplex;
1044 chip->width = CFG_SPI_WORDSIZE16;
1045 chip->read = bfin_spi_u16_reader;
1046 chip->write = bfin_spi_u16_writer;
1047 chip->duplex = bfin_spi_u16_duplex;
1051 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1052 chip->bits_per_word);
1056 if (chip->enable_dma && chip->pio_interrupt) {
1057 dev_err(&spi->dev, "enable_dma is set, "
1058 "do not set pio_interrupt\n");
1062 * if any one SPI chip is registered and wants DMA, request the
1063 * DMA channel for it
1065 if (chip->enable_dma && !drv_data->dma_requested) {
1066 /* register dma irq handler */
1067 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1070 "Unable to request BlackFin SPI DMA channel\n");
1073 drv_data->dma_requested = 1;
1075 ret = set_dma_callback(drv_data->dma_channel,
1076 bfin_spi_dma_irq_handler, drv_data);
1078 dev_err(&spi->dev, "Unable to set dma callback\n");
1081 dma_disable_irq(drv_data->dma_channel);
1084 if (chip->pio_interrupt && !drv_data->irq_requested) {
1085 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1086 IRQF_DISABLED, "BFIN_SPI", drv_data);
1088 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1091 drv_data->irq_requested = 1;
1092 /* we use write mode, spi irq has to be disabled here */
1093 disable_irq(drv_data->spi_irq);
1096 if (chip->chip_select_num == 0) {
1097 ret = gpio_request(chip->cs_gpio, spi->modalias);
1099 dev_err(&spi->dev, "gpio_request() error\n");
1102 gpio_direction_output(chip->cs_gpio, 1);
1105 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1106 spi->modalias, chip->width, chip->enable_dma);
1107 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1108 chip->ctl_reg, chip->flag);
1110 spi_set_ctldata(spi, chip);
1112 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1113 if (chip->chip_select_num > 0 &&
1114 chip->chip_select_num <= spi->master->num_chipselect) {
1115 ret = peripheral_request(ssel[spi->master->bus_num]
1116 [chip->chip_select_num-1], spi->modalias);
1118 dev_err(&spi->dev, "peripheral_request() error\n");
1123 bfin_spi_cs_enable(drv_data, chip);
1124 bfin_spi_cs_deactive(drv_data, chip);
1129 if (chip->chip_select_num == 0)
1130 gpio_free(chip->cs_gpio);
1132 peripheral_free(ssel[spi->master->bus_num]
1133 [chip->chip_select_num - 1]);
1136 if (drv_data->dma_requested)
1137 free_dma(drv_data->dma_channel);
1138 drv_data->dma_requested = 0;
1141 /* prevent free 'chip' twice */
1142 spi_set_ctldata(spi, NULL);
1149 * callback for spi framework.
1150 * clean driver specific data
1152 static void bfin_spi_cleanup(struct spi_device *spi)
1154 struct chip_data *chip = spi_get_ctldata(spi);
1155 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1160 if ((chip->chip_select_num > 0)
1161 && (chip->chip_select_num <= spi->master->num_chipselect)) {
1162 peripheral_free(ssel[spi->master->bus_num]
1163 [chip->chip_select_num-1]);
1164 bfin_spi_cs_disable(drv_data, chip);
1167 if (chip->chip_select_num == 0)
1168 gpio_free(chip->cs_gpio);
1171 /* prevent free 'chip' twice */
1172 spi_set_ctldata(spi, NULL);
1175 static inline int bfin_spi_init_queue(struct driver_data *drv_data)
1177 INIT_LIST_HEAD(&drv_data->queue);
1178 spin_lock_init(&drv_data->lock);
1180 drv_data->run = QUEUE_STOPPED;
1183 /* init transfer tasklet */
1184 tasklet_init(&drv_data->pump_transfers,
1185 bfin_spi_pump_transfers, (unsigned long)drv_data);
1187 /* init messages workqueue */
1188 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1189 drv_data->workqueue = create_singlethread_workqueue(
1190 dev_name(drv_data->master->dev.parent));
1191 if (drv_data->workqueue == NULL)
1197 static inline int bfin_spi_start_queue(struct driver_data *drv_data)
1199 unsigned long flags;
1201 spin_lock_irqsave(&drv_data->lock, flags);
1203 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1204 spin_unlock_irqrestore(&drv_data->lock, flags);
1208 drv_data->run = QUEUE_RUNNING;
1209 drv_data->cur_msg = NULL;
1210 drv_data->cur_transfer = NULL;
1211 drv_data->cur_chip = NULL;
1212 spin_unlock_irqrestore(&drv_data->lock, flags);
1214 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1219 static inline int bfin_spi_stop_queue(struct driver_data *drv_data)
1221 unsigned long flags;
1222 unsigned limit = 500;
1225 spin_lock_irqsave(&drv_data->lock, flags);
1228 * This is a bit lame, but is optimized for the common execution path.
1229 * A wait_queue on the drv_data->busy could be used, but then the common
1230 * execution path (pump_messages) would be required to call wake_up or
1231 * friends on every SPI message. Do this instead
1233 drv_data->run = QUEUE_STOPPED;
1234 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1235 spin_unlock_irqrestore(&drv_data->lock, flags);
1237 spin_lock_irqsave(&drv_data->lock, flags);
1240 if (!list_empty(&drv_data->queue) || drv_data->busy)
1243 spin_unlock_irqrestore(&drv_data->lock, flags);
1248 static inline int bfin_spi_destroy_queue(struct driver_data *drv_data)
1252 status = bfin_spi_stop_queue(drv_data);
1256 destroy_workqueue(drv_data->workqueue);
1261 static int __init bfin_spi_probe(struct platform_device *pdev)
1263 struct device *dev = &pdev->dev;
1264 struct bfin5xx_spi_master *platform_info;
1265 struct spi_master *master;
1266 struct driver_data *drv_data = 0;
1267 struct resource *res;
1270 platform_info = dev->platform_data;
1272 /* Allocate master with space for drv_data */
1273 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1275 dev_err(&pdev->dev, "can not alloc spi_master\n");
1279 drv_data = spi_master_get_devdata(master);
1280 drv_data->master = master;
1281 drv_data->master_info = platform_info;
1282 drv_data->pdev = pdev;
1283 drv_data->pin_req = platform_info->pin_req;
1285 /* the spi->mode bits supported by this driver: */
1286 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1288 master->bus_num = pdev->id;
1289 master->num_chipselect = platform_info->num_chipselect;
1290 master->cleanup = bfin_spi_cleanup;
1291 master->setup = bfin_spi_setup;
1292 master->transfer = bfin_spi_transfer;
1294 /* Find and map our resources */
1295 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1297 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1299 goto out_error_get_res;
1302 drv_data->regs_base = ioremap(res->start, resource_size(res));
1303 if (drv_data->regs_base == NULL) {
1304 dev_err(dev, "Cannot map IO\n");
1306 goto out_error_ioremap;
1309 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1311 dev_err(dev, "No DMA channel specified\n");
1313 goto out_error_free_io;
1315 drv_data->dma_channel = res->start;
1317 drv_data->spi_irq = platform_get_irq(pdev, 0);
1318 if (drv_data->spi_irq < 0) {
1319 dev_err(dev, "No spi pio irq specified\n");
1321 goto out_error_free_io;
1324 /* Initial and start queue */
1325 status = bfin_spi_init_queue(drv_data);
1327 dev_err(dev, "problem initializing queue\n");
1328 goto out_error_queue_alloc;
1331 status = bfin_spi_start_queue(drv_data);
1333 dev_err(dev, "problem starting queue\n");
1334 goto out_error_queue_alloc;
1337 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1339 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1340 goto out_error_queue_alloc;
1343 /* Reset SPI registers. If these registers were used by the boot loader,
1344 * the sky may fall on your head if you enable the dma controller.
1346 write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1347 write_FLAG(drv_data, 0xFF00);
1349 /* Register with the SPI framework */
1350 platform_set_drvdata(pdev, drv_data);
1351 status = spi_register_master(master);
1353 dev_err(dev, "problem registering spi master\n");
1354 goto out_error_queue_alloc;
1357 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1358 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1359 drv_data->dma_channel);
1362 out_error_queue_alloc:
1363 bfin_spi_destroy_queue(drv_data);
1365 iounmap((void *) drv_data->regs_base);
1368 spi_master_put(master);
1373 /* stop hardware and remove the driver */
1374 static int __devexit bfin_spi_remove(struct platform_device *pdev)
1376 struct driver_data *drv_data = platform_get_drvdata(pdev);
1382 /* Remove the queue */
1383 status = bfin_spi_destroy_queue(drv_data);
1387 /* Disable the SSP at the peripheral and SOC level */
1388 bfin_spi_disable(drv_data);
1391 if (drv_data->master_info->enable_dma) {
1392 if (dma_channel_active(drv_data->dma_channel))
1393 free_dma(drv_data->dma_channel);
1396 if (drv_data->irq_requested) {
1397 free_irq(drv_data->spi_irq, drv_data);
1398 drv_data->irq_requested = 0;
1401 /* Disconnect from the SPI framework */
1402 spi_unregister_master(drv_data->master);
1404 peripheral_free_list(drv_data->pin_req);
1406 /* Prevent double remove */
1407 platform_set_drvdata(pdev, NULL);
1413 static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1415 struct driver_data *drv_data = platform_get_drvdata(pdev);
1418 status = bfin_spi_stop_queue(drv_data);
1423 bfin_spi_disable(drv_data);
1428 static int bfin_spi_resume(struct platform_device *pdev)
1430 struct driver_data *drv_data = platform_get_drvdata(pdev);
1433 /* Enable the SPI interface */
1434 bfin_spi_enable(drv_data);
1436 /* Start the queue running */
1437 status = bfin_spi_start_queue(drv_data);
1439 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1446 #define bfin_spi_suspend NULL
1447 #define bfin_spi_resume NULL
1448 #endif /* CONFIG_PM */
1450 MODULE_ALIAS("platform:bfin-spi");
1451 static struct platform_driver bfin_spi_driver = {
1454 .owner = THIS_MODULE,
1456 .suspend = bfin_spi_suspend,
1457 .resume = bfin_spi_resume,
1458 .remove = __devexit_p(bfin_spi_remove),
1461 static int __init bfin_spi_init(void)
1463 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1465 module_init(bfin_spi_init);
1467 static void __exit bfin_spi_exit(void)
1469 platform_driver_unregister(&bfin_spi_driver);
1471 module_exit(bfin_spi_exit);