drivers/spi/spi-topcliff-pch.c

   1 /*
   2  * SPI bus driver for the Topcliff PCH used by Intel SoCs
   3  *
   4  * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/pci.h>
  22 #include <linux/wait.h>
  23 #include <linux/spi/spi.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sched.h>
  26 #include <linux/spi/spidev.h>
  27 #include <linux/module.h>
  28 #include <linux/device.h>
  29 #include <linux/platform_device.h>
  30
  31 #include <linux/dmaengine.h>
  32 #include <linux/pch_dma.h>
  33
  34 /* Register offsets */
  35 #define PCH_SPCR                0x00    /* SPI control register */
  36 #define PCH_SPBRR               0x04    /* SPI baud rate register */
  37 #define PCH_SPSR                0x08    /* SPI status register */
  38 #define PCH_SPDWR               0x0C    /* SPI write data register */
  39 #define PCH_SPDRR               0x10    /* SPI read data register */
  40 #define PCH_SSNXCR              0x18    /* SSN Expand Control Register */
  41 #define PCH_SRST                0x1C    /* SPI reset register */
  42 #define PCH_ADDRESS_SIZE        0x20
  43
  44 #define PCH_SPSR_TFD            0x000007C0
  45 #define PCH_SPSR_RFD            0x0000F800
  46
  47 #define PCH_READABLE(x)         (((x) & PCH_SPSR_RFD)>>11)
  48 #define PCH_WRITABLE(x)         (((x) & PCH_SPSR_TFD)>>6)
  49
  50 #define PCH_RX_THOLD            7
  51 #define PCH_RX_THOLD_MAX        15
  52
  53 #define PCH_MAX_BAUDRATE        5000000
  54 #define PCH_MAX_FIFO_DEPTH      16
  55
  56 #define STATUS_RUNNING          1
  57 #define STATUS_EXITING          2
  58 #define PCH_SLEEP_TIME          10
  59
  60 #define SSN_LOW                 0x02U
  61 #define SSN_NO_CONTROL          0x00U
  62 #define PCH_MAX_CS              0xFF
  63 #define PCI_DEVICE_ID_GE_SPI    0x8816
  64
  65 #define SPCR_SPE_BIT            (1 << 0)
  66 #define SPCR_MSTR_BIT           (1 << 1)
  67 #define SPCR_LSBF_BIT           (1 << 4)
  68 #define SPCR_CPHA_BIT           (1 << 5)
  69 #define SPCR_CPOL_BIT           (1 << 6)
  70 #define SPCR_TFIE_BIT           (1 << 8)
  71 #define SPCR_RFIE_BIT           (1 << 9)
  72 #define SPCR_FIE_BIT            (1 << 10)
  73 #define SPCR_ORIE_BIT           (1 << 11)
  74 #define SPCR_MDFIE_BIT          (1 << 12)
  75 #define SPCR_FICLR_BIT          (1 << 24)
  76 #define SPSR_TFI_BIT            (1 << 0)
  77 #define SPSR_RFI_BIT            (1 << 1)
  78 #define SPSR_FI_BIT             (1 << 2)
  79 #define SPSR_ORF_BIT            (1 << 3)
  80 #define SPBRR_SIZE_BIT          (1 << 10)
  81
  82 #define PCH_ALL                 (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
  83                                 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
  84
  85 #define SPCR_RFIC_FIELD         20
  86 #define SPCR_TFIC_FIELD         16
  87
  88 #define MASK_SPBRR_SPBR_BITS    ((1 << 10) - 1)
  89 #define MASK_RFIC_SPCR_BITS     (0xf << SPCR_RFIC_FIELD)
  90 #define MASK_TFIC_SPCR_BITS     (0xf << SPCR_TFIC_FIELD)
  91
  92 #define PCH_CLOCK_HZ            50000000
  93 #define PCH_MAX_SPBR            1023
  94
  95 /* Definition for ML7213 by OKI SEMICONDUCTOR */
  96 #define PCI_VENDOR_ID_ROHM              0x10DB
  97 #define PCI_DEVICE_ID_ML7213_SPI        0x802c
  98
  99 /*
 100  * Set the number of SPI instance max
 101  * Intel EG20T PCH :            1ch
 102  * OKI SEMICONDUCTOR ML7213 IOH :       2ch
 103 */
 104 #define PCH_SPI_MAX_DEV                 2
 105
 106 #define PCH_BUF_SIZE            4096
 107 #define PCH_DMA_TRANS_SIZE      12
 108
 109 static int use_dma = 1;
 110
 111 struct pch_spi_dma_ctrl {
 112         struct dma_async_tx_descriptor  *desc_tx;
 113         struct dma_async_tx_descriptor  *desc_rx;
 114         struct pch_dma_slave            param_tx;
 115         struct pch_dma_slave            param_rx;
 116         struct dma_chan         *chan_tx;
 117         struct dma_chan         *chan_rx;
 118         struct scatterlist              *sg_tx_p;
 119         struct scatterlist              *sg_rx_p;
 120         struct scatterlist              sg_tx;
 121         struct scatterlist              sg_rx;
 122         int                             nent;
 123         void                            *tx_buf_virt;
 124         void                            *rx_buf_virt;
 125         dma_addr_t                      tx_buf_dma;
 126         dma_addr_t                      rx_buf_dma;
 127 };
 128 /**
 129  * struct pch_spi_data - Holds the SPI channel specific details
 130  * @io_remap_addr:              The remapped PCI base address
 131  * @master:                     Pointer to the SPI master structure
 132  * @work:                       Reference to work queue handler
 133  * @wk:                         Workqueue for carrying out execution of the
 134  *                              requests
 135  * @wait:                       Wait queue for waking up upon receiving an
 136  *                              interrupt.
 137  * @transfer_complete:          Status of SPI Transfer
 138  * @bcurrent_msg_processing:    Status flag for message processing
 139  * @lock:                       Lock for protecting this structure
 140  * @queue:                      SPI Message queue
 141  * @status:                     Status of the SPI driver
 142  * @bpw_len:                    Length of data to be transferred in bits per
 143  *                              word
 144  * @transfer_active:            Flag showing active transfer
 145  * @tx_index:                   Transmit data count; for bookkeeping during
 146  *                              transfer
 147  * @rx_index:                   Receive data count; for bookkeeping during
 148  *                              transfer
 149  * @tx_buff:                    Buffer for data to be transmitted
 150  * @rx_index:                   Buffer for Received data
 151  * @n_curnt_chip:               The chip number that this SPI driver currently
 152  *                              operates on
 153  * @current_chip:               Reference to the current chip that this SPI
 154  *                              driver currently operates on
 155  * @current_msg:                The current message that this SPI driver is
 156  *                              handling
 157  * @cur_trans:                  The current transfer that this SPI driver is
 158  *                              handling
 159  * @board_dat:                  Reference to the SPI device data structure
 160  * @plat_dev:                   platform_device structure
 161  * @ch:                         SPI channel number
 162  * @irq_reg_sts:                Status of IRQ registration
 163  */
 164 struct pch_spi_data {
 165         void __iomem *io_remap_addr;
 166         unsigned long io_base_addr;
 167         struct spi_master *master;
 168         struct work_struct work;
 169         struct workqueue_struct *wk;
 170         wait_queue_head_t wait;
 171         u8 transfer_complete;
 172         u8 bcurrent_msg_processing;
 173         spinlock_t lock;
 174         struct list_head queue;
 175         u8 status;
 176         u32 bpw_len;
 177         u8 transfer_active;
 178         u32 tx_index;
 179         u32 rx_index;
 180         u16 *pkt_tx_buff;
 181         u16 *pkt_rx_buff;
 182         u8 n_curnt_chip;
 183         struct spi_device *current_chip;
 184         struct spi_message *current_msg;
 185         struct spi_transfer *cur_trans;
 186         struct pch_spi_board_data *board_dat;
 187         struct platform_device  *plat_dev;
 188         int ch;
 189         struct pch_spi_dma_ctrl dma;
 190         int use_dma;
 191         u8 irq_reg_sts;
 192 };
 193
 194 /**
 195  * struct pch_spi_board_data - Holds the SPI device specific details
 196  * @pdev:               Pointer to the PCI device
 197  * @suspend_sts:        Status of suspend
 198  * @num:                The number of SPI device instance
 199  */
 200 struct pch_spi_board_data {
 201         struct pci_dev *pdev;
 202         u8 suspend_sts;
 203         int num;
 204 };
 205
 206 struct pch_pd_dev_save {
 207         int num;
 208         struct platform_device *pd_save[PCH_SPI_MAX_DEV];
 209         struct pch_spi_board_data *board_dat;
 210 };
 211
 212 static struct pci_device_id pch_spi_pcidev_id[] = {
 213         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),    1, },
 214         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
 215         { }
 216 };
 217
 218 /**
 219  * pch_spi_writereg() - Performs  register writes
 220  * @master:     Pointer to struct spi_master.
 221  * @idx:        Register offset.
 222  * @val:        Value to be written to register.
 223  */
 224 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
 225 {
 226         struct pch_spi_data *data = spi_master_get_devdata(master);
 227         iowrite32(val, (data->io_remap_addr + idx));
 228 }
 229
 230 /**
 231  * pch_spi_readreg() - Performs register reads
 232  * @master:     Pointer to struct spi_master.
 233  * @idx:        Register offset.
 234  */
 235 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
 236 {
 237         struct pch_spi_data *data = spi_master_get_devdata(master);
 238         return ioread32(data->io_remap_addr + idx);
 239 }
 240
 241 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
 242                                       u32 set, u32 clr)
 243 {
 244         u32 tmp = pch_spi_readreg(master, idx);
 245         tmp = (tmp & ~clr) | set;
 246         pch_spi_writereg(master, idx, tmp);
 247 }
 248
 249 static void pch_spi_set_master_mode(struct spi_master *master)
 250 {
 251         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
 252 }
 253
 254 /**
 255  * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
 256  * @master:     Pointer to struct spi_master.
 257  */
 258 static void pch_spi_clear_fifo(struct spi_master *master)
 259 {
 260         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
 261         pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
 262 }
 263
 264 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
 265                                 void __iomem *io_remap_addr)
 266 {
 267         u32 n_read, tx_index, rx_index, bpw_len;
 268         u16 *pkt_rx_buffer, *pkt_tx_buff;
 269         int read_cnt;
 270         u32 reg_spcr_val;
 271         void __iomem *spsr;
 272         void __iomem *spdrr;
 273         void __iomem *spdwr;
 274
 275         spsr = io_remap_addr + PCH_SPSR;
 276         iowrite32(reg_spsr_val, spsr);
 277
 278         if (data->transfer_active) {
 279                 rx_index = data->rx_index;
 280                 tx_index = data->tx_index;
 281                 bpw_len = data->bpw_len;
 282                 pkt_rx_buffer = data->pkt_rx_buff;
 283                 pkt_tx_buff = data->pkt_tx_buff;
 284
 285                 spdrr = io_remap_addr + PCH_SPDRR;
 286                 spdwr = io_remap_addr + PCH_SPDWR;
 287
 288                 n_read = PCH_READABLE(reg_spsr_val);
 289
 290                 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
 291                         pkt_rx_buffer[rx_index++] = ioread32(spdrr);
 292                         if (tx_index < bpw_len)
 293                                 iowrite32(pkt_tx_buff[tx_index++], spdwr);
 294                 }
 295
 296                 /* disable RFI if not needed */
 297                 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
 298                         reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
 299                         reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
 300
 301                         /* reset rx threshold */
 302                         reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
 303                         reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
 304
 305                         iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
 306                 }
 307
 308                 /* update counts */
 309                 data->tx_index = tx_index;
 310                 data->rx_index = rx_index;
 311
 312         }
 313
 314         /* if transfer complete interrupt */
 315         if (reg_spsr_val & SPSR_FI_BIT) {
 316                 if (tx_index < bpw_len)
 317                         dev_err(&data->master->dev,
 318                                 "%s : Transfer is not completed", __func__);
 319                 /* disable interrupts */
 320                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
 321
 322                 /* transfer is completed;inform pch_spi_process_messages */
 323                 data->transfer_complete = true;
 324                 data->transfer_active = false;
 325                 wake_up(&data->wait);
 326         }
 327 }
 328
 329 /**
 330  * pch_spi_handler() - Interrupt handler
 331  * @irq:        The interrupt number.
 332  * @dev_id:     Pointer to struct pch_spi_board_data.
 333  */
 334 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
 335 {
 336         u32 reg_spsr_val;
 337         void __iomem *spsr;
 338         void __iomem *io_remap_addr;
 339         irqreturn_t ret = IRQ_NONE;
 340         struct pch_spi_data *data = dev_id;
 341         struct pch_spi_board_data *board_dat = data->board_dat;
 342
 343         if (board_dat->suspend_sts) {
 344                 dev_dbg(&board_dat->pdev->dev,
 345                         "%s returning due to suspend\n", __func__);
 346                 return IRQ_NONE;
 347         }
 348         if (data->use_dma)
 349                 return IRQ_NONE;
 350
 351         io_remap_addr = data->io_remap_addr;
 352         spsr = io_remap_addr + PCH_SPSR;
 353
 354         reg_spsr_val = ioread32(spsr);
 355
 356         if (reg_spsr_val & SPSR_ORF_BIT)
 357                 dev_err(&board_dat->pdev->dev, "%s Over run error", __func__);
 358
 359         /* Check if the interrupt is for SPI device */
 360         if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
 361                 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
 362                 ret = IRQ_HANDLED;
 363         }
 364
 365         dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
 366                 __func__, ret);
 367
 368         return ret;
 369 }
 370
 371 /**
 372  * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
 373  * @master:     Pointer to struct spi_master.
 374  * @speed_hz:   Baud rate.
 375  */
 376 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
 377 {
 378         u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
 379
 380         /* if baud rate is less than we can support limit it */
 381         if (n_spbr > PCH_MAX_SPBR)
 382                 n_spbr = PCH_MAX_SPBR;
 383
 384         pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
 385 }
 386
 387 /**
 388  * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
 389  * @master:             Pointer to struct spi_master.
 390  * @bits_per_word:      Bits per word for SPI transfer.
 391  */
 392 static void pch_spi_set_bits_per_word(struct spi_master *master,
 393                                       u8 bits_per_word)
 394 {
 395         if (bits_per_word == 8)
 396                 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
 397         else
 398                 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
 399 }
 400
 401 /**
 402  * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
 403  * @spi:        Pointer to struct spi_device.
 404  */
 405 static void pch_spi_setup_transfer(struct spi_device *spi)
 406 {
 407         u32 flags = 0;
 408
 409         dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
 410                 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
 411                 spi->max_speed_hz);
 412         pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
 413
 414         /* set bits per word */
 415         pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
 416
 417         if (!(spi->mode & SPI_LSB_FIRST))
 418                 flags |= SPCR_LSBF_BIT;
 419         if (spi->mode & SPI_CPOL)
 420                 flags |= SPCR_CPOL_BIT;
 421         if (spi->mode & SPI_CPHA)
 422                 flags |= SPCR_CPHA_BIT;
 423         pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
 424                            (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
 425
 426         /* Clear the FIFO by toggling  FICLR to 1 and back to 0 */
 427         pch_spi_clear_fifo(spi->master);
 428 }
 429
 430 /**
 431  * pch_spi_reset() - Clears SPI registers
 432  * @master:     Pointer to struct spi_master.
 433  */
 434 static void pch_spi_reset(struct spi_master *master)
 435 {
 436         /* write 1 to reset SPI */
 437         pch_spi_writereg(master, PCH_SRST, 0x1);
 438
 439         /* clear reset */
 440         pch_spi_writereg(master, PCH_SRST, 0x0);
 441 }
 442
 443 static int pch_spi_setup(struct spi_device *pspi)
 444 {
 445         /* check bits per word */
 446         if (pspi->bits_per_word == 0) {
 447                 pspi->bits_per_word = 8;
 448                 dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__);
 449         }
 450
 451         if ((pspi->bits_per_word != 8) && (pspi->bits_per_word != 16)) {
 452                 dev_err(&pspi->dev, "%s Invalid bits per word\n", __func__);
 453                 return -EINVAL;
 454         }
 455
 456         /* Check baud rate setting */
 457         /* if baud rate of chip is greater than
 458            max we can support,return error */
 459         if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE)
 460                 pspi->max_speed_hz = PCH_MAX_BAUDRATE;
 461
 462         dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__,
 463                 (pspi->mode) & (SPI_CPOL | SPI_CPHA));
 464
 465         return 0;
 466 }
 467
 468 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
 469 {
 470
 471         struct spi_transfer *transfer;
 472         struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
 473         int retval;
 474         unsigned long flags;
 475
 476         /* validate spi message and baud rate */
 477         if (unlikely(list_empty(&pmsg->transfers) == 1)) {
 478                 dev_err(&pspi->dev, "%s list empty\n", __func__);
 479                 retval = -EINVAL;
 480                 goto err_out;
 481         }
 482
 483         if (unlikely(pspi->max_speed_hz == 0)) {
 484                 dev_err(&pspi->dev, "%s pch_spi_tranfer maxspeed=%d\n",
 485                         __func__, pspi->max_speed_hz);
 486                 retval = -EINVAL;
 487                 goto err_out;
 488         }
 489
 490         dev_dbg(&pspi->dev, "%s Transfer List not empty. "
 491                 "Transfer Speed is set.\n", __func__);
 492
 493         spin_lock_irqsave(&data->lock, flags);
 494         /* validate Tx/Rx buffers and Transfer length */
 495         list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
 496                 if (!transfer->tx_buf && !transfer->rx_buf) {
 497                         dev_err(&pspi->dev,
 498                                 "%s Tx and Rx buffer NULL\n", __func__);
 499                         retval = -EINVAL;
 500                         goto err_return_spinlock;
 501                 }
 502
 503                 if (!transfer->len) {
 504                         dev_err(&pspi->dev, "%s Transfer length invalid\n",
 505                                 __func__);
 506                         retval = -EINVAL;
 507                         goto err_return_spinlock;
 508                 }
 509
 510                 dev_dbg(&pspi->dev, "%s Tx/Rx buffer valid. Transfer length"
 511                         " valid\n", __func__);
 512
 513                 /* if baud rate has been specified validate the same */
 514                 if (transfer->speed_hz > PCH_MAX_BAUDRATE)
 515                         transfer->speed_hz = PCH_MAX_BAUDRATE;
 516
 517                 /* if bits per word has been specified validate the same */
 518                 if (transfer->bits_per_word) {
 519                         if ((transfer->bits_per_word != 8)
 520                             && (transfer->bits_per_word != 16)) {
 521                                 retval = -EINVAL;
 522                                 dev_err(&pspi->dev,
 523                                         "%s Invalid bits per word\n", __func__);
 524                                 goto err_return_spinlock;
 525                         }
 526                 }
 527         }
 528         spin_unlock_irqrestore(&data->lock, flags);
 529
 530         /* We won't process any messages if we have been asked to terminate */
 531         if (data->status == STATUS_EXITING) {
 532                 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
 533                 retval = -ESHUTDOWN;
 534                 goto err_out;
 535         }
 536
 537         /* If suspended ,return -EINVAL */
 538         if (data->board_dat->suspend_sts) {
 539                 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
 540                 retval = -EINVAL;
 541                 goto err_out;
 542         }
 543
 544         /* set status of message */
 545         pmsg->actual_length = 0;
 546         dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
 547
 548         pmsg->status = -EINPROGRESS;
 549         spin_lock_irqsave(&data->lock, flags);
 550         /* add message to queue */
 551         list_add_tail(&pmsg->queue, &data->queue);
 552         spin_unlock_irqrestore(&data->lock, flags);
 553
 554         dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
 555
 556         /* schedule work queue to run */
 557         queue_work(data->wk, &data->work);
 558         dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
 559
 560         retval = 0;
 561
 562 err_out:
 563         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
 564         return retval;
 565 err_return_spinlock:
 566         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
 567         spin_unlock_irqrestore(&data->lock, flags);
 568         return retval;
 569 }
 570
 571 static inline void pch_spi_select_chip(struct pch_spi_data *data,
 572                                        struct spi_device *pspi)
 573 {
 574         if (data->current_chip != NULL) {
 575                 if (pspi->chip_select != data->n_curnt_chip) {
 576                         dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
 577                         data->current_chip = NULL;
 578                 }
 579         }
 580
 581         data->current_chip = pspi;
 582
 583         data->n_curnt_chip = data->current_chip->chip_select;
 584
 585         dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
 586         pch_spi_setup_transfer(pspi);
 587 }
 588
 589 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
 590 {
 591         int size;
 592         u32 n_writes;
 593         int j;
 594         struct spi_message *pmsg;
 595         const u8 *tx_buf;
 596         const u16 *tx_sbuf;
 597
 598         /* set baud rate if needed */
 599         if (data->cur_trans->speed_hz) {
 600                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
 601                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
 602         }
 603
 604         /* set bits per word if needed */
 605         if (data->cur_trans->bits_per_word &&
 606             (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
 607                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
 608                 pch_spi_set_bits_per_word(data->master,
 609                                           data->cur_trans->bits_per_word);
 610                 *bpw = data->cur_trans->bits_per_word;
 611         } else {
 612                 *bpw = data->current_msg->spi->bits_per_word;
 613         }
 614
 615         /* reset Tx/Rx index */
 616         data->tx_index = 0;
 617         data->rx_index = 0;
 618
 619         data->bpw_len = data->cur_trans->len / (*bpw / 8);
 620
 621         /* find alloc size */
 622         size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
 623
 624         /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
 625         data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
 626         if (data->pkt_tx_buff != NULL) {
 627                 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
 628                 if (!data->pkt_rx_buff)
 629                         kfree(data->pkt_tx_buff);
 630         }
 631
 632         if (!data->pkt_rx_buff) {
 633                 /* flush queue and set status of all transfers to -ENOMEM */
 634                 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__);
 635                 list_for_each_entry(pmsg, data->queue.next, queue) {
 636                         pmsg->status = -ENOMEM;
 637
 638                         if (pmsg->complete != 0)
 639                                 pmsg->complete(pmsg->context);
 640
 641                         /* delete from queue */
 642                         list_del_init(&pmsg->queue);
 643                 }
 644                 return;
 645         }
 646
 647         /* copy Tx Data */
 648         if (data->cur_trans->tx_buf != NULL) {
 649                 if (*bpw == 8) {
 650                         tx_buf = data->cur_trans->tx_buf;
 651                         for (j = 0; j < data->bpw_len; j++)
 652                                 data->pkt_tx_buff[j] = *tx_buf++;
 653                 } else {
 654                         tx_sbuf = data->cur_trans->tx_buf;
 655                         for (j = 0; j < data->bpw_len; j++)
 656                                 data->pkt_tx_buff[j] = *tx_sbuf++;
 657                 }
 658         }
 659
 660         /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
 661         n_writes = data->bpw_len;
 662         if (n_writes > PCH_MAX_FIFO_DEPTH)
 663                 n_writes = PCH_MAX_FIFO_DEPTH;
 664
 665         dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
 666                 "0x2 to SSNXCR\n", __func__);
 667         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
 668
 669         for (j = 0; j < n_writes; j++)
 670                 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
 671
 672         /* update tx_index */
 673         data->tx_index = j;
 674
 675         /* reset transfer complete flag */
 676         data->transfer_complete = false;
 677         data->transfer_active = true;
 678 }
 679
 680 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
 681 {
 682         struct spi_message *pmsg;
 683         dev_dbg(&data->master->dev, "%s called\n", __func__);
 684         /* Invoke complete callback
 685          * [To the spi core..indicating end of transfer] */
 686         data->current_msg->status = 0;
 687
 688         if (data->current_msg->complete != 0) {
 689                 dev_dbg(&data->master->dev,
 690                         "%s:Invoking callback of SPI core\n", __func__);
 691                 data->current_msg->complete(data->current_msg->context);
 692         }
 693
 694         /* update status in global variable */
 695         data->bcurrent_msg_processing = false;
 696
 697         dev_dbg(&data->master->dev,
 698                 "%s:data->bcurrent_msg_processing = false\n", __func__);
 699
 700         data->current_msg = NULL;
 701         data->cur_trans = NULL;
 702
 703         /* check if we have items in list and not suspending
 704          * return 1 if list empty */
 705         if ((list_empty(&data->queue) == 0) &&
 706             (!data->board_dat->suspend_sts) &&
 707             (data->status != STATUS_EXITING)) {
 708                 /* We have some more work to do (either there is more tranint
 709                  * bpw;sfer requests in the current message or there are
 710                  *more messages)
 711                  */
 712                 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
 713                 queue_work(data->wk, &data->work);
 714         } else if (data->board_dat->suspend_sts ||
 715                    data->status == STATUS_EXITING) {
 716                 dev_dbg(&data->master->dev,
 717                         "%s suspend/remove initiated, flushing queue\n",
 718                         __func__);
 719                 list_for_each_entry(pmsg, data->queue.next, queue) {
 720                         pmsg->status = -EIO;
 721
 722                         if (pmsg->complete)
 723                                 pmsg->complete(pmsg->context);
 724
 725                         /* delete from queue */
 726                         list_del_init(&pmsg->queue);
 727                 }
 728         }
 729 }
 730
 731 static void pch_spi_set_ir(struct pch_spi_data *data)
 732 {
 733         /* enable interrupts, set threshold, enable SPI */
 734         if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
 735                 /* set receive threshold to PCH_RX_THOLD */
 736                 pch_spi_setclr_reg(data->master, PCH_SPCR,
 737                                    PCH_RX_THOLD << SPCR_RFIC_FIELD |
 738                                    SPCR_FIE_BIT | SPCR_RFIE_BIT |
 739                                    SPCR_ORIE_BIT | SPCR_SPE_BIT,
 740                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
 741         else
 742                 /* set receive threshold to maximum */
 743                 pch_spi_setclr_reg(data->master, PCH_SPCR,
 744                                    PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
 745                                    SPCR_FIE_BIT | SPCR_ORIE_BIT |
 746                                    SPCR_SPE_BIT,
 747                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
 748
 749         /* Wait until the transfer completes; go to sleep after
 750                                  initiating the transfer. */
 751         dev_dbg(&data->master->dev,
 752                 "%s:waiting for transfer to get over\n", __func__);
 753
 754         wait_event_interruptible(data->wait, data->transfer_complete);
 755
 756         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
 757         dev_dbg(&data->master->dev,
 758                 "%s:no more control over SSN-writing 0 to SSNXCR.", __func__);
 759
 760         /* clear all interrupts */
 761         pch_spi_writereg(data->master, PCH_SPSR,
 762                          pch_spi_readreg(data->master, PCH_SPSR));
 763         /* Disable interrupts and SPI transfer */
 764         pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
 765         /* clear FIFO */
 766         pch_spi_clear_fifo(data->master);
 767 }
 768
 769 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
 770 {
 771         int j;
 772         u8 *rx_buf;
 773         u16 *rx_sbuf;
 774
 775         /* copy Rx Data */
 776         if (!data->cur_trans->rx_buf)
 777                 return;
 778
 779         if (bpw == 8) {
 780                 rx_buf = data->cur_trans->rx_buf;
 781                 for (j = 0; j < data->bpw_len; j++)
 782                         *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
 783         } else {
 784                 rx_sbuf = data->cur_trans->rx_buf;
 785                 for (j = 0; j < data->bpw_len; j++)
 786                         *rx_sbuf++ = data->pkt_rx_buff[j];
 787         }
 788 }
 789
 790 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
 791 {
 792         int j;
 793         u8 *rx_buf;
 794         u16 *rx_sbuf;
 795         const u8 *rx_dma_buf;
 796         const u16 *rx_dma_sbuf;
 797
 798         /* copy Rx Data */
 799         if (!data->cur_trans->rx_buf)
 800                 return;
 801
 802         if (bpw == 8) {
 803                 rx_buf = data->cur_trans->rx_buf;
 804                 rx_dma_buf = data->dma.rx_buf_virt;
 805                 for (j = 0; j < data->bpw_len; j++)
 806                         *rx_buf++ = *rx_dma_buf++ & 0xFF;
 807         } else {
 808                 rx_sbuf = data->cur_trans->rx_buf;
 809                 rx_dma_sbuf = data->dma.rx_buf_virt;
 810                 for (j = 0; j < data->bpw_len; j++)
 811                         *rx_sbuf++ = *rx_dma_sbuf++;
 812         }
 813 }
 814
 815 static void pch_spi_start_transfer(struct pch_spi_data *data)
 816 {
 817         struct pch_spi_dma_ctrl *dma;
 818         unsigned long flags;
 819
 820         dma = &data->dma;
 821
 822         spin_lock_irqsave(&data->lock, flags);
 823
 824         /* disable interrupts, SPI set enable */
 825         pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
 826
 827         spin_unlock_irqrestore(&data->lock, flags);
 828
 829         /* Wait until the transfer completes; go to sleep after
 830                                  initiating the transfer. */
 831         dev_dbg(&data->master->dev,
 832                 "%s:waiting for transfer to get over\n", __func__);
 833         wait_event_interruptible(data->wait, data->transfer_complete);
 834
 835         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
 836                             DMA_FROM_DEVICE);
 837         async_tx_ack(dma->desc_rx);
 838         async_tx_ack(dma->desc_tx);
 839         kfree(dma->sg_tx_p);
 840         kfree(dma->sg_rx_p);
 841
 842         spin_lock_irqsave(&data->lock, flags);
 843         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
 844         dev_dbg(&data->master->dev,
 845                 "%s:no more control over SSN-writing 0 to SSNXCR.", __func__);
 846
 847         /* clear fifo threshold, disable interrupts, disable SPI transfer */
 848         pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
 849                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
 850                            SPCR_SPE_BIT);
 851         /* clear all interrupts */
 852         pch_spi_writereg(data->master, PCH_SPSR,
 853                          pch_spi_readreg(data->master, PCH_SPSR));
 854         /* clear FIFO */
 855         pch_spi_clear_fifo(data->master);
 856
 857         spin_unlock_irqrestore(&data->lock, flags);
 858 }
 859
 860 static void pch_dma_rx_complete(void *arg)
 861 {
 862         struct pch_spi_data *data = arg;
 863
 864         /* transfer is completed;inform pch_spi_process_messages_dma */
 865         data->transfer_complete = true;
 866         wake_up_interruptible(&data->wait);
 867 }
 868
 869 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
 870 {
 871         struct pch_dma_slave *param = slave;
 872
 873         if ((chan->chan_id == param->chan_id) &&
 874             (param->dma_dev == chan->device->dev)) {
 875                 chan->private = param;
 876                 return true;
 877         } else {
 878                 return false;
 879         }
 880 }
 881
 882 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
 883 {
 884         dma_cap_mask_t mask;
 885         struct dma_chan *chan;
 886         struct pci_dev *dma_dev;
 887         struct pch_dma_slave *param;
 888         struct pch_spi_dma_ctrl *dma;
 889         unsigned int width;
 890
 891         if (bpw == 8)
 892                 width = PCH_DMA_WIDTH_1_BYTE;
 893         else
 894                 width = PCH_DMA_WIDTH_2_BYTES;
 895
 896         dma = &data->dma;
 897         dma_cap_zero(mask);
 898         dma_cap_set(DMA_SLAVE, mask);
 899
 900         /* Get DMA's dev information */
 901         dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(12, 0));
 902
 903         /* Set Tx DMA */
 904         param = &dma->param_tx;
 905         param->dma_dev = &dma_dev->dev;
 906         param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */
 907         param->tx_reg = data->io_base_addr + PCH_SPDWR;
 908         param->width = width;
 909         chan = dma_request_channel(mask, pch_spi_filter, param);
 910         if (!chan) {
 911                 dev_err(&data->master->dev,
 912                         "ERROR: dma_request_channel FAILS(Tx)\n");
 913                 data->use_dma = 0;
 914                 return;
 915         }
 916         dma->chan_tx = chan;
 917
 918         /* Set Rx DMA */
 919         param = &dma->param_rx;
 920         param->dma_dev = &dma_dev->dev;
 921         param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */
 922         param->rx_reg = data->io_base_addr + PCH_SPDRR;
 923         param->width = width;
 924         chan = dma_request_channel(mask, pch_spi_filter, param);
 925         if (!chan) {
 926                 dev_err(&data->master->dev,
 927                         "ERROR: dma_request_channel FAILS(Rx)\n");
 928                 dma_release_channel(dma->chan_tx);
 929                 dma->chan_tx = NULL;
 930                 data->use_dma = 0;
 931                 return;
 932         }
 933         dma->chan_rx = chan;
 934 }
 935
 936 static void pch_spi_release_dma(struct pch_spi_data *data)
 937 {
 938         struct pch_spi_dma_ctrl *dma;
 939
 940         dma = &data->dma;
 941         if (dma->chan_tx) {
 942                 dma_release_channel(dma->chan_tx);
 943                 dma->chan_tx = NULL;
 944         }
 945         if (dma->chan_rx) {
 946                 dma_release_channel(dma->chan_rx);
 947                 dma->chan_rx = NULL;
 948         }
 949         return;
 950 }
 951
 952 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
 953 {
 954         const u8 *tx_buf;
 955         const u16 *tx_sbuf;
 956         u8 *tx_dma_buf;
 957         u16 *tx_dma_sbuf;
 958         struct scatterlist *sg;
 959         struct dma_async_tx_descriptor *desc_tx;
 960         struct dma_async_tx_descriptor *desc_rx;
 961         int num;
 962         int i;
 963         int size;
 964         int rem;
 965         unsigned long flags;
 966         struct pch_spi_dma_ctrl *dma;
 967
 968         dma = &data->dma;
 969
 970         /* set baud rate if needed */
 971         if (data->cur_trans->speed_hz) {
 972                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
 973                 spin_lock_irqsave(&data->lock, flags);
 974                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
 975                 spin_unlock_irqrestore(&data->lock, flags);
 976         }
 977
 978         /* set bits per word if needed */
 979         if (data->cur_trans->bits_per_word &&
 980             (data->current_msg->spi->bits_per_word !=
 981              data->cur_trans->bits_per_word)) {
 982                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
 983                 spin_lock_irqsave(&data->lock, flags);
 984                 pch_spi_set_bits_per_word(data->master,
 985                                           data->cur_trans->bits_per_word);
 986                 spin_unlock_irqrestore(&data->lock, flags);
 987                 *bpw = data->cur_trans->bits_per_word;
 988         } else {
 989                 *bpw = data->current_msg->spi->bits_per_word;
 990         }
 991         data->bpw_len = data->cur_trans->len / (*bpw / 8);
 992
 993         /* copy Tx Data */
 994         if (data->cur_trans->tx_buf != NULL) {
 995                 if (*bpw == 8) {
 996                         tx_buf = data->cur_trans->tx_buf;
 997                         tx_dma_buf = dma->tx_buf_virt;
 998                         for (i = 0; i < data->bpw_len; i++)
 999                                 *tx_dma_buf++ = *tx_buf++;
1000                 } else {
1001                         tx_sbuf = data->cur_trans->tx_buf;
1002                         tx_dma_sbuf = dma->tx_buf_virt;
1003                         for (i = 0; i < data->bpw_len; i++)
1004                                 *tx_dma_sbuf++ = *tx_sbuf++;
1005                 }
1006         }
1007         if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
1008                 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1009                 size = PCH_DMA_TRANS_SIZE;
1010                 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
1011         } else {
1012                 num = 1;
1013                 size = data->bpw_len;
1014                 rem = data->bpw_len;
1015         }
1016         dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1017                 __func__, num, size, rem);
1018         spin_lock_irqsave(&data->lock, flags);
1019
1020         /* set receive fifo threshold and transmit fifo threshold */
1021         pch_spi_setclr_reg(data->master, PCH_SPCR,
1022                            ((size - 1) << SPCR_RFIC_FIELD) |
1023                            ((PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE) <<
1024                             SPCR_TFIC_FIELD),
1025                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1026
1027         spin_unlock_irqrestore(&data->lock, flags);
1028
1029         /* RX */
1030         dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1031         sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1032         /* offset, length setting */
1033         sg = dma->sg_rx_p;
1034         for (i = 0; i < num; i++, sg++) {
1035                 if (i == 0) {
1036                         sg->offset = 0;
1037                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1038                                     sg->offset);
1039                         sg_dma_len(sg) = rem;
1040                 } else {
1041                         sg->offset = rem + size * (i - 1);
1042                         sg->offset = sg->offset * (*bpw / 8);
1043                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1044                                     sg->offset);
1045                         sg_dma_len(sg) = size;
1046                 }
1047                 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1048         }
1049         sg = dma->sg_rx_p;
1050         desc_rx = dma->chan_rx->device->device_prep_slave_sg(dma->chan_rx, sg,
1051                                         num, DMA_FROM_DEVICE,
1052                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1053         if (!desc_rx) {
1054                 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1055                         __func__);
1056                 return;
1057         }
1058         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1059         desc_rx->callback = pch_dma_rx_complete;
1060         desc_rx->callback_param = data;
1061         dma->nent = num;
1062         dma->desc_rx = desc_rx;
1063
1064         /* TX */
1065         dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1066         sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1067         /* offset, length setting */
1068         sg = dma->sg_tx_p;
1069         for (i = 0; i < num; i++, sg++) {
1070                 if (i == 0) {
1071                         sg->offset = 0;
1072                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1073                                     sg->offset);
1074                         sg_dma_len(sg) = rem;
1075                 } else {
1076                         sg->offset = rem + size * (i - 1);
1077                         sg->offset = sg->offset * (*bpw / 8);
1078                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1079                                     sg->offset);
1080                         sg_dma_len(sg) = size;
1081                 }
1082                 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1083         }
1084         sg = dma->sg_tx_p;
1085         desc_tx = dma->chan_tx->device->device_prep_slave_sg(dma->chan_tx,
1086                                         sg, num, DMA_TO_DEVICE,
1087                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1088         if (!desc_tx) {
1089                 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1090                         __func__);
1091                 return;
1092         }
1093         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1094         desc_tx->callback = NULL;
1095         desc_tx->callback_param = data;
1096         dma->nent = num;
1097         dma->desc_tx = desc_tx;
1098
1099         dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
1100                 "0x2 to SSNXCR\n", __func__);
1101
1102         spin_lock_irqsave(&data->lock, flags);
1103         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1104         desc_rx->tx_submit(desc_rx);
1105         desc_tx->tx_submit(desc_tx);
1106         spin_unlock_irqrestore(&data->lock, flags);
1107
1108         /* reset transfer complete flag */
1109         data->transfer_complete = false;
1110 }
1111
1112 static void pch_spi_process_messages(struct work_struct *pwork)
1113 {
1114         struct spi_message *pmsg;
1115         struct pch_spi_data *data;
1116         int bpw;
1117
1118         data = container_of(pwork, struct pch_spi_data, work);
1119         dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1120
1121         spin_lock(&data->lock);
1122         /* check if suspend has been initiated;if yes flush queue */
1123         if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1124                 dev_dbg(&data->master->dev, "%s suspend/remove initiated,"
1125                         "flushing queue\n", __func__);
1126                 list_for_each_entry(pmsg, data->queue.next, queue) {
1127                         pmsg->status = -EIO;
1128
1129                         if (pmsg->complete != 0) {
1130                                 spin_unlock(&data->lock);
1131                                 pmsg->complete(pmsg->context);
1132                                 spin_lock(&data->lock);
1133                         }
1134
1135                         /* delete from queue */
1136                         list_del_init(&pmsg->queue);
1137                 }
1138
1139                 spin_unlock(&data->lock);
1140                 return;
1141         }
1142
1143         data->bcurrent_msg_processing = true;
1144         dev_dbg(&data->master->dev,
1145                 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1146
1147         /* Get the message from the queue and delete it from there. */
1148         data->current_msg = list_entry(data->queue.next, struct spi_message,
1149                                         queue);
1150
1151         list_del_init(&data->current_msg->queue);
1152
1153         data->current_msg->status = 0;
1154
1155         pch_spi_select_chip(data, data->current_msg->spi);
1156
1157         spin_unlock(&data->lock);
1158
1159         if (data->use_dma)
1160                 pch_spi_request_dma(data,
1161                                     data->current_msg->spi->bits_per_word);
1162         do {
1163                 /* If we are already processing a message get the next
1164                 transfer structure from the message otherwise retrieve
1165                 the 1st transfer request from the message. */
1166                 spin_lock(&data->lock);
1167                 if (data->cur_trans == NULL) {
1168                         data->cur_trans =
1169                                 list_entry(data->current_msg->transfers.next,
1170                                            struct spi_transfer, transfer_list);
1171                         dev_dbg(&data->master->dev, "%s "
1172                                 ":Getting 1st transfer message\n", __func__);
1173                 } else {
1174                         data->cur_trans =
1175                                 list_entry(data->cur_trans->transfer_list.next,
1176                                            struct spi_transfer, transfer_list);
1177                         dev_dbg(&data->master->dev, "%s "
1178                                 ":Getting next transfer message\n", __func__);
1179                 }
1180                 spin_unlock(&data->lock);
1181
1182                 if (data->use_dma) {
1183                         pch_spi_handle_dma(data, &bpw);
1184                         pch_spi_start_transfer(data);
1185                         pch_spi_copy_rx_data_for_dma(data, bpw);
1186                 } else {
1187                         pch_spi_set_tx(data, &bpw);
1188                         pch_spi_set_ir(data);
1189                         pch_spi_copy_rx_data(data, bpw);
1190                         kfree(data->pkt_rx_buff);
1191                         data->pkt_rx_buff = NULL;
1192                         kfree(data->pkt_tx_buff);
1193                         data->pkt_tx_buff = NULL;
1194                 }
1195                 /* increment message count */
1196                 data->current_msg->actual_length += data->cur_trans->len;
1197
1198                 dev_dbg(&data->master->dev,
1199                         "%s:data->current_msg->actual_length=%d\n",
1200                         __func__, data->current_msg->actual_length);
1201
1202                 /* check for delay */
1203                 if (data->cur_trans->delay_usecs) {
1204                         dev_dbg(&data->master->dev, "%s:"
1205                                 "delay in usec=%d\n", __func__,
1206                                 data->cur_trans->delay_usecs);
1207                         udelay(data->cur_trans->delay_usecs);
1208                 }
1209
1210                 spin_lock(&data->lock);
1211
1212                 /* No more transfer in this message. */
1213                 if ((data->cur_trans->transfer_list.next) ==
1214                     &(data->current_msg->transfers)) {
1215                         pch_spi_nomore_transfer(data);
1216                 }
1217
1218                 spin_unlock(&data->lock);
1219
1220         } while (data->cur_trans != NULL);
1221
1222         if (data->use_dma)
1223                 pch_spi_release_dma(data);
1224 }
1225
1226 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1227                                    struct pch_spi_data *data)
1228 {
1229         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1230
1231         /* free workqueue */
1232         if (data->wk != NULL) {
1233                 destroy_workqueue(data->wk);
1234                 data->wk = NULL;
1235                 dev_dbg(&board_dat->pdev->dev,
1236                         "%s destroy_workqueue invoked successfully\n",
1237                         __func__);
1238         }
1239 }
1240
1241 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1242                                  struct pch_spi_data *data)
1243 {
1244         int retval = 0;
1245
1246         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1247
1248         /* create workqueue */
1249         data->wk = create_singlethread_workqueue(KBUILD_MODNAME);
1250         if (!data->wk) {
1251                 dev_err(&board_dat->pdev->dev,
1252                         "%s create_singlet hread_workqueue failed\n", __func__);
1253                 retval = -EBUSY;
1254                 goto err_return;
1255         }
1256
1257         /* reset PCH SPI h/w */
1258         pch_spi_reset(data->master);
1259         dev_dbg(&board_dat->pdev->dev,
1260                 "%s pch_spi_reset invoked successfully\n", __func__);
1261
1262         dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1263
1264 err_return:
1265         if (retval != 0) {
1266                 dev_err(&board_dat->pdev->dev,
1267                         "%s FAIL:invoking pch_spi_free_resources\n", __func__);
1268                 pch_spi_free_resources(board_dat, data);
1269         }
1270
1271         dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
1272
1273         return retval;
1274 }
1275
1276 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1277                              struct pch_spi_data *data)
1278 {
1279         struct pch_spi_dma_ctrl *dma;
1280
1281         dma = &data->dma;
1282         if (dma->tx_buf_dma)
1283                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1284                                   dma->tx_buf_virt, dma->tx_buf_dma);
1285         if (dma->rx_buf_dma)
1286                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1287                                   dma->rx_buf_virt, dma->rx_buf_dma);
1288         return;
1289 }
1290
1291 static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1292                               struct pch_spi_data *data)
1293 {
1294         struct pch_spi_dma_ctrl *dma;
1295
1296         dma = &data->dma;
1297         /* Get Consistent memory for Tx DMA */
1298         dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1299                                 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1300         /* Get Consistent memory for Rx DMA */
1301         dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1302                                 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1303 }
1304
1305 static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
1306 {
1307         int ret;
1308         struct spi_master *master;
1309         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1310         struct pch_spi_data *data;
1311
1312         dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1313
1314         master = spi_alloc_master(&board_dat->pdev->dev,
1315                                   sizeof(struct pch_spi_data));
1316         if (!master) {
1317                 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1318                         plat_dev->id);
1319                 return -ENOMEM;
1320         }
1321
1322         data = spi_master_get_devdata(master);
1323         data->master = master;
1324
1325         platform_set_drvdata(plat_dev, data);
1326
1327         /* baseaddress + address offset) */
1328         data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1329                                          PCH_ADDRESS_SIZE * plat_dev->id;
1330         data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0) +
1331                                          PCH_ADDRESS_SIZE * plat_dev->id;
1332         if (!data->io_remap_addr) {
1333                 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1334                 ret = -ENOMEM;
1335                 goto err_pci_iomap;
1336         }
1337
1338         dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1339                 plat_dev->id, data->io_remap_addr);
1340
1341         /* initialize members of SPI master */
1342         master->bus_num = -1;
1343         master->num_chipselect = PCH_MAX_CS;
1344         master->setup = pch_spi_setup;
1345         master->transfer = pch_spi_transfer;
1346
1347         data->board_dat = board_dat;
1348         data->plat_dev = plat_dev;
1349         data->n_curnt_chip = 255;
1350         data->status = STATUS_RUNNING;
1351         data->ch = plat_dev->id;
1352         data->use_dma = use_dma;
1353
1354         INIT_LIST_HEAD(&data->queue);
1355         spin_lock_init(&data->lock);
1356         INIT_WORK(&data->work, pch_spi_process_messages);
1357         init_waitqueue_head(&data->wait);
1358
1359         ret = pch_spi_get_resources(board_dat, data);
1360         if (ret) {
1361                 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1362                 goto err_spi_get_resources;
1363         }
1364
1365         ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1366                           IRQF_SHARED, KBUILD_MODNAME, data);
1367         if (ret) {
1368                 dev_err(&plat_dev->dev,
1369                         "%s request_irq failed\n", __func__);
1370                 goto err_request_irq;
1371         }
1372         data->irq_reg_sts = true;
1373
1374         pch_spi_set_master_mode(master);
1375
1376         ret = spi_register_master(master);
1377         if (ret != 0) {
1378                 dev_err(&plat_dev->dev,
1379                         "%s spi_register_master FAILED\n", __func__);
1380                 goto err_spi_register_master;
1381         }
1382
1383         if (use_dma) {
1384                 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1385                 pch_alloc_dma_buf(board_dat, data);
1386         }
1387
1388         return 0;
1389
1390 err_spi_register_master:
1391         free_irq(board_dat->pdev->irq, board_dat);
1392 err_request_irq:
1393         pch_spi_free_resources(board_dat, data);
1394 err_spi_get_resources:
1395         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1396 err_pci_iomap:
1397         spi_master_put(master);
1398
1399         return ret;
1400 }
1401
1402 static int __devexit pch_spi_pd_remove(struct platform_device *plat_dev)
1403 {
1404         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1405         struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1406         int count;
1407         unsigned long flags;
1408
1409         dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1410                 __func__, plat_dev->id, board_dat->pdev->irq);
1411
1412         if (use_dma)
1413                 pch_free_dma_buf(board_dat, data);
1414
1415         /* check for any pending messages; no action is taken if the queue
1416          * is still full; but at least we tried.  Unload anyway */
1417         count = 500;
1418         spin_lock_irqsave(&data->lock, flags);
1419         data->status = STATUS_EXITING;
1420         while ((list_empty(&data->queue) == 0) && --count) {
1421                 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1422                         __func__);
1423                 spin_unlock_irqrestore(&data->lock, flags);
1424                 msleep(PCH_SLEEP_TIME);
1425                 spin_lock_irqsave(&data->lock, flags);
1426         }
1427         spin_unlock_irqrestore(&data->lock, flags);
1428
1429         pch_spi_free_resources(board_dat, data);
1430         /* disable interrupts & free IRQ */
1431         if (data->irq_reg_sts) {
1432                 /* disable interrupts */
1433                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1434                 data->irq_reg_sts = false;
1435                 free_irq(board_dat->pdev->irq, data);
1436         }
1437
1438         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1439         spi_unregister_master(data->master);
1440         spi_master_put(data->master);
1441         platform_set_drvdata(plat_dev, NULL);
1442
1443         return 0;
1444 }
1445 #ifdef CONFIG_PM
1446 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1447                               pm_message_t state)
1448 {
1449         u8 count;
1450         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1451         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1452
1453         dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1454
1455         if (!board_dat) {
1456                 dev_err(&pd_dev->dev,
1457                         "%s pci_get_drvdata returned NULL\n", __func__);
1458                 return -EFAULT;
1459         }
1460
1461         /* check if the current message is processed:
1462            Only after thats done the transfer will be suspended */
1463         count = 255;
1464         while ((--count) > 0) {
1465                 if (!(data->bcurrent_msg_processing))
1466                         break;
1467                 msleep(PCH_SLEEP_TIME);
1468         }
1469
1470         /* Free IRQ */
1471         if (data->irq_reg_sts) {
1472                 /* disable all interrupts */
1473                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1474                 pch_spi_reset(data->master);
1475                 free_irq(board_dat->pdev->irq, data);
1476
1477                 data->irq_reg_sts = false;
1478                 dev_dbg(&pd_dev->dev,
1479                         "%s free_irq invoked successfully.\n", __func__);
1480         }
1481
1482         return 0;
1483 }
1484
1485 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1486 {
1487         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1488         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1489         int retval;
1490
1491         if (!board_dat) {
1492                 dev_err(&pd_dev->dev,
1493                         "%s pci_get_drvdata returned NULL\n", __func__);
1494                 return -EFAULT;
1495         }
1496
1497         if (!data->irq_reg_sts) {
1498                 /* register IRQ */
1499                 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1500                                      IRQF_SHARED, KBUILD_MODNAME, data);
1501                 if (retval < 0) {
1502                         dev_err(&pd_dev->dev,
1503                                 "%s request_irq failed\n", __func__);
1504                         return retval;
1505                 }
1506
1507                 /* reset PCH SPI h/w */
1508                 pch_spi_reset(data->master);
1509                 pch_spi_set_master_mode(data->master);
1510                 data->irq_reg_sts = true;
1511         }
1512         return 0;
1513 }
1514 #else
1515 #define pch_spi_pd_suspend NULL
1516 #define pch_spi_pd_resume NULL
1517 #endif
1518
1519 static struct platform_driver pch_spi_pd_driver = {
1520         .driver = {
1521                 .name = "pch-spi",
1522                 .owner = THIS_MODULE,
1523         },
1524         .probe = pch_spi_pd_probe,
1525         .remove = __devexit_p(pch_spi_pd_remove),
1526         .suspend = pch_spi_pd_suspend,
1527         .resume = pch_spi_pd_resume
1528 };
1529
1530 static int __devinit pch_spi_probe(struct pci_dev *pdev,
1531                                    const struct pci_device_id *id)
1532 {
1533         struct pch_spi_board_data *board_dat;
1534         struct platform_device *pd_dev = NULL;
1535         int retval;
1536         int i;
1537         struct pch_pd_dev_save *pd_dev_save;
1538
1539         pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL);
1540         if (!pd_dev_save) {
1541                 dev_err(&pdev->dev, "%s Can't allocate pd_dev_sav\n", __func__);
1542                 return -ENOMEM;
1543         }
1544
1545         board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
1546         if (!board_dat) {
1547                 dev_err(&pdev->dev, "%s Can't allocate board_dat\n", __func__);
1548                 retval = -ENOMEM;
1549                 goto err_no_mem;
1550         }
1551
1552         retval = pci_request_regions(pdev, KBUILD_MODNAME);
1553         if (retval) {
1554                 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1555                 goto pci_request_regions;
1556         }
1557
1558         board_dat->pdev = pdev;
1559         board_dat->num = id->driver_data;
1560         pd_dev_save->num = id->driver_data;
1561         pd_dev_save->board_dat = board_dat;
1562
1563         retval = pci_enable_device(pdev);
1564         if (retval) {
1565                 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1566                 goto pci_enable_device;
1567         }
1568
1569         for (i = 0; i < board_dat->num; i++) {
1570                 pd_dev = platform_device_alloc("pch-spi", i);
1571                 if (!pd_dev) {
1572                         dev_err(&pdev->dev, "platform_device_alloc failed\n");
1573                         goto err_platform_device;
1574                 }
1575                 pd_dev_save->pd_save[i] = pd_dev;
1576                 pd_dev->dev.parent = &pdev->dev;
1577
1578                 retval = platform_device_add_data(pd_dev, board_dat,
1579                                                   sizeof(*board_dat));
1580                 if (retval) {
1581                         dev_err(&pdev->dev,
1582                                 "platform_device_add_data failed\n");
1583                         platform_device_put(pd_dev);
1584                         goto err_platform_device;
1585                 }
1586
1587                 retval = platform_device_add(pd_dev);
1588                 if (retval) {
1589                         dev_err(&pdev->dev, "platform_device_add failed\n");
1590                         platform_device_put(pd_dev);
1591                         goto err_platform_device;
1592                 }
1593         }
1594
1595         pci_set_drvdata(pdev, pd_dev_save);
1596
1597         return 0;
1598
1599 err_platform_device:
1600         pci_disable_device(pdev);
1601 pci_enable_device:
1602         pci_release_regions(pdev);
1603 pci_request_regions:
1604         kfree(board_dat);
1605 err_no_mem:
1606         kfree(pd_dev_save);
1607
1608         return retval;
1609 }
1610
1611 static void __devexit pch_spi_remove(struct pci_dev *pdev)
1612 {
1613         int i;
1614         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1615
1616         dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1617
1618         for (i = 0; i < pd_dev_save->num; i++)
1619                 platform_device_unregister(pd_dev_save->pd_save[i]);
1620
1621         pci_disable_device(pdev);
1622         pci_release_regions(pdev);
1623         kfree(pd_dev_save->board_dat);
1624         kfree(pd_dev_save);
1625 }
1626
1627 #ifdef CONFIG_PM
1628 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1629 {
1630         int retval;
1631         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1632
1633         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1634
1635         pd_dev_save->board_dat->suspend_sts = true;
1636
1637         /* save config space */
1638         retval = pci_save_state(pdev);
1639         if (retval == 0) {
1640                 pci_enable_wake(pdev, PCI_D3hot, 0);
1641                 pci_disable_device(pdev);
1642                 pci_set_power_state(pdev, PCI_D3hot);
1643         } else {
1644                 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1645         }
1646
1647         return retval;
1648 }
1649
1650 static int pch_spi_resume(struct pci_dev *pdev)
1651 {
1652         int retval;
1653         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1654         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1655
1656         pci_set_power_state(pdev, PCI_D0);
1657         pci_restore_state(pdev);
1658
1659         retval = pci_enable_device(pdev);
1660         if (retval < 0) {
1661                 dev_err(&pdev->dev,
1662                         "%s pci_enable_device failed\n", __func__);
1663         } else {
1664                 pci_enable_wake(pdev, PCI_D3hot, 0);
1665
1666                 /* set suspend status to false */
1667                 pd_dev_save->board_dat->suspend_sts = false;
1668         }
1669
1670         return retval;
1671 }
1672 #else
1673 #define pch_spi_suspend NULL
1674 #define pch_spi_resume NULL
1675
1676 #endif
1677
1678 static struct pci_driver pch_spi_pcidev = {
1679         .name = "pch_spi",
1680         .id_table = pch_spi_pcidev_id,
1681         .probe = pch_spi_probe,
1682         .remove = pch_spi_remove,
1683         .suspend = pch_spi_suspend,
1684         .resume = pch_spi_resume,
1685 };
1686
1687 static int __init pch_spi_init(void)
1688 {
1689         int ret;
1690         ret = platform_driver_register(&pch_spi_pd_driver);
1691         if (ret)
1692                 return ret;
1693
1694         ret = pci_register_driver(&pch_spi_pcidev);
1695         if (ret)
1696                 return ret;
1697
1698         return 0;
1699 }
1700 module_init(pch_spi_init);
1701
1702 static void __exit pch_spi_exit(void)
1703 {
1704         pci_unregister_driver(&pch_spi_pcidev);
1705         platform_driver_unregister(&pch_spi_pd_driver);
1706 }
1707 module_exit(pch_spi_exit);
1708
1709 module_param(use_dma, int, 0644);
1710 MODULE_PARM_DESC(use_dma,
1711                  "to use DMA for data transfers pass 1 else 0; default 1");
1712
1713 MODULE_LICENSE("GPL");
1714 MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH SPI Driver");