2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/spi/pxa2xx_spi.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/spi/spi.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/gpio.h>
32 #include <linux/slab.h>
36 #include <asm/delay.h>
39 MODULE_AUTHOR("Stephen Street");
40 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
41 MODULE_LICENSE("GPL");
42 MODULE_ALIAS("platform:pxa2xx-spi");
46 #define TIMOUT_DFLT 1000
48 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
49 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
50 #define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0)
51 #define MAX_DMA_LEN 8191
52 #define DMA_ALIGNMENT 8
55 * for testing SSCR1 changes that require SSP restart, basically
56 * everything except the service and interrupt enables, the pxa270 developer
57 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
58 * list, but the PXA255 dev man says all bits without really meaning the
59 * service and interrupt enables
61 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
62 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
63 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
64 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
65 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
66 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
68 #define DEFINE_SSP_REG(reg, off) \
69 static inline u32 read_##reg(void const __iomem *p) \
70 { return __raw_readl(p + (off)); } \
72 static inline void write_##reg(u32 v, void __iomem *p) \
73 { __raw_writel(v, p + (off)); }
75 DEFINE_SSP_REG(SSCR0, 0x00)
76 DEFINE_SSP_REG(SSCR1, 0x04)
77 DEFINE_SSP_REG(SSSR, 0x08)
78 DEFINE_SSP_REG(SSITR, 0x0c)
79 DEFINE_SSP_REG(SSDR, 0x10)
80 DEFINE_SSP_REG(SSTO, 0x28)
81 DEFINE_SSP_REG(SSPSP, 0x2c)
83 #define START_STATE ((void*)0)
84 #define RUNNING_STATE ((void*)1)
85 #define DONE_STATE ((void*)2)
86 #define ERROR_STATE ((void*)-1)
88 #define QUEUE_RUNNING 0
89 #define QUEUE_STOPPED 1
92 /* Driver model hookup */
93 struct platform_device *pdev;
96 struct ssp_device *ssp;
98 /* SPI framework hookup */
99 enum pxa_ssp_type ssp_type;
100 struct spi_master *master;
103 struct pxa2xx_spi_master *master_info;
105 /* DMA setup stuff */
110 /* SSP register addresses */
111 void __iomem *ioaddr;
120 /* Driver message queue */
121 struct workqueue_struct *workqueue;
122 struct work_struct pump_messages;
124 struct list_head queue;
128 /* Message Transfer pump */
129 struct tasklet_struct pump_transfers;
131 /* Current message transfer state info */
132 struct spi_message* cur_msg;
133 struct spi_transfer* cur_transfer;
134 struct chip_data *cur_chip;
147 int (*write)(struct driver_data *drv_data);
148 int (*read)(struct driver_data *drv_data);
149 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
150 void (*cs_control)(u32 command);
170 int gpio_cs_inverted;
171 int (*write)(struct driver_data *drv_data);
172 int (*read)(struct driver_data *drv_data);
173 void (*cs_control)(u32 command);
176 static void pump_messages(struct work_struct *work);
178 static void cs_assert(struct driver_data *drv_data)
180 struct chip_data *chip = drv_data->cur_chip;
182 if (drv_data->ssp_type == CE4100_SSP) {
183 write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
187 if (chip->cs_control) {
188 chip->cs_control(PXA2XX_CS_ASSERT);
192 if (gpio_is_valid(chip->gpio_cs))
193 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
196 static void cs_deassert(struct driver_data *drv_data)
198 struct chip_data *chip = drv_data->cur_chip;
200 if (drv_data->ssp_type == CE4100_SSP)
203 if (chip->cs_control) {
204 chip->cs_control(PXA2XX_CS_DEASSERT);
208 if (gpio_is_valid(chip->gpio_cs))
209 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
212 static void write_SSSR_CS(struct driver_data *drv_data, u32 val)
214 void __iomem *reg = drv_data->ioaddr;
216 if (drv_data->ssp_type == CE4100_SSP)
217 val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK;
219 write_SSSR(val, reg);
222 static int pxa25x_ssp_comp(struct driver_data *drv_data)
224 if (drv_data->ssp_type == PXA25x_SSP)
226 if (drv_data->ssp_type == CE4100_SSP)
231 static int flush(struct driver_data *drv_data)
233 unsigned long limit = loops_per_jiffy << 1;
235 void __iomem *reg = drv_data->ioaddr;
238 while (read_SSSR(reg) & SSSR_RNE) {
241 } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
242 write_SSSR_CS(drv_data, SSSR_ROR);
247 static int null_writer(struct driver_data *drv_data)
249 void __iomem *reg = drv_data->ioaddr;
250 u8 n_bytes = drv_data->n_bytes;
252 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
253 || (drv_data->tx == drv_data->tx_end))
257 drv_data->tx += n_bytes;
262 static int null_reader(struct driver_data *drv_data)
264 void __iomem *reg = drv_data->ioaddr;
265 u8 n_bytes = drv_data->n_bytes;
267 while ((read_SSSR(reg) & SSSR_RNE)
268 && (drv_data->rx < drv_data->rx_end)) {
270 drv_data->rx += n_bytes;
273 return drv_data->rx == drv_data->rx_end;
276 static int u8_writer(struct driver_data *drv_data)
278 void __iomem *reg = drv_data->ioaddr;
280 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
281 || (drv_data->tx == drv_data->tx_end))
284 write_SSDR(*(u8 *)(drv_data->tx), reg);
290 static int u8_reader(struct driver_data *drv_data)
292 void __iomem *reg = drv_data->ioaddr;
294 while ((read_SSSR(reg) & SSSR_RNE)
295 && (drv_data->rx < drv_data->rx_end)) {
296 *(u8 *)(drv_data->rx) = read_SSDR(reg);
300 return drv_data->rx == drv_data->rx_end;
303 static int u16_writer(struct driver_data *drv_data)
305 void __iomem *reg = drv_data->ioaddr;
307 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
308 || (drv_data->tx == drv_data->tx_end))
311 write_SSDR(*(u16 *)(drv_data->tx), reg);
317 static int u16_reader(struct driver_data *drv_data)
319 void __iomem *reg = drv_data->ioaddr;
321 while ((read_SSSR(reg) & SSSR_RNE)
322 && (drv_data->rx < drv_data->rx_end)) {
323 *(u16 *)(drv_data->rx) = read_SSDR(reg);
327 return drv_data->rx == drv_data->rx_end;
330 static int u32_writer(struct driver_data *drv_data)
332 void __iomem *reg = drv_data->ioaddr;
334 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
335 || (drv_data->tx == drv_data->tx_end))
338 write_SSDR(*(u32 *)(drv_data->tx), reg);
344 static int u32_reader(struct driver_data *drv_data)
346 void __iomem *reg = drv_data->ioaddr;
348 while ((read_SSSR(reg) & SSSR_RNE)
349 && (drv_data->rx < drv_data->rx_end)) {
350 *(u32 *)(drv_data->rx) = read_SSDR(reg);
354 return drv_data->rx == drv_data->rx_end;
357 static void *next_transfer(struct driver_data *drv_data)
359 struct spi_message *msg = drv_data->cur_msg;
360 struct spi_transfer *trans = drv_data->cur_transfer;
362 /* Move to next transfer */
363 if (trans->transfer_list.next != &msg->transfers) {
364 drv_data->cur_transfer =
365 list_entry(trans->transfer_list.next,
368 return RUNNING_STATE;
373 static int map_dma_buffers(struct driver_data *drv_data)
375 struct spi_message *msg = drv_data->cur_msg;
376 struct device *dev = &msg->spi->dev;
378 if (!drv_data->cur_chip->enable_dma)
381 if (msg->is_dma_mapped)
382 return drv_data->rx_dma && drv_data->tx_dma;
384 if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
387 /* Modify setup if rx buffer is null */
388 if (drv_data->rx == NULL) {
389 *drv_data->null_dma_buf = 0;
390 drv_data->rx = drv_data->null_dma_buf;
391 drv_data->rx_map_len = 4;
393 drv_data->rx_map_len = drv_data->len;
396 /* Modify setup if tx buffer is null */
397 if (drv_data->tx == NULL) {
398 *drv_data->null_dma_buf = 0;
399 drv_data->tx = drv_data->null_dma_buf;
400 drv_data->tx_map_len = 4;
402 drv_data->tx_map_len = drv_data->len;
404 /* Stream map the tx buffer. Always do DMA_TO_DEVICE first
405 * so we flush the cache *before* invalidating it, in case
406 * the tx and rx buffers overlap.
408 drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
409 drv_data->tx_map_len, DMA_TO_DEVICE);
410 if (dma_mapping_error(dev, drv_data->tx_dma))
413 /* Stream map the rx buffer */
414 drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
415 drv_data->rx_map_len, DMA_FROM_DEVICE);
416 if (dma_mapping_error(dev, drv_data->rx_dma)) {
417 dma_unmap_single(dev, drv_data->tx_dma,
418 drv_data->tx_map_len, DMA_TO_DEVICE);
425 static void unmap_dma_buffers(struct driver_data *drv_data)
429 if (!drv_data->dma_mapped)
432 if (!drv_data->cur_msg->is_dma_mapped) {
433 dev = &drv_data->cur_msg->spi->dev;
434 dma_unmap_single(dev, drv_data->rx_dma,
435 drv_data->rx_map_len, DMA_FROM_DEVICE);
436 dma_unmap_single(dev, drv_data->tx_dma,
437 drv_data->tx_map_len, DMA_TO_DEVICE);
440 drv_data->dma_mapped = 0;
443 /* caller already set message->status; dma and pio irqs are blocked */
444 static void giveback(struct driver_data *drv_data)
446 struct spi_transfer* last_transfer;
448 struct spi_message *msg;
450 spin_lock_irqsave(&drv_data->lock, flags);
451 msg = drv_data->cur_msg;
452 drv_data->cur_msg = NULL;
453 drv_data->cur_transfer = NULL;
454 queue_work(drv_data->workqueue, &drv_data->pump_messages);
455 spin_unlock_irqrestore(&drv_data->lock, flags);
457 last_transfer = list_entry(msg->transfers.prev,
461 /* Delay if requested before any change in chip select */
462 if (last_transfer->delay_usecs)
463 udelay(last_transfer->delay_usecs);
465 /* Drop chip select UNLESS cs_change is true or we are returning
466 * a message with an error, or next message is for another chip
468 if (!last_transfer->cs_change)
469 cs_deassert(drv_data);
471 struct spi_message *next_msg;
473 /* Holding of cs was hinted, but we need to make sure
474 * the next message is for the same chip. Don't waste
475 * time with the following tests unless this was hinted.
477 * We cannot postpone this until pump_messages, because
478 * after calling msg->complete (below) the driver that
479 * sent the current message could be unloaded, which
480 * could invalidate the cs_control() callback...
483 /* get a pointer to the next message, if any */
484 spin_lock_irqsave(&drv_data->lock, flags);
485 if (list_empty(&drv_data->queue))
488 next_msg = list_entry(drv_data->queue.next,
489 struct spi_message, queue);
490 spin_unlock_irqrestore(&drv_data->lock, flags);
492 /* see if the next and current messages point
495 if (next_msg && next_msg->spi != msg->spi)
497 if (!next_msg || msg->state == ERROR_STATE)
498 cs_deassert(drv_data);
503 msg->complete(msg->context);
505 drv_data->cur_chip = NULL;
508 static int wait_ssp_rx_stall(void const __iomem *ioaddr)
510 unsigned long limit = loops_per_jiffy << 1;
512 while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit)
518 static int wait_dma_channel_stop(int channel)
520 unsigned long limit = loops_per_jiffy << 1;
522 while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit)
528 static void dma_error_stop(struct driver_data *drv_data, const char *msg)
530 void __iomem *reg = drv_data->ioaddr;
533 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
534 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
535 write_SSSR_CS(drv_data, drv_data->clear_sr);
536 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
537 if (!pxa25x_ssp_comp(drv_data))
540 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
542 unmap_dma_buffers(drv_data);
544 dev_err(&drv_data->pdev->dev, "%s\n", msg);
546 drv_data->cur_msg->state = ERROR_STATE;
547 tasklet_schedule(&drv_data->pump_transfers);
550 static void dma_transfer_complete(struct driver_data *drv_data)
552 void __iomem *reg = drv_data->ioaddr;
553 struct spi_message *msg = drv_data->cur_msg;
555 /* Clear and disable interrupts on SSP and DMA channels*/
556 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
557 write_SSSR_CS(drv_data, drv_data->clear_sr);
558 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
559 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
561 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
562 dev_err(&drv_data->pdev->dev,
563 "dma_handler: dma rx channel stop failed\n");
565 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
566 dev_err(&drv_data->pdev->dev,
567 "dma_transfer: ssp rx stall failed\n");
569 unmap_dma_buffers(drv_data);
571 /* update the buffer pointer for the amount completed in dma */
572 drv_data->rx += drv_data->len -
573 (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
575 /* read trailing data from fifo, it does not matter how many
576 * bytes are in the fifo just read until buffer is full
577 * or fifo is empty, which ever occurs first */
578 drv_data->read(drv_data);
580 /* return count of what was actually read */
581 msg->actual_length += drv_data->len -
582 (drv_data->rx_end - drv_data->rx);
584 /* Transfer delays and chip select release are
585 * handled in pump_transfers or giveback
588 /* Move to next transfer */
589 msg->state = next_transfer(drv_data);
591 /* Schedule transfer tasklet */
592 tasklet_schedule(&drv_data->pump_transfers);
595 static void dma_handler(int channel, void *data)
597 struct driver_data *drv_data = data;
598 u32 irq_status = DCSR(channel) & DMA_INT_MASK;
600 if (irq_status & DCSR_BUSERR) {
602 if (channel == drv_data->tx_channel)
603 dma_error_stop(drv_data,
605 "bad bus address on tx channel");
607 dma_error_stop(drv_data,
609 "bad bus address on rx channel");
613 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
614 if ((channel == drv_data->tx_channel)
615 && (irq_status & DCSR_ENDINTR)
616 && (drv_data->ssp_type == PXA25x_SSP)) {
618 /* Wait for rx to stall */
619 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
620 dev_err(&drv_data->pdev->dev,
621 "dma_handler: ssp rx stall failed\n");
623 /* finish this transfer, start the next */
624 dma_transfer_complete(drv_data);
628 static irqreturn_t dma_transfer(struct driver_data *drv_data)
631 void __iomem *reg = drv_data->ioaddr;
633 irq_status = read_SSSR(reg) & drv_data->mask_sr;
634 if (irq_status & SSSR_ROR) {
635 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
639 /* Check for false positive timeout */
640 if ((irq_status & SSSR_TINT)
641 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
642 write_SSSR(SSSR_TINT, reg);
646 if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
648 /* Clear and disable timeout interrupt, do the rest in
649 * dma_transfer_complete */
650 if (!pxa25x_ssp_comp(drv_data))
653 /* finish this transfer, start the next */
654 dma_transfer_complete(drv_data);
659 /* Opps problem detected */
663 static void reset_sccr1(struct driver_data *drv_data)
665 void __iomem *reg = drv_data->ioaddr;
666 struct chip_data *chip = drv_data->cur_chip;
669 sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
670 sccr1_reg &= ~SSCR1_RFT;
671 sccr1_reg |= chip->threshold;
672 write_SSCR1(sccr1_reg, reg);
675 static void int_error_stop(struct driver_data *drv_data, const char* msg)
677 void __iomem *reg = drv_data->ioaddr;
679 /* Stop and reset SSP */
680 write_SSSR_CS(drv_data, drv_data->clear_sr);
681 reset_sccr1(drv_data);
682 if (!pxa25x_ssp_comp(drv_data))
685 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
687 dev_err(&drv_data->pdev->dev, "%s\n", msg);
689 drv_data->cur_msg->state = ERROR_STATE;
690 tasklet_schedule(&drv_data->pump_transfers);
693 static void int_transfer_complete(struct driver_data *drv_data)
695 void __iomem *reg = drv_data->ioaddr;
698 write_SSSR_CS(drv_data, drv_data->clear_sr);
699 reset_sccr1(drv_data);
700 if (!pxa25x_ssp_comp(drv_data))
703 /* Update total byte transferred return count actual bytes read */
704 drv_data->cur_msg->actual_length += drv_data->len -
705 (drv_data->rx_end - drv_data->rx);
707 /* Transfer delays and chip select release are
708 * handled in pump_transfers or giveback
711 /* Move to next transfer */
712 drv_data->cur_msg->state = next_transfer(drv_data);
714 /* Schedule transfer tasklet */
715 tasklet_schedule(&drv_data->pump_transfers);
718 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
720 void __iomem *reg = drv_data->ioaddr;
722 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
723 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
725 u32 irq_status = read_SSSR(reg) & irq_mask;
727 if (irq_status & SSSR_ROR) {
728 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
732 if (irq_status & SSSR_TINT) {
733 write_SSSR(SSSR_TINT, reg);
734 if (drv_data->read(drv_data)) {
735 int_transfer_complete(drv_data);
740 /* Drain rx fifo, Fill tx fifo and prevent overruns */
742 if (drv_data->read(drv_data)) {
743 int_transfer_complete(drv_data);
746 } while (drv_data->write(drv_data));
748 if (drv_data->read(drv_data)) {
749 int_transfer_complete(drv_data);
753 if (drv_data->tx == drv_data->tx_end) {
757 sccr1_reg = read_SSCR1(reg);
758 sccr1_reg &= ~SSCR1_TIE;
761 * PXA25x_SSP has no timeout, set up rx threshould for the
762 * remaining RX bytes.
764 if (pxa25x_ssp_comp(drv_data)) {
766 sccr1_reg &= ~SSCR1_RFT;
768 bytes_left = drv_data->rx_end - drv_data->rx;
769 switch (drv_data->n_bytes) {
776 if (bytes_left > RX_THRESH_DFLT)
777 bytes_left = RX_THRESH_DFLT;
779 sccr1_reg |= SSCR1_RxTresh(bytes_left);
781 write_SSCR1(sccr1_reg, reg);
784 /* We did something */
788 static irqreturn_t ssp_int(int irq, void *dev_id)
790 struct driver_data *drv_data = dev_id;
791 void __iomem *reg = drv_data->ioaddr;
792 u32 sccr1_reg = read_SSCR1(reg);
793 u32 mask = drv_data->mask_sr;
796 status = read_SSSR(reg);
798 /* Ignore possible writes if we don't need to write */
799 if (!(sccr1_reg & SSCR1_TIE))
802 /* Ignore RX timeout interrupt if it is disabled */
803 if (!(sccr1_reg & SSCR1_TINTE))
806 if (!(status & mask))
809 if (!drv_data->cur_msg) {
811 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
812 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
813 if (!pxa25x_ssp_comp(drv_data))
815 write_SSSR_CS(drv_data, drv_data->clear_sr);
817 dev_err(&drv_data->pdev->dev, "bad message state "
818 "in interrupt handler\n");
824 return drv_data->transfer_handler(drv_data);
827 static int set_dma_burst_and_threshold(struct chip_data *chip,
828 struct spi_device *spi,
829 u8 bits_per_word, u32 *burst_code,
832 struct pxa2xx_spi_chip *chip_info =
833 (struct pxa2xx_spi_chip *)spi->controller_data;
840 /* Set the threshold (in registers) to equal the same amount of data
841 * as represented by burst size (in bytes). The computation below
842 * is (burst_size rounded up to nearest 8 byte, word or long word)
843 * divided by (bytes/register); the tx threshold is the inverse of
844 * the rx, so that there will always be enough data in the rx fifo
845 * to satisfy a burst, and there will always be enough space in the
846 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
847 * there is not enough space), there must always remain enough empty
848 * space in the rx fifo for any data loaded to the tx fifo.
849 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
850 * will be 8, or half the fifo;
851 * The threshold can only be set to 2, 4 or 8, but not 16, because
852 * to burst 16 to the tx fifo, the fifo would have to be empty;
853 * however, the minimum fifo trigger level is 1, and the tx will
854 * request service when the fifo is at this level, with only 15 spaces.
857 /* find bytes/word */
858 if (bits_per_word <= 8)
860 else if (bits_per_word <= 16)
865 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
867 req_burst_size = chip_info->dma_burst_size;
869 switch (chip->dma_burst_size) {
871 /* if the default burst size is not set,
873 chip->dma_burst_size = DCMD_BURST8;
885 if (req_burst_size <= 8) {
886 *burst_code = DCMD_BURST8;
888 } else if (req_burst_size <= 16) {
889 if (bytes_per_word == 1) {
890 /* don't burst more than 1/2 the fifo */
891 *burst_code = DCMD_BURST8;
895 *burst_code = DCMD_BURST16;
899 if (bytes_per_word == 1) {
900 /* don't burst more than 1/2 the fifo */
901 *burst_code = DCMD_BURST8;
904 } else if (bytes_per_word == 2) {
905 /* don't burst more than 1/2 the fifo */
906 *burst_code = DCMD_BURST16;
910 *burst_code = DCMD_BURST32;
915 thresh_words = burst_bytes / bytes_per_word;
917 /* thresh_words will be between 2 and 8 */
918 *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
919 | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
924 static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
926 unsigned long ssp_clk = clk_get_rate(ssp->clk);
928 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
929 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
931 return ((ssp_clk / rate - 1) & 0xfff) << 8;
934 static void pump_transfers(unsigned long data)
936 struct driver_data *drv_data = (struct driver_data *)data;
937 struct spi_message *message = NULL;
938 struct spi_transfer *transfer = NULL;
939 struct spi_transfer *previous = NULL;
940 struct chip_data *chip = NULL;
941 struct ssp_device *ssp = drv_data->ssp;
942 void __iomem *reg = drv_data->ioaddr;
948 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
949 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
951 /* Get current state information */
952 message = drv_data->cur_msg;
953 transfer = drv_data->cur_transfer;
954 chip = drv_data->cur_chip;
956 /* Handle for abort */
957 if (message->state == ERROR_STATE) {
958 message->status = -EIO;
963 /* Handle end of message */
964 if (message->state == DONE_STATE) {
970 /* Delay if requested at end of transfer before CS change */
971 if (message->state == RUNNING_STATE) {
972 previous = list_entry(transfer->transfer_list.prev,
975 if (previous->delay_usecs)
976 udelay(previous->delay_usecs);
978 /* Drop chip select only if cs_change is requested */
979 if (previous->cs_change)
980 cs_deassert(drv_data);
983 /* Check for transfers that need multiple DMA segments */
984 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
986 /* reject already-mapped transfers; PIO won't always work */
987 if (message->is_dma_mapped
988 || transfer->rx_dma || transfer->tx_dma) {
989 dev_err(&drv_data->pdev->dev,
990 "pump_transfers: mapped transfer length "
991 "of %u is greater than %d\n",
992 transfer->len, MAX_DMA_LEN);
993 message->status = -EINVAL;
998 /* warn ... we force this to PIO mode */
999 if (printk_ratelimit())
1000 dev_warn(&message->spi->dev, "pump_transfers: "
1001 "DMA disabled for transfer length %ld "
1002 "greater than %d\n",
1003 (long)drv_data->len, MAX_DMA_LEN);
1006 /* Setup the transfer state based on the type of transfer */
1007 if (flush(drv_data) == 0) {
1008 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
1009 message->status = -EIO;
1013 drv_data->n_bytes = chip->n_bytes;
1014 drv_data->dma_width = chip->dma_width;
1015 drv_data->tx = (void *)transfer->tx_buf;
1016 drv_data->tx_end = drv_data->tx + transfer->len;
1017 drv_data->rx = transfer->rx_buf;
1018 drv_data->rx_end = drv_data->rx + transfer->len;
1019 drv_data->rx_dma = transfer->rx_dma;
1020 drv_data->tx_dma = transfer->tx_dma;
1021 drv_data->len = transfer->len & DCMD_LENGTH;
1022 drv_data->write = drv_data->tx ? chip->write : null_writer;
1023 drv_data->read = drv_data->rx ? chip->read : null_reader;
1025 /* Change speed and bit per word on a per transfer */
1027 if (transfer->speed_hz || transfer->bits_per_word) {
1029 bits = chip->bits_per_word;
1030 speed = chip->speed_hz;
1032 if (transfer->speed_hz)
1033 speed = transfer->speed_hz;
1035 if (transfer->bits_per_word)
1036 bits = transfer->bits_per_word;
1038 clk_div = ssp_get_clk_div(ssp, speed);
1041 drv_data->n_bytes = 1;
1042 drv_data->dma_width = DCMD_WIDTH1;
1043 drv_data->read = drv_data->read != null_reader ?
1044 u8_reader : null_reader;
1045 drv_data->write = drv_data->write != null_writer ?
1046 u8_writer : null_writer;
1047 } else if (bits <= 16) {
1048 drv_data->n_bytes = 2;
1049 drv_data->dma_width = DCMD_WIDTH2;
1050 drv_data->read = drv_data->read != null_reader ?
1051 u16_reader : null_reader;
1052 drv_data->write = drv_data->write != null_writer ?
1053 u16_writer : null_writer;
1054 } else if (bits <= 32) {
1055 drv_data->n_bytes = 4;
1056 drv_data->dma_width = DCMD_WIDTH4;
1057 drv_data->read = drv_data->read != null_reader ?
1058 u32_reader : null_reader;
1059 drv_data->write = drv_data->write != null_writer ?
1060 u32_writer : null_writer;
1062 /* if bits/word is changed in dma mode, then must check the
1063 * thresholds and burst also */
1064 if (chip->enable_dma) {
1065 if (set_dma_burst_and_threshold(chip, message->spi,
1068 if (printk_ratelimit())
1069 dev_warn(&message->spi->dev,
1071 "DMA burst size reduced to "
1072 "match bits_per_word\n");
1077 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
1079 | (bits > 16 ? SSCR0_EDSS : 0);
1082 message->state = RUNNING_STATE;
1084 /* Try to map dma buffer and do a dma transfer if successful, but
1085 * only if the length is non-zero and less than MAX_DMA_LEN.
1087 * Zero-length non-descriptor DMA is illegal on PXA2xx; force use
1088 * of PIO instead. Care is needed above because the transfer may
1089 * have have been passed with buffers that are already dma mapped.
1090 * A zero-length transfer in PIO mode will not try to write/read
1091 * to/from the buffers
1093 * REVISIT large transfers are exactly where we most want to be
1094 * using DMA. If this happens much, split those transfers into
1095 * multiple DMA segments rather than forcing PIO.
1097 drv_data->dma_mapped = 0;
1098 if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN)
1099 drv_data->dma_mapped = map_dma_buffers(drv_data);
1100 if (drv_data->dma_mapped) {
1102 /* Ensure we have the correct interrupt handler */
1103 drv_data->transfer_handler = dma_transfer;
1105 /* Setup rx DMA Channel */
1106 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
1107 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
1108 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
1109 if (drv_data->rx == drv_data->null_dma_buf)
1110 /* No target address increment */
1111 DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
1112 | drv_data->dma_width
1116 DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
1118 | drv_data->dma_width
1122 /* Setup tx DMA Channel */
1123 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
1124 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
1125 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
1126 if (drv_data->tx == drv_data->null_dma_buf)
1127 /* No source address increment */
1128 DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
1129 | drv_data->dma_width
1133 DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
1135 | drv_data->dma_width
1139 /* Enable dma end irqs on SSP to detect end of transfer */
1140 if (drv_data->ssp_type == PXA25x_SSP)
1141 DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
1143 /* Clear status and start DMA engine */
1144 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1145 write_SSSR(drv_data->clear_sr, reg);
1146 DCSR(drv_data->rx_channel) |= DCSR_RUN;
1147 DCSR(drv_data->tx_channel) |= DCSR_RUN;
1149 /* Ensure we have the correct interrupt handler */
1150 drv_data->transfer_handler = interrupt_transfer;
1153 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1154 write_SSSR_CS(drv_data, drv_data->clear_sr);
1157 /* see if we need to reload the config registers */
1158 if ((read_SSCR0(reg) != cr0)
1159 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
1160 (cr1 & SSCR1_CHANGE_MASK)) {
1162 /* stop the SSP, and update the other bits */
1163 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
1164 if (!pxa25x_ssp_comp(drv_data))
1165 write_SSTO(chip->timeout, reg);
1166 /* first set CR1 without interrupt and service enables */
1167 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
1168 /* restart the SSP */
1169 write_SSCR0(cr0, reg);
1172 if (!pxa25x_ssp_comp(drv_data))
1173 write_SSTO(chip->timeout, reg);
1176 cs_assert(drv_data);
1178 /* after chip select, release the data by enabling service
1179 * requests and interrupts, without changing any mode bits */
1180 write_SSCR1(cr1, reg);
1183 static void pump_messages(struct work_struct *work)
1185 struct driver_data *drv_data =
1186 container_of(work, struct driver_data, pump_messages);
1187 unsigned long flags;
1189 /* Lock queue and check for queue work */
1190 spin_lock_irqsave(&drv_data->lock, flags);
1191 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1193 spin_unlock_irqrestore(&drv_data->lock, flags);
1197 /* Make sure we are not already running a message */
1198 if (drv_data->cur_msg) {
1199 spin_unlock_irqrestore(&drv_data->lock, flags);
1203 /* Extract head of queue */
1204 drv_data->cur_msg = list_entry(drv_data->queue.next,
1205 struct spi_message, queue);
1206 list_del_init(&drv_data->cur_msg->queue);
1208 /* Initial message state*/
1209 drv_data->cur_msg->state = START_STATE;
1210 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1211 struct spi_transfer,
1214 /* prepare to setup the SSP, in pump_transfers, using the per
1215 * chip configuration */
1216 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1218 /* Mark as busy and launch transfers */
1219 tasklet_schedule(&drv_data->pump_transfers);
1222 spin_unlock_irqrestore(&drv_data->lock, flags);
1225 static int transfer(struct spi_device *spi, struct spi_message *msg)
1227 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1228 unsigned long flags;
1230 spin_lock_irqsave(&drv_data->lock, flags);
1232 if (drv_data->run == QUEUE_STOPPED) {
1233 spin_unlock_irqrestore(&drv_data->lock, flags);
1237 msg->actual_length = 0;
1238 msg->status = -EINPROGRESS;
1239 msg->state = START_STATE;
1241 list_add_tail(&msg->queue, &drv_data->queue);
1243 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1244 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1246 spin_unlock_irqrestore(&drv_data->lock, flags);
1251 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1252 struct pxa2xx_spi_chip *chip_info)
1256 if (chip == NULL || chip_info == NULL)
1259 /* NOTE: setup() can be called multiple times, possibly with
1260 * different chip_info, release previously requested GPIO
1262 if (gpio_is_valid(chip->gpio_cs))
1263 gpio_free(chip->gpio_cs);
1265 /* If (*cs_control) is provided, ignore GPIO chip select */
1266 if (chip_info->cs_control) {
1267 chip->cs_control = chip_info->cs_control;
1271 if (gpio_is_valid(chip_info->gpio_cs)) {
1272 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1274 dev_err(&spi->dev, "failed to request chip select "
1275 "GPIO%d\n", chip_info->gpio_cs);
1279 chip->gpio_cs = chip_info->gpio_cs;
1280 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1282 err = gpio_direction_output(chip->gpio_cs,
1283 !chip->gpio_cs_inverted);
1289 static int setup(struct spi_device *spi)
1291 struct pxa2xx_spi_chip *chip_info = NULL;
1292 struct chip_data *chip;
1293 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1294 struct ssp_device *ssp = drv_data->ssp;
1295 unsigned int clk_div;
1296 uint tx_thres = TX_THRESH_DFLT;
1297 uint rx_thres = RX_THRESH_DFLT;
1299 if (!pxa25x_ssp_comp(drv_data)
1300 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1301 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1302 "b/w not 4-32 for type non-PXA25x_SSP\n",
1303 drv_data->ssp_type, spi->bits_per_word);
1305 } else if (pxa25x_ssp_comp(drv_data)
1306 && (spi->bits_per_word < 4
1307 || spi->bits_per_word > 16)) {
1308 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1309 "b/w not 4-16 for type PXA25x_SSP\n",
1310 drv_data->ssp_type, spi->bits_per_word);
1314 /* Only alloc on first setup */
1315 chip = spi_get_ctldata(spi);
1317 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1320 "failed setup: can't allocate chip data\n");
1324 if (drv_data->ssp_type == CE4100_SSP) {
1325 if (spi->chip_select > 4) {
1326 dev_err(&spi->dev, "failed setup: "
1327 "cs number must not be > 4.\n");
1332 chip->frm = spi->chip_select;
1335 chip->enable_dma = 0;
1336 chip->timeout = TIMOUT_DFLT;
1337 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1341 /* protocol drivers may change the chip settings, so...
1342 * if chip_info exists, use it */
1343 chip_info = spi->controller_data;
1345 /* chip_info isn't always needed */
1348 if (chip_info->timeout)
1349 chip->timeout = chip_info->timeout;
1350 if (chip_info->tx_threshold)
1351 tx_thres = chip_info->tx_threshold;
1352 if (chip_info->rx_threshold)
1353 rx_thres = chip_info->rx_threshold;
1354 chip->enable_dma = drv_data->master_info->enable_dma;
1355 chip->dma_threshold = 0;
1356 if (chip_info->enable_loopback)
1357 chip->cr1 = SSCR1_LBM;
1360 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1361 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1363 /* set dma burst and threshold outside of chip_info path so that if
1364 * chip_info goes away after setting chip->enable_dma, the
1365 * burst and threshold can still respond to changes in bits_per_word */
1366 if (chip->enable_dma) {
1367 /* set up legal burst and threshold for dma */
1368 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1369 &chip->dma_burst_size,
1370 &chip->dma_threshold)) {
1371 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1372 "to match bits_per_word\n");
1376 clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
1377 chip->speed_hz = spi->max_speed_hz;
1381 | SSCR0_DataSize(spi->bits_per_word > 16 ?
1382 spi->bits_per_word - 16 : spi->bits_per_word)
1384 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1385 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1386 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1387 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1389 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1390 if (!pxa25x_ssp_comp(drv_data))
1391 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1392 clk_get_rate(ssp->clk)
1393 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
1394 chip->enable_dma ? "DMA" : "PIO");
1396 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1397 clk_get_rate(ssp->clk) / 2
1398 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1399 chip->enable_dma ? "DMA" : "PIO");
1401 if (spi->bits_per_word <= 8) {
1403 chip->dma_width = DCMD_WIDTH1;
1404 chip->read = u8_reader;
1405 chip->write = u8_writer;
1406 } else if (spi->bits_per_word <= 16) {
1408 chip->dma_width = DCMD_WIDTH2;
1409 chip->read = u16_reader;
1410 chip->write = u16_writer;
1411 } else if (spi->bits_per_word <= 32) {
1412 chip->cr0 |= SSCR0_EDSS;
1414 chip->dma_width = DCMD_WIDTH4;
1415 chip->read = u32_reader;
1416 chip->write = u32_writer;
1418 dev_err(&spi->dev, "invalid wordsize\n");
1421 chip->bits_per_word = spi->bits_per_word;
1423 spi_set_ctldata(spi, chip);
1425 if (drv_data->ssp_type == CE4100_SSP)
1428 return setup_cs(spi, chip, chip_info);
1431 static void cleanup(struct spi_device *spi)
1433 struct chip_data *chip = spi_get_ctldata(spi);
1434 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1439 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1440 gpio_free(chip->gpio_cs);
1445 static int __devinit init_queue(struct driver_data *drv_data)
1447 INIT_LIST_HEAD(&drv_data->queue);
1448 spin_lock_init(&drv_data->lock);
1450 drv_data->run = QUEUE_STOPPED;
1453 tasklet_init(&drv_data->pump_transfers,
1454 pump_transfers, (unsigned long)drv_data);
1456 INIT_WORK(&drv_data->pump_messages, pump_messages);
1457 drv_data->workqueue = create_singlethread_workqueue(
1458 dev_name(drv_data->master->dev.parent));
1459 if (drv_data->workqueue == NULL)
1465 static int start_queue(struct driver_data *drv_data)
1467 unsigned long flags;
1469 spin_lock_irqsave(&drv_data->lock, flags);
1471 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1472 spin_unlock_irqrestore(&drv_data->lock, flags);
1476 drv_data->run = QUEUE_RUNNING;
1477 drv_data->cur_msg = NULL;
1478 drv_data->cur_transfer = NULL;
1479 drv_data->cur_chip = NULL;
1480 spin_unlock_irqrestore(&drv_data->lock, flags);
1482 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1487 static int stop_queue(struct driver_data *drv_data)
1489 unsigned long flags;
1490 unsigned limit = 500;
1493 spin_lock_irqsave(&drv_data->lock, flags);
1495 /* This is a bit lame, but is optimized for the common execution path.
1496 * A wait_queue on the drv_data->busy could be used, but then the common
1497 * execution path (pump_messages) would be required to call wake_up or
1498 * friends on every SPI message. Do this instead */
1499 drv_data->run = QUEUE_STOPPED;
1500 while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) {
1501 spin_unlock_irqrestore(&drv_data->lock, flags);
1503 spin_lock_irqsave(&drv_data->lock, flags);
1506 if (!list_empty(&drv_data->queue) || drv_data->busy)
1509 spin_unlock_irqrestore(&drv_data->lock, flags);
1514 static int destroy_queue(struct driver_data *drv_data)
1518 status = stop_queue(drv_data);
1519 /* we are unloading the module or failing to load (only two calls
1520 * to this routine), and neither call can handle a return value.
1521 * However, destroy_workqueue calls flush_workqueue, and that will
1522 * block until all work is done. If the reason that stop_queue
1523 * timed out is that the work will never finish, then it does no
1524 * good to call destroy_workqueue, so return anyway. */
1528 destroy_workqueue(drv_data->workqueue);
1533 static int __devinit pxa2xx_spi_probe(struct platform_device *pdev)
1535 struct device *dev = &pdev->dev;
1536 struct pxa2xx_spi_master *platform_info;
1537 struct spi_master *master;
1538 struct driver_data *drv_data;
1539 struct ssp_device *ssp;
1542 platform_info = dev->platform_data;
1544 ssp = pxa_ssp_request(pdev->id, pdev->name);
1546 dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
1550 /* Allocate master with space for drv_data and null dma buffer */
1551 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1553 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1557 drv_data = spi_master_get_devdata(master);
1558 drv_data->master = master;
1559 drv_data->master_info = platform_info;
1560 drv_data->pdev = pdev;
1561 drv_data->ssp = ssp;
1563 master->dev.parent = &pdev->dev;
1564 master->dev.of_node = pdev->dev.of_node;
1565 /* the spi->mode bits understood by this driver: */
1566 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1568 master->bus_num = pdev->id;
1569 master->num_chipselect = platform_info->num_chipselect;
1570 master->dma_alignment = DMA_ALIGNMENT;
1571 master->cleanup = cleanup;
1572 master->setup = setup;
1573 master->transfer = transfer;
1575 drv_data->ssp_type = ssp->type;
1576 drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1577 sizeof(struct driver_data)), 8);
1579 drv_data->ioaddr = ssp->mmio_base;
1580 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1581 if (pxa25x_ssp_comp(drv_data)) {
1582 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1583 drv_data->dma_cr1 = 0;
1584 drv_data->clear_sr = SSSR_ROR;
1585 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1587 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1588 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1589 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1590 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1593 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1596 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1597 goto out_error_master_alloc;
1600 /* Setup DMA if requested */
1601 drv_data->tx_channel = -1;
1602 drv_data->rx_channel = -1;
1603 if (platform_info->enable_dma) {
1605 /* Get two DMA channels (rx and tx) */
1606 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1610 if (drv_data->rx_channel < 0) {
1611 dev_err(dev, "problem (%d) requesting rx channel\n",
1612 drv_data->rx_channel);
1614 goto out_error_irq_alloc;
1616 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1620 if (drv_data->tx_channel < 0) {
1621 dev_err(dev, "problem (%d) requesting tx channel\n",
1622 drv_data->tx_channel);
1624 goto out_error_dma_alloc;
1627 DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
1628 DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
1631 /* Enable SOC clock */
1632 clk_enable(ssp->clk);
1634 /* Load default SSP configuration */
1635 write_SSCR0(0, drv_data->ioaddr);
1636 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1637 SSCR1_TxTresh(TX_THRESH_DFLT),
1639 write_SSCR0(SSCR0_SCR(2)
1641 | SSCR0_DataSize(8),
1643 if (!pxa25x_ssp_comp(drv_data))
1644 write_SSTO(0, drv_data->ioaddr);
1645 write_SSPSP(0, drv_data->ioaddr);
1647 /* Initial and start queue */
1648 status = init_queue(drv_data);
1650 dev_err(&pdev->dev, "problem initializing queue\n");
1651 goto out_error_clock_enabled;
1653 status = start_queue(drv_data);
1655 dev_err(&pdev->dev, "problem starting queue\n");
1656 goto out_error_clock_enabled;
1659 /* Register with the SPI framework */
1660 platform_set_drvdata(pdev, drv_data);
1661 status = spi_register_master(master);
1663 dev_err(&pdev->dev, "problem registering spi master\n");
1664 goto out_error_queue_alloc;
1669 out_error_queue_alloc:
1670 destroy_queue(drv_data);
1672 out_error_clock_enabled:
1673 clk_disable(ssp->clk);
1675 out_error_dma_alloc:
1676 if (drv_data->tx_channel != -1)
1677 pxa_free_dma(drv_data->tx_channel);
1678 if (drv_data->rx_channel != -1)
1679 pxa_free_dma(drv_data->rx_channel);
1681 out_error_irq_alloc:
1682 free_irq(ssp->irq, drv_data);
1684 out_error_master_alloc:
1685 spi_master_put(master);
1690 static int pxa2xx_spi_remove(struct platform_device *pdev)
1692 struct driver_data *drv_data = platform_get_drvdata(pdev);
1693 struct ssp_device *ssp;
1698 ssp = drv_data->ssp;
1700 /* Remove the queue */
1701 status = destroy_queue(drv_data);
1703 /* the kernel does not check the return status of this
1704 * this routine (mod->exit, within the kernel). Therefore
1705 * nothing is gained by returning from here, the module is
1706 * going away regardless, and we should not leave any more
1707 * resources allocated than necessary. We cannot free the
1708 * message memory in drv_data->queue, but we can release the
1709 * resources below. I think the kernel should honor -EBUSY
1711 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1712 "complete, message memory not freed\n");
1714 /* Disable the SSP at the peripheral and SOC level */
1715 write_SSCR0(0, drv_data->ioaddr);
1716 clk_disable(ssp->clk);
1719 if (drv_data->master_info->enable_dma) {
1720 DRCMR(ssp->drcmr_rx) = 0;
1721 DRCMR(ssp->drcmr_tx) = 0;
1722 pxa_free_dma(drv_data->tx_channel);
1723 pxa_free_dma(drv_data->rx_channel);
1727 free_irq(ssp->irq, drv_data);
1732 /* Disconnect from the SPI framework */
1733 spi_unregister_master(drv_data->master);
1735 /* Prevent double remove */
1736 platform_set_drvdata(pdev, NULL);
1741 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1745 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1746 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1750 static int pxa2xx_spi_suspend(struct device *dev)
1752 struct driver_data *drv_data = dev_get_drvdata(dev);
1753 struct ssp_device *ssp = drv_data->ssp;
1756 status = stop_queue(drv_data);
1759 write_SSCR0(0, drv_data->ioaddr);
1760 clk_disable(ssp->clk);
1765 static int pxa2xx_spi_resume(struct device *dev)
1767 struct driver_data *drv_data = dev_get_drvdata(dev);
1768 struct ssp_device *ssp = drv_data->ssp;
1771 if (drv_data->rx_channel != -1)
1772 DRCMR(drv_data->ssp->drcmr_rx) =
1773 DRCMR_MAPVLD | drv_data->rx_channel;
1774 if (drv_data->tx_channel != -1)
1775 DRCMR(drv_data->ssp->drcmr_tx) =
1776 DRCMR_MAPVLD | drv_data->tx_channel;
1778 /* Enable the SSP clock */
1779 clk_enable(ssp->clk);
1781 /* Start the queue running */
1782 status = start_queue(drv_data);
1784 dev_err(dev, "problem starting queue (%d)\n", status);
1791 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1792 .suspend = pxa2xx_spi_suspend,
1793 .resume = pxa2xx_spi_resume,
1797 static struct platform_driver driver = {
1799 .name = "pxa2xx-spi",
1800 .owner = THIS_MODULE,
1802 .pm = &pxa2xx_spi_pm_ops,
1805 .probe = pxa2xx_spi_probe,
1806 .remove = pxa2xx_spi_remove,
1807 .shutdown = pxa2xx_spi_shutdown,
1810 static int __init pxa2xx_spi_init(void)
1812 return platform_driver_register(&driver);
1814 subsys_initcall(pxa2xx_spi_init);
1816 static void __exit pxa2xx_spi_exit(void)
1818 platform_driver_unregister(&driver);
1820 module_exit(pxa2xx_spi_exit);