2 * IMG SPFI controller driver
4 * Copyright (C) 2007,2008,2013 Imagination Technologies Ltd.
5 * Copyright (C) 2014 Google, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dmaengine.h>
15 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/scatterlist.h>
23 #include <linux/slab.h>
24 #include <linux/spi/spi.h>
25 #include <linux/spinlock.h>
27 #define SPFI_DEVICE_PARAMETER(x) (0x00 + 0x4 * (x))
28 #define SPFI_DEVICE_PARAMETER_BITCLK_SHIFT 24
29 #define SPFI_DEVICE_PARAMETER_BITCLK_MASK 0xff
30 #define SPFI_DEVICE_PARAMETER_CSSETUP_SHIFT 16
31 #define SPFI_DEVICE_PARAMETER_CSSETUP_MASK 0xff
32 #define SPFI_DEVICE_PARAMETER_CSHOLD_SHIFT 8
33 #define SPFI_DEVICE_PARAMETER_CSHOLD_MASK 0xff
34 #define SPFI_DEVICE_PARAMETER_CSDELAY_SHIFT 0
35 #define SPFI_DEVICE_PARAMETER_CSDELAY_MASK 0xff
37 #define SPFI_CONTROL 0x14
38 #define SPFI_CONTROL_CONTINUE BIT(12)
39 #define SPFI_CONTROL_SOFT_RESET BIT(11)
40 #define SPFI_CONTROL_SEND_DMA BIT(10)
41 #define SPFI_CONTROL_GET_DMA BIT(9)
42 #define SPFI_CONTROL_TMODE_SHIFT 5
43 #define SPFI_CONTROL_TMODE_MASK 0x7
44 #define SPFI_CONTROL_TMODE_SINGLE 0
45 #define SPFI_CONTROL_TMODE_DUAL 1
46 #define SPFI_CONTROL_TMODE_QUAD 2
47 #define SPFI_CONTROL_SPFI_EN BIT(0)
49 #define SPFI_TRANSACTION 0x18
50 #define SPFI_TRANSACTION_TSIZE_SHIFT 16
51 #define SPFI_TRANSACTION_TSIZE_MASK 0xffff
53 #define SPFI_PORT_STATE 0x1c
54 #define SPFI_PORT_STATE_DEV_SEL_SHIFT 20
55 #define SPFI_PORT_STATE_DEV_SEL_MASK 0x7
56 #define SPFI_PORT_STATE_CK_POL(x) BIT(19 - (x))
57 #define SPFI_PORT_STATE_CK_PHASE(x) BIT(14 - (x))
59 #define SPFI_TX_32BIT_VALID_DATA 0x20
60 #define SPFI_TX_8BIT_VALID_DATA 0x24
61 #define SPFI_RX_32BIT_VALID_DATA 0x28
62 #define SPFI_RX_8BIT_VALID_DATA 0x2c
64 #define SPFI_INTERRUPT_STATUS 0x30
65 #define SPFI_INTERRUPT_ENABLE 0x34
66 #define SPFI_INTERRUPT_CLEAR 0x38
67 #define SPFI_INTERRUPT_IACCESS BIT(12)
68 #define SPFI_INTERRUPT_GDEX8BIT BIT(11)
69 #define SPFI_INTERRUPT_ALLDONETRIG BIT(9)
70 #define SPFI_INTERRUPT_GDFUL BIT(8)
71 #define SPFI_INTERRUPT_GDHF BIT(7)
72 #define SPFI_INTERRUPT_GDEX32BIT BIT(6)
73 #define SPFI_INTERRUPT_GDTRIG BIT(5)
74 #define SPFI_INTERRUPT_SDFUL BIT(3)
75 #define SPFI_INTERRUPT_SDHF BIT(2)
76 #define SPFI_INTERRUPT_SDE BIT(1)
77 #define SPFI_INTERRUPT_SDTRIG BIT(0)
80 * There are four parallel FIFOs of 16 bytes each. The word buffer
81 * (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an
82 * effective FIFO size of 64 bytes. The byte buffer (*_8BIT_VALID_DATA)
83 * accesses only a single FIFO, resulting in an effective FIFO size of
86 #define SPFI_32BIT_FIFO_SIZE 64
87 #define SPFI_8BIT_FIFO_SIZE 16
91 struct spi_master *master;
100 struct dma_chan *rx_ch;
101 struct dma_chan *tx_ch;
106 static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg)
108 return readl(spfi->regs + reg);
111 static inline void spfi_writel(struct img_spfi *spfi, u32 val, u32 reg)
113 writel(val, spfi->regs + reg);
116 static inline void spfi_start(struct img_spfi *spfi)
120 val = spfi_readl(spfi, SPFI_CONTROL);
121 val |= SPFI_CONTROL_SPFI_EN;
122 spfi_writel(spfi, val, SPFI_CONTROL);
125 static inline void spfi_stop(struct img_spfi *spfi)
129 val = spfi_readl(spfi, SPFI_CONTROL);
130 val &= ~SPFI_CONTROL_SPFI_EN;
131 spfi_writel(spfi, val, SPFI_CONTROL);
134 static inline void spfi_reset(struct img_spfi *spfi)
136 spfi_writel(spfi, SPFI_CONTROL_SOFT_RESET, SPFI_CONTROL);
137 spfi_writel(spfi, 0, SPFI_CONTROL);
140 static void spfi_flush_tx_fifo(struct img_spfi *spfi)
142 unsigned long timeout = jiffies + msecs_to_jiffies(10);
144 spfi_writel(spfi, SPFI_INTERRUPT_SDE, SPFI_INTERRUPT_CLEAR);
145 while (time_before(jiffies, timeout)) {
146 if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) &
152 dev_err(spfi->dev, "Timed out waiting for FIFO to drain\n");
156 static unsigned int spfi_pio_write32(struct img_spfi *spfi, const u32 *buf,
159 unsigned int count = 0;
162 while (count < max / 4) {
163 spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
164 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
165 if (status & SPFI_INTERRUPT_SDFUL)
167 spfi_writel(spfi, buf[count], SPFI_TX_32BIT_VALID_DATA);
174 static unsigned int spfi_pio_write8(struct img_spfi *spfi, const u8 *buf,
177 unsigned int count = 0;
180 while (count < max) {
181 spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
182 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
183 if (status & SPFI_INTERRUPT_SDFUL)
185 spfi_writel(spfi, buf[count], SPFI_TX_8BIT_VALID_DATA);
192 static unsigned int spfi_pio_read32(struct img_spfi *spfi, u32 *buf,
195 unsigned int count = 0;
198 while (count < max / 4) {
199 spfi_writel(spfi, SPFI_INTERRUPT_GDEX32BIT,
200 SPFI_INTERRUPT_CLEAR);
201 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
202 if (!(status & SPFI_INTERRUPT_GDEX32BIT))
204 buf[count] = spfi_readl(spfi, SPFI_RX_32BIT_VALID_DATA);
211 static unsigned int spfi_pio_read8(struct img_spfi *spfi, u8 *buf,
214 unsigned int count = 0;
217 while (count < max) {
218 spfi_writel(spfi, SPFI_INTERRUPT_GDEX8BIT,
219 SPFI_INTERRUPT_CLEAR);
220 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
221 if (!(status & SPFI_INTERRUPT_GDEX8BIT))
223 buf[count] = spfi_readl(spfi, SPFI_RX_8BIT_VALID_DATA);
230 static int img_spfi_start_pio(struct spi_master *master,
231 struct spi_device *spi,
232 struct spi_transfer *xfer)
234 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
235 unsigned int tx_bytes = 0, rx_bytes = 0;
236 const void *tx_buf = xfer->tx_buf;
237 void *rx_buf = xfer->rx_buf;
238 unsigned long timeout;
241 tx_bytes = xfer->len;
243 rx_bytes = xfer->len;
248 msecs_to_jiffies(xfer->len * 8 * 1000 / xfer->speed_hz + 100);
249 while ((tx_bytes > 0 || rx_bytes > 0) &&
250 time_before(jiffies, timeout)) {
251 unsigned int tx_count, rx_count;
254 tx_count = spfi_pio_write32(spfi, tx_buf, tx_bytes);
256 tx_count = spfi_pio_write8(spfi, tx_buf, tx_bytes);
259 rx_count = spfi_pio_read32(spfi, rx_buf, rx_bytes);
261 rx_count = spfi_pio_read8(spfi, rx_buf, rx_bytes);
265 tx_bytes -= tx_count;
266 rx_bytes -= rx_count;
271 if (rx_bytes > 0 || tx_bytes > 0) {
272 dev_err(spfi->dev, "PIO transfer timed out\n");
277 spfi_flush_tx_fifo(spfi);
283 static void img_spfi_dma_rx_cb(void *data)
285 struct img_spfi *spfi = data;
288 spin_lock_irqsave(&spfi->lock, flags);
290 spfi->rx_dma_busy = false;
291 if (!spfi->tx_dma_busy) {
293 spi_finalize_current_transfer(spfi->master);
296 spin_unlock_irqrestore(&spfi->lock, flags);
299 static void img_spfi_dma_tx_cb(void *data)
301 struct img_spfi *spfi = data;
304 spfi_flush_tx_fifo(spfi);
306 spin_lock_irqsave(&spfi->lock, flags);
308 spfi->tx_dma_busy = false;
309 if (!spfi->rx_dma_busy) {
311 spi_finalize_current_transfer(spfi->master);
314 spin_unlock_irqrestore(&spfi->lock, flags);
317 static int img_spfi_start_dma(struct spi_master *master,
318 struct spi_device *spi,
319 struct spi_transfer *xfer)
321 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
322 struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL;
323 struct dma_slave_config rxconf, txconf;
325 spfi->rx_dma_busy = false;
326 spfi->tx_dma_busy = false;
329 rxconf.direction = DMA_DEV_TO_MEM;
330 if (xfer->len % 4 == 0) {
331 rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA;
332 rxconf.src_addr_width = 4;
333 rxconf.src_maxburst = 4;
335 rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA;
336 rxconf.src_addr_width = 1;
337 rxconf.src_maxburst = 4;
339 dmaengine_slave_config(spfi->rx_ch, &rxconf);
341 rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl,
348 rxdesc->callback = img_spfi_dma_rx_cb;
349 rxdesc->callback_param = spfi;
353 txconf.direction = DMA_MEM_TO_DEV;
354 if (xfer->len % 4 == 0) {
355 txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA;
356 txconf.dst_addr_width = 4;
357 txconf.dst_maxburst = 4;
359 txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA;
360 txconf.dst_addr_width = 1;
361 txconf.dst_maxburst = 4;
363 dmaengine_slave_config(spfi->tx_ch, &txconf);
365 txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl,
372 txdesc->callback = img_spfi_dma_tx_cb;
373 txdesc->callback_param = spfi;
377 spfi->rx_dma_busy = true;
378 dmaengine_submit(rxdesc);
379 dma_async_issue_pending(spfi->rx_ch);
385 spfi->tx_dma_busy = true;
386 dmaengine_submit(txdesc);
387 dma_async_issue_pending(spfi->tx_ch);
393 dmaengine_terminate_all(spfi->rx_ch);
394 dmaengine_terminate_all(spfi->tx_ch);
398 static void img_spfi_handle_err(struct spi_master *master,
399 struct spi_message *msg)
401 struct img_spfi *spfi = spi_master_get_devdata(master);
405 * Stop all DMA and reset the controller if the previous transaction
406 * timed-out and never completed it's DMA.
408 spin_lock_irqsave(&spfi->lock, flags);
409 if (spfi->tx_dma_busy || spfi->rx_dma_busy) {
410 spfi->tx_dma_busy = false;
411 spfi->rx_dma_busy = false;
413 dmaengine_terminate_all(spfi->tx_ch);
414 dmaengine_terminate_all(spfi->rx_ch);
416 spin_unlock_irqrestore(&spfi->lock, flags);
421 static int img_spfi_prepare(struct spi_master *master, struct spi_message *msg)
423 struct img_spfi *spfi = spi_master_get_devdata(master);
426 val = spfi_readl(spfi, SPFI_PORT_STATE);
427 if (msg->spi->mode & SPI_CPHA)
428 val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
430 val &= ~SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
431 if (msg->spi->mode & SPI_CPOL)
432 val |= SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
434 val &= ~SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
435 spfi_writel(spfi, val, SPFI_PORT_STATE);
440 static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
441 struct spi_transfer *xfer)
443 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
447 * output = spfi_clk * (BITCLK / 512), where BITCLK must be a
448 * power of 2 up to 256 (where 255 == 256 since BITCLK is 8 bits)
450 div = DIV_ROUND_UP(master->max_speed_hz, xfer->speed_hz);
451 div = clamp(512 / (1 << get_count_order(div)), 1, 255);
453 val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select));
454 val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK <<
455 SPFI_DEVICE_PARAMETER_BITCLK_SHIFT);
456 val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;
457 spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));
459 spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,
462 val = spfi_readl(spfi, SPFI_CONTROL);
463 val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA);
465 val |= SPFI_CONTROL_SEND_DMA;
467 val |= SPFI_CONTROL_GET_DMA;
468 val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT);
469 if (xfer->tx_nbits == SPI_NBITS_DUAL &&
470 xfer->rx_nbits == SPI_NBITS_DUAL)
471 val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT;
472 else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
473 xfer->rx_nbits == SPI_NBITS_QUAD)
474 val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;
475 val &= ~SPFI_CONTROL_CONTINUE;
476 if (!xfer->cs_change && !list_is_last(&xfer->transfer_list,
477 &master->cur_msg->transfers))
478 val |= SPFI_CONTROL_CONTINUE;
479 spfi_writel(spfi, val, SPFI_CONTROL);
482 static int img_spfi_transfer_one(struct spi_master *master,
483 struct spi_device *spi,
484 struct spi_transfer *xfer)
486 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
489 if (xfer->len > SPFI_TRANSACTION_TSIZE_MASK) {
491 "Transfer length (%d) is greater than the max supported (%d)",
492 xfer->len, SPFI_TRANSACTION_TSIZE_MASK);
496 img_spfi_config(master, spi, xfer);
497 if (master->can_dma && master->can_dma(master, spi, xfer))
498 ret = img_spfi_start_dma(master, spi, xfer);
500 ret = img_spfi_start_pio(master, spi, xfer);
505 static void img_spfi_set_cs(struct spi_device *spi, bool enable)
507 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
510 val = spfi_readl(spfi, SPFI_PORT_STATE);
511 val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK << SPFI_PORT_STATE_DEV_SEL_SHIFT);
512 val |= spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT;
513 spfi_writel(spfi, val, SPFI_PORT_STATE);
516 static bool img_spfi_can_dma(struct spi_master *master, struct spi_device *spi,
517 struct spi_transfer *xfer)
519 if (xfer->len > SPFI_32BIT_FIFO_SIZE)
524 static irqreturn_t img_spfi_irq(int irq, void *dev_id)
526 struct img_spfi *spfi = (struct img_spfi *)dev_id;
529 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
530 if (status & SPFI_INTERRUPT_IACCESS) {
531 spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_CLEAR);
532 dev_err(spfi->dev, "Illegal access interrupt");
539 static int img_spfi_probe(struct platform_device *pdev)
541 struct spi_master *master;
542 struct img_spfi *spfi;
543 struct resource *res;
546 master = spi_alloc_master(&pdev->dev, sizeof(*spfi));
549 platform_set_drvdata(pdev, master);
551 spfi = spi_master_get_devdata(master);
552 spfi->dev = &pdev->dev;
553 spfi->master = master;
554 spin_lock_init(&spfi->lock);
556 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
557 spfi->regs = devm_ioremap_resource(spfi->dev, res);
558 if (IS_ERR(spfi->regs)) {
559 ret = PTR_ERR(spfi->regs);
562 spfi->phys = res->start;
564 spfi->irq = platform_get_irq(pdev, 0);
569 ret = devm_request_irq(spfi->dev, spfi->irq, img_spfi_irq,
570 IRQ_TYPE_LEVEL_HIGH, dev_name(spfi->dev), spfi);
574 spfi->sys_clk = devm_clk_get(spfi->dev, "sys");
575 if (IS_ERR(spfi->sys_clk)) {
576 ret = PTR_ERR(spfi->sys_clk);
579 spfi->spfi_clk = devm_clk_get(spfi->dev, "spfi");
580 if (IS_ERR(spfi->spfi_clk)) {
581 ret = PTR_ERR(spfi->spfi_clk);
585 ret = clk_prepare_enable(spfi->sys_clk);
588 ret = clk_prepare_enable(spfi->spfi_clk);
594 * Only enable the error (IACCESS) interrupt. In PIO mode we'll
595 * poll the status of the FIFOs.
597 spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_ENABLE);
599 master->auto_runtime_pm = true;
600 master->bus_num = pdev->id;
601 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_DUAL | SPI_RX_DUAL;
602 if (of_property_read_bool(spfi->dev->of_node, "img,supports-quad-mode"))
603 master->mode_bits |= SPI_TX_QUAD | SPI_RX_QUAD;
604 master->num_chipselect = 5;
605 master->dev.of_node = pdev->dev.of_node;
606 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8);
607 master->max_speed_hz = clk_get_rate(spfi->spfi_clk);
608 master->min_speed_hz = master->max_speed_hz / 512;
610 master->set_cs = img_spfi_set_cs;
611 master->transfer_one = img_spfi_transfer_one;
612 master->prepare_message = img_spfi_prepare;
613 master->handle_err = img_spfi_handle_err;
615 spfi->tx_ch = dma_request_slave_channel(spfi->dev, "tx");
616 spfi->rx_ch = dma_request_slave_channel(spfi->dev, "rx");
617 if (!spfi->tx_ch || !spfi->rx_ch) {
619 dma_release_channel(spfi->tx_ch);
621 dma_release_channel(spfi->rx_ch);
622 dev_warn(spfi->dev, "Failed to get DMA channels, falling back to PIO mode\n");
624 master->dma_tx = spfi->tx_ch;
625 master->dma_rx = spfi->rx_ch;
626 master->can_dma = img_spfi_can_dma;
629 pm_runtime_set_active(spfi->dev);
630 pm_runtime_enable(spfi->dev);
632 ret = devm_spi_register_master(spfi->dev, master);
639 pm_runtime_disable(spfi->dev);
641 dma_release_channel(spfi->rx_ch);
643 dma_release_channel(spfi->tx_ch);
644 clk_disable_unprepare(spfi->spfi_clk);
646 clk_disable_unprepare(spfi->sys_clk);
648 spi_master_put(master);
653 static int img_spfi_remove(struct platform_device *pdev)
655 struct spi_master *master = platform_get_drvdata(pdev);
656 struct img_spfi *spfi = spi_master_get_devdata(master);
659 dma_release_channel(spfi->tx_ch);
661 dma_release_channel(spfi->rx_ch);
663 pm_runtime_disable(spfi->dev);
664 if (!pm_runtime_status_suspended(spfi->dev)) {
665 clk_disable_unprepare(spfi->spfi_clk);
666 clk_disable_unprepare(spfi->sys_clk);
669 spi_master_put(master);
675 static int img_spfi_runtime_suspend(struct device *dev)
677 struct spi_master *master = dev_get_drvdata(dev);
678 struct img_spfi *spfi = spi_master_get_devdata(master);
680 clk_disable_unprepare(spfi->spfi_clk);
681 clk_disable_unprepare(spfi->sys_clk);
686 static int img_spfi_runtime_resume(struct device *dev)
688 struct spi_master *master = dev_get_drvdata(dev);
689 struct img_spfi *spfi = spi_master_get_devdata(master);
692 ret = clk_prepare_enable(spfi->sys_clk);
695 ret = clk_prepare_enable(spfi->spfi_clk);
697 clk_disable_unprepare(spfi->sys_clk);
703 #endif /* CONFIG_PM */
705 #ifdef CONFIG_PM_SLEEP
706 static int img_spfi_suspend(struct device *dev)
708 struct spi_master *master = dev_get_drvdata(dev);
710 return spi_master_suspend(master);
713 static int img_spfi_resume(struct device *dev)
715 struct spi_master *master = dev_get_drvdata(dev);
716 struct img_spfi *spfi = spi_master_get_devdata(master);
719 ret = pm_runtime_get_sync(dev);
725 return spi_master_resume(master);
727 #endif /* CONFIG_PM_SLEEP */
729 static const struct dev_pm_ops img_spfi_pm_ops = {
730 SET_RUNTIME_PM_OPS(img_spfi_runtime_suspend, img_spfi_runtime_resume,
732 SET_SYSTEM_SLEEP_PM_OPS(img_spfi_suspend, img_spfi_resume)
735 static const struct of_device_id img_spfi_of_match[] = {
736 { .compatible = "img,spfi", },
739 MODULE_DEVICE_TABLE(of, img_spfi_of_match);
741 static struct platform_driver img_spfi_driver = {
744 .pm = &img_spfi_pm_ops,
745 .of_match_table = of_match_ptr(img_spfi_of_match),
747 .probe = img_spfi_probe,
748 .remove = img_spfi_remove,
750 module_platform_driver(img_spfi_driver);
752 MODULE_DESCRIPTION("IMG SPFI controller driver");
753 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
754 MODULE_LICENSE("GPL v2");