2 * Designware SPI core controller driver (refer pxa2xx_spi.c)
4 * Copyright (c) 2009, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/highmem.h>
24 #include <linux/delay.h>
25 #include <linux/slab.h>
26 #include <linux/spi/spi.h>
30 #ifdef CONFIG_DEBUG_FS
31 #include <linux/debugfs.h>
34 #define START_STATE ((void *)0)
35 #define RUNNING_STATE ((void *)1)
36 #define DONE_STATE ((void *)2)
37 #define ERROR_STATE ((void *)-1)
39 #define QUEUE_RUNNING 0
40 #define QUEUE_STOPPED 1
42 #define MRST_SPI_DEASSERT 0
43 #define MRST_SPI_ASSERT 1
45 /* Slave spi_dev related */
48 u8 cs; /* chip select pin */
49 u8 n_bytes; /* current is a 1/2/4 byte op */
50 u8 tmode; /* TR/TO/RO/EEPROM */
51 u8 type; /* SPI/SSP/MicroWire */
53 u8 poll_mode; /* 1 means use poll mode */
60 u16 clk_div; /* baud rate divider */
61 u32 speed_hz; /* baud rate */
62 void (*cs_control)(u32 command);
65 #ifdef CONFIG_DEBUG_FS
66 static int spi_show_regs_open(struct inode *inode, struct file *file)
68 file->private_data = inode->i_private;
72 #define SPI_REGS_BUFSIZE 1024
73 static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
74 size_t count, loff_t *ppos)
81 dws = file->private_data;
83 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
87 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
88 "MRST SPI0 registers:\n");
89 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
90 "=================================\n");
91 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
92 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
93 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
94 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
95 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
96 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
97 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
98 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
99 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
100 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
101 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
102 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
103 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
104 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
105 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
106 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
107 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
108 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
109 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
110 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
111 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
112 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
113 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
114 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
115 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
116 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
117 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
118 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
119 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
120 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
121 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
122 "=================================\n");
124 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
129 static const struct file_operations mrst_spi_regs_ops = {
130 .owner = THIS_MODULE,
131 .open = spi_show_regs_open,
132 .read = spi_show_regs,
133 .llseek = default_llseek,
136 static int mrst_spi_debugfs_init(struct dw_spi *dws)
138 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
142 debugfs_create_file("registers", S_IFREG | S_IRUGO,
143 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
147 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
150 debugfs_remove_recursive(dws->debugfs);
154 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
159 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
162 #endif /* CONFIG_DEBUG_FS */
164 /* Return the max entries we can fill into tx fifo */
165 static inline u32 tx_max(struct dw_spi *dws)
167 u32 tx_left, tx_room, rxtx_gap;
169 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
170 tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);
173 * Another concern is about the tx/rx mismatch, we
174 * though to use (dws->fifo_len - rxflr - txflr) as
175 * one maximum value for tx, but it doesn't cover the
176 * data which is out of tx/rx fifo and inside the
177 * shift registers. So a control from sw point of
180 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
183 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
186 /* Return the max entries we should read out of rx fifo */
187 static inline u32 rx_max(struct dw_spi *dws)
189 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
191 return min(rx_left, (u32)dw_readw(dws, DW_SPI_RXFLR));
194 static void dw_writer(struct dw_spi *dws)
196 u32 max = tx_max(dws);
200 /* Set the tx word if the transfer's original "tx" is not null */
201 if (dws->tx_end - dws->len) {
202 if (dws->n_bytes == 1)
203 txw = *(u8 *)(dws->tx);
205 txw = *(u16 *)(dws->tx);
207 dw_writew(dws, DW_SPI_DR, txw);
208 dws->tx += dws->n_bytes;
212 static void dw_reader(struct dw_spi *dws)
214 u32 max = rx_max(dws);
218 rxw = dw_readw(dws, DW_SPI_DR);
219 /* Care rx only if the transfer's original "rx" is not null */
220 if (dws->rx_end - dws->len) {
221 if (dws->n_bytes == 1)
222 *(u8 *)(dws->rx) = rxw;
224 *(u16 *)(dws->rx) = rxw;
226 dws->rx += dws->n_bytes;
230 static void *next_transfer(struct dw_spi *dws)
232 struct spi_message *msg = dws->cur_msg;
233 struct spi_transfer *trans = dws->cur_transfer;
235 /* Move to next transfer */
236 if (trans->transfer_list.next != &msg->transfers) {
238 list_entry(trans->transfer_list.next,
241 return RUNNING_STATE;
247 * Note: first step is the protocol driver prepares
248 * a dma-capable memory, and this func just need translate
249 * the virt addr to physical
251 static int map_dma_buffers(struct dw_spi *dws)
253 if (!dws->cur_msg->is_dma_mapped
255 || !dws->cur_chip->enable_dma
259 if (dws->cur_transfer->tx_dma)
260 dws->tx_dma = dws->cur_transfer->tx_dma;
262 if (dws->cur_transfer->rx_dma)
263 dws->rx_dma = dws->cur_transfer->rx_dma;
268 /* Caller already set message->status; dma and pio irqs are blocked */
269 static void giveback(struct dw_spi *dws)
271 struct spi_transfer *last_transfer;
273 struct spi_message *msg;
275 spin_lock_irqsave(&dws->lock, flags);
278 dws->cur_transfer = NULL;
279 dws->prev_chip = dws->cur_chip;
280 dws->cur_chip = NULL;
282 queue_work(dws->workqueue, &dws->pump_messages);
283 spin_unlock_irqrestore(&dws->lock, flags);
285 last_transfer = list_entry(msg->transfers.prev,
289 if (!last_transfer->cs_change && dws->cs_control)
290 dws->cs_control(MRST_SPI_DEASSERT);
294 msg->complete(msg->context);
297 static void int_error_stop(struct dw_spi *dws, const char *msg)
300 spi_enable_chip(dws, 0);
302 dev_err(&dws->master->dev, "%s\n", msg);
303 dws->cur_msg->state = ERROR_STATE;
304 tasklet_schedule(&dws->pump_transfers);
307 void dw_spi_xfer_done(struct dw_spi *dws)
309 /* Update total byte transferred return count actual bytes read */
310 dws->cur_msg->actual_length += dws->len;
312 /* Move to next transfer */
313 dws->cur_msg->state = next_transfer(dws);
315 /* Handle end of message */
316 if (dws->cur_msg->state == DONE_STATE) {
317 dws->cur_msg->status = 0;
320 tasklet_schedule(&dws->pump_transfers);
322 EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
324 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
326 u16 irq_status = dw_readw(dws, DW_SPI_ISR);
329 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
330 dw_readw(dws, DW_SPI_TXOICR);
331 dw_readw(dws, DW_SPI_RXOICR);
332 dw_readw(dws, DW_SPI_RXUICR);
333 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
338 if (dws->rx_end == dws->rx) {
339 spi_mask_intr(dws, SPI_INT_TXEI);
340 dw_spi_xfer_done(dws);
343 if (irq_status & SPI_INT_TXEI) {
344 spi_mask_intr(dws, SPI_INT_TXEI);
346 /* Enable TX irq always, it will be disabled when RX finished */
347 spi_umask_intr(dws, SPI_INT_TXEI);
353 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
355 struct dw_spi *dws = dev_id;
356 u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
362 spi_mask_intr(dws, SPI_INT_TXEI);
366 return dws->transfer_handler(dws);
369 /* Must be called inside pump_transfers() */
370 static void poll_transfer(struct dw_spi *dws)
376 } while (dws->rx_end > dws->rx);
378 dw_spi_xfer_done(dws);
381 static void pump_transfers(unsigned long data)
383 struct dw_spi *dws = (struct dw_spi *)data;
384 struct spi_message *message = NULL;
385 struct spi_transfer *transfer = NULL;
386 struct spi_transfer *previous = NULL;
387 struct spi_device *spi = NULL;
388 struct chip_data *chip = NULL;
397 /* Get current state information */
398 message = dws->cur_msg;
399 transfer = dws->cur_transfer;
400 chip = dws->cur_chip;
403 if (message->state == ERROR_STATE) {
404 message->status = -EIO;
408 /* Handle end of message */
409 if (message->state == DONE_STATE) {
414 /* Delay if requested at end of transfer*/
415 if (message->state == RUNNING_STATE) {
416 previous = list_entry(transfer->transfer_list.prev,
419 if (previous->delay_usecs)
420 udelay(previous->delay_usecs);
423 dws->n_bytes = chip->n_bytes;
424 dws->dma_width = chip->dma_width;
425 dws->cs_control = chip->cs_control;
427 dws->rx_dma = transfer->rx_dma;
428 dws->tx_dma = transfer->tx_dma;
429 dws->tx = (void *)transfer->tx_buf;
430 dws->tx_end = dws->tx + transfer->len;
431 dws->rx = transfer->rx_buf;
432 dws->rx_end = dws->rx + transfer->len;
433 dws->cs_change = transfer->cs_change;
434 dws->len = dws->cur_transfer->len;
435 if (chip != dws->prev_chip)
440 /* Handle per transfer options for bpw and speed */
441 if (transfer->speed_hz) {
442 speed = chip->speed_hz;
444 if ((transfer->speed_hz != speed) || (!chip->clk_div)) {
445 speed = transfer->speed_hz;
446 if (speed > dws->max_freq) {
447 printk(KERN_ERR "MRST SPI0: unsupported"
448 "freq: %dHz\n", speed);
449 message->status = -EIO;
453 /* clk_div doesn't support odd number */
454 clk_div = dws->max_freq / speed;
455 clk_div = (clk_div + 1) & 0xfffe;
457 chip->speed_hz = speed;
458 chip->clk_div = clk_div;
461 if (transfer->bits_per_word) {
462 bits = transfer->bits_per_word;
467 dws->n_bytes = dws->dma_width = bits >> 3;
470 printk(KERN_ERR "MRST SPI0: unsupported bits:"
472 message->status = -EIO;
477 | (chip->type << SPI_FRF_OFFSET)
478 | (spi->mode << SPI_MODE_OFFSET)
479 | (chip->tmode << SPI_TMOD_OFFSET);
481 message->state = RUNNING_STATE;
484 * Adjust transfer mode if necessary. Requires platform dependent
485 * chipselect mechanism.
487 if (dws->cs_control) {
488 if (dws->rx && dws->tx)
489 chip->tmode = SPI_TMOD_TR;
491 chip->tmode = SPI_TMOD_RO;
493 chip->tmode = SPI_TMOD_TO;
495 cr0 &= ~SPI_TMOD_MASK;
496 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
499 /* Check if current transfer is a DMA transaction */
500 dws->dma_mapped = map_dma_buffers(dws);
504 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
506 if (!dws->dma_mapped && !chip->poll_mode) {
507 int templen = dws->len / dws->n_bytes;
508 txint_level = dws->fifo_len / 2;
509 txint_level = (templen > txint_level) ? txint_level : templen;
511 imask |= SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI;
512 dws->transfer_handler = interrupt_transfer;
516 * Reprogram registers only if
517 * 1. chip select changes
518 * 2. clk_div is changed
519 * 3. control value changes
521 if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) {
522 spi_enable_chip(dws, 0);
524 if (dw_readw(dws, DW_SPI_CTRL0) != cr0)
525 dw_writew(dws, DW_SPI_CTRL0, cr0);
527 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
528 spi_chip_sel(dws, spi->chip_select);
530 /* Set the interrupt mask, for poll mode just disable all int */
531 spi_mask_intr(dws, 0xff);
533 spi_umask_intr(dws, imask);
535 dw_writew(dws, DW_SPI_TXFLTR, txint_level);
537 spi_enable_chip(dws, 1);
539 dws->prev_chip = chip;
543 dws->dma_ops->dma_transfer(dws, cs_change);
555 static void pump_messages(struct work_struct *work)
558 container_of(work, struct dw_spi, pump_messages);
561 /* Lock queue and check for queue work */
562 spin_lock_irqsave(&dws->lock, flags);
563 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
565 spin_unlock_irqrestore(&dws->lock, flags);
569 /* Make sure we are not already running a message */
571 spin_unlock_irqrestore(&dws->lock, flags);
575 /* Extract head of queue */
576 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
577 list_del_init(&dws->cur_msg->queue);
579 /* Initial message state*/
580 dws->cur_msg->state = START_STATE;
581 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
584 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
586 /* Mark as busy and launch transfers */
587 tasklet_schedule(&dws->pump_transfers);
590 spin_unlock_irqrestore(&dws->lock, flags);
593 /* spi_device use this to queue in their spi_msg */
594 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
596 struct dw_spi *dws = spi_master_get_devdata(spi->master);
599 spin_lock_irqsave(&dws->lock, flags);
601 if (dws->run == QUEUE_STOPPED) {
602 spin_unlock_irqrestore(&dws->lock, flags);
606 msg->actual_length = 0;
607 msg->status = -EINPROGRESS;
608 msg->state = START_STATE;
610 list_add_tail(&msg->queue, &dws->queue);
612 if (dws->run == QUEUE_RUNNING && !dws->busy) {
614 if (dws->cur_transfer || dws->cur_msg)
615 queue_work(dws->workqueue,
616 &dws->pump_messages);
618 /* If no other data transaction in air, just go */
619 spin_unlock_irqrestore(&dws->lock, flags);
620 pump_messages(&dws->pump_messages);
625 spin_unlock_irqrestore(&dws->lock, flags);
629 /* This may be called twice for each spi dev */
630 static int dw_spi_setup(struct spi_device *spi)
632 struct dw_spi_chip *chip_info = NULL;
633 struct chip_data *chip;
635 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
638 /* Only alloc on first setup */
639 chip = spi_get_ctldata(spi);
641 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
647 * Protocol drivers may change the chip settings, so...
648 * if chip_info exists, use it
650 chip_info = spi->controller_data;
652 /* chip_info doesn't always exist */
654 if (chip_info->cs_control)
655 chip->cs_control = chip_info->cs_control;
657 chip->poll_mode = chip_info->poll_mode;
658 chip->type = chip_info->type;
660 chip->rx_threshold = 0;
661 chip->tx_threshold = 0;
663 chip->enable_dma = chip_info->enable_dma;
666 if (spi->bits_per_word <= 8) {
669 } else if (spi->bits_per_word <= 16) {
673 /* Never take >16b case for MRST SPIC */
674 dev_err(&spi->dev, "invalid wordsize\n");
677 chip->bits_per_word = spi->bits_per_word;
679 if (!spi->max_speed_hz) {
680 dev_err(&spi->dev, "No max speed HZ parameter\n");
684 chip->tmode = 0; /* Tx & Rx */
685 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
686 chip->cr0 = (chip->bits_per_word - 1)
687 | (chip->type << SPI_FRF_OFFSET)
688 | (spi->mode << SPI_MODE_OFFSET)
689 | (chip->tmode << SPI_TMOD_OFFSET);
691 spi_set_ctldata(spi, chip);
695 static void dw_spi_cleanup(struct spi_device *spi)
697 struct chip_data *chip = spi_get_ctldata(spi);
701 static int __devinit init_queue(struct dw_spi *dws)
703 INIT_LIST_HEAD(&dws->queue);
704 spin_lock_init(&dws->lock);
706 dws->run = QUEUE_STOPPED;
709 tasklet_init(&dws->pump_transfers,
710 pump_transfers, (unsigned long)dws);
712 INIT_WORK(&dws->pump_messages, pump_messages);
713 dws->workqueue = create_singlethread_workqueue(
714 dev_name(dws->master->dev.parent));
715 if (dws->workqueue == NULL)
721 static int start_queue(struct dw_spi *dws)
725 spin_lock_irqsave(&dws->lock, flags);
727 if (dws->run == QUEUE_RUNNING || dws->busy) {
728 spin_unlock_irqrestore(&dws->lock, flags);
732 dws->run = QUEUE_RUNNING;
734 dws->cur_transfer = NULL;
735 dws->cur_chip = NULL;
736 dws->prev_chip = NULL;
737 spin_unlock_irqrestore(&dws->lock, flags);
739 queue_work(dws->workqueue, &dws->pump_messages);
744 static int stop_queue(struct dw_spi *dws)
750 spin_lock_irqsave(&dws->lock, flags);
751 dws->run = QUEUE_STOPPED;
752 while ((!list_empty(&dws->queue) || dws->busy) && limit--) {
753 spin_unlock_irqrestore(&dws->lock, flags);
755 spin_lock_irqsave(&dws->lock, flags);
758 if (!list_empty(&dws->queue) || dws->busy)
760 spin_unlock_irqrestore(&dws->lock, flags);
765 static int destroy_queue(struct dw_spi *dws)
769 status = stop_queue(dws);
772 destroy_workqueue(dws->workqueue);
776 /* Restart the controller, disable all interrupts, clean rx fifo */
777 static void spi_hw_init(struct dw_spi *dws)
779 spi_enable_chip(dws, 0);
780 spi_mask_intr(dws, 0xff);
781 spi_enable_chip(dws, 1);
784 * Try to detect the FIFO depth if not set by interface driver,
785 * the depth could be from 2 to 256 from HW spec
787 if (!dws->fifo_len) {
789 for (fifo = 2; fifo <= 256; fifo++) {
790 dw_writew(dws, DW_SPI_TXFLTR, fifo);
791 if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
795 dws->fifo_len = (fifo == 2) ? 0 : fifo - 1;
796 dw_writew(dws, DW_SPI_TXFLTR, 0);
800 int __devinit dw_spi_add_host(struct dw_spi *dws)
802 struct spi_master *master;
807 master = spi_alloc_master(dws->parent_dev, 0);
813 dws->master = master;
814 dws->type = SSI_MOTO_SPI;
815 dws->prev_chip = NULL;
817 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
818 snprintf(dws->name, sizeof(dws->name), "dw_spi%d",
821 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
824 dev_err(&master->dev, "can not get IRQ\n");
825 goto err_free_master;
828 master->mode_bits = SPI_CPOL | SPI_CPHA;
829 master->bus_num = dws->bus_num;
830 master->num_chipselect = dws->num_cs;
831 master->cleanup = dw_spi_cleanup;
832 master->setup = dw_spi_setup;
833 master->transfer = dw_spi_transfer;
838 if (dws->dma_ops && dws->dma_ops->dma_init) {
839 ret = dws->dma_ops->dma_init(dws);
841 dev_warn(&master->dev, "DMA init failed\n");
846 /* Initial and start queue */
847 ret = init_queue(dws);
849 dev_err(&master->dev, "problem initializing queue\n");
852 ret = start_queue(dws);
854 dev_err(&master->dev, "problem starting queue\n");
858 spi_master_set_devdata(master, dws);
859 ret = spi_register_master(master);
861 dev_err(&master->dev, "problem registering spi master\n");
862 goto err_queue_alloc;
865 mrst_spi_debugfs_init(dws);
870 if (dws->dma_ops && dws->dma_ops->dma_exit)
871 dws->dma_ops->dma_exit(dws);
873 spi_enable_chip(dws, 0);
874 free_irq(dws->irq, dws);
876 spi_master_put(master);
880 EXPORT_SYMBOL_GPL(dw_spi_add_host);
882 void __devexit dw_spi_remove_host(struct dw_spi *dws)
888 mrst_spi_debugfs_remove(dws);
890 /* Remove the queue */
891 status = destroy_queue(dws);
893 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
894 "complete, message memory not freed\n");
896 if (dws->dma_ops && dws->dma_ops->dma_exit)
897 dws->dma_ops->dma_exit(dws);
898 spi_enable_chip(dws, 0);
901 free_irq(dws->irq, dws);
903 /* Disconnect from the SPI framework */
904 spi_unregister_master(dws->master);
906 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
908 int dw_spi_suspend_host(struct dw_spi *dws)
912 ret = stop_queue(dws);
915 spi_enable_chip(dws, 0);
919 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
921 int dw_spi_resume_host(struct dw_spi *dws)
926 ret = start_queue(dws);
928 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
931 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
933 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
934 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
935 MODULE_LICENSE("GPL v2");