drivers/spi/pxa2xx_spi.c

   1 /*
   2  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21 #include <linux/device.h>
  22 #include <linux/ioport.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/spi/spi.h>
  28 #include <linux/workqueue.h>
  29 #include <linux/errno.h>
  30 #include <linux/delay.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34 #include <asm/hardware.h>
  35 #include <asm/delay.h>
  36 #include <asm/dma.h>
  37
  38 #include <asm/arch/hardware.h>
  39 #include <asm/arch/pxa-regs.h>
  40 #include <asm/arch/pxa2xx_spi.h>
  41
  42 MODULE_AUTHOR("Stephen Street");
  43 MODULE_DESCRIPTION("PXA2xx SSP SPI Contoller");
  44 MODULE_LICENSE("GPL");
  45
  46 #define MAX_BUSES 3
  47
  48 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
  49 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
  50 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
  51
  52 #define DEFINE_SSP_REG(reg, off) \
  53 static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \
  54 static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); }
  55
  56 DEFINE_SSP_REG(SSCR0, 0x00)
  57 DEFINE_SSP_REG(SSCR1, 0x04)
  58 DEFINE_SSP_REG(SSSR, 0x08)
  59 DEFINE_SSP_REG(SSITR, 0x0c)
  60 DEFINE_SSP_REG(SSDR, 0x10)
  61 DEFINE_SSP_REG(SSTO, 0x28)
  62 DEFINE_SSP_REG(SSPSP, 0x2c)
  63
  64 #define START_STATE ((void*)0)
  65 #define RUNNING_STATE ((void*)1)
  66 #define DONE_STATE ((void*)2)
  67 #define ERROR_STATE ((void*)-1)
  68
  69 #define QUEUE_RUNNING 0
  70 #define QUEUE_STOPPED 1
  71
  72 struct driver_data {
  73         /* Driver model hookup */
  74         struct platform_device *pdev;
  75
  76         /* SPI framework hookup */
  77         enum pxa_ssp_type ssp_type;
  78         struct spi_master *master;
  79
  80         /* PXA hookup */
  81         struct pxa2xx_spi_master *master_info;
  82
  83         /* DMA setup stuff */
  84         int rx_channel;
  85         int tx_channel;
  86         u32 *null_dma_buf;
  87
  88         /* SSP register addresses */
  89         void *ioaddr;
  90         u32 ssdr_physical;
  91
  92         /* SSP masks*/
  93         u32 dma_cr1;
  94         u32 int_cr1;
  95         u32 clear_sr;
  96         u32 mask_sr;
  97
  98         /* Driver message queue */
  99         struct workqueue_struct *workqueue;
 100         struct work_struct pump_messages;
 101         spinlock_t lock;
 102         struct list_head queue;
 103         int busy;
 104         int run;
 105
 106         /* Message Transfer pump */
 107         struct tasklet_struct pump_transfers;
 108
 109         /* Current message transfer state info */
 110         struct spi_message* cur_msg;
 111         struct spi_transfer* cur_transfer;
 112         struct chip_data *cur_chip;
 113         size_t len;
 114         void *tx;
 115         void *tx_end;
 116         void *rx;
 117         void *rx_end;
 118         int dma_mapped;
 119         dma_addr_t rx_dma;
 120         dma_addr_t tx_dma;
 121         size_t rx_map_len;
 122         size_t tx_map_len;
 123         u8 n_bytes;
 124         u32 dma_width;
 125         int cs_change;
 126         void (*write)(struct driver_data *drv_data);
 127         void (*read)(struct driver_data *drv_data);
 128         irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
 129         void (*cs_control)(u32 command);
 130 };
 131
 132 struct chip_data {
 133         u32 cr0;
 134         u32 cr1;
 135         u32 to;
 136         u32 psp;
 137         u32 timeout;
 138         u8 n_bytes;
 139         u32 dma_width;
 140         u32 dma_burst_size;
 141         u32 threshold;
 142         u32 dma_threshold;
 143         u8 enable_dma;
 144         u8 bits_per_word;
 145         u32 speed_hz;
 146         void (*write)(struct driver_data *drv_data);
 147         void (*read)(struct driver_data *drv_data);
 148         void (*cs_control)(u32 command);
 149 };
 150
 151 static void pump_messages(void *data);
 152
 153 static int flush(struct driver_data *drv_data)
 154 {
 155         unsigned long limit = loops_per_jiffy << 1;
 156
 157         void *reg = drv_data->ioaddr;
 158
 159         do {
 160                 while (read_SSSR(reg) & SSSR_RNE) {
 161                         read_SSDR(reg);
 162                 }
 163         } while ((read_SSSR(reg) & SSSR_BSY) && limit--);
 164         write_SSSR(SSSR_ROR, reg);
 165
 166         return limit;
 167 }
 168
 169 static void restore_state(struct driver_data *drv_data)
 170 {
 171         void *reg = drv_data->ioaddr;
 172
 173         /* Clear status and disable clock */
 174         write_SSSR(drv_data->clear_sr, reg);
 175         write_SSCR0(drv_data->cur_chip->cr0 & ~SSCR0_SSE, reg);
 176
 177         /* Load the registers */
 178         write_SSCR1(drv_data->cur_chip->cr1, reg);
 179         write_SSCR0(drv_data->cur_chip->cr0, reg);
 180         if (drv_data->ssp_type != PXA25x_SSP) {
 181                 write_SSTO(0, reg);
 182                 write_SSPSP(drv_data->cur_chip->psp, reg);
 183         }
 184 }
 185
 186 static void null_cs_control(u32 command)
 187 {
 188 }
 189
 190 static void null_writer(struct driver_data *drv_data)
 191 {
 192         void *reg = drv_data->ioaddr;
 193         u8 n_bytes = drv_data->n_bytes;
 194
 195         while ((read_SSSR(reg) & SSSR_TNF)
 196                         && (drv_data->tx < drv_data->tx_end)) {
 197                 write_SSDR(0, reg);
 198                 drv_data->tx += n_bytes;
 199         }
 200 }
 201
 202 static void null_reader(struct driver_data *drv_data)
 203 {
 204         void *reg = drv_data->ioaddr;
 205         u8 n_bytes = drv_data->n_bytes;
 206
 207         while ((read_SSSR(reg) & SSSR_RNE)
 208                         && (drv_data->rx < drv_data->rx_end)) {
 209                 read_SSDR(reg);
 210                 drv_data->rx += n_bytes;
 211         }
 212 }
 213
 214 static void u8_writer(struct driver_data *drv_data)
 215 {
 216         void *reg = drv_data->ioaddr;
 217
 218         while ((read_SSSR(reg) & SSSR_TNF)
 219                         && (drv_data->tx < drv_data->tx_end)) {
 220                 write_SSDR(*(u8 *)(drv_data->tx), reg);
 221                 ++drv_data->tx;
 222         }
 223 }
 224
 225 static void u8_reader(struct driver_data *drv_data)
 226 {
 227         void *reg = drv_data->ioaddr;
 228
 229         while ((read_SSSR(reg) & SSSR_RNE)
 230                         && (drv_data->rx < drv_data->rx_end)) {
 231                 *(u8 *)(drv_data->rx) = read_SSDR(reg);
 232                 ++drv_data->rx;
 233         }
 234 }
 235
 236 static void u16_writer(struct driver_data *drv_data)
 237 {
 238         void *reg = drv_data->ioaddr;
 239
 240         while ((read_SSSR(reg) & SSSR_TNF)
 241                         && (drv_data->tx < drv_data->tx_end)) {
 242                 write_SSDR(*(u16 *)(drv_data->tx), reg);
 243                 drv_data->tx += 2;
 244         }
 245 }
 246
 247 static void u16_reader(struct driver_data *drv_data)
 248 {
 249         void *reg = drv_data->ioaddr;
 250
 251         while ((read_SSSR(reg) & SSSR_RNE)
 252                         && (drv_data->rx < drv_data->rx_end)) {
 253                 *(u16 *)(drv_data->rx) = read_SSDR(reg);
 254                 drv_data->rx += 2;
 255         }
 256 }
 257 static void u32_writer(struct driver_data *drv_data)
 258 {
 259         void *reg = drv_data->ioaddr;
 260
 261         while ((read_SSSR(reg) & SSSR_TNF)
 262                         && (drv_data->tx < drv_data->tx_end)) {
 263                 write_SSDR(*(u32 *)(drv_data->tx), reg);
 264                 drv_data->tx += 4;
 265         }
 266 }
 267
 268 static void u32_reader(struct driver_data *drv_data)
 269 {
 270         void *reg = drv_data->ioaddr;
 271
 272         while ((read_SSSR(reg) & SSSR_RNE)
 273                         && (drv_data->rx < drv_data->rx_end)) {
 274                 *(u32 *)(drv_data->rx) = read_SSDR(reg);
 275                 drv_data->rx += 4;
 276         }
 277 }
 278
 279 static void *next_transfer(struct driver_data *drv_data)
 280 {
 281         struct spi_message *msg = drv_data->cur_msg;
 282         struct spi_transfer *trans = drv_data->cur_transfer;
 283
 284         /* Move to next transfer */
 285         if (trans->transfer_list.next != &msg->transfers) {
 286                 drv_data->cur_transfer =
 287                         list_entry(trans->transfer_list.next,
 288                                         struct spi_transfer,
 289                                         transfer_list);
 290                 return RUNNING_STATE;
 291         } else
 292                 return DONE_STATE;
 293 }
 294
 295 static int map_dma_buffers(struct driver_data *drv_data)
 296 {
 297         struct spi_message *msg = drv_data->cur_msg;
 298         struct device *dev = &msg->spi->dev;
 299
 300         if (!drv_data->cur_chip->enable_dma)
 301                 return 0;
 302
 303         if (msg->is_dma_mapped)
 304                 return  drv_data->rx_dma && drv_data->tx_dma;
 305
 306         if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
 307                 return 0;
 308
 309         /* Modify setup if rx buffer is null */
 310         if (drv_data->rx == NULL) {
 311                 *drv_data->null_dma_buf = 0;
 312                 drv_data->rx = drv_data->null_dma_buf;
 313                 drv_data->rx_map_len = 4;
 314         } else
 315                 drv_data->rx_map_len = drv_data->len;
 316
 317
 318         /* Modify setup if tx buffer is null */
 319         if (drv_data->tx == NULL) {
 320                 *drv_data->null_dma_buf = 0;
 321                 drv_data->tx = drv_data->null_dma_buf;
 322                 drv_data->tx_map_len = 4;
 323         } else
 324                 drv_data->tx_map_len = drv_data->len;
 325
 326         /* Stream map the rx buffer */
 327         drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
 328                                                 drv_data->rx_map_len,
 329                                                 DMA_FROM_DEVICE);
 330         if (dma_mapping_error(drv_data->rx_dma))
 331                 return 0;
 332
 333         /* Stream map the tx buffer */
 334         drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
 335                                                 drv_data->tx_map_len,
 336                                                 DMA_TO_DEVICE);
 337
 338         if (dma_mapping_error(drv_data->tx_dma)) {
 339                 dma_unmap_single(dev, drv_data->rx_dma,
 340                                         drv_data->rx_map_len, DMA_FROM_DEVICE);
 341                 return 0;
 342         }
 343
 344         return 1;
 345 }
 346
 347 static void unmap_dma_buffers(struct driver_data *drv_data)
 348 {
 349         struct device *dev;
 350
 351         if (!drv_data->dma_mapped)
 352                 return;
 353
 354         if (!drv_data->cur_msg->is_dma_mapped) {
 355                 dev = &drv_data->cur_msg->spi->dev;
 356                 dma_unmap_single(dev, drv_data->rx_dma,
 357                                         drv_data->rx_map_len, DMA_FROM_DEVICE);
 358                 dma_unmap_single(dev, drv_data->tx_dma,
 359                                         drv_data->tx_map_len, DMA_TO_DEVICE);
 360         }
 361
 362         drv_data->dma_mapped = 0;
 363 }
 364
 365 /* caller already set message->status; dma and pio irqs are blocked */
 366 static void giveback(struct spi_message *message, struct driver_data *drv_data)
 367 {
 368         struct spi_transfer* last_transfer;
 369
 370         last_transfer = list_entry(message->transfers.prev,
 371                                         struct spi_transfer,
 372                                         transfer_list);
 373
 374         if (!last_transfer->cs_change)
 375                 drv_data->cs_control(PXA2XX_CS_DEASSERT);
 376
 377         message->state = NULL;
 378         if (message->complete)
 379                 message->complete(message->context);
 380
 381         drv_data->cur_msg = NULL;
 382         drv_data->cur_transfer = NULL;
 383         drv_data->cur_chip = NULL;
 384         queue_work(drv_data->workqueue, &drv_data->pump_messages);
 385 }
 386
 387 static int wait_ssp_rx_stall(void *ioaddr)
 388 {
 389         unsigned long limit = loops_per_jiffy << 1;
 390
 391         while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)
 392                 cpu_relax();
 393
 394         return limit;
 395 }
 396
 397 static int wait_dma_channel_stop(int channel)
 398 {
 399         unsigned long limit = loops_per_jiffy << 1;
 400
 401         while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)
 402                 cpu_relax();
 403
 404         return limit;
 405 }
 406
 407 static void dma_handler(int channel, void *data, struct pt_regs *regs)
 408 {
 409         struct driver_data *drv_data = data;
 410         struct spi_message *msg = drv_data->cur_msg;
 411         void *reg = drv_data->ioaddr;
 412         u32 irq_status = DCSR(channel) & DMA_INT_MASK;
 413         u32 trailing_sssr = 0;
 414
 415         if (irq_status & DCSR_BUSERR) {
 416
 417                 /* Disable interrupts, clear status and reset DMA */
 418                 if (drv_data->ssp_type != PXA25x_SSP)
 419                         write_SSTO(0, reg);
 420                 write_SSSR(drv_data->clear_sr, reg);
 421                 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
 422                 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 423                 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 424
 425                 if (flush(drv_data) == 0)
 426                         dev_err(&drv_data->pdev->dev,
 427                                         "dma_handler: flush fail\n");
 428
 429                 unmap_dma_buffers(drv_data);
 430
 431                 if (channel == drv_data->tx_channel)
 432                         dev_err(&drv_data->pdev->dev,
 433                                 "dma_handler: bad bus address on "
 434                                 "tx channel %d, source %x target = %x\n",
 435                                 channel, DSADR(channel), DTADR(channel));
 436                 else
 437                         dev_err(&drv_data->pdev->dev,
 438                                 "dma_handler: bad bus address on "
 439                                 "rx channel %d, source %x target = %x\n",
 440                                 channel, DSADR(channel), DTADR(channel));
 441
 442                 msg->state = ERROR_STATE;
 443                 tasklet_schedule(&drv_data->pump_transfers);
 444         }
 445
 446         /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
 447         if ((drv_data->ssp_type == PXA25x_SSP)
 448                 && (channel == drv_data->tx_channel)
 449                 && (irq_status & DCSR_ENDINTR)) {
 450
 451                 /* Wait for rx to stall */
 452                 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
 453                         dev_err(&drv_data->pdev->dev,
 454                                 "dma_handler: ssp rx stall failed\n");
 455
 456                 /* Clear and disable interrupts on SSP and DMA channels*/
 457                 write_SSSR(drv_data->clear_sr, reg);
 458                 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
 459                 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 460                 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 461                 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
 462                         dev_err(&drv_data->pdev->dev,
 463                                 "dma_handler: dma rx channel stop failed\n");
 464
 465                 unmap_dma_buffers(drv_data);
 466
 467                 /* Read trailing bytes */
 468                 /* Calculate number of trailing bytes, read them */
 469                 trailing_sssr = read_SSSR(reg);
 470                 if ((trailing_sssr & 0xf008) != 0xf000) {
 471                         drv_data->rx = drv_data->rx_end -
 472                                         (((trailing_sssr >> 12) & 0x0f) + 1);
 473                         drv_data->read(drv_data);
 474                 }
 475                 msg->actual_length += drv_data->len;
 476
 477                 /* Release chip select if requested, transfer delays are
 478                  * handled in pump_transfers */
 479                 if (drv_data->cs_change)
 480                         drv_data->cs_control(PXA2XX_CS_DEASSERT);
 481
 482                 /* Move to next transfer */
 483                 msg->state = next_transfer(drv_data);
 484
 485                 /* Schedule transfer tasklet */
 486                 tasklet_schedule(&drv_data->pump_transfers);
 487         }
 488 }
 489
 490 static irqreturn_t dma_transfer(struct driver_data *drv_data)
 491 {
 492         u32 irq_status;
 493         u32 trailing_sssr = 0;
 494         struct spi_message *msg = drv_data->cur_msg;
 495         void *reg = drv_data->ioaddr;
 496
 497         irq_status = read_SSSR(reg) & drv_data->mask_sr;
 498         if (irq_status & SSSR_ROR) {
 499                 /* Clear and disable interrupts on SSP and DMA channels*/
 500                 if (drv_data->ssp_type != PXA25x_SSP)
 501                         write_SSTO(0, reg);
 502                 write_SSSR(drv_data->clear_sr, reg);
 503                 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
 504                 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 505                 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 506                 unmap_dma_buffers(drv_data);
 507
 508                 if (flush(drv_data) == 0)
 509                         dev_err(&drv_data->pdev->dev,
 510                                         "dma_transfer: flush fail\n");
 511
 512                 dev_warn(&drv_data->pdev->dev, "dma_transfer: fifo overun\n");
 513
 514                 drv_data->cur_msg->state = ERROR_STATE;
 515                 tasklet_schedule(&drv_data->pump_transfers);
 516
 517                 return IRQ_HANDLED;
 518         }
 519
 520         /* Check for false positive timeout */
 521         if ((irq_status & SSSR_TINT) && DCSR(drv_data->tx_channel) & DCSR_RUN) {
 522                 write_SSSR(SSSR_TINT, reg);
 523                 return IRQ_HANDLED;
 524         }
 525
 526         if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
 527
 528                 /* Clear and disable interrupts on SSP and DMA channels*/
 529                 if (drv_data->ssp_type != PXA25x_SSP)
 530                         write_SSTO(0, reg);
 531                 write_SSSR(drv_data->clear_sr, reg);
 532                 write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
 533                 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 534                 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 535
 536                 if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
 537                         dev_err(&drv_data->pdev->dev,
 538                                 "dma_transfer: dma rx channel stop failed\n");
 539
 540                 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
 541                         dev_err(&drv_data->pdev->dev,
 542                                 "dma_transfer: ssp rx stall failed\n");
 543
 544                 unmap_dma_buffers(drv_data);
 545
 546                 /* Calculate number of trailing bytes, read them */
 547                 trailing_sssr = read_SSSR(reg);
 548                 if ((trailing_sssr & 0xf008) != 0xf000) {
 549                         drv_data->rx = drv_data->rx_end -
 550                                         (((trailing_sssr >> 12) & 0x0f) + 1);
 551                         drv_data->read(drv_data);
 552                 }
 553                 msg->actual_length += drv_data->len;
 554
 555                 /* Release chip select if requested, transfer delays are
 556                  * handled in pump_transfers */
 557                 if (drv_data->cs_change)
 558                         drv_data->cs_control(PXA2XX_CS_DEASSERT);
 559
 560                 /* Move to next transfer */
 561                 msg->state = next_transfer(drv_data);
 562
 563                 /* Schedule transfer tasklet */
 564                 tasklet_schedule(&drv_data->pump_transfers);
 565
 566                 return IRQ_HANDLED;
 567         }
 568
 569         /* Opps problem detected */
 570         return IRQ_NONE;
 571 }
 572
 573 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 574 {
 575         u32 irq_status;
 576         struct spi_message *msg = drv_data->cur_msg;
 577         void *reg = drv_data->ioaddr;
 578         irqreturn_t handled = IRQ_NONE;
 579         unsigned long limit = loops_per_jiffy << 1;
 580
 581         while ((irq_status = (read_SSSR(reg) & drv_data->mask_sr))) {
 582
 583                 if (irq_status & SSSR_ROR) {
 584
 585                         /* Clear and disable interrupts */
 586                         if (drv_data->ssp_type != PXA25x_SSP)
 587                                 write_SSTO(0, reg);
 588                         write_SSSR(drv_data->clear_sr, reg);
 589                         write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 590
 591                         if (flush(drv_data) == 0)
 592                                 dev_err(&drv_data->pdev->dev,
 593                                         "interrupt_transfer: flush fail\n");
 594
 595                         dev_warn(&drv_data->pdev->dev,
 596                                         "interrupt_transfer: fifo overun\n");
 597
 598                         msg->state = ERROR_STATE;
 599                         tasklet_schedule(&drv_data->pump_transfers);
 600
 601                         return IRQ_HANDLED;
 602                 }
 603
 604                 /* Look for false positive timeout */
 605                 if ((irq_status & SSSR_TINT)
 606                                 && (drv_data->rx < drv_data->rx_end))
 607                         write_SSSR(SSSR_TINT, reg);
 608
 609                 /* Pump data */
 610                 drv_data->read(drv_data);
 611                 drv_data->write(drv_data);
 612
 613                 if (drv_data->tx == drv_data->tx_end) {
 614                         /* Disable tx interrupt */
 615                         write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
 616
 617                         /* PXA25x_SSP has no timeout, read trailing bytes */
 618                         if (drv_data->ssp_type == PXA25x_SSP) {
 619                                 while ((read_SSSR(reg) & SSSR_BSY) && limit--)
 620                                         drv_data->read(drv_data);
 621
 622                                 if (limit == 0)
 623                                         dev_err(&drv_data->pdev->dev,
 624                                                 "interrupt_transfer: "
 625                                                 "trailing byte read failed\n");
 626                         }
 627                 }
 628
 629                 if ((irq_status & SSSR_TINT)
 630                                 || (drv_data->rx == drv_data->rx_end)) {
 631
 632                         /* Clear timeout */
 633                         if (drv_data->ssp_type != PXA25x_SSP)
 634                                 write_SSTO(0, reg);
 635                         write_SSSR(drv_data->clear_sr, reg);
 636                         write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 637
 638                         /* Update total byte transfered */
 639                         msg->actual_length += drv_data->len;
 640
 641                         /* Release chip select if requested, transfer delays are
 642                          * handled in pump_transfers */
 643                         if (drv_data->cs_change)
 644                                 drv_data->cs_control(PXA2XX_CS_DEASSERT);
 645
 646                         /* Move to next transfer */
 647                         msg->state = next_transfer(drv_data);
 648
 649                         /* Schedule transfer tasklet */
 650                         tasklet_schedule(&drv_data->pump_transfers);
 651
 652                         return IRQ_HANDLED;
 653                 }
 654
 655                 /* We did something */
 656                 handled = IRQ_HANDLED;
 657         }
 658
 659         return handled;
 660 }
 661
 662 static irqreturn_t ssp_int(int irq, void *dev_id, struct pt_regs *regs)
 663 {
 664         struct driver_data *drv_data = (struct driver_data *)dev_id;
 665
 666         if (!drv_data->cur_msg) {
 667                 dev_err(&drv_data->pdev->dev, "bad message state "
 668                                 "in interrupt handler\n");
 669                 /* Never fail */
 670                 return IRQ_HANDLED;
 671         }
 672
 673         return drv_data->transfer_handler(drv_data);
 674 }
 675
 676 static void pump_transfers(unsigned long data)
 677 {
 678         struct driver_data *drv_data = (struct driver_data *)data;
 679         struct spi_message *message = NULL;
 680         struct spi_transfer *transfer = NULL;
 681         struct spi_transfer *previous = NULL;
 682         struct chip_data *chip = NULL;
 683         void *reg = drv_data->ioaddr;
 684         u32 clk_div = 0;
 685         u8 bits = 0;
 686         u32 speed = 0;
 687         u32 cr0;
 688
 689         /* Get current state information */
 690         message = drv_data->cur_msg;
 691         transfer = drv_data->cur_transfer;
 692         chip = drv_data->cur_chip;
 693
 694         /* Handle for abort */
 695         if (message->state == ERROR_STATE) {
 696                 message->status = -EIO;
 697                 giveback(message, drv_data);
 698                 return;
 699         }
 700
 701         /* Handle end of message */
 702         if (message->state == DONE_STATE) {
 703                 message->status = 0;
 704                 giveback(message, drv_data);
 705                 return;
 706         }
 707
 708         /* Delay if requested at end of transfer*/
 709         if (message->state == RUNNING_STATE) {
 710                 previous = list_entry(transfer->transfer_list.prev,
 711                                         struct spi_transfer,
 712                                         transfer_list);
 713                 if (previous->delay_usecs)
 714                         udelay(previous->delay_usecs);
 715         }
 716
 717         /* Setup the transfer state based on the type of transfer */
 718         if (flush(drv_data) == 0) {
 719                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
 720                 message->status = -EIO;
 721                 giveback(message, drv_data);
 722                 return;
 723         }
 724         drv_data->n_bytes = chip->n_bytes;
 725         drv_data->dma_width = chip->dma_width;
 726         drv_data->cs_control = chip->cs_control;
 727         drv_data->tx = (void *)transfer->tx_buf;
 728         drv_data->tx_end = drv_data->tx + transfer->len;
 729         drv_data->rx = transfer->rx_buf;
 730         drv_data->rx_end = drv_data->rx + transfer->len;
 731         drv_data->rx_dma = transfer->rx_dma;
 732         drv_data->tx_dma = transfer->tx_dma;
 733         drv_data->len = transfer->len;
 734         drv_data->write = drv_data->tx ? chip->write : null_writer;
 735         drv_data->read = drv_data->rx ? chip->read : null_reader;
 736         drv_data->cs_change = transfer->cs_change;
 737
 738         /* Change speed and bit per word on a per transfer */
 739         if (transfer->speed_hz || transfer->bits_per_word) {
 740
 741                 /* Disable clock */
 742                 write_SSCR0(chip->cr0 & ~SSCR0_SSE, reg);
 743                 cr0 = chip->cr0;
 744                 bits = chip->bits_per_word;
 745                 speed = chip->speed_hz;
 746
 747                 if (transfer->speed_hz)
 748                         speed = transfer->speed_hz;
 749
 750                 if (transfer->bits_per_word)
 751                         bits = transfer->bits_per_word;
 752
 753                 if (reg == SSP1_VIRT)
 754                         clk_div = SSP1_SerClkDiv(speed);
 755                 else if (reg == SSP2_VIRT)
 756                         clk_div = SSP2_SerClkDiv(speed);
 757                 else if (reg == SSP3_VIRT)
 758                         clk_div = SSP3_SerClkDiv(speed);
 759
 760                 if (bits <= 8) {
 761                         drv_data->n_bytes = 1;
 762                         drv_data->dma_width = DCMD_WIDTH1;
 763                         drv_data->read = drv_data->read != null_reader ?
 764                                                 u8_reader : null_reader;
 765                         drv_data->write = drv_data->write != null_writer ?
 766                                                 u8_writer : null_writer;
 767                 } else if (bits <= 16) {
 768                         drv_data->n_bytes = 2;
 769                         drv_data->dma_width = DCMD_WIDTH2;
 770                         drv_data->read = drv_data->read != null_reader ?
 771                                                 u16_reader : null_reader;
 772                         drv_data->write = drv_data->write != null_writer ?
 773                                                 u16_writer : null_writer;
 774                 } else if (bits <= 32) {
 775                         drv_data->n_bytes = 4;
 776                         drv_data->dma_width = DCMD_WIDTH4;
 777                         drv_data->read = drv_data->read != null_reader ?
 778                                                 u32_reader : null_reader;
 779                         drv_data->write = drv_data->write != null_writer ?
 780                                                 u32_writer : null_writer;
 781                 }
 782
 783                 cr0 = clk_div
 784                         | SSCR0_Motorola
 785                         | SSCR0_DataSize(bits & 0x0f)
 786                         | SSCR0_SSE
 787                         | (bits > 16 ? SSCR0_EDSS : 0);
 788
 789                 /* Start it back up */
 790                 write_SSCR0(cr0, reg);
 791         }
 792
 793         message->state = RUNNING_STATE;
 794
 795         /* Try to map dma buffer and do a dma transfer if successful */
 796         if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) {
 797
 798                 /* Ensure we have the correct interrupt handler */
 799                 drv_data->transfer_handler = dma_transfer;
 800
 801                 /* Setup rx DMA Channel */
 802                 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 803                 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
 804                 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
 805                 if (drv_data->rx == drv_data->null_dma_buf)
 806                         /* No target address increment */
 807                         DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
 808                                                         | drv_data->dma_width
 809                                                         | chip->dma_burst_size
 810                                                         | drv_data->len;
 811                 else
 812                         DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
 813                                                         | DCMD_FLOWSRC
 814                                                         | drv_data->dma_width
 815                                                         | chip->dma_burst_size
 816                                                         | drv_data->len;
 817
 818                 /* Setup tx DMA Channel */
 819                 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 820                 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
 821                 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
 822                 if (drv_data->tx == drv_data->null_dma_buf)
 823                         /* No source address increment */
 824                         DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
 825                                                         | drv_data->dma_width
 826                                                         | chip->dma_burst_size
 827                                                         | drv_data->len;
 828                 else
 829                         DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
 830                                                         | DCMD_FLOWTRG
 831                                                         | drv_data->dma_width
 832                                                         | chip->dma_burst_size
 833                                                         | drv_data->len;
 834
 835                 /* Enable dma end irqs on SSP to detect end of transfer */
 836                 if (drv_data->ssp_type == PXA25x_SSP)
 837                         DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
 838
 839                 /* Fix me, need to handle cs polarity */
 840                 drv_data->cs_control(PXA2XX_CS_ASSERT);
 841
 842                 /* Go baby, go */
 843                 write_SSSR(drv_data->clear_sr, reg);
 844                 DCSR(drv_data->rx_channel) |= DCSR_RUN;
 845                 DCSR(drv_data->tx_channel) |= DCSR_RUN;
 846                 if (drv_data->ssp_type != PXA25x_SSP)
 847                         write_SSTO(chip->timeout, reg);
 848                 write_SSCR1(chip->cr1
 849                                 | chip->dma_threshold
 850                                 | drv_data->dma_cr1,
 851                                 reg);
 852         } else {
 853                 /* Ensure we have the correct interrupt handler */
 854                 drv_data->transfer_handler = interrupt_transfer;
 855
 856                 /* Fix me, need to handle cs polarity */
 857                 drv_data->cs_control(PXA2XX_CS_ASSERT);
 858
 859                 /* Go baby, go */
 860                 write_SSSR(drv_data->clear_sr, reg);
 861                 if (drv_data->ssp_type != PXA25x_SSP)
 862                         write_SSTO(chip->timeout, reg);
 863                 write_SSCR1(chip->cr1
 864                                 | chip->threshold
 865                                 | drv_data->int_cr1,
 866                                 reg);
 867         }
 868 }
 869
 870 static void pump_messages(void *data)
 871 {
 872         struct driver_data *drv_data = data;
 873         unsigned long flags;
 874
 875         /* Lock queue and check for queue work */
 876         spin_lock_irqsave(&drv_data->lock, flags);
 877         if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
 878                 drv_data->busy = 0;
 879                 spin_unlock_irqrestore(&drv_data->lock, flags);
 880                 return;
 881         }
 882
 883         /* Make sure we are not already running a message */
 884         if (drv_data->cur_msg) {
 885                 spin_unlock_irqrestore(&drv_data->lock, flags);
 886                 return;
 887         }
 888
 889         /* Extract head of queue */
 890         drv_data->cur_msg = list_entry(drv_data->queue.next,
 891                                         struct spi_message, queue);
 892         list_del_init(&drv_data->cur_msg->queue);
 893         drv_data->busy = 1;
 894         spin_unlock_irqrestore(&drv_data->lock, flags);
 895
 896         /* Initial message state*/
 897         drv_data->cur_msg->state = START_STATE;
 898         drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
 899                                                 struct spi_transfer,
 900                                                 transfer_list);
 901
 902         /* Setup the SSP using the per chip configuration */
 903         drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
 904         restore_state(drv_data);
 905
 906         /* Mark as busy and launch transfers */
 907         tasklet_schedule(&drv_data->pump_transfers);
 908 }
 909
 910 static int transfer(struct spi_device *spi, struct spi_message *msg)
 911 {
 912         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 913         unsigned long flags;
 914
 915         spin_lock_irqsave(&drv_data->lock, flags);
 916
 917         if (drv_data->run == QUEUE_STOPPED) {
 918                 spin_unlock_irqrestore(&drv_data->lock, flags);
 919                 return -ESHUTDOWN;
 920         }
 921
 922         msg->actual_length = 0;
 923         msg->status = -EINPROGRESS;
 924         msg->state = START_STATE;
 925
 926         list_add_tail(&msg->queue, &drv_data->queue);
 927
 928         if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
 929                 queue_work(drv_data->workqueue, &drv_data->pump_messages);
 930
 931         spin_unlock_irqrestore(&drv_data->lock, flags);
 932
 933         return 0;
 934 }
 935
 936 static int setup(struct spi_device *spi)
 937 {
 938         struct pxa2xx_spi_chip *chip_info = NULL;
 939         struct chip_data *chip;
 940         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 941         unsigned int clk_div;
 942
 943         if (!spi->bits_per_word)
 944                 spi->bits_per_word = 8;
 945
 946         if (drv_data->ssp_type != PXA25x_SSP
 947                         && (spi->bits_per_word < 4 || spi->bits_per_word > 32))
 948                 return -EINVAL;
 949         else if (spi->bits_per_word < 4 || spi->bits_per_word > 16)
 950                 return -EINVAL;
 951
 952         /* Only alloc (or use chip_info) on first setup */
 953         chip = spi_get_ctldata(spi);
 954         if (chip == NULL) {
 955                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 956                 if (!chip)
 957                         return -ENOMEM;
 958
 959                 chip->cs_control = null_cs_control;
 960                 chip->enable_dma = 0;
 961                 chip->timeout = 5;
 962                 chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
 963                 chip->dma_burst_size = drv_data->master_info->enable_dma ?
 964                                         DCMD_BURST8 : 0;
 965
 966                 chip_info = spi->controller_data;
 967         }
 968
 969         /* chip_info isn't always needed */
 970         if (chip_info) {
 971                 if (chip_info->cs_control)
 972                         chip->cs_control = chip_info->cs_control;
 973
 974                 chip->timeout = (chip_info->timeout_microsecs * 10000) / 2712;
 975
 976                 chip->threshold = SSCR1_RxTresh(chip_info->rx_threshold)
 977                                         | SSCR1_TxTresh(chip_info->tx_threshold);
 978
 979                 chip->enable_dma = chip_info->dma_burst_size != 0
 980                                         && drv_data->master_info->enable_dma;
 981                 chip->dma_threshold = 0;
 982
 983                 if (chip->enable_dma) {
 984                         if (chip_info->dma_burst_size <= 8) {
 985                                 chip->dma_threshold = SSCR1_RxTresh(8)
 986                                                         | SSCR1_TxTresh(8);
 987                                 chip->dma_burst_size = DCMD_BURST8;
 988                         } else if (chip_info->dma_burst_size <= 16) {
 989                                 chip->dma_threshold = SSCR1_RxTresh(16)
 990                                                         | SSCR1_TxTresh(16);
 991                                 chip->dma_burst_size = DCMD_BURST16;
 992                         } else {
 993                                 chip->dma_threshold = SSCR1_RxTresh(32)
 994                                                         | SSCR1_TxTresh(32);
 995                                 chip->dma_burst_size = DCMD_BURST32;
 996                         }
 997                 }
 998
 999
1000                 if (chip_info->enable_loopback)
1001                         chip->cr1 = SSCR1_LBM;
1002         }
1003
1004         if (drv_data->ioaddr == SSP1_VIRT)
1005                 clk_div = SSP1_SerClkDiv(spi->max_speed_hz);
1006         else if (drv_data->ioaddr == SSP2_VIRT)
1007                 clk_div = SSP2_SerClkDiv(spi->max_speed_hz);
1008         else if (drv_data->ioaddr == SSP3_VIRT)
1009                 clk_div = SSP3_SerClkDiv(spi->max_speed_hz);
1010         else
1011                 return -ENODEV;
1012         chip->speed_hz = spi->max_speed_hz;
1013
1014         chip->cr0 = clk_div
1015                         | SSCR0_Motorola
1016                         | SSCR0_DataSize(spi->bits_per_word & 0x0f)
1017                         | SSCR0_SSE
1018                         | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1019         chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) << 4)
1020                         | (((spi->mode & SPI_CPOL) != 0) << 3);
1021
1022         /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1023         if (drv_data->ssp_type != PXA25x_SSP)
1024                 dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",
1025                                 spi->bits_per_word,
1026                                 (CLOCK_SPEED_HZ)
1027                                         / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1028                                 spi->mode & 0x3);
1029         else
1030                 dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",
1031                                 spi->bits_per_word,
1032                                 (CLOCK_SPEED_HZ/2)
1033                                         / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1034                                 spi->mode & 0x3);
1035
1036         if (spi->bits_per_word <= 8) {
1037                 chip->n_bytes = 1;
1038                 chip->dma_width = DCMD_WIDTH1;
1039                 chip->read = u8_reader;
1040                 chip->write = u8_writer;
1041         } else if (spi->bits_per_word <= 16) {
1042                 chip->n_bytes = 2;
1043                 chip->dma_width = DCMD_WIDTH2;
1044                 chip->read = u16_reader;
1045                 chip->write = u16_writer;
1046         } else if (spi->bits_per_word <= 32) {
1047                 chip->cr0 |= SSCR0_EDSS;
1048                 chip->n_bytes = 4;
1049                 chip->dma_width = DCMD_WIDTH4;
1050                 chip->read = u32_reader;
1051                 chip->write = u32_writer;
1052         } else {
1053                 dev_err(&spi->dev, "invalid wordsize\n");
1054                 kfree(chip);
1055                 return -ENODEV;
1056         }
1057         chip->bits_per_word = spi->bits_per_word;
1058
1059         spi_set_ctldata(spi, chip);
1060
1061         return 0;
1062 }
1063
1064 static void cleanup(const struct spi_device *spi)
1065 {
1066         struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
1067
1068         kfree(chip);
1069 }
1070
1071 static int init_queue(struct driver_data *drv_data)
1072 {
1073         INIT_LIST_HEAD(&drv_data->queue);
1074         spin_lock_init(&drv_data->lock);
1075
1076         drv_data->run = QUEUE_STOPPED;
1077         drv_data->busy = 0;
1078
1079         tasklet_init(&drv_data->pump_transfers,
1080                         pump_transfers, (unsigned long)drv_data);
1081
1082         INIT_WORK(&drv_data->pump_messages, pump_messages, drv_data);
1083         drv_data->workqueue = create_singlethread_workqueue(
1084                                         drv_data->master->cdev.dev->bus_id);
1085         if (drv_data->workqueue == NULL)
1086                 return -EBUSY;
1087
1088         return 0;
1089 }
1090
1091 static int start_queue(struct driver_data *drv_data)
1092 {
1093         unsigned long flags;
1094
1095         spin_lock_irqsave(&drv_data->lock, flags);
1096
1097         if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1098                 spin_unlock_irqrestore(&drv_data->lock, flags);
1099                 return -EBUSY;
1100         }
1101
1102         drv_data->run = QUEUE_RUNNING;
1103         drv_data->cur_msg = NULL;
1104         drv_data->cur_transfer = NULL;
1105         drv_data->cur_chip = NULL;
1106         spin_unlock_irqrestore(&drv_data->lock, flags);
1107
1108         queue_work(drv_data->workqueue, &drv_data->pump_messages);
1109
1110         return 0;
1111 }
1112
1113 static int stop_queue(struct driver_data *drv_data)
1114 {
1115         unsigned long flags;
1116         unsigned limit = 500;
1117         int status = 0;
1118
1119         spin_lock_irqsave(&drv_data->lock, flags);
1120
1121         /* This is a bit lame, but is optimized for the common execution path.
1122          * A wait_queue on the drv_data->busy could be used, but then the common
1123          * execution path (pump_messages) would be required to call wake_up or
1124          * friends on every SPI message. Do this instead */
1125         drv_data->run = QUEUE_STOPPED;
1126         while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1127                 spin_unlock_irqrestore(&drv_data->lock, flags);
1128                 msleep(10);
1129                 spin_lock_irqsave(&drv_data->lock, flags);
1130         }
1131
1132         if (!list_empty(&drv_data->queue) || drv_data->busy)
1133                 status = -EBUSY;
1134
1135         spin_unlock_irqrestore(&drv_data->lock, flags);
1136
1137         return status;
1138 }
1139
1140 static int destroy_queue(struct driver_data *drv_data)
1141 {
1142         int status;
1143
1144         status = stop_queue(drv_data);
1145         if (status != 0)
1146                 return status;
1147
1148         destroy_workqueue(drv_data->workqueue);
1149
1150         return 0;
1151 }
1152
1153 static int pxa2xx_spi_probe(struct platform_device *pdev)
1154 {
1155         struct device *dev = &pdev->dev;
1156         struct pxa2xx_spi_master *platform_info;
1157         struct spi_master *master;
1158         struct driver_data *drv_data = 0;
1159         struct resource *memory_resource;
1160         int irq;
1161         int status = 0;
1162
1163         platform_info = dev->platform_data;
1164
1165         if (platform_info->ssp_type == SSP_UNDEFINED) {
1166                 dev_err(&pdev->dev, "undefined SSP\n");
1167                 return -ENODEV;
1168         }
1169
1170         /* Allocate master with space for drv_data and null dma buffer */
1171         master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1172         if (!master) {
1173                 dev_err(&pdev->dev, "can not alloc spi_master\n");
1174                 return -ENOMEM;
1175         }
1176         drv_data = spi_master_get_devdata(master);
1177         drv_data->master = master;
1178         drv_data->master_info = platform_info;
1179         drv_data->pdev = pdev;
1180
1181         master->bus_num = pdev->id;
1182         master->num_chipselect = platform_info->num_chipselect;
1183         master->cleanup = cleanup;
1184         master->setup = setup;
1185         master->transfer = transfer;
1186
1187         drv_data->ssp_type = platform_info->ssp_type;
1188         drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1189                                                 sizeof(struct driver_data)), 8);
1190
1191         /* Setup register addresses */
1192         memory_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1193         if (!memory_resource) {
1194                 dev_err(&pdev->dev, "memory resources not defined\n");
1195                 status = -ENODEV;
1196                 goto out_error_master_alloc;
1197         }
1198
1199         drv_data->ioaddr = (void *)io_p2v(memory_resource->start);
1200         drv_data->ssdr_physical = memory_resource->start + 0x00000010;
1201         if (platform_info->ssp_type == PXA25x_SSP) {
1202                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1203                 drv_data->dma_cr1 = 0;
1204                 drv_data->clear_sr = SSSR_ROR;
1205                 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1206         } else {
1207                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1208                 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1209                 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1210                 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1211         }
1212
1213         /* Attach to IRQ */
1214         irq = platform_get_irq(pdev, 0);
1215         if (irq < 0) {
1216                 dev_err(&pdev->dev, "irq resource not defined\n");
1217                 status = -ENODEV;
1218                 goto out_error_master_alloc;
1219         }
1220
1221         status = request_irq(irq, ssp_int, SA_INTERRUPT, dev->bus_id, drv_data);
1222         if (status < 0) {
1223                 dev_err(&pdev->dev, "can not get IRQ\n");
1224                 goto out_error_master_alloc;
1225         }
1226
1227         /* Setup DMA if requested */
1228         drv_data->tx_channel = -1;
1229         drv_data->rx_channel = -1;
1230         if (platform_info->enable_dma) {
1231
1232                 /* Get two DMA channels (rx and tx) */
1233                 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1234                                                         DMA_PRIO_HIGH,
1235                                                         dma_handler,
1236                                                         drv_data);
1237                 if (drv_data->rx_channel < 0) {
1238                         dev_err(dev, "problem (%d) requesting rx channel\n",
1239                                 drv_data->rx_channel);
1240                         status = -ENODEV;
1241                         goto out_error_irq_alloc;
1242                 }
1243                 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1244                                                         DMA_PRIO_MEDIUM,
1245                                                         dma_handler,
1246                                                         drv_data);
1247                 if (drv_data->tx_channel < 0) {
1248                         dev_err(dev, "problem (%d) requesting tx channel\n",
1249                                 drv_data->tx_channel);
1250                         status = -ENODEV;
1251                         goto out_error_dma_alloc;
1252                 }
1253
1254                 if (drv_data->ioaddr == SSP1_VIRT) {
1255                                 DRCMRRXSSDR = DRCMR_MAPVLD
1256                                                 | drv_data->rx_channel;
1257                                 DRCMRTXSSDR = DRCMR_MAPVLD
1258                                                 | drv_data->tx_channel;
1259                 } else if (drv_data->ioaddr == SSP2_VIRT) {
1260                                 DRCMRRXSS2DR = DRCMR_MAPVLD
1261                                                 | drv_data->rx_channel;
1262                                 DRCMRTXSS2DR = DRCMR_MAPVLD
1263                                                 | drv_data->tx_channel;
1264                 } else if (drv_data->ioaddr == SSP3_VIRT) {
1265                                 DRCMRRXSS3DR = DRCMR_MAPVLD
1266                                                 | drv_data->rx_channel;
1267                                 DRCMRTXSS3DR = DRCMR_MAPVLD
1268                                                 | drv_data->tx_channel;
1269                 } else {
1270                         dev_err(dev, "bad SSP type\n");
1271                         goto out_error_dma_alloc;
1272                 }
1273         }
1274
1275         /* Enable SOC clock */
1276         pxa_set_cken(platform_info->clock_enable, 1);
1277
1278         /* Load default SSP configuration */
1279         write_SSCR0(0, drv_data->ioaddr);
1280         write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);
1281         write_SSCR0(SSCR0_SerClkDiv(2)
1282                         | SSCR0_Motorola
1283                         | SSCR0_DataSize(8),
1284                         drv_data->ioaddr);
1285         if (drv_data->ssp_type != PXA25x_SSP)
1286                 write_SSTO(0, drv_data->ioaddr);
1287         write_SSPSP(0, drv_data->ioaddr);
1288
1289         /* Initial and start queue */
1290         status = init_queue(drv_data);
1291         if (status != 0) {
1292                 dev_err(&pdev->dev, "problem initializing queue\n");
1293                 goto out_error_clock_enabled;
1294         }
1295         status = start_queue(drv_data);
1296         if (status != 0) {
1297                 dev_err(&pdev->dev, "problem starting queue\n");
1298                 goto out_error_clock_enabled;
1299         }
1300
1301         /* Register with the SPI framework */
1302         platform_set_drvdata(pdev, drv_data);
1303         status = spi_register_master(master);
1304         if (status != 0) {
1305                 dev_err(&pdev->dev, "problem registering spi master\n");
1306                 goto out_error_queue_alloc;
1307         }
1308
1309         return status;
1310
1311 out_error_queue_alloc:
1312         destroy_queue(drv_data);
1313
1314 out_error_clock_enabled:
1315         pxa_set_cken(platform_info->clock_enable, 0);
1316
1317 out_error_dma_alloc:
1318         if (drv_data->tx_channel != -1)
1319                 pxa_free_dma(drv_data->tx_channel);
1320         if (drv_data->rx_channel != -1)
1321                 pxa_free_dma(drv_data->rx_channel);
1322
1323 out_error_irq_alloc:
1324         free_irq(irq, drv_data);
1325
1326 out_error_master_alloc:
1327         spi_master_put(master);
1328         return status;
1329 }
1330
1331 static int pxa2xx_spi_remove(struct platform_device *pdev)
1332 {
1333         struct driver_data *drv_data = platform_get_drvdata(pdev);
1334         int irq;
1335         int status = 0;
1336
1337         if (!drv_data)
1338                 return 0;
1339
1340         /* Remove the queue */
1341         status = destroy_queue(drv_data);
1342         if (status != 0)
1343                 return status;
1344
1345         /* Disable the SSP at the peripheral and SOC level */
1346         write_SSCR0(0, drv_data->ioaddr);
1347         pxa_set_cken(drv_data->master_info->clock_enable, 0);
1348
1349         /* Release DMA */
1350         if (drv_data->master_info->enable_dma) {
1351                 if (drv_data->ioaddr == SSP1_VIRT) {
1352                         DRCMRRXSSDR = 0;
1353                         DRCMRTXSSDR = 0;
1354                 } else if (drv_data->ioaddr == SSP2_VIRT) {
1355                         DRCMRRXSS2DR = 0;
1356                         DRCMRTXSS2DR = 0;
1357                 } else if (drv_data->ioaddr == SSP3_VIRT) {
1358                         DRCMRRXSS3DR = 0;
1359                         DRCMRTXSS3DR = 0;
1360                 }
1361                 pxa_free_dma(drv_data->tx_channel);
1362                 pxa_free_dma(drv_data->rx_channel);
1363         }
1364
1365         /* Release IRQ */
1366         irq = platform_get_irq(pdev, 0);
1367         if (irq >= 0)
1368                 free_irq(irq, drv_data);
1369
1370         /* Disconnect from the SPI framework */
1371         spi_unregister_master(drv_data->master);
1372
1373         /* Prevent double remove */
1374         platform_set_drvdata(pdev, NULL);
1375
1376         return 0;
1377 }
1378
1379 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1380 {
1381         int status = 0;
1382
1383         if ((status = pxa2xx_spi_remove(pdev)) != 0)
1384                 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1385 }
1386
1387 #ifdef CONFIG_PM
1388 static int suspend_devices(struct device *dev, void *pm_message)
1389 {
1390         pm_message_t *state = pm_message;
1391
1392         if (dev->power.power_state.event != state->event) {
1393                 dev_warn(dev, "pm state does not match request\n");
1394                 return -1;
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1401 {
1402         struct driver_data *drv_data = platform_get_drvdata(pdev);
1403         int status = 0;
1404
1405         /* Check all childern for current power state */
1406         if (device_for_each_child(&pdev->dev, &state, suspend_devices) != 0) {
1407                 dev_warn(&pdev->dev, "suspend aborted\n");
1408                 return -1;
1409         }
1410
1411         status = stop_queue(drv_data);
1412         if (status != 0)
1413                 return status;
1414         write_SSCR0(0, drv_data->ioaddr);
1415         pxa_set_cken(drv_data->master_info->clock_enable, 0);
1416
1417         return 0;
1418 }
1419
1420 static int pxa2xx_spi_resume(struct platform_device *pdev)
1421 {
1422         struct driver_data *drv_data = platform_get_drvdata(pdev);
1423         int status = 0;
1424
1425         /* Enable the SSP clock */
1426         pxa_set_cken(drv_data->master_info->clock_enable, 1);
1427
1428         /* Start the queue running */
1429         status = start_queue(drv_data);
1430         if (status != 0) {
1431                 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1432                 return status;
1433         }
1434
1435         return 0;
1436 }
1437 #else
1438 #define pxa2xx_spi_suspend NULL
1439 #define pxa2xx_spi_resume NULL
1440 #endif /* CONFIG_PM */
1441
1442 static struct platform_driver driver = {
1443         .driver = {
1444                 .name = "pxa2xx-spi",
1445                 .bus = &platform_bus_type,
1446                 .owner = THIS_MODULE,
1447         },
1448         .probe = pxa2xx_spi_probe,
1449         .remove = __devexit_p(pxa2xx_spi_remove),
1450         .shutdown = pxa2xx_spi_shutdown,
1451         .suspend = pxa2xx_spi_suspend,
1452         .resume = pxa2xx_spi_resume,
1453 };
1454
1455 static int __init pxa2xx_spi_init(void)
1456 {
1457         platform_driver_register(&driver);
1458
1459         return 0;
1460 }
1461 module_init(pxa2xx_spi_init);
1462
1463 static void __exit pxa2xx_spi_exit(void)
1464 {
1465         platform_driver_unregister(&driver);
1466 }
1467 module_exit(pxa2xx_spi_exit);