drivers/spi/omap2_mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrjölä <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/module.h>
  28 #include <linux/device.h>
  29 #include <linux/delay.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/io.h>
  35 #include <linux/slab.h>
  36
  37 #include <linux/spi/spi.h>
  38
  39 #include <plat/dma.h>
  40 #include <plat/clock.h>
  41 #include <plat/mcspi.h>
  42
  43 #define OMAP2_MCSPI_MAX_FREQ            48000000
  44
  45 /* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
  46 #define OMAP2_MCSPI_MAX_CTRL            4
  47
  48 #define OMAP2_MCSPI_REVISION            0x00
  49 #define OMAP2_MCSPI_SYSCONFIG           0x10
  50 #define OMAP2_MCSPI_SYSSTATUS           0x14
  51 #define OMAP2_MCSPI_IRQSTATUS           0x18
  52 #define OMAP2_MCSPI_IRQENABLE           0x1c
  53 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  54 #define OMAP2_MCSPI_SYST                0x24
  55 #define OMAP2_MCSPI_MODULCTRL           0x28
  56
  57 /* per-channel banks, 0x14 bytes each, first is: */
  58 #define OMAP2_MCSPI_CHCONF0             0x2c
  59 #define OMAP2_MCSPI_CHSTAT0             0x30
  60 #define OMAP2_MCSPI_CHCTRL0             0x34
  61 #define OMAP2_MCSPI_TX0                 0x38
  62 #define OMAP2_MCSPI_RX0                 0x3c
  63
  64 /* per-register bitmasks: */
  65
  66 #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
  67 #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
  68 #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE  BIT(0)
  69 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
  70
  71 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
  72
  73 #define OMAP2_MCSPI_MODULCTRL_SINGLE    BIT(0)
  74 #define OMAP2_MCSPI_MODULCTRL_MS        BIT(2)
  75 #define OMAP2_MCSPI_MODULCTRL_STEST     BIT(3)
  76
  77 #define OMAP2_MCSPI_CHCONF_PHA          BIT(0)
  78 #define OMAP2_MCSPI_CHCONF_POL          BIT(1)
  79 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  80 #define OMAP2_MCSPI_CHCONF_EPOL         BIT(6)
  81 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  82 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  BIT(12)
  83 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  BIT(13)
  84 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  85 #define OMAP2_MCSPI_CHCONF_DMAW         BIT(14)
  86 #define OMAP2_MCSPI_CHCONF_DMAR         BIT(15)
  87 #define OMAP2_MCSPI_CHCONF_DPE0         BIT(16)
  88 #define OMAP2_MCSPI_CHCONF_DPE1         BIT(17)
  89 #define OMAP2_MCSPI_CHCONF_IS           BIT(18)
  90 #define OMAP2_MCSPI_CHCONF_TURBO        BIT(19)
  91 #define OMAP2_MCSPI_CHCONF_FORCE        BIT(20)
  92
  93 #define OMAP2_MCSPI_CHSTAT_RXS          BIT(0)
  94 #define OMAP2_MCSPI_CHSTAT_TXS          BIT(1)
  95 #define OMAP2_MCSPI_CHSTAT_EOT          BIT(2)
  96
  97 #define OMAP2_MCSPI_CHCTRL_EN           BIT(0)
  98
  99 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   BIT(0)
 100
 101 /* We have 2 DMA channels per CS, one for RX and one for TX */
 102 struct omap2_mcspi_dma {
 103         int dma_tx_channel;
 104         int dma_rx_channel;
 105
 106         int dma_tx_sync_dev;
 107         int dma_rx_sync_dev;
 108
 109         struct completion dma_tx_completion;
 110         struct completion dma_rx_completion;
 111 };
 112
 113 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 114  * cache operations; better heuristics consider wordsize and bitrate.
 115  */
 116 #define DMA_MIN_BYTES                   160
 117
 118
 119 struct omap2_mcspi {
 120         struct work_struct      work;
 121         /* lock protects queue and registers */
 122         spinlock_t              lock;
 123         struct list_head        msg_queue;
 124         struct spi_master       *master;
 125         struct clk              *ick;
 126         struct clk              *fck;
 127         /* Virtual base address of the controller */
 128         void __iomem            *base;
 129         unsigned long           phys;
 130         /* SPI1 has 4 channels, while SPI2 has 2 */
 131         struct omap2_mcspi_dma  *dma_channels;
 132 };
 133
 134 struct omap2_mcspi_cs {
 135         void __iomem            *base;
 136         unsigned long           phys;
 137         int                     word_len;
 138         struct list_head        node;
 139         /* Context save and restore shadow register */
 140         u32                     chconf0;
 141 };
 142
 143 /* used for context save and restore, structure members to be updated whenever
 144  * corresponding registers are modified.
 145  */
 146 struct omap2_mcspi_regs {
 147         u32 sysconfig;
 148         u32 modulctrl;
 149         u32 wakeupenable;
 150         struct list_head cs;
 151 };
 152
 153 static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
 154
 155 static struct workqueue_struct *omap2_mcspi_wq;
 156
 157 #define MOD_REG_BIT(val, mask, set) do { \
 158         if (set) \
 159                 val |= mask; \
 160         else \
 161                 val &= ~mask; \
 162 } while (0)
 163
 164 static inline void mcspi_write_reg(struct spi_master *master,
 165                 int idx, u32 val)
 166 {
 167         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 168
 169         __raw_writel(val, mcspi->base + idx);
 170 }
 171
 172 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 173 {
 174         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 175
 176         return __raw_readl(mcspi->base + idx);
 177 }
 178
 179 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 180                 int idx, u32 val)
 181 {
 182         struct omap2_mcspi_cs   *cs = spi->controller_state;
 183
 184         __raw_writel(val, cs->base +  idx);
 185 }
 186
 187 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 188 {
 189         struct omap2_mcspi_cs   *cs = spi->controller_state;
 190
 191         return __raw_readl(cs->base + idx);
 192 }
 193
 194 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
 195 {
 196         struct omap2_mcspi_cs *cs = spi->controller_state;
 197
 198         return cs->chconf0;
 199 }
 200
 201 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
 202 {
 203         struct omap2_mcspi_cs *cs = spi->controller_state;
 204
 205         cs->chconf0 = val;
 206         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
 207         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 208 }
 209
 210 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 211                 int is_read, int enable)
 212 {
 213         u32 l, rw;
 214
 215         l = mcspi_cached_chconf0(spi);
 216
 217         if (is_read) /* 1 is read, 0 write */
 218                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 219         else
 220                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 221
 222         MOD_REG_BIT(l, rw, enable);
 223         mcspi_write_chconf0(spi, l);
 224 }
 225
 226 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 227 {
 228         u32 l;
 229
 230         l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
 231         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
 232         /* Flash post-writes */
 233         mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
 234 }
 235
 236 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 237 {
 238         u32 l;
 239
 240         l = mcspi_cached_chconf0(spi);
 241         MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
 242         mcspi_write_chconf0(spi, l);
 243 }
 244
 245 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 246 {
 247         u32 l;
 248
 249         /* setup when switching from (reset default) slave mode
 250          * to single-channel master mode
 251          */
 252         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 253         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
 254         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
 255         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
 256         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 257
 258         omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
 259 }
 260
 261 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 262 {
 263         struct spi_master *spi_cntrl;
 264         struct omap2_mcspi_cs *cs;
 265         spi_cntrl = mcspi->master;
 266
 267         /* McSPI: context restore */
 268         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
 269                         omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
 270
 271         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
 272                         omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
 273
 274         mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
 275                         omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
 276
 277         list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
 278                         node)
 279                 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
 280 }
 281 static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
 282 {
 283         clk_disable(mcspi->ick);
 284         clk_disable(mcspi->fck);
 285 }
 286
 287 static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
 288 {
 289         if (clk_enable(mcspi->ick))
 290                 return -ENODEV;
 291         if (clk_enable(mcspi->fck))
 292                 return -ENODEV;
 293
 294         omap2_mcspi_restore_ctx(mcspi);
 295
 296         return 0;
 297 }
 298
 299 static unsigned
 300 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 301 {
 302         struct omap2_mcspi      *mcspi;
 303         struct omap2_mcspi_cs   *cs = spi->controller_state;
 304         struct omap2_mcspi_dma  *mcspi_dma;
 305         unsigned int            count, c;
 306         unsigned long           base, tx_reg, rx_reg;
 307         int                     word_len, data_type, element_count;
 308         int                     elements;
 309         u32                     l;
 310         u8                      * rx;
 311         const u8                * tx;
 312
 313         mcspi = spi_master_get_devdata(spi->master);
 314         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 315         l = mcspi_cached_chconf0(spi);
 316
 317         count = xfer->len;
 318         c = count;
 319         word_len = cs->word_len;
 320
 321         base = cs->phys;
 322         tx_reg = base + OMAP2_MCSPI_TX0;
 323         rx_reg = base + OMAP2_MCSPI_RX0;
 324         rx = xfer->rx_buf;
 325         tx = xfer->tx_buf;
 326
 327         if (word_len <= 8) {
 328                 data_type = OMAP_DMA_DATA_TYPE_S8;
 329                 element_count = count;
 330         } else if (word_len <= 16) {
 331                 data_type = OMAP_DMA_DATA_TYPE_S16;
 332                 element_count = count >> 1;
 333         } else /* word_len <= 32 */ {
 334                 data_type = OMAP_DMA_DATA_TYPE_S32;
 335                 element_count = count >> 2;
 336         }
 337
 338         if (tx != NULL) {
 339                 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
 340                                 data_type, element_count, 1,
 341                                 OMAP_DMA_SYNC_ELEMENT,
 342                                 mcspi_dma->dma_tx_sync_dev, 0);
 343
 344                 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
 345                                 OMAP_DMA_AMODE_CONSTANT,
 346                                 tx_reg, 0, 0);
 347
 348                 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
 349                                 OMAP_DMA_AMODE_POST_INC,
 350                                 xfer->tx_dma, 0, 0);
 351         }
 352
 353         if (rx != NULL) {
 354                 elements = element_count - 1;
 355                 if (l & OMAP2_MCSPI_CHCONF_TURBO)
 356                         elements--;
 357
 358                 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
 359                                 data_type, elements, 1,
 360                                 OMAP_DMA_SYNC_ELEMENT,
 361                                 mcspi_dma->dma_rx_sync_dev, 1);
 362
 363                 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
 364                                 OMAP_DMA_AMODE_CONSTANT,
 365                                 rx_reg, 0, 0);
 366
 367                 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
 368                                 OMAP_DMA_AMODE_POST_INC,
 369                                 xfer->rx_dma, 0, 0);
 370         }
 371
 372         if (tx != NULL) {
 373                 omap_start_dma(mcspi_dma->dma_tx_channel);
 374                 omap2_mcspi_set_dma_req(spi, 0, 1);
 375         }
 376
 377         if (rx != NULL) {
 378                 omap_start_dma(mcspi_dma->dma_rx_channel);
 379                 omap2_mcspi_set_dma_req(spi, 1, 1);
 380         }
 381
 382         if (tx != NULL) {
 383                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 384                 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
 385         }
 386
 387         if (rx != NULL) {
 388                 wait_for_completion(&mcspi_dma->dma_rx_completion);
 389                 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
 390                 omap2_mcspi_set_enable(spi, 0);
 391
 392                 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
 393
 394                         if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 395                                    & OMAP2_MCSPI_CHSTAT_RXS)) {
 396                                 u32 w;
 397
 398                                 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 399                                 if (word_len <= 8)
 400                                         ((u8 *)xfer->rx_buf)[elements++] = w;
 401                                 else if (word_len <= 16)
 402                                         ((u16 *)xfer->rx_buf)[elements++] = w;
 403                                 else /* word_len <= 32 */
 404                                         ((u32 *)xfer->rx_buf)[elements++] = w;
 405                         } else {
 406                                 dev_err(&spi->dev,
 407                                         "DMA RX penultimate word empty");
 408                                 count -= (word_len <= 8)  ? 2 :
 409                                         (word_len <= 16) ? 4 :
 410                                         /* word_len <= 32 */ 8;
 411                                 omap2_mcspi_set_enable(spi, 1);
 412                                 return count;
 413                         }
 414                 }
 415
 416                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 417                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
 418                         u32 w;
 419
 420                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 421                         if (word_len <= 8)
 422                                 ((u8 *)xfer->rx_buf)[elements] = w;
 423                         else if (word_len <= 16)
 424                                 ((u16 *)xfer->rx_buf)[elements] = w;
 425                         else /* word_len <= 32 */
 426                                 ((u32 *)xfer->rx_buf)[elements] = w;
 427                 } else {
 428                         dev_err(&spi->dev, "DMA RX last word empty");
 429                         count -= (word_len <= 8)  ? 1 :
 430                                  (word_len <= 16) ? 2 :
 431                                /* word_len <= 32 */ 4;
 432                 }
 433                 omap2_mcspi_set_enable(spi, 1);
 434         }
 435         return count;
 436 }
 437
 438 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 439 {
 440         unsigned long timeout;
 441
 442         timeout = jiffies + msecs_to_jiffies(1000);
 443         while (!(__raw_readl(reg) & bit)) {
 444                 if (time_after(jiffies, timeout))
 445                         return -1;
 446                 cpu_relax();
 447         }
 448         return 0;
 449 }
 450
 451 static unsigned
 452 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 453 {
 454         struct omap2_mcspi      *mcspi;
 455         struct omap2_mcspi_cs   *cs = spi->controller_state;
 456         unsigned int            count, c;
 457         u32                     l;
 458         void __iomem            *base = cs->base;
 459         void __iomem            *tx_reg;
 460         void __iomem            *rx_reg;
 461         void __iomem            *chstat_reg;
 462         int                     word_len;
 463
 464         mcspi = spi_master_get_devdata(spi->master);
 465         count = xfer->len;
 466         c = count;
 467         word_len = cs->word_len;
 468
 469         l = mcspi_cached_chconf0(spi);
 470
 471         /* We store the pre-calculated register addresses on stack to speed
 472          * up the transfer loop. */
 473         tx_reg          = base + OMAP2_MCSPI_TX0;
 474         rx_reg          = base + OMAP2_MCSPI_RX0;
 475         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 476
 477         if (word_len <= 8) {
 478                 u8              *rx;
 479                 const u8        *tx;
 480
 481                 rx = xfer->rx_buf;
 482                 tx = xfer->tx_buf;
 483
 484                 do {
 485                         c -= 1;
 486                         if (tx != NULL) {
 487                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 488                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 489                                         dev_err(&spi->dev, "TXS timed out\n");
 490                                         goto out;
 491                                 }
 492                                 dev_vdbg(&spi->dev, "write-%d %02x\n",
 493                                                 word_len, *tx);
 494                                 __raw_writel(*tx++, tx_reg);
 495                         }
 496                         if (rx != NULL) {
 497                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 498                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 499                                         dev_err(&spi->dev, "RXS timed out\n");
 500                                         goto out;
 501                                 }
 502
 503                                 if (c == 1 && tx == NULL &&
 504                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 505                                         omap2_mcspi_set_enable(spi, 0);
 506                                         *rx++ = __raw_readl(rx_reg);
 507                                         dev_vdbg(&spi->dev, "read-%d %02x\n",
 508                                                     word_len, *(rx - 1));
 509                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 510                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 511                                                 dev_err(&spi->dev,
 512                                                         "RXS timed out\n");
 513                                                 goto out;
 514                                         }
 515                                         c = 0;
 516                                 } else if (c == 0 && tx == NULL) {
 517                                         omap2_mcspi_set_enable(spi, 0);
 518                                 }
 519
 520                                 *rx++ = __raw_readl(rx_reg);
 521                                 dev_vdbg(&spi->dev, "read-%d %02x\n",
 522                                                 word_len, *(rx - 1));
 523                         }
 524                 } while (c);
 525         } else if (word_len <= 16) {
 526                 u16             *rx;
 527                 const u16       *tx;
 528
 529                 rx = xfer->rx_buf;
 530                 tx = xfer->tx_buf;
 531                 do {
 532                         c -= 2;
 533                         if (tx != NULL) {
 534                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 535                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 536                                         dev_err(&spi->dev, "TXS timed out\n");
 537                                         goto out;
 538                                 }
 539                                 dev_vdbg(&spi->dev, "write-%d %04x\n",
 540                                                 word_len, *tx);
 541                                 __raw_writel(*tx++, tx_reg);
 542                         }
 543                         if (rx != NULL) {
 544                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 545                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 546                                         dev_err(&spi->dev, "RXS timed out\n");
 547                                         goto out;
 548                                 }
 549
 550                                 if (c == 2 && tx == NULL &&
 551                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 552                                         omap2_mcspi_set_enable(spi, 0);
 553                                         *rx++ = __raw_readl(rx_reg);
 554                                         dev_vdbg(&spi->dev, "read-%d %04x\n",
 555                                                     word_len, *(rx - 1));
 556                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 557                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 558                                                 dev_err(&spi->dev,
 559                                                         "RXS timed out\n");
 560                                                 goto out;
 561                                         }
 562                                         c = 0;
 563                                 } else if (c == 0 && tx == NULL) {
 564                                         omap2_mcspi_set_enable(spi, 0);
 565                                 }
 566
 567                                 *rx++ = __raw_readl(rx_reg);
 568                                 dev_vdbg(&spi->dev, "read-%d %04x\n",
 569                                                 word_len, *(rx - 1));
 570                         }
 571                 } while (c);
 572         } else if (word_len <= 32) {
 573                 u32             *rx;
 574                 const u32       *tx;
 575
 576                 rx = xfer->rx_buf;
 577                 tx = xfer->tx_buf;
 578                 do {
 579                         c -= 4;
 580                         if (tx != NULL) {
 581                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 582                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 583                                         dev_err(&spi->dev, "TXS timed out\n");
 584                                         goto out;
 585                                 }
 586                                 dev_vdbg(&spi->dev, "write-%d %08x\n",
 587                                                 word_len, *tx);
 588                                 __raw_writel(*tx++, tx_reg);
 589                         }
 590                         if (rx != NULL) {
 591                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 592                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 593                                         dev_err(&spi->dev, "RXS timed out\n");
 594                                         goto out;
 595                                 }
 596
 597                                 if (c == 4 && tx == NULL &&
 598                                     (l & OMAP2_MCSPI_CHCONF_TURBO)) {
 599                                         omap2_mcspi_set_enable(spi, 0);
 600                                         *rx++ = __raw_readl(rx_reg);
 601                                         dev_vdbg(&spi->dev, "read-%d %08x\n",
 602                                                     word_len, *(rx - 1));
 603                                         if (mcspi_wait_for_reg_bit(chstat_reg,
 604                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 605                                                 dev_err(&spi->dev,
 606                                                         "RXS timed out\n");
 607                                                 goto out;
 608                                         }
 609                                         c = 0;
 610                                 } else if (c == 0 && tx == NULL) {
 611                                         omap2_mcspi_set_enable(spi, 0);
 612                                 }
 613
 614                                 *rx++ = __raw_readl(rx_reg);
 615                                 dev_vdbg(&spi->dev, "read-%d %08x\n",
 616                                                 word_len, *(rx - 1));
 617                         }
 618                 } while (c);
 619         }
 620
 621         /* for TX_ONLY mode, be sure all words have shifted out */
 622         if (xfer->rx_buf == NULL) {
 623                 if (mcspi_wait_for_reg_bit(chstat_reg,
 624                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 625                         dev_err(&spi->dev, "TXS timed out\n");
 626                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 627                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 628                         dev_err(&spi->dev, "EOT timed out\n");
 629         }
 630 out:
 631         omap2_mcspi_set_enable(spi, 1);
 632         return count - c;
 633 }
 634
 635 /* called only when no transfer is active to this device */
 636 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 637                 struct spi_transfer *t)
 638 {
 639         struct omap2_mcspi_cs *cs = spi->controller_state;
 640         struct omap2_mcspi *mcspi;
 641         struct spi_master *spi_cntrl;
 642         u32 l = 0, div = 0;
 643         u8 word_len = spi->bits_per_word;
 644         u32 speed_hz = spi->max_speed_hz;
 645
 646         mcspi = spi_master_get_devdata(spi->master);
 647         spi_cntrl = mcspi->master;
 648
 649         if (t != NULL && t->bits_per_word)
 650                 word_len = t->bits_per_word;
 651
 652         cs->word_len = word_len;
 653
 654         if (t && t->speed_hz)
 655                 speed_hz = t->speed_hz;
 656
 657         if (speed_hz) {
 658                 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
 659                                         > speed_hz)
 660                         div++;
 661         } else
 662                 div = 15;
 663
 664         l = mcspi_cached_chconf0(spi);
 665
 666         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 667          * REVISIT: this controller could support SPI_3WIRE mode.
 668          */
 669         l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
 670         l |= OMAP2_MCSPI_CHCONF_DPE0;
 671
 672         /* wordlength */
 673         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 674         l |= (word_len - 1) << 7;
 675
 676         /* set chipselect polarity; manage with FORCE */
 677         if (!(spi->mode & SPI_CS_HIGH))
 678                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 679         else
 680                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 681
 682         /* set clock divisor */
 683         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 684         l |= div << 2;
 685
 686         /* set SPI mode 0..3 */
 687         if (spi->mode & SPI_CPOL)
 688                 l |= OMAP2_MCSPI_CHCONF_POL;
 689         else
 690                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 691         if (spi->mode & SPI_CPHA)
 692                 l |= OMAP2_MCSPI_CHCONF_PHA;
 693         else
 694                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 695
 696         mcspi_write_chconf0(spi, l);
 697
 698         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 699                         OMAP2_MCSPI_MAX_FREQ / (1 << div),
 700                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 701                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 702
 703         return 0;
 704 }
 705
 706 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
 707 {
 708         struct spi_device       *spi = data;
 709         struct omap2_mcspi      *mcspi;
 710         struct omap2_mcspi_dma  *mcspi_dma;
 711
 712         mcspi = spi_master_get_devdata(spi->master);
 713         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 714
 715         complete(&mcspi_dma->dma_rx_completion);
 716
 717         /* We must disable the DMA RX request */
 718         omap2_mcspi_set_dma_req(spi, 1, 0);
 719 }
 720
 721 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
 722 {
 723         struct spi_device       *spi = data;
 724         struct omap2_mcspi      *mcspi;
 725         struct omap2_mcspi_dma  *mcspi_dma;
 726
 727         mcspi = spi_master_get_devdata(spi->master);
 728         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 729
 730         complete(&mcspi_dma->dma_tx_completion);
 731
 732         /* We must disable the DMA TX request */
 733         omap2_mcspi_set_dma_req(spi, 0, 0);
 734 }
 735
 736 static int omap2_mcspi_request_dma(struct spi_device *spi)
 737 {
 738         struct spi_master       *master = spi->master;
 739         struct omap2_mcspi      *mcspi;
 740         struct omap2_mcspi_dma  *mcspi_dma;
 741
 742         mcspi = spi_master_get_devdata(master);
 743         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 744
 745         if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
 746                         omap2_mcspi_dma_rx_callback, spi,
 747                         &mcspi_dma->dma_rx_channel)) {
 748                 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
 749                 return -EAGAIN;
 750         }
 751
 752         if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
 753                         omap2_mcspi_dma_tx_callback, spi,
 754                         &mcspi_dma->dma_tx_channel)) {
 755                 omap_free_dma(mcspi_dma->dma_rx_channel);
 756                 mcspi_dma->dma_rx_channel = -1;
 757                 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
 758                 return -EAGAIN;
 759         }
 760
 761         init_completion(&mcspi_dma->dma_rx_completion);
 762         init_completion(&mcspi_dma->dma_tx_completion);
 763
 764         return 0;
 765 }
 766
 767 static int omap2_mcspi_setup(struct spi_device *spi)
 768 {
 769         int                     ret;
 770         struct omap2_mcspi      *mcspi;
 771         struct omap2_mcspi_dma  *mcspi_dma;
 772         struct omap2_mcspi_cs   *cs = spi->controller_state;
 773
 774         if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
 775                 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
 776                         spi->bits_per_word);
 777                 return -EINVAL;
 778         }
 779
 780         mcspi = spi_master_get_devdata(spi->master);
 781         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 782
 783         if (!cs) {
 784                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 785                 if (!cs)
 786                         return -ENOMEM;
 787                 cs->base = mcspi->base + spi->chip_select * 0x14;
 788                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
 789                 cs->chconf0 = 0;
 790                 spi->controller_state = cs;
 791                 /* Link this to context save list */
 792                 list_add_tail(&cs->node,
 793                         &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
 794         }
 795
 796         if (mcspi_dma->dma_rx_channel == -1
 797                         || mcspi_dma->dma_tx_channel == -1) {
 798                 ret = omap2_mcspi_request_dma(spi);
 799                 if (ret < 0)
 800                         return ret;
 801         }
 802
 803         if (omap2_mcspi_enable_clocks(mcspi))
 804                 return -ENODEV;
 805
 806         ret = omap2_mcspi_setup_transfer(spi, NULL);
 807         omap2_mcspi_disable_clocks(mcspi);
 808
 809         return ret;
 810 }
 811
 812 static void omap2_mcspi_cleanup(struct spi_device *spi)
 813 {
 814         struct omap2_mcspi      *mcspi;
 815         struct omap2_mcspi_dma  *mcspi_dma;
 816         struct omap2_mcspi_cs   *cs;
 817
 818         mcspi = spi_master_get_devdata(spi->master);
 819
 820         if (spi->controller_state) {
 821                 /* Unlink controller state from context save list */
 822                 cs = spi->controller_state;
 823                 list_del(&cs->node);
 824
 825                 kfree(spi->controller_state);
 826         }
 827
 828         if (spi->chip_select < spi->master->num_chipselect) {
 829                 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 830
 831                 if (mcspi_dma->dma_rx_channel != -1) {
 832                         omap_free_dma(mcspi_dma->dma_rx_channel);
 833                         mcspi_dma->dma_rx_channel = -1;
 834                 }
 835                 if (mcspi_dma->dma_tx_channel != -1) {
 836                         omap_free_dma(mcspi_dma->dma_tx_channel);
 837                         mcspi_dma->dma_tx_channel = -1;
 838                 }
 839         }
 840 }
 841
 842 static void omap2_mcspi_work(struct work_struct *work)
 843 {
 844         struct omap2_mcspi      *mcspi;
 845
 846         mcspi = container_of(work, struct omap2_mcspi, work);
 847         spin_lock_irq(&mcspi->lock);
 848
 849         if (omap2_mcspi_enable_clocks(mcspi))
 850                 goto out;
 851
 852         /* We only enable one channel at a time -- the one whose message is
 853          * at the head of the queue -- although this controller would gladly
 854          * arbitrate among multiple channels.  This corresponds to "single
 855          * channel" master mode.  As a side effect, we need to manage the
 856          * chipselect with the FORCE bit ... CS != channel enable.
 857          */
 858         while (!list_empty(&mcspi->msg_queue)) {
 859                 struct spi_message              *m;
 860                 struct spi_device               *spi;
 861                 struct spi_transfer             *t = NULL;
 862                 int                             cs_active = 0;
 863                 struct omap2_mcspi_cs           *cs;
 864                 struct omap2_mcspi_device_config *cd;
 865                 int                             par_override = 0;
 866                 int                             status = 0;
 867                 u32                             chconf;
 868
 869                 m = container_of(mcspi->msg_queue.next, struct spi_message,
 870                                  queue);
 871
 872                 list_del_init(&m->queue);
 873                 spin_unlock_irq(&mcspi->lock);
 874
 875                 spi = m->spi;
 876                 cs = spi->controller_state;
 877                 cd = spi->controller_data;
 878
 879                 omap2_mcspi_set_enable(spi, 1);
 880                 list_for_each_entry(t, &m->transfers, transfer_list) {
 881                         if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 882                                 status = -EINVAL;
 883                                 break;
 884                         }
 885                         if (par_override || t->speed_hz || t->bits_per_word) {
 886                                 par_override = 1;
 887                                 status = omap2_mcspi_setup_transfer(spi, t);
 888                                 if (status < 0)
 889                                         break;
 890                                 if (!t->speed_hz && !t->bits_per_word)
 891                                         par_override = 0;
 892                         }
 893
 894                         if (!cs_active) {
 895                                 omap2_mcspi_force_cs(spi, 1);
 896                                 cs_active = 1;
 897                         }
 898
 899                         chconf = mcspi_cached_chconf0(spi);
 900                         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 901                         chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
 902
 903                         if (t->tx_buf == NULL)
 904                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
 905                         else if (t->rx_buf == NULL)
 906                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
 907
 908                         if (cd && cd->turbo_mode && t->tx_buf == NULL) {
 909                                 /* Turbo mode is for more than one word */
 910                                 if (t->len > ((cs->word_len + 7) >> 3))
 911                                         chconf |= OMAP2_MCSPI_CHCONF_TURBO;
 912                         }
 913
 914                         mcspi_write_chconf0(spi, chconf);
 915
 916                         if (t->len) {
 917                                 unsigned        count;
 918
 919                                 /* RX_ONLY mode needs dummy data in TX reg */
 920                                 if (t->tx_buf == NULL)
 921                                         __raw_writel(0, cs->base
 922                                                         + OMAP2_MCSPI_TX0);
 923
 924                                 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
 925                                         count = omap2_mcspi_txrx_dma(spi, t);
 926                                 else
 927                                         count = omap2_mcspi_txrx_pio(spi, t);
 928                                 m->actual_length += count;
 929
 930                                 if (count != t->len) {
 931                                         status = -EIO;
 932                                         break;
 933                                 }
 934                         }
 935
 936                         if (t->delay_usecs)
 937                                 udelay(t->delay_usecs);
 938
 939                         /* ignore the "leave it on after last xfer" hint */
 940                         if (t->cs_change) {
 941                                 omap2_mcspi_force_cs(spi, 0);
 942                                 cs_active = 0;
 943                         }
 944                 }
 945
 946                 /* Restore defaults if they were overriden */
 947                 if (par_override) {
 948                         par_override = 0;
 949                         status = omap2_mcspi_setup_transfer(spi, NULL);
 950                 }
 951
 952                 if (cs_active)
 953                         omap2_mcspi_force_cs(spi, 0);
 954
 955                 omap2_mcspi_set_enable(spi, 0);
 956
 957                 m->status = status;
 958                 m->complete(m->context);
 959
 960                 spin_lock_irq(&mcspi->lock);
 961         }
 962
 963         omap2_mcspi_disable_clocks(mcspi);
 964
 965 out:
 966         spin_unlock_irq(&mcspi->lock);
 967 }
 968
 969 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
 970 {
 971         struct omap2_mcspi      *mcspi;
 972         unsigned long           flags;
 973         struct spi_transfer     *t;
 974
 975         m->actual_length = 0;
 976         m->status = 0;
 977
 978         /* reject invalid messages and transfers */
 979         if (list_empty(&m->transfers) || !m->complete)
 980                 return -EINVAL;
 981         list_for_each_entry(t, &m->transfers, transfer_list) {
 982                 const void      *tx_buf = t->tx_buf;
 983                 void            *rx_buf = t->rx_buf;
 984                 unsigned        len = t->len;
 985
 986                 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
 987                                 || (len && !(rx_buf || tx_buf))
 988                                 || (t->bits_per_word &&
 989                                         (  t->bits_per_word < 4
 990                                         || t->bits_per_word > 32))) {
 991                         dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
 992                                         t->speed_hz,
 993                                         len,
 994                                         tx_buf ? "tx" : "",
 995                                         rx_buf ? "rx" : "",
 996                                         t->bits_per_word);
 997                         return -EINVAL;
 998                 }
 999                 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
1000                         dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
1001                                         t->speed_hz,
1002                                         OMAP2_MCSPI_MAX_FREQ/(1<<16));
1003                         return -EINVAL;
1004                 }
1005
1006                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1007                         continue;
1008
1009                 /* Do DMA mapping "early" for better error reporting and
1010                  * dcache use.  Note that if dma_unmap_single() ever starts
1011                  * to do real work on ARM, we'd need to clean up mappings
1012                  * for previous transfers on *ALL* exits of this loop...
1013                  */
1014                 if (tx_buf != NULL) {
1015                         t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
1016                                         len, DMA_TO_DEVICE);
1017                         if (dma_mapping_error(&spi->dev, t->tx_dma)) {
1018                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
1019                                                 'T', len);
1020                                 return -EINVAL;
1021                         }
1022                 }
1023                 if (rx_buf != NULL) {
1024                         t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
1025                                         DMA_FROM_DEVICE);
1026                         if (dma_mapping_error(&spi->dev, t->rx_dma)) {
1027                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
1028                                                 'R', len);
1029                                 if (tx_buf != NULL)
1030                                         dma_unmap_single(NULL, t->tx_dma,
1031                                                         len, DMA_TO_DEVICE);
1032                                 return -EINVAL;
1033                         }
1034                 }
1035         }
1036
1037         mcspi = spi_master_get_devdata(spi->master);
1038
1039         spin_lock_irqsave(&mcspi->lock, flags);
1040         list_add_tail(&m->queue, &mcspi->msg_queue);
1041         queue_work(omap2_mcspi_wq, &mcspi->work);
1042         spin_unlock_irqrestore(&mcspi->lock, flags);
1043
1044         return 0;
1045 }
1046
1047 static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
1048 {
1049         struct spi_master       *master = mcspi->master;
1050         u32                     tmp;
1051
1052         if (omap2_mcspi_enable_clocks(mcspi))
1053                 return -1;
1054
1055         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
1056                         OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
1057         do {
1058                 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
1059         } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
1060
1061         tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
1062                 OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
1063                 OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
1064         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
1065         omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
1066
1067         tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1068         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
1069         omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
1070
1071         omap2_mcspi_set_master_mode(master);
1072         omap2_mcspi_disable_clocks(mcspi);
1073         return 0;
1074 }
1075
1076 static u8 __initdata spi1_rxdma_id [] = {
1077         OMAP24XX_DMA_SPI1_RX0,
1078         OMAP24XX_DMA_SPI1_RX1,
1079         OMAP24XX_DMA_SPI1_RX2,
1080         OMAP24XX_DMA_SPI1_RX3,
1081 };
1082
1083 static u8 __initdata spi1_txdma_id [] = {
1084         OMAP24XX_DMA_SPI1_TX0,
1085         OMAP24XX_DMA_SPI1_TX1,
1086         OMAP24XX_DMA_SPI1_TX2,
1087         OMAP24XX_DMA_SPI1_TX3,
1088 };
1089
1090 static u8 __initdata spi2_rxdma_id[] = {
1091         OMAP24XX_DMA_SPI2_RX0,
1092         OMAP24XX_DMA_SPI2_RX1,
1093 };
1094
1095 static u8 __initdata spi2_txdma_id[] = {
1096         OMAP24XX_DMA_SPI2_TX0,
1097         OMAP24XX_DMA_SPI2_TX1,
1098 };
1099
1100 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1101         || defined(CONFIG_ARCH_OMAP4)
1102 static u8 __initdata spi3_rxdma_id[] = {
1103         OMAP24XX_DMA_SPI3_RX0,
1104         OMAP24XX_DMA_SPI3_RX1,
1105 };
1106
1107 static u8 __initdata spi3_txdma_id[] = {
1108         OMAP24XX_DMA_SPI3_TX0,
1109         OMAP24XX_DMA_SPI3_TX1,
1110 };
1111 #endif
1112
1113 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1114 static u8 __initdata spi4_rxdma_id[] = {
1115         OMAP34XX_DMA_SPI4_RX0,
1116 };
1117
1118 static u8 __initdata spi4_txdma_id[] = {
1119         OMAP34XX_DMA_SPI4_TX0,
1120 };
1121 #endif
1122
1123 static int __init omap2_mcspi_probe(struct platform_device *pdev)
1124 {
1125         struct spi_master       *master;
1126         struct omap2_mcspi      *mcspi;
1127         struct resource         *r;
1128         int                     status = 0, i;
1129         const u8                *rxdma_id, *txdma_id;
1130         unsigned                num_chipselect;
1131
1132         switch (pdev->id) {
1133         case 1:
1134                 rxdma_id = spi1_rxdma_id;
1135                 txdma_id = spi1_txdma_id;
1136                 num_chipselect = 4;
1137                 break;
1138         case 2:
1139                 rxdma_id = spi2_rxdma_id;
1140                 txdma_id = spi2_txdma_id;
1141                 num_chipselect = 2;
1142                 break;
1143 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1144         || defined(CONFIG_ARCH_OMAP4)
1145         case 3:
1146                 rxdma_id = spi3_rxdma_id;
1147                 txdma_id = spi3_txdma_id;
1148                 num_chipselect = 2;
1149                 break;
1150 #endif
1151 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1152         case 4:
1153                 rxdma_id = spi4_rxdma_id;
1154                 txdma_id = spi4_txdma_id;
1155                 num_chipselect = 1;
1156                 break;
1157 #endif
1158         default:
1159                 return -EINVAL;
1160         }
1161
1162         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1163         if (master == NULL) {
1164                 dev_dbg(&pdev->dev, "master allocation failed\n");
1165                 return -ENOMEM;
1166         }
1167
1168         /* the spi->mode bits understood by this driver: */
1169         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1170
1171         if (pdev->id != -1)
1172                 master->bus_num = pdev->id;
1173
1174         master->setup = omap2_mcspi_setup;
1175         master->transfer = omap2_mcspi_transfer;
1176         master->cleanup = omap2_mcspi_cleanup;
1177         master->num_chipselect = num_chipselect;
1178
1179         dev_set_drvdata(&pdev->dev, master);
1180
1181         mcspi = spi_master_get_devdata(master);
1182         mcspi->master = master;
1183
1184         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1185         if (r == NULL) {
1186                 status = -ENODEV;
1187                 goto err1;
1188         }
1189         if (!request_mem_region(r->start, (r->end - r->start) + 1,
1190                         dev_name(&pdev->dev))) {
1191                 status = -EBUSY;
1192                 goto err1;
1193         }
1194
1195         mcspi->phys = r->start;
1196         mcspi->base = ioremap(r->start, r->end - r->start + 1);
1197         if (!mcspi->base) {
1198                 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1199                 status = -ENOMEM;
1200                 goto err1aa;
1201         }
1202
1203         INIT_WORK(&mcspi->work, omap2_mcspi_work);
1204
1205         spin_lock_init(&mcspi->lock);
1206         INIT_LIST_HEAD(&mcspi->msg_queue);
1207         INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
1208
1209         mcspi->ick = clk_get(&pdev->dev, "ick");
1210         if (IS_ERR(mcspi->ick)) {
1211                 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1212                 status = PTR_ERR(mcspi->ick);
1213                 goto err1a;
1214         }
1215         mcspi->fck = clk_get(&pdev->dev, "fck");
1216         if (IS_ERR(mcspi->fck)) {
1217                 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1218                 status = PTR_ERR(mcspi->fck);
1219                 goto err2;
1220         }
1221
1222         mcspi->dma_channels = kcalloc(master->num_chipselect,
1223                         sizeof(struct omap2_mcspi_dma),
1224                         GFP_KERNEL);
1225
1226         if (mcspi->dma_channels == NULL)
1227                 goto err3;
1228
1229         for (i = 0; i < num_chipselect; i++) {
1230                 mcspi->dma_channels[i].dma_rx_channel = -1;
1231                 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
1232                 mcspi->dma_channels[i].dma_tx_channel = -1;
1233                 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
1234         }
1235
1236         if (omap2_mcspi_reset(mcspi) < 0)
1237                 goto err4;
1238
1239         status = spi_register_master(master);
1240         if (status < 0)
1241                 goto err4;
1242
1243         return status;
1244
1245 err4:
1246         kfree(mcspi->dma_channels);
1247 err3:
1248         clk_put(mcspi->fck);
1249 err2:
1250         clk_put(mcspi->ick);
1251 err1a:
1252         iounmap(mcspi->base);
1253 err1aa:
1254         release_mem_region(r->start, (r->end - r->start) + 1);
1255 err1:
1256         spi_master_put(master);
1257         return status;
1258 }
1259
1260 static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1261 {
1262         struct spi_master       *master;
1263         struct omap2_mcspi      *mcspi;
1264         struct omap2_mcspi_dma  *dma_channels;
1265         struct resource         *r;
1266         void __iomem *base;
1267
1268         master = dev_get_drvdata(&pdev->dev);
1269         mcspi = spi_master_get_devdata(master);
1270         dma_channels = mcspi->dma_channels;
1271
1272         clk_put(mcspi->fck);
1273         clk_put(mcspi->ick);
1274
1275         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1276         release_mem_region(r->start, (r->end - r->start) + 1);
1277
1278         base = mcspi->base;
1279         spi_unregister_master(master);
1280         iounmap(base);
1281         kfree(dma_channels);
1282
1283         return 0;
1284 }
1285
1286 /* work with hotplug and coldplug */
1287 MODULE_ALIAS("platform:omap2_mcspi");
1288
1289 static struct platform_driver omap2_mcspi_driver = {
1290         .driver = {
1291                 .name =         "omap2_mcspi",
1292                 .owner =        THIS_MODULE,
1293         },
1294         .remove =       __exit_p(omap2_mcspi_remove),
1295 };
1296
1297
1298 static int __init omap2_mcspi_init(void)
1299 {
1300         omap2_mcspi_wq = create_singlethread_workqueue(
1301                                 omap2_mcspi_driver.driver.name);
1302         if (omap2_mcspi_wq == NULL)
1303                 return -1;
1304         return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1305 }
1306 subsys_initcall(omap2_mcspi_init);
1307
1308 static void __exit omap2_mcspi_exit(void)
1309 {
1310         platform_driver_unregister(&omap2_mcspi_driver);
1311
1312         destroy_workqueue(omap2_mcspi_wq);
1313 }
1314 module_exit(omap2_mcspi_exit);
1315
1316 MODULE_LICENSE("GPL");