drivers/spi/davinci_spi.c

   1 /*
   2  * Copyright (C) 2009 Texas Instruments.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  17  */
  18
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/gpio.h>
  22 #include <linux/module.h>
  23 #include <linux/delay.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/err.h>
  26 #include <linux/clk.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/spi/spi.h>
  29 #include <linux/spi/spi_bitbang.h>
  30 #include <linux/slab.h>
  31
  32 #include <mach/spi.h>
  33 #include <mach/edma.h>
  34
  35 #define SPI_NO_RESOURCE         ((resource_size_t)-1)
  36
  37 #define SPI_MAX_CHIPSELECT      2
  38
  39 #define CS_DEFAULT      0xFF
  40
  41 #define SPI_BUFSIZ      (SMP_CACHE_BYTES + 1)
  42
  43 #define SPIFMT_PHASE_MASK       BIT(16)
  44 #define SPIFMT_POLARITY_MASK    BIT(17)
  45 #define SPIFMT_DISTIMER_MASK    BIT(18)
  46 #define SPIFMT_SHIFTDIR_MASK    BIT(20)
  47 #define SPIFMT_WAITENA_MASK     BIT(21)
  48 #define SPIFMT_PARITYENA_MASK   BIT(22)
  49 #define SPIFMT_ODD_PARITY_MASK  BIT(23)
  50 #define SPIFMT_WDELAY_MASK      0x3f000000u
  51 #define SPIFMT_WDELAY_SHIFT     24
  52 #define SPIFMT_PRESCALE_SHIFT   8
  53
  54
  55 /* SPIPC0 */
  56 #define SPIPC0_DIFUN_MASK       BIT(11)         /* MISO */
  57 #define SPIPC0_DOFUN_MASK       BIT(10)         /* MOSI */
  58 #define SPIPC0_CLKFUN_MASK      BIT(9)          /* CLK */
  59 #define SPIPC0_SPIENA_MASK      BIT(8)          /* nREADY */
  60
  61 #define SPIINT_MASKALL          0x0101035F
  62 #define SPIINT_MASKINT          0x0000015F
  63 #define SPI_INTLVL_1            0x000001FF
  64 #define SPI_INTLVL_0            0x00000000
  65
  66 /* SPIDAT1 (upper 16 bit defines) */
  67 #define SPIDAT1_CSHOLD_MASK     BIT(12)
  68
  69 /* SPIGCR1 */
  70 #define SPIGCR1_CLKMOD_MASK     BIT(1)
  71 #define SPIGCR1_MASTER_MASK     BIT(0)
  72 #define SPIGCR1_LOOPBACK_MASK   BIT(16)
  73 #define SPIGCR1_SPIENA_MASK     BIT(24)
  74
  75 /* SPIBUF */
  76 #define SPIBUF_TXFULL_MASK      BIT(29)
  77 #define SPIBUF_RXEMPTY_MASK     BIT(31)
  78
  79 /* SPIDELAY */
  80 #define SPIDELAY_C2TDELAY_SHIFT 24
  81 #define SPIDELAY_C2TDELAY_MASK  (0xFF << SPIDELAY_C2TDELAY_SHIFT)
  82 #define SPIDELAY_T2CDELAY_SHIFT 16
  83 #define SPIDELAY_T2CDELAY_MASK  (0xFF << SPIDELAY_T2CDELAY_SHIFT)
  84 #define SPIDELAY_T2EDELAY_SHIFT 8
  85 #define SPIDELAY_T2EDELAY_MASK  (0xFF << SPIDELAY_T2EDELAY_SHIFT)
  86 #define SPIDELAY_C2EDELAY_SHIFT 0
  87 #define SPIDELAY_C2EDELAY_MASK  0xFF
  88
  89 /* Error Masks */
  90 #define SPIFLG_DLEN_ERR_MASK            BIT(0)
  91 #define SPIFLG_TIMEOUT_MASK             BIT(1)
  92 #define SPIFLG_PARERR_MASK              BIT(2)
  93 #define SPIFLG_DESYNC_MASK              BIT(3)
  94 #define SPIFLG_BITERR_MASK              BIT(4)
  95 #define SPIFLG_OVRRUN_MASK              BIT(6)
  96 #define SPIFLG_BUF_INIT_ACTIVE_MASK     BIT(24)
  97 #define SPIFLG_ERROR_MASK               (SPIFLG_DLEN_ERR_MASK \
  98                                 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
  99                                 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
 100                                 | SPIFLG_OVRRUN_MASK)
 101
 102 #define SPIINT_DMA_REQ_EN       BIT(16)
 103
 104 /* SPI Controller registers */
 105 #define SPIGCR0         0x00
 106 #define SPIGCR1         0x04
 107 #define SPIINT          0x08
 108 #define SPILVL          0x0c
 109 #define SPIFLG          0x10
 110 #define SPIPC0          0x14
 111 #define SPIDAT1         0x3c
 112 #define SPIBUF          0x40
 113 #define SPIDELAY        0x48
 114 #define SPIDEF          0x4c
 115 #define SPIFMT0         0x50
 116
 117 /* We have 2 DMA channels per CS, one for RX and one for TX */
 118 struct davinci_spi_dma {
 119         int                     dma_tx_channel;
 120         int                     dma_rx_channel;
 121         int                     dma_tx_sync_dev;
 122         int                     dma_rx_sync_dev;
 123         enum dma_event_q        eventq;
 124
 125         struct completion       dma_tx_completion;
 126         struct completion       dma_rx_completion;
 127 };
 128
 129 /* SPI Controller driver's private data. */
 130 struct davinci_spi {
 131         struct spi_bitbang      bitbang;
 132         struct clk              *clk;
 133
 134         u8                      version;
 135         resource_size_t         pbase;
 136         void __iomem            *base;
 137         size_t                  region_size;
 138         u32                     irq;
 139         struct completion       done;
 140
 141         const void              *tx;
 142         void                    *rx;
 143         u8                      *tmp_buf;
 144         int                     rcount;
 145         int                     wcount;
 146         struct davinci_spi_dma  *dma_channels;
 147         struct davinci_spi_platform_data *pdata;
 148
 149         void                    (*get_rx)(u32 rx_data, struct davinci_spi *);
 150         u32                     (*get_tx)(struct davinci_spi *);
 151
 152         u8                      bytes_per_word[SPI_MAX_CHIPSELECT];
 153 };
 154
 155 static struct davinci_spi_config davinci_spi_default_cfg;
 156
 157 static unsigned use_dma;
 158
 159 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
 160 {
 161         if (davinci_spi->rx) {
 162                 u8 *rx = davinci_spi->rx;
 163                 *rx++ = (u8)data;
 164                 davinci_spi->rx = rx;
 165         }
 166 }
 167
 168 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
 169 {
 170         if (davinci_spi->rx) {
 171                 u16 *rx = davinci_spi->rx;
 172                 *rx++ = (u16)data;
 173                 davinci_spi->rx = rx;
 174         }
 175 }
 176
 177 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
 178 {
 179         u32 data = 0;
 180         if (davinci_spi->tx) {
 181                 const u8 *tx = davinci_spi->tx;
 182                 data = *tx++;
 183                 davinci_spi->tx = tx;
 184         }
 185         return data;
 186 }
 187
 188 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
 189 {
 190         u32 data = 0;
 191         if (davinci_spi->tx) {
 192                 const u16 *tx = davinci_spi->tx;
 193                 data = *tx++;
 194                 davinci_spi->tx = tx;
 195         }
 196         return data;
 197 }
 198
 199 static inline void set_io_bits(void __iomem *addr, u32 bits)
 200 {
 201         u32 v = ioread32(addr);
 202
 203         v |= bits;
 204         iowrite32(v, addr);
 205 }
 206
 207 static inline void clear_io_bits(void __iomem *addr, u32 bits)
 208 {
 209         u32 v = ioread32(addr);
 210
 211         v &= ~bits;
 212         iowrite32(v, addr);
 213 }
 214
 215 static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
 216 {
 217         struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
 218
 219         if (enable)
 220                 set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
 221         else
 222                 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
 223 }
 224
 225 /*
 226  * Interface to control the chip select signal
 227  */
 228 static void davinci_spi_chipselect(struct spi_device *spi, int value)
 229 {
 230         struct davinci_spi *davinci_spi;
 231         struct davinci_spi_platform_data *pdata;
 232         u8 chip_sel = spi->chip_select;
 233         u16 spidat1_cfg = CS_DEFAULT;
 234         bool gpio_chipsel = false;
 235
 236         davinci_spi = spi_master_get_devdata(spi->master);
 237         pdata = davinci_spi->pdata;
 238
 239         if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
 240                                 pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
 241                 gpio_chipsel = true;
 242
 243         /*
 244          * Board specific chip select logic decides the polarity and cs
 245          * line for the controller
 246          */
 247         if (gpio_chipsel) {
 248                 if (value == BITBANG_CS_ACTIVE)
 249                         gpio_set_value(pdata->chip_sel[chip_sel], 0);
 250                 else
 251                         gpio_set_value(pdata->chip_sel[chip_sel], 1);
 252         } else {
 253                 if (value == BITBANG_CS_ACTIVE) {
 254                         spidat1_cfg |= SPIDAT1_CSHOLD_MASK;
 255                         spidat1_cfg &= ~(0x1 << chip_sel);
 256                 }
 257
 258                 iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2);
 259         }
 260 }
 261
 262 /**
 263  * davinci_spi_get_prescale - Calculates the correct prescale value
 264  * @maxspeed_hz: the maximum rate the SPI clock can run at
 265  *
 266  * This function calculates the prescale value that generates a clock rate
 267  * less than or equal to the specified maximum.
 268  *
 269  * Returns: calculated prescale - 1 for easy programming into SPI registers
 270  * or negative error number if valid prescalar cannot be updated.
 271  */
 272 static inline int davinci_spi_get_prescale(struct davinci_spi *davinci_spi,
 273                                                         u32 max_speed_hz)
 274 {
 275         int ret;
 276
 277         ret = DIV_ROUND_UP(clk_get_rate(davinci_spi->clk), max_speed_hz);
 278
 279         if (ret < 3 || ret > 256)
 280                 return -EINVAL;
 281
 282         return ret - 1;
 283 }
 284
 285 /**
 286  * davinci_spi_setup_transfer - This functions will determine transfer method
 287  * @spi: spi device on which data transfer to be done
 288  * @t: spi transfer in which transfer info is filled
 289  *
 290  * This function determines data transfer method (8/16/32 bit transfer).
 291  * It will also set the SPI Clock Control register according to
 292  * SPI slave device freq.
 293  */
 294 static int davinci_spi_setup_transfer(struct spi_device *spi,
 295                 struct spi_transfer *t)
 296 {
 297
 298         struct davinci_spi *davinci_spi;
 299         struct davinci_spi_config *spicfg;
 300         u8 bits_per_word = 0;
 301         u32 hz = 0, spifmt = 0, prescale = 0;
 302
 303         davinci_spi = spi_master_get_devdata(spi->master);
 304         spicfg = (struct davinci_spi_config *)spi->controller_data;
 305         if (!spicfg)
 306                 spicfg = &davinci_spi_default_cfg;
 307
 308         if (t) {
 309                 bits_per_word = t->bits_per_word;
 310                 hz = t->speed_hz;
 311         }
 312
 313         /* if bits_per_word is not set then set it default */
 314         if (!bits_per_word)
 315                 bits_per_word = spi->bits_per_word;
 316
 317         /*
 318          * Assign function pointer to appropriate transfer method
 319          * 8bit, 16bit or 32bit transfer
 320          */
 321         if (bits_per_word <= 8 && bits_per_word >= 2) {
 322                 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
 323                 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
 324                 davinci_spi->bytes_per_word[spi->chip_select] = 1;
 325         } else if (bits_per_word <= 16 && bits_per_word >= 2) {
 326                 davinci_spi->get_rx = davinci_spi_rx_buf_u16;
 327                 davinci_spi->get_tx = davinci_spi_tx_buf_u16;
 328                 davinci_spi->bytes_per_word[spi->chip_select] = 2;
 329         } else
 330                 return -EINVAL;
 331
 332         if (!hz)
 333                 hz = spi->max_speed_hz;
 334
 335         /* Set up SPIFMTn register, unique to this chipselect. */
 336
 337         prescale = davinci_spi_get_prescale(davinci_spi, hz);
 338         if (prescale < 0)
 339                 return prescale;
 340
 341         spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
 342
 343         if (spi->mode & SPI_LSB_FIRST)
 344                 spifmt |= SPIFMT_SHIFTDIR_MASK;
 345
 346         if (spi->mode & SPI_CPOL)
 347                 spifmt |= SPIFMT_POLARITY_MASK;
 348
 349         if (!(spi->mode & SPI_CPHA))
 350                 spifmt |= SPIFMT_PHASE_MASK;
 351
 352         /*
 353          * Version 1 hardware supports two basic SPI modes:
 354          *  - Standard SPI mode uses 4 pins, with chipselect
 355          *  - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
 356          *      (distinct from SPI_3WIRE, with just one data wire;
 357          *      or similar variants without MOSI or without MISO)
 358          *
 359          * Version 2 hardware supports an optional handshaking signal,
 360          * so it can support two more modes:
 361          *  - 5 pin SPI variant is standard SPI plus SPI_READY
 362          *  - 4 pin with enable is (SPI_READY | SPI_NO_CS)
 363          */
 364
 365         if (davinci_spi->version == SPI_VERSION_2) {
 366
 367                 u32 delay = 0;
 368
 369                 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
 370                                                         & SPIFMT_WDELAY_MASK);
 371
 372                 if (spicfg->odd_parity)
 373                         spifmt |= SPIFMT_ODD_PARITY_MASK;
 374
 375                 if (spicfg->parity_enable)
 376                         spifmt |= SPIFMT_PARITYENA_MASK;
 377
 378                 if (spicfg->timer_disable) {
 379                         spifmt |= SPIFMT_DISTIMER_MASK;
 380                 } else {
 381                         delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
 382                                                 & SPIDELAY_C2TDELAY_MASK;
 383                         delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
 384                                                 & SPIDELAY_T2CDELAY_MASK;
 385                 }
 386
 387                 if (spi->mode & SPI_READY) {
 388                         spifmt |= SPIFMT_WAITENA_MASK;
 389                         delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
 390                                                 & SPIDELAY_T2EDELAY_MASK;
 391                         delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
 392                                                 & SPIDELAY_C2EDELAY_MASK;
 393                 }
 394
 395                 iowrite32(delay, davinci_spi->base + SPIDELAY);
 396         }
 397
 398         iowrite32(spifmt, davinci_spi->base + SPIFMT0);
 399
 400         return 0;
 401 }
 402
 403 static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
 404 {
 405         struct spi_device *spi = (struct spi_device *)data;
 406         struct davinci_spi *davinci_spi;
 407         struct davinci_spi_dma *davinci_spi_dma;
 408
 409         davinci_spi = spi_master_get_devdata(spi->master);
 410         davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
 411
 412         if (ch_status == DMA_COMPLETE)
 413                 edma_stop(davinci_spi_dma->dma_rx_channel);
 414         else
 415                 edma_clean_channel(davinci_spi_dma->dma_rx_channel);
 416
 417         complete(&davinci_spi_dma->dma_rx_completion);
 418         /* We must disable the DMA RX request */
 419         davinci_spi_set_dma_req(spi, 0);
 420 }
 421
 422 static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data)
 423 {
 424         struct spi_device *spi = (struct spi_device *)data;
 425         struct davinci_spi *davinci_spi;
 426         struct davinci_spi_dma *davinci_spi_dma;
 427
 428         davinci_spi = spi_master_get_devdata(spi->master);
 429         davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
 430
 431         if (ch_status == DMA_COMPLETE)
 432                 edma_stop(davinci_spi_dma->dma_tx_channel);
 433         else
 434                 edma_clean_channel(davinci_spi_dma->dma_tx_channel);
 435
 436         complete(&davinci_spi_dma->dma_tx_completion);
 437         /* We must disable the DMA TX request */
 438         davinci_spi_set_dma_req(spi, 0);
 439 }
 440
 441 static int davinci_spi_request_dma(struct spi_device *spi)
 442 {
 443         struct davinci_spi *davinci_spi;
 444         struct davinci_spi_dma *davinci_spi_dma;
 445         struct device *sdev;
 446         int r;
 447
 448         davinci_spi = spi_master_get_devdata(spi->master);
 449         davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
 450         sdev = davinci_spi->bitbang.master->dev.parent;
 451
 452         r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev,
 453                                 davinci_spi_dma_rx_callback, spi,
 454                                 davinci_spi_dma->eventq);
 455         if (r < 0) {
 456                 dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n");
 457                 return -EAGAIN;
 458         }
 459         davinci_spi_dma->dma_rx_channel = r;
 460         r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev,
 461                                 davinci_spi_dma_tx_callback, spi,
 462                                 davinci_spi_dma->eventq);
 463         if (r < 0) {
 464                 edma_free_channel(davinci_spi_dma->dma_rx_channel);
 465                 davinci_spi_dma->dma_rx_channel = -1;
 466                 dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n");
 467                 return -EAGAIN;
 468         }
 469         davinci_spi_dma->dma_tx_channel = r;
 470
 471         return 0;
 472 }
 473
 474 /**
 475  * davinci_spi_setup - This functions will set default transfer method
 476  * @spi: spi device on which data transfer to be done
 477  *
 478  * This functions sets the default transfer method.
 479  */
 480 static int davinci_spi_setup(struct spi_device *spi)
 481 {
 482         int retval;
 483         struct davinci_spi *davinci_spi;
 484         struct davinci_spi_dma *davinci_spi_dma;
 485
 486         davinci_spi = spi_master_get_devdata(spi->master);
 487
 488         /* if bits per word length is zero then set it default 8 */
 489         if (!spi->bits_per_word)
 490                 spi->bits_per_word = 8;
 491
 492         if (use_dma && davinci_spi->dma_channels) {
 493                 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
 494
 495                 if ((davinci_spi_dma->dma_rx_channel == -1)
 496                                 || (davinci_spi_dma->dma_tx_channel == -1)) {
 497                         retval = davinci_spi_request_dma(spi);
 498                         if (retval < 0)
 499                                 return retval;
 500                 }
 501         }
 502
 503         retval = davinci_spi_setup_transfer(spi, NULL);
 504
 505         return retval;
 506 }
 507
 508 static void davinci_spi_cleanup(struct spi_device *spi)
 509 {
 510         struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
 511         struct davinci_spi_dma *davinci_spi_dma;
 512
 513         davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
 514
 515         if (use_dma && davinci_spi->dma_channels) {
 516                 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
 517
 518                 if ((davinci_spi_dma->dma_rx_channel != -1)
 519                                 && (davinci_spi_dma->dma_tx_channel != -1)) {
 520                         edma_free_channel(davinci_spi_dma->dma_tx_channel);
 521                         edma_free_channel(davinci_spi_dma->dma_rx_channel);
 522                 }
 523         }
 524 }
 525
 526 static int davinci_spi_bufs_prep(struct spi_device *spi,
 527                                  struct davinci_spi *davinci_spi)
 528 {
 529         struct davinci_spi_platform_data *pdata;
 530         int op_mode = 0;
 531
 532         /*
 533          * REVISIT  unless devices disagree about SPI_LOOP or
 534          * SPI_READY (SPI_NO_CS only allows one device!), this
 535          * should not need to be done before each message...
 536          * optimize for both flags staying cleared.
 537          */
 538
 539         if (!(spi->mode & SPI_NO_CS)) {
 540                 pdata = davinci_spi->pdata;
 541                 if (!pdata->chip_sel ||
 542                      pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)
 543                         op_mode |= 1 << spi->chip_select;
 544         }
 545         if (spi->mode & SPI_READY)
 546                 op_mode |= SPIPC0_SPIENA_MASK;
 547
 548         iowrite32(op_mode, davinci_spi->base + SPIPC0);
 549
 550         if (spi->mode & SPI_LOOP)
 551                 set_io_bits(davinci_spi->base + SPIGCR1,
 552                                 SPIGCR1_LOOPBACK_MASK);
 553         else
 554                 clear_io_bits(davinci_spi->base + SPIGCR1,
 555                                 SPIGCR1_LOOPBACK_MASK);
 556
 557         return 0;
 558 }
 559
 560 static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
 561                                    int int_status)
 562 {
 563         struct device *sdev = davinci_spi->bitbang.master->dev.parent;
 564
 565         if (int_status & SPIFLG_TIMEOUT_MASK) {
 566                 dev_dbg(sdev, "SPI Time-out Error\n");
 567                 return -ETIMEDOUT;
 568         }
 569         if (int_status & SPIFLG_DESYNC_MASK) {
 570                 dev_dbg(sdev, "SPI Desynchronization Error\n");
 571                 return -EIO;
 572         }
 573         if (int_status & SPIFLG_BITERR_MASK) {
 574                 dev_dbg(sdev, "SPI Bit error\n");
 575                 return -EIO;
 576         }
 577
 578         if (davinci_spi->version == SPI_VERSION_2) {
 579                 if (int_status & SPIFLG_DLEN_ERR_MASK) {
 580                         dev_dbg(sdev, "SPI Data Length Error\n");
 581                         return -EIO;
 582                 }
 583                 if (int_status & SPIFLG_PARERR_MASK) {
 584                         dev_dbg(sdev, "SPI Parity Error\n");
 585                         return -EIO;
 586                 }
 587                 if (int_status & SPIFLG_OVRRUN_MASK) {
 588                         dev_dbg(sdev, "SPI Data Overrun error\n");
 589                         return -EIO;
 590                 }
 591                 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
 592                         dev_dbg(sdev, "SPI Buffer Init Active\n");
 593                         return -EBUSY;
 594                 }
 595         }
 596
 597         return 0;
 598 }
 599
 600 /**
 601  * davinci_spi_process_events - check for and handle any SPI controller events
 602  * @davinci_spi: the controller data
 603  *
 604  * This function will check the SPIFLG register and handle any events that are
 605  * detected there
 606  */
 607 static int davinci_spi_process_events(struct davinci_spi *davinci_spi)
 608 {
 609         u32 buf, status, errors = 0, data1_reg_val;
 610
 611         buf = ioread32(davinci_spi->base + SPIBUF);
 612
 613         if (davinci_spi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
 614                 davinci_spi->get_rx(buf & 0xFFFF, davinci_spi);
 615                 davinci_spi->rcount--;
 616         }
 617
 618         status = ioread32(davinci_spi->base + SPIFLG);
 619
 620         if (unlikely(status & SPIFLG_ERROR_MASK)) {
 621                 errors = status & SPIFLG_ERROR_MASK;
 622                 goto out;
 623         }
 624
 625         if (davinci_spi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
 626                 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
 627                 davinci_spi->wcount--;
 628                 data1_reg_val &= ~0xFFFF;
 629                 data1_reg_val |= 0xFFFF & davinci_spi->get_tx(davinci_spi);
 630                 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
 631         }
 632
 633 out:
 634         return errors;
 635 }
 636
 637 /**
 638  * davinci_spi_bufs - functions which will handle transfer data
 639  * @spi: spi device on which data transfer to be done
 640  * @t: spi transfer in which transfer info is filled
 641  *
 642  * This function will put data to be transferred into data register
 643  * of SPI controller and then wait until the completion will be marked
 644  * by the IRQ Handler.
 645  */
 646 static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
 647 {
 648         struct davinci_spi *davinci_spi;
 649         int ret;
 650         u32 tx_data, data1_reg_val;
 651         u32 errors = 0;
 652         struct davinci_spi_config *spicfg;
 653         struct davinci_spi_platform_data *pdata;
 654
 655         davinci_spi = spi_master_get_devdata(spi->master);
 656         pdata = davinci_spi->pdata;
 657         spicfg = (struct davinci_spi_config *)spi->controller_data;
 658         if (!spicfg)
 659                 spicfg = &davinci_spi_default_cfg;
 660
 661         davinci_spi->tx = t->tx_buf;
 662         davinci_spi->rx = t->rx_buf;
 663         davinci_spi->wcount = t->len /
 664                                 davinci_spi->bytes_per_word[spi->chip_select];
 665         davinci_spi->rcount = davinci_spi->wcount;
 666
 667         ret = davinci_spi_bufs_prep(spi, davinci_spi);
 668         if (ret)
 669                 return ret;
 670
 671         data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
 672
 673         /* Enable SPI */
 674         set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
 675
 676         if (spicfg->io_type == SPI_IO_TYPE_INTR) {
 677                 set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT);
 678                 INIT_COMPLETION(davinci_spi->done);
 679         }
 680
 681         /* start the transfer */
 682         davinci_spi->wcount--;
 683         tx_data = davinci_spi->get_tx(davinci_spi);
 684         data1_reg_val &= 0xFFFF0000;
 685         data1_reg_val |= tx_data & 0xFFFF;
 686         iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
 687
 688         /* Wait for the transfer to complete */
 689         if (spicfg->io_type == SPI_IO_TYPE_INTR) {
 690                 wait_for_completion_interruptible(&(davinci_spi->done));
 691         } else {
 692                 while (davinci_spi->rcount > 0 || davinci_spi->wcount > 0) {
 693                         errors = davinci_spi_process_events(davinci_spi);
 694                         if (errors)
 695                                 break;
 696                         cpu_relax();
 697                 }
 698         }
 699
 700         clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
 701
 702         /*
 703          * Check for bit error, desync error,parity error,timeout error and
 704          * receive overflow errors
 705          */
 706         if (errors) {
 707                 ret = davinci_spi_check_error(davinci_spi, errors);
 708                 WARN(!ret, "%s: error reported but no error found!\n",
 709                                                         dev_name(&spi->dev));
 710                 return ret;
 711         }
 712
 713         return t->len;
 714 }
 715
 716 /**
 717  * davinci_spi_irq - Interrupt handler for SPI Master Controller
 718  * @irq: IRQ number for this SPI Master
 719  * @context_data: structure for SPI Master controller davinci_spi
 720  *
 721  * ISR will determine that interrupt arrives either for READ or WRITE command.
 722  * According to command it will do the appropriate action. It will check
 723  * transfer length and if it is not zero then dispatch transfer command again.
 724  * If transfer length is zero then it will indicate the COMPLETION so that
 725  * davinci_spi_bufs function can go ahead.
 726  */
 727 static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
 728 {
 729         struct davinci_spi *davinci_spi = context_data;
 730         int status;
 731
 732         status = davinci_spi_process_events(davinci_spi);
 733         if (unlikely(status != 0))
 734                 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT);
 735
 736         if ((!davinci_spi->rcount && !davinci_spi->wcount) || status)
 737                 complete(&davinci_spi->done);
 738
 739         return IRQ_HANDLED;
 740 }
 741
 742 static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
 743 {
 744         struct davinci_spi *davinci_spi;
 745         int int_status = 0;
 746         int count, temp_count;
 747         u32 data1_reg_val;
 748         struct davinci_spi_dma *davinci_spi_dma;
 749         int data_type, ret;
 750         unsigned long tx_reg, rx_reg;
 751         struct device *sdev;
 752
 753         davinci_spi = spi_master_get_devdata(spi->master);
 754         sdev = davinci_spi->bitbang.master->dev.parent;
 755
 756         davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
 757
 758         tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
 759         rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
 760
 761         davinci_spi->tx = t->tx_buf;
 762         davinci_spi->rx = t->rx_buf;
 763
 764         /* convert len to words based on bits_per_word */
 765         data_type = davinci_spi->bytes_per_word[spi->chip_select];
 766
 767         data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
 768
 769         init_completion(&davinci_spi_dma->dma_rx_completion);
 770         init_completion(&davinci_spi_dma->dma_tx_completion);
 771
 772         ret = davinci_spi_bufs_prep(spi, davinci_spi);
 773         if (ret)
 774                 return ret;
 775
 776         count = t->len / data_type;     /* the number of elements */
 777
 778         /* disable all interrupts for dma transfers */
 779         clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
 780         /* Enable SPI */
 781         set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
 782
 783         if (t->tx_buf) {
 784                 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
 785                                 DMA_TO_DEVICE);
 786                 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
 787                         dev_dbg(sdev, "Unable to DMA map a %d bytes"
 788                                 " TX buffer\n", count);
 789                         return -ENOMEM;
 790                 }
 791                 temp_count = count;
 792         } else {
 793                 /* We need TX clocking for RX transaction */
 794                 t->tx_dma = dma_map_single(&spi->dev,
 795                                 (void *)davinci_spi->tmp_buf, count + 1,
 796                                 DMA_TO_DEVICE);
 797                 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
 798                         dev_dbg(sdev, "Unable to DMA map a %d bytes"
 799                                 " TX tmp buffer\n", count);
 800                         return -ENOMEM;
 801                 }
 802                 temp_count = count + 1;
 803         }
 804
 805         edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
 806                                         data_type, temp_count, 1, 0, ASYNC);
 807         edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
 808         edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
 809         edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
 810         edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
 811
 812         if (t->rx_buf) {
 813                 /* initiate transaction */
 814                 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
 815
 816                 t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count,
 817                                 DMA_FROM_DEVICE);
 818                 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
 819                         dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
 820                                         count);
 821                         if (t->tx_buf != NULL)
 822                                 dma_unmap_single(NULL, t->tx_dma,
 823                                                  count, DMA_TO_DEVICE);
 824                         return -ENOMEM;
 825                 }
 826                 edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
 827                                 data_type, count, 1, 0, ASYNC);
 828                 edma_set_src(davinci_spi_dma->dma_rx_channel,
 829                                 rx_reg, INCR, W8BIT);
 830                 edma_set_dest(davinci_spi_dma->dma_rx_channel,
 831                                 t->rx_dma, INCR, W8BIT);
 832                 edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
 833                 edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
 834                                 data_type, 0);
 835         }
 836
 837         if ((t->tx_buf) || (t->rx_buf))
 838                 edma_start(davinci_spi_dma->dma_tx_channel);
 839
 840         if (t->rx_buf)
 841                 edma_start(davinci_spi_dma->dma_rx_channel);
 842
 843         if ((t->rx_buf) || (t->tx_buf))
 844                 davinci_spi_set_dma_req(spi, 1);
 845
 846         if (t->tx_buf)
 847                 wait_for_completion_interruptible(
 848                                 &davinci_spi_dma->dma_tx_completion);
 849
 850         if (t->rx_buf)
 851                 wait_for_completion_interruptible(
 852                                 &davinci_spi_dma->dma_rx_completion);
 853
 854         dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE);
 855
 856         if (t->rx_buf)
 857                 dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE);
 858
 859         /*
 860          * Check for bit error, desync error,parity error,timeout error and
 861          * receive overflow errors
 862          */
 863         int_status = ioread32(davinci_spi->base + SPIFLG);
 864
 865         ret = davinci_spi_check_error(davinci_spi, int_status);
 866         if (ret != 0)
 867                 return ret;
 868
 869         return t->len;
 870 }
 871
 872 /**
 873  * davinci_spi_probe - probe function for SPI Master Controller
 874  * @pdev: platform_device structure which contains plateform specific data
 875  */
 876 static int davinci_spi_probe(struct platform_device *pdev)
 877 {
 878         struct spi_master *master;
 879         struct davinci_spi *davinci_spi;
 880         struct davinci_spi_platform_data *pdata;
 881         struct resource *r, *mem;
 882         resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
 883         resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
 884         resource_size_t dma_eventq = SPI_NO_RESOURCE;
 885         int i = 0, ret = 0;
 886         u32 spipc0;
 887
 888         pdata = pdev->dev.platform_data;
 889         if (pdata == NULL) {
 890                 ret = -ENODEV;
 891                 goto err;
 892         }
 893
 894         master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
 895         if (master == NULL) {
 896                 ret = -ENOMEM;
 897                 goto err;
 898         }
 899
 900         dev_set_drvdata(&pdev->dev, master);
 901
 902         davinci_spi = spi_master_get_devdata(master);
 903         if (davinci_spi == NULL) {
 904                 ret = -ENOENT;
 905                 goto free_master;
 906         }
 907
 908         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 909         if (r == NULL) {
 910                 ret = -ENOENT;
 911                 goto free_master;
 912         }
 913
 914         davinci_spi->pbase = r->start;
 915         davinci_spi->region_size = resource_size(r);
 916         davinci_spi->pdata = pdata;
 917
 918         mem = request_mem_region(r->start, davinci_spi->region_size,
 919                                         pdev->name);
 920         if (mem == NULL) {
 921                 ret = -EBUSY;
 922                 goto free_master;
 923         }
 924
 925         davinci_spi->base = ioremap(r->start, davinci_spi->region_size);
 926         if (davinci_spi->base == NULL) {
 927                 ret = -ENOMEM;
 928                 goto release_region;
 929         }
 930
 931         davinci_spi->irq = platform_get_irq(pdev, 0);
 932         if (davinci_spi->irq <= 0) {
 933                 ret = -EINVAL;
 934                 goto unmap_io;
 935         }
 936
 937         ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0,
 938                                         dev_name(&pdev->dev), davinci_spi);
 939         if (ret)
 940                 goto unmap_io;
 941
 942         /* Allocate tmp_buf for tx_buf */
 943         davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
 944         if (davinci_spi->tmp_buf == NULL) {
 945                 ret = -ENOMEM;
 946                 goto irq_free;
 947         }
 948
 949         davinci_spi->bitbang.master = spi_master_get(master);
 950         if (davinci_spi->bitbang.master == NULL) {
 951                 ret = -ENODEV;
 952                 goto free_tmp_buf;
 953         }
 954
 955         davinci_spi->clk = clk_get(&pdev->dev, NULL);
 956         if (IS_ERR(davinci_spi->clk)) {
 957                 ret = -ENODEV;
 958                 goto put_master;
 959         }
 960         clk_enable(davinci_spi->clk);
 961
 962         master->bus_num = pdev->id;
 963         master->num_chipselect = pdata->num_chipselect;
 964         master->setup = davinci_spi_setup;
 965         master->cleanup = davinci_spi_cleanup;
 966
 967         davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
 968         davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
 969
 970         davinci_spi->version = pdata->version;
 971         use_dma = pdata->use_dma;
 972
 973         davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
 974         if (davinci_spi->version == SPI_VERSION_2)
 975                 davinci_spi->bitbang.flags |= SPI_READY;
 976
 977         if (use_dma) {
 978                 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 979                 if (r)
 980                         dma_rx_chan = r->start;
 981                 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
 982                 if (r)
 983                         dma_tx_chan = r->start;
 984                 r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
 985                 if (r)
 986                         dma_eventq = r->start;
 987         }
 988
 989         if (!use_dma ||
 990             dma_rx_chan == SPI_NO_RESOURCE ||
 991             dma_tx_chan == SPI_NO_RESOURCE ||
 992             dma_eventq  == SPI_NO_RESOURCE) {
 993                 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
 994                 use_dma = 0;
 995         } else {
 996                 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
 997                 davinci_spi->dma_channels = kzalloc(master->num_chipselect
 998                                 * sizeof(struct davinci_spi_dma), GFP_KERNEL);
 999                 if (davinci_spi->dma_channels == NULL) {
1000                         ret = -ENOMEM;
1001                         goto free_clk;
1002                 }
1003
1004                 for (i = 0; i < master->num_chipselect; i++) {
1005                         davinci_spi->dma_channels[i].dma_rx_channel = -1;
1006                         davinci_spi->dma_channels[i].dma_rx_sync_dev =
1007                                 dma_rx_chan;
1008                         davinci_spi->dma_channels[i].dma_tx_channel = -1;
1009                         davinci_spi->dma_channels[i].dma_tx_sync_dev =
1010                                 dma_tx_chan;
1011                         davinci_spi->dma_channels[i].eventq = dma_eventq;
1012                 }
1013                 dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
1014                                 "Using RX channel = %d , TX channel = %d and "
1015                                 "event queue = %d", dma_rx_chan, dma_tx_chan,
1016                                 dma_eventq);
1017         }
1018
1019         davinci_spi->get_rx = davinci_spi_rx_buf_u8;
1020         davinci_spi->get_tx = davinci_spi_tx_buf_u8;
1021
1022         init_completion(&davinci_spi->done);
1023
1024         /* Reset In/OUT SPI module */
1025         iowrite32(0, davinci_spi->base + SPIGCR0);
1026         udelay(100);
1027         iowrite32(1, davinci_spi->base + SPIGCR0);
1028
1029         /* Set up SPIPC0.  CS and ENA init is done in davinci_spi_bufs_prep */
1030         spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
1031         iowrite32(spipc0, davinci_spi->base + SPIPC0);
1032
1033         /* initialize chip selects */
1034         if (pdata->chip_sel) {
1035                 for (i = 0; i < pdata->num_chipselect; i++) {
1036                         if (pdata->chip_sel[i] != SPI_INTERN_CS)
1037                                 gpio_direction_output(pdata->chip_sel[i], 1);
1038                 }
1039         }
1040
1041         /* Clock internal */
1042         if (davinci_spi->pdata->clk_internal)
1043                 set_io_bits(davinci_spi->base + SPIGCR1,
1044                                 SPIGCR1_CLKMOD_MASK);
1045         else
1046                 clear_io_bits(davinci_spi->base + SPIGCR1,
1047                                 SPIGCR1_CLKMOD_MASK);
1048
1049         if (pdata->intr_line)
1050                 iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
1051         else
1052                 iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
1053
1054         iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF);
1055
1056         /* master mode default */
1057         set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1058
1059         ret = spi_bitbang_start(&davinci_spi->bitbang);
1060         if (ret)
1061                 goto free_clk;
1062
1063         dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base);
1064
1065         return ret;
1066
1067 free_clk:
1068         clk_disable(davinci_spi->clk);
1069         clk_put(davinci_spi->clk);
1070 put_master:
1071         spi_master_put(master);
1072 free_tmp_buf:
1073         kfree(davinci_spi->tmp_buf);
1074 irq_free:
1075         free_irq(davinci_spi->irq, davinci_spi);
1076 unmap_io:
1077         iounmap(davinci_spi->base);
1078 release_region:
1079         release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1080 free_master:
1081         kfree(master);
1082 err:
1083         return ret;
1084 }
1085
1086 /**
1087  * davinci_spi_remove - remove function for SPI Master Controller
1088  * @pdev: platform_device structure which contains plateform specific data
1089  *
1090  * This function will do the reverse action of davinci_spi_probe function
1091  * It will free the IRQ and SPI controller's memory region.
1092  * It will also call spi_bitbang_stop to destroy the work queue which was
1093  * created by spi_bitbang_start.
1094  */
1095 static int __exit davinci_spi_remove(struct platform_device *pdev)
1096 {
1097         struct davinci_spi *davinci_spi;
1098         struct spi_master *master;
1099
1100         master = dev_get_drvdata(&pdev->dev);
1101         davinci_spi = spi_master_get_devdata(master);
1102
1103         spi_bitbang_stop(&davinci_spi->bitbang);
1104
1105         clk_disable(davinci_spi->clk);
1106         clk_put(davinci_spi->clk);
1107         spi_master_put(master);
1108         kfree(davinci_spi->tmp_buf);
1109         free_irq(davinci_spi->irq, davinci_spi);
1110         iounmap(davinci_spi->base);
1111         release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1112
1113         return 0;
1114 }
1115
1116 static struct platform_driver davinci_spi_driver = {
1117         .driver.name = "spi_davinci",
1118         .remove = __exit_p(davinci_spi_remove),
1119 };
1120
1121 static int __init davinci_spi_init(void)
1122 {
1123         return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe);
1124 }
1125 module_init(davinci_spi_init);
1126
1127 static void __exit davinci_spi_exit(void)
1128 {
1129         platform_driver_unregister(&davinci_spi_driver);
1130 }
1131 module_exit(davinci_spi_exit);
1132
1133 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1134 MODULE_LICENSE("GPL");