2 * Pinmuxed GPIO support for SuperH.
4 * Copyright (C) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/errno.h>
13 #include <linux/kernel.h>
14 #include <linux/list.h>
15 #include <linux/module.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
19 #include <linux/irq.h>
20 #include <linux/bitops.h>
21 #include <linux/gpio.h>
23 static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
25 if (enum_id < r->begin)
34 static unsigned long gpio_read_raw_reg(unsigned long reg,
35 unsigned long reg_width)
39 return __raw_readb(reg);
41 return __raw_readw(reg);
43 return __raw_readl(reg);
50 static void gpio_write_raw_reg(unsigned long reg,
51 unsigned long reg_width,
56 __raw_writeb(data, reg);
59 __raw_writew(data, reg);
62 __raw_writel(data, reg);
69 static void gpio_write_bit(struct pinmux_data_reg *dr,
70 unsigned long in_pos, unsigned long value)
74 pos = dr->reg_width - (in_pos + 1);
76 pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
78 dr->reg, !!value, pos, dr->reg_width);
81 set_bit(pos, &dr->reg_shadow);
83 clear_bit(pos, &dr->reg_shadow);
85 gpio_write_raw_reg(dr->reg, dr->reg_width, dr->reg_shadow);
88 static int gpio_read_reg(unsigned long reg, unsigned long reg_width,
89 unsigned long field_width, unsigned long in_pos)
91 unsigned long data, mask, pos;
94 mask = (1 << field_width) - 1;
95 pos = reg_width - ((in_pos + 1) * field_width);
97 pr_debug("read_reg: addr = %lx, pos = %ld, "
98 "r_width = %ld, f_width = %ld\n",
99 reg, pos, reg_width, field_width);
101 data = gpio_read_raw_reg(reg, reg_width);
102 return (data >> pos) & mask;
105 static void gpio_write_reg(unsigned long reg, unsigned long reg_width,
106 unsigned long field_width, unsigned long in_pos,
109 unsigned long mask, pos;
111 mask = (1 << field_width) - 1;
112 pos = reg_width - ((in_pos + 1) * field_width);
114 pr_debug("write_reg addr = %lx, value = %ld, pos = %ld, "
115 "r_width = %ld, f_width = %ld\n",
116 reg, value, pos, reg_width, field_width);
118 mask = ~(mask << pos);
119 value = value << pos;
123 __raw_writeb((__raw_readb(reg) & mask) | value, reg);
126 __raw_writew((__raw_readw(reg) & mask) | value, reg);
129 __raw_writel((__raw_readl(reg) & mask) | value, reg);
134 static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
136 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
137 struct pinmux_data_reg *data_reg;
140 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
145 data_reg = gpioc->data_regs + k;
147 if (!data_reg->reg_width)
150 for (n = 0; n < data_reg->reg_width; n++) {
151 if (data_reg->enum_ids[n] == gpiop->enum_id) {
152 gpiop->flags &= ~PINMUX_FLAG_DREG;
153 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
154 gpiop->flags &= ~PINMUX_FLAG_DBIT;
155 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
167 static void setup_data_regs(struct pinmux_info *gpioc)
169 struct pinmux_data_reg *drp;
172 for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
173 setup_data_reg(gpioc, k);
177 drp = gpioc->data_regs + k;
182 drp->reg_shadow = gpio_read_raw_reg(drp->reg, drp->reg_width);
187 static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
188 struct pinmux_data_reg **drp, int *bitp)
190 struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
193 if (!enum_in_range(gpiop->enum_id, &gpioc->data))
196 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
197 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
198 *drp = gpioc->data_regs + k;
203 static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
204 struct pinmux_cfg_reg **crp, int *indexp,
205 unsigned long **cntp)
207 struct pinmux_cfg_reg *config_reg;
208 unsigned long r_width, f_width;
213 config_reg = gpioc->cfg_regs + k;
215 r_width = config_reg->reg_width;
216 f_width = config_reg->field_width;
220 for (n = 0; n < (r_width / f_width) * (1 << f_width); n++) {
221 if (config_reg->enum_ids[n] == enum_id) {
224 *cntp = &config_reg->cnt[n / (1 << f_width)];
234 static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
235 int pos, pinmux_enum_t *enum_idp)
237 pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
238 pinmux_enum_t *data = gpioc->gpio_data;
241 if (!enum_in_range(enum_id, &gpioc->data)) {
242 if (!enum_in_range(enum_id, &gpioc->mark)) {
243 pr_err("non data/mark enum_id for gpio %d\n", gpio);
249 *enum_idp = data[pos + 1];
253 for (k = 0; k < gpioc->gpio_data_size; k++) {
254 if (data[k] == enum_id) {
255 *enum_idp = data[k + 1];
260 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
264 static void write_config_reg(struct pinmux_info *gpioc,
265 struct pinmux_cfg_reg *crp,
268 unsigned long ncomb, pos, value;
270 ncomb = 1 << crp->field_width;
272 value = index % ncomb;
274 gpio_write_reg(crp->reg, crp->reg_width, crp->field_width, pos, value);
277 static int check_config_reg(struct pinmux_info *gpioc,
278 struct pinmux_cfg_reg *crp,
281 unsigned long ncomb, pos, value;
283 ncomb = 1 << crp->field_width;
285 value = index % ncomb;
287 if (gpio_read_reg(crp->reg, crp->reg_width,
288 crp->field_width, pos) == value)
294 enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
296 static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
297 int pinmux_type, int cfg_mode)
299 struct pinmux_cfg_reg *cr = NULL;
300 pinmux_enum_t enum_id;
301 struct pinmux_range *range;
302 int in_range, pos, index;
305 switch (pinmux_type) {
307 case PINMUX_TYPE_FUNCTION:
311 case PINMUX_TYPE_OUTPUT:
312 range = &gpioc->output;
315 case PINMUX_TYPE_INPUT:
316 range = &gpioc->input;
319 case PINMUX_TYPE_INPUT_PULLUP:
320 range = &gpioc->input_pu;
323 case PINMUX_TYPE_INPUT_PULLDOWN:
324 range = &gpioc->input_pd;
335 pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
342 /* first check if this is a function enum */
343 in_range = enum_in_range(enum_id, &gpioc->function);
345 /* not a function enum */
348 * other range exists, so this pin is
349 * a regular GPIO pin that now is being
350 * bound to a specific direction.
352 * for this case we only allow function enums
353 * and the enums that match the other range.
355 in_range = enum_in_range(enum_id, range);
358 * special case pass through for fixed
359 * input-only or output-only pins without
360 * function enum register association.
362 if (in_range && enum_id == range->force)
366 * no other range exists, so this pin
367 * must then be of the function type.
369 * allow function type pins to select
370 * any combination of function/in/out
371 * in their MARK lists.
380 if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0)
384 case GPIO_CFG_DRYRUN:
385 if (!*cntp || !check_config_reg(gpioc, cr, index))
390 write_config_reg(gpioc, cr, index);
405 static DEFINE_SPINLOCK(gpio_lock);
407 static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
409 return container_of(chip, struct pinmux_info, chip);
412 static int sh_gpio_request(struct gpio_chip *chip, unsigned offset)
414 struct pinmux_info *gpioc = chip_to_pinmux(chip);
415 struct pinmux_data_reg *dummy;
417 int i, ret, pinmux_type;
424 spin_lock_irqsave(&gpio_lock, flags);
426 if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
429 /* setup pin function here if no data is associated with pin */
431 if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
432 pinmux_type = PINMUX_TYPE_FUNCTION;
434 pinmux_type = PINMUX_TYPE_GPIO;
436 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
437 if (pinmux_config_gpio(gpioc, offset,
439 GPIO_CFG_DRYRUN) != 0)
442 if (pinmux_config_gpio(gpioc, offset,
448 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
449 gpioc->gpios[offset].flags |= pinmux_type;
453 spin_unlock_irqrestore(&gpio_lock, flags);
458 static void sh_gpio_free(struct gpio_chip *chip, unsigned offset)
460 struct pinmux_info *gpioc = chip_to_pinmux(chip);
467 spin_lock_irqsave(&gpio_lock, flags);
469 pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
470 pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
471 gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
472 gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;
474 spin_unlock_irqrestore(&gpio_lock, flags);
477 static int pinmux_direction(struct pinmux_info *gpioc,
478 unsigned gpio, int new_pinmux_type)
486 pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
488 switch (pinmux_type) {
489 case PINMUX_TYPE_GPIO:
491 case PINMUX_TYPE_OUTPUT:
492 case PINMUX_TYPE_INPUT:
493 case PINMUX_TYPE_INPUT_PULLUP:
494 case PINMUX_TYPE_INPUT_PULLDOWN:
495 pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
501 if (pinmux_config_gpio(gpioc, gpio,
503 GPIO_CFG_DRYRUN) != 0)
506 if (pinmux_config_gpio(gpioc, gpio,
511 gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
512 gpioc->gpios[gpio].flags |= new_pinmux_type;
519 static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
521 struct pinmux_info *gpioc = chip_to_pinmux(chip);
525 spin_lock_irqsave(&gpio_lock, flags);
526 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
527 spin_unlock_irqrestore(&gpio_lock, flags);
532 static void sh_gpio_set_value(struct pinmux_info *gpioc,
533 unsigned gpio, int value)
535 struct pinmux_data_reg *dr = NULL;
538 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
541 gpio_write_bit(dr, bit, value);
544 static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
547 struct pinmux_info *gpioc = chip_to_pinmux(chip);
551 sh_gpio_set_value(gpioc, offset, value);
552 spin_lock_irqsave(&gpio_lock, flags);
553 ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
554 spin_unlock_irqrestore(&gpio_lock, flags);
559 static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
561 struct pinmux_data_reg *dr = NULL;
564 if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
567 return gpio_read_reg(dr->reg, dr->reg_width, 1, bit);
570 static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
572 return sh_gpio_get_value(chip_to_pinmux(chip), offset);
575 static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
577 sh_gpio_set_value(chip_to_pinmux(chip), offset, value);
580 static int sh_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
582 struct pinmux_info *gpioc = chip_to_pinmux(chip);
583 pinmux_enum_t enum_id;
584 pinmux_enum_t *enum_ids;
590 pos = get_gpio_enum_id(gpioc, offset, pos, &enum_id);
591 if (pos <= 0 || !enum_id)
594 for (i = 0; i < gpioc->gpio_irq_size; i++) {
595 enum_ids = gpioc->gpio_irq[i].enum_ids;
596 for (k = 0; enum_ids[k]; k++) {
597 if (enum_ids[k] == enum_id)
598 return gpioc->gpio_irq[i].irq;
606 int register_pinmux(struct pinmux_info *pip)
608 struct gpio_chip *chip = &pip->chip;
610 pr_info("%s handling gpio %d -> %d\n",
611 pip->name, pip->first_gpio, pip->last_gpio);
613 setup_data_regs(pip);
615 chip->request = sh_gpio_request;
616 chip->free = sh_gpio_free;
617 chip->direction_input = sh_gpio_direction_input;
618 chip->get = sh_gpio_get;
619 chip->direction_output = sh_gpio_direction_output;
620 chip->set = sh_gpio_set;
621 chip->to_irq = sh_gpio_to_irq;
623 WARN_ON(pip->first_gpio != 0); /* needs testing */
625 chip->label = pip->name;
626 chip->owner = THIS_MODULE;
627 chip->base = pip->first_gpio;
628 chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;
630 return gpiochip_add(chip);
633 int unregister_pinmux(struct pinmux_info *pip)
635 pr_info("%s deregistering\n", pip->name);
637 return gpiochip_remove(&pip->chip);