1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@redhat.com>
18 #include <linux/config.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/errno.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/major.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/ioport.h>
29 #include <linux/circ_buf.h>
30 #include <linux/serial.h>
31 #include <linux/sysrq.h>
32 #include <linux/console.h>
33 #include <linux/spinlock.h>
34 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
40 #include <asm/oplib.h>
43 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
47 #include <linux/serial_core.h>
52 struct uart_sunsab_port {
53 struct uart_port port; /* Generic UART port */
54 union sab82532_async_regs __iomem *regs; /* Chip registers */
55 unsigned long irqflags; /* IRQ state flags */
56 int dsr; /* Current DSR state */
57 unsigned int cec_timeout; /* Chip poll timeout... */
58 unsigned int tec_timeout; /* likewise */
59 unsigned char interrupt_mask0;/* ISR0 masking */
60 unsigned char interrupt_mask1;/* ISR1 masking */
61 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
62 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
63 int type; /* SAB82532 version */
65 /* Setting configuration bits while the transmitter is active
66 * can cause garbage characters to get emitted by the chip.
67 * Therefore, we cache such writes here and do the real register
68 * write the next time the transmitter becomes idle.
70 unsigned int cached_ebrg;
71 unsigned char cached_mode;
72 unsigned char cached_pvr;
73 unsigned char cached_dafo;
77 * This assumes you have a 29.4912 MHz clock for your UART.
79 #define SAB_BASE_BAUD ( 29491200 / 16 )
81 static char *sab82532_version[16] = {
82 "V1.0", "V2.0", "V3.2", "V(0x03)",
83 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
84 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
85 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
88 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
89 #define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
91 #define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
92 #define SAB82532_XMIT_FIFO_SIZE 32
94 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
96 int timeout = up->tec_timeout;
98 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
102 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
104 int timeout = up->cec_timeout;
106 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
110 static struct tty_struct *
111 receive_chars(struct uart_sunsab_port *up,
112 union sab82532_irq_status *stat,
113 struct pt_regs *regs)
115 struct tty_struct *tty = NULL;
116 unsigned char buf[32];
117 int saw_console_brk = 0;
122 if (up->port.info != NULL) /* Unopened serial console */
123 tty = up->port.info->tty;
125 /* Read number of BYTES (Character + Status) available. */
126 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
127 count = SAB82532_RECV_FIFO_SIZE;
131 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
132 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
136 /* Issue a FIFO read command in case we where idle. */
137 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
139 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
143 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
147 for (i = 0; i < count; i++)
148 buf[i] = readb(&up->regs->r.rfifo[i]);
150 /* Issue Receive Message Complete command. */
153 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
156 /* Count may be zero for BRK, so we check for it here */
157 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
158 (up->port.line == up->port.cons->index))
161 for (i = 0; i < count; i++) {
162 unsigned char ch = buf[i], flag;
165 uart_handle_sysrq_char(&up->port, ch, regs);
170 up->port.icount.rx++;
172 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
174 SAB82532_ISR0_RFO)) ||
175 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
177 * For statistics only
179 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
180 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
182 up->port.icount.brk++;
184 * We do the SysRQ and SAK checking
185 * here because otherwise the break
186 * may get masked by ignore_status_mask
187 * or read_status_mask.
189 if (uart_handle_break(&up->port))
191 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
192 up->port.icount.parity++;
193 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
194 up->port.icount.frame++;
195 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
196 up->port.icount.overrun++;
199 * Mask off conditions which should be ingored.
201 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
202 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
204 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
206 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
208 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
212 if (uart_handle_sysrq_char(&up->port, ch, regs))
215 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
216 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
217 tty_insert_flip_char(tty, ch, flag);
218 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
219 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
228 static void sunsab_stop_tx(struct uart_port *);
229 static void sunsab_tx_idle(struct uart_sunsab_port *);
231 static void transmit_chars(struct uart_sunsab_port *up,
232 union sab82532_irq_status *stat)
234 struct circ_buf *xmit = &up->port.info->xmit;
237 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
238 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
239 writeb(up->interrupt_mask1, &up->regs->w.imr1);
240 set_bit(SAB82532_ALLS, &up->irqflags);
243 #if 0 /* bde@nwlink.com says this check causes problems */
244 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
248 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
251 set_bit(SAB82532_XPR, &up->irqflags);
254 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
255 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
256 writeb(up->interrupt_mask1, &up->regs->w.imr1);
260 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
261 writeb(up->interrupt_mask1, &up->regs->w.imr1);
262 clear_bit(SAB82532_ALLS, &up->irqflags);
264 /* Stuff 32 bytes into Transmit FIFO. */
265 clear_bit(SAB82532_XPR, &up->irqflags);
266 for (i = 0; i < up->port.fifosize; i++) {
267 writeb(xmit->buf[xmit->tail],
268 &up->regs->w.xfifo[i]);
269 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
270 up->port.icount.tx++;
271 if (uart_circ_empty(xmit))
275 /* Issue a Transmit Frame command. */
277 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
279 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
280 uart_write_wakeup(&up->port);
282 if (uart_circ_empty(xmit))
283 sunsab_stop_tx(&up->port);
286 static void check_status(struct uart_sunsab_port *up,
287 union sab82532_irq_status *stat)
289 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
290 uart_handle_dcd_change(&up->port,
291 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
293 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
294 uart_handle_cts_change(&up->port,
295 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
297 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
298 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
299 up->port.icount.dsr++;
302 wake_up_interruptible(&up->port.info->delta_msr_wait);
305 static irqreturn_t sunsab_interrupt(int irq, void *dev_id, struct pt_regs *regs)
307 struct uart_sunsab_port *up = dev_id;
308 struct tty_struct *tty;
309 union sab82532_irq_status status;
312 spin_lock_irqsave(&up->port.lock, flags);
315 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA0)
316 status.sreg.isr0 = readb(&up->regs->r.isr0);
317 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA1)
318 status.sreg.isr1 = readb(&up->regs->r.isr1);
322 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
323 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
324 (status.sreg.isr1 & SAB82532_ISR1_BRK))
325 tty = receive_chars(up, &status, regs);
326 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
327 (status.sreg.isr1 & SAB82532_ISR1_CSC))
328 check_status(up, &status);
329 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
330 transmit_chars(up, &status);
333 spin_unlock(&up->port.lock);
336 tty_flip_buffer_push(tty);
340 spin_lock(&up->port.lock);
343 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB0)
344 status.sreg.isr0 = readb(&up->regs->r.isr0);
345 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB1)
346 status.sreg.isr1 = readb(&up->regs->r.isr1);
350 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
351 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
352 (status.sreg.isr1 & SAB82532_ISR1_BRK))
354 tty = receive_chars(up, &status, regs);
355 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
356 (status.sreg.isr1 & (SAB82532_ISR1_BRK | SAB82532_ISR1_CSC)))
357 check_status(up, &status);
358 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
359 transmit_chars(up, &status);
362 spin_unlock_irqrestore(&up->port.lock, flags);
365 tty_flip_buffer_push(tty);
370 /* port->lock is not held. */
371 static unsigned int sunsab_tx_empty(struct uart_port *port)
373 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
376 /* Do not need a lock for a state test like this. */
377 if (test_bit(SAB82532_ALLS, &up->irqflags))
385 /* port->lock held by caller. */
386 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
388 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
390 if (mctrl & TIOCM_RTS) {
391 up->cached_mode &= ~SAB82532_MODE_FRTS;
392 up->cached_mode |= SAB82532_MODE_RTS;
394 up->cached_mode |= (SAB82532_MODE_FRTS |
397 if (mctrl & TIOCM_DTR) {
398 up->cached_pvr &= ~(up->pvr_dtr_bit);
400 up->cached_pvr |= up->pvr_dtr_bit;
403 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
404 if (test_bit(SAB82532_XPR, &up->irqflags))
408 /* port->lock is held by caller and interrupts are disabled. */
409 static unsigned int sunsab_get_mctrl(struct uart_port *port)
411 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
417 val = readb(&up->regs->r.pvr);
418 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
420 val = readb(&up->regs->r.vstr);
421 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
423 val = readb(&up->regs->r.star);
424 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
429 /* port->lock held by caller. */
430 static void sunsab_stop_tx(struct uart_port *port)
432 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
434 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
435 writeb(up->interrupt_mask1, &up->regs->w.imr1);
438 /* port->lock held by caller. */
439 static void sunsab_tx_idle(struct uart_sunsab_port *up)
441 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
444 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
445 writeb(up->cached_mode, &up->regs->rw.mode);
446 writeb(up->cached_pvr, &up->regs->rw.pvr);
447 writeb(up->cached_dafo, &up->regs->w.dafo);
449 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
450 tmp = readb(&up->regs->rw.ccr2);
452 tmp |= (up->cached_ebrg >> 2) & 0xc0;
453 writeb(tmp, &up->regs->rw.ccr2);
457 /* port->lock held by caller. */
458 static void sunsab_start_tx(struct uart_port *port)
460 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
461 struct circ_buf *xmit = &up->port.info->xmit;
464 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
465 writeb(up->interrupt_mask1, &up->regs->w.imr1);
467 if (!test_bit(SAB82532_XPR, &up->irqflags))
470 clear_bit(SAB82532_ALLS, &up->irqflags);
471 clear_bit(SAB82532_XPR, &up->irqflags);
473 for (i = 0; i < up->port.fifosize; i++) {
474 writeb(xmit->buf[xmit->tail],
475 &up->regs->w.xfifo[i]);
476 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
477 up->port.icount.tx++;
478 if (uart_circ_empty(xmit))
482 /* Issue a Transmit Frame command. */
484 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
487 /* port->lock is not held. */
488 static void sunsab_send_xchar(struct uart_port *port, char ch)
490 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
493 spin_lock_irqsave(&up->port.lock, flags);
496 writeb(ch, &up->regs->w.tic);
498 spin_unlock_irqrestore(&up->port.lock, flags);
501 /* port->lock held by caller. */
502 static void sunsab_stop_rx(struct uart_port *port)
504 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
506 up->interrupt_mask0 |= SAB82532_ISR0_TCD;
507 writeb(up->interrupt_mask1, &up->regs->w.imr0);
510 /* port->lock held by caller. */
511 static void sunsab_enable_ms(struct uart_port *port)
513 /* For now we always receive these interrupts. */
516 /* port->lock is not held. */
517 static void sunsab_break_ctl(struct uart_port *port, int break_state)
519 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
523 spin_lock_irqsave(&up->port.lock, flags);
525 val = up->cached_dafo;
527 val |= SAB82532_DAFO_XBRK;
529 val &= ~SAB82532_DAFO_XBRK;
530 up->cached_dafo = val;
532 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
533 if (test_bit(SAB82532_XPR, &up->irqflags))
536 spin_unlock_irqrestore(&up->port.lock, flags);
539 /* port->lock is not held. */
540 static int sunsab_startup(struct uart_port *port)
542 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
546 spin_lock_irqsave(&up->port.lock, flags);
549 * Wait for any commands or immediate characters
555 * Clear the FIFO buffers.
557 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
559 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
562 * Clear the interrupt registers.
564 (void) readb(&up->regs->r.isr0);
565 (void) readb(&up->regs->r.isr1);
568 * Now, initialize the UART
570 writeb(0, &up->regs->w.ccr0); /* power-down */
571 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
572 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
573 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
574 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
575 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
576 writeb(0, &up->regs->w.ccr3);
577 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
578 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
580 writeb(up->cached_mode, &up->regs->w.mode);
581 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
583 tmp = readb(&up->regs->rw.ccr0);
584 tmp |= SAB82532_CCR0_PU; /* power-up */
585 writeb(tmp, &up->regs->rw.ccr0);
588 * Finally, enable interrupts
590 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
592 writeb(up->interrupt_mask0, &up->regs->w.imr0);
593 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
594 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
595 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
597 writeb(up->interrupt_mask1, &up->regs->w.imr1);
598 set_bit(SAB82532_ALLS, &up->irqflags);
599 set_bit(SAB82532_XPR, &up->irqflags);
601 spin_unlock_irqrestore(&up->port.lock, flags);
606 /* port->lock is not held. */
607 static void sunsab_shutdown(struct uart_port *port)
609 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
612 spin_lock_irqsave(&up->port.lock, flags);
614 /* Disable Interrupts */
615 up->interrupt_mask0 = 0xff;
616 writeb(up->interrupt_mask0, &up->regs->w.imr0);
617 up->interrupt_mask1 = 0xff;
618 writeb(up->interrupt_mask1, &up->regs->w.imr1);
620 /* Disable break condition */
621 up->cached_dafo = readb(&up->regs->rw.dafo);
622 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
623 writeb(up->cached_dafo, &up->regs->rw.dafo);
625 /* Disable Receiver */
626 up->cached_mode &= ~SAB82532_MODE_RAC;
627 writeb(up->cached_mode, &up->regs->rw.mode);
632 * If the chip is powered down here the system hangs/crashes during
633 * reboot or shutdown. This needs to be investigated further,
634 * similar behaviour occurs in 2.4 when the driver is configured
635 * as a module only. One hint may be that data is sometimes
636 * transmitted at 9600 baud during shutdown (regardless of the
637 * speed the chip was configured for when the port was open).
641 tmp = readb(&up->regs->rw.ccr0);
642 tmp &= ~SAB82532_CCR0_PU;
643 writeb(tmp, &up->regs->rw.ccr0);
646 spin_unlock_irqrestore(&up->port.lock, flags);
650 * This is used to figure out the divisor speeds.
652 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
654 * with 0 <= N < 64 and 0 <= M < 16
657 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
668 * We scale numbers by 10 so that we get better accuracy
669 * without having to use floating point. Here we increment m
670 * until n is within the valid range.
672 n = (SAB_BASE_BAUD * 10) / baud;
680 * We try very hard to avoid speeds with M == 0 since they may
681 * not work correctly for XTAL frequences above 10 MHz.
683 if ((m == 0) && ((n & 1) == 0)) {
691 /* Internal routine, port->lock is held and local interrupts are disabled. */
692 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
693 unsigned int iflag, unsigned int baud,
699 /* Byte size and parity */
700 switch (cflag & CSIZE) {
701 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
702 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
703 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
704 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
705 /* Never happens, but GCC is too dumb to figure it out */
706 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
709 if (cflag & CSTOPB) {
710 dafo |= SAB82532_DAFO_STOP;
714 if (cflag & PARENB) {
715 dafo |= SAB82532_DAFO_PARE;
719 if (cflag & PARODD) {
720 dafo |= SAB82532_DAFO_PAR_ODD;
722 dafo |= SAB82532_DAFO_PAR_EVEN;
724 up->cached_dafo = dafo;
726 calc_ebrg(baud, &n, &m);
728 up->cached_ebrg = n | (m << 6);
730 up->tec_timeout = (10 * 1000000) / baud;
731 up->cec_timeout = up->tec_timeout >> 2;
733 /* CTS flow control flags */
734 /* We encode read_status_mask and ignore_status_mask like so:
736 * ---------------------
737 * | ... | ISR1 | ISR0 |
738 * ---------------------
742 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
743 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
745 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
747 SAB82532_ISR1_XPR) << 8;
749 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
751 if (iflag & (BRKINT | PARMRK))
752 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
755 * Characteres to ignore
757 up->port.ignore_status_mask = 0;
759 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
761 if (iflag & IGNBRK) {
762 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
764 * If we're ignoring parity and break indicators,
765 * ignore overruns too (for real raw support).
768 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
772 * ignore all characters if CREAD is not set
774 if ((cflag & CREAD) == 0)
775 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
778 uart_update_timeout(&up->port, cflag,
779 (up->port.uartclk / (16 * quot)));
781 /* Now schedule a register update when the chip's
782 * transmitter is idle.
784 up->cached_mode |= SAB82532_MODE_RAC;
785 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
786 if (test_bit(SAB82532_XPR, &up->irqflags))
790 /* port->lock is not held. */
791 static void sunsab_set_termios(struct uart_port *port, struct termios *termios,
794 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
796 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
797 unsigned int quot = uart_get_divisor(port, baud);
799 spin_lock_irqsave(&up->port.lock, flags);
800 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
801 spin_unlock_irqrestore(&up->port.lock, flags);
804 static const char *sunsab_type(struct uart_port *port)
806 struct uart_sunsab_port *up = (void *)port;
809 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
813 static void sunsab_release_port(struct uart_port *port)
817 static int sunsab_request_port(struct uart_port *port)
822 static void sunsab_config_port(struct uart_port *port, int flags)
826 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
831 static struct uart_ops sunsab_pops = {
832 .tx_empty = sunsab_tx_empty,
833 .set_mctrl = sunsab_set_mctrl,
834 .get_mctrl = sunsab_get_mctrl,
835 .stop_tx = sunsab_stop_tx,
836 .start_tx = sunsab_start_tx,
837 .send_xchar = sunsab_send_xchar,
838 .stop_rx = sunsab_stop_rx,
839 .enable_ms = sunsab_enable_ms,
840 .break_ctl = sunsab_break_ctl,
841 .startup = sunsab_startup,
842 .shutdown = sunsab_shutdown,
843 .set_termios = sunsab_set_termios,
845 .release_port = sunsab_release_port,
846 .request_port = sunsab_request_port,
847 .config_port = sunsab_config_port,
848 .verify_port = sunsab_verify_port,
851 static struct uart_driver sunsab_reg = {
852 .owner = THIS_MODULE,
853 .driver_name = "serial",
854 .devfs_name = "tts/",
859 static struct uart_sunsab_port *sunsab_ports;
860 static int num_channels;
862 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
864 static __inline__ void sunsab_console_putchar(struct uart_sunsab_port *up, char c)
868 spin_lock_irqsave(&up->port.lock, flags);
871 writeb(c, &up->regs->w.tic);
873 spin_unlock_irqrestore(&up->port.lock, flags);
876 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
878 struct uart_sunsab_port *up = &sunsab_ports[con->index];
881 for (i = 0; i < n; i++) {
883 sunsab_console_putchar(up, '\r');
884 sunsab_console_putchar(up, *s++);
889 static int sunsab_console_setup(struct console *con, char *options)
891 struct uart_sunsab_port *up = &sunsab_ports[con->index];
893 unsigned int baud, quot;
895 printk("Console: ttyS%d (SAB82532)\n",
896 (sunsab_reg.minor - 64) + con->index);
898 sunserial_console_termios(con);
900 /* Firmware console speed is limited to 150-->38400 baud so
901 * this hackish cflag thing is OK.
903 switch (con->cflag & CBAUD) {
904 case B150: baud = 150; break;
905 case B300: baud = 300; break;
906 case B600: baud = 600; break;
907 case B1200: baud = 1200; break;
908 case B2400: baud = 2400; break;
909 case B4800: baud = 4800; break;
910 default: case B9600: baud = 9600; break;
911 case B19200: baud = 19200; break;
912 case B38400: baud = 38400; break;
918 spin_lock_init(&up->port.lock);
921 * Initialize the hardware
923 sunsab_startup(&up->port);
925 spin_lock_irqsave(&up->port.lock, flags);
928 * Finally, enable interrupts
930 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
931 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
932 writeb(up->interrupt_mask0, &up->regs->w.imr0);
933 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
934 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
935 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
937 writeb(up->interrupt_mask1, &up->regs->w.imr1);
939 quot = uart_get_divisor(&up->port, baud);
940 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
941 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
943 spin_unlock_irqrestore(&up->port.lock, flags);
948 static struct console sunsab_console = {
950 .write = sunsab_console_write,
951 .device = uart_console_device,
952 .setup = sunsab_console_setup,
953 .flags = CON_PRINTBUFFER,
957 #define SUNSAB_CONSOLE (&sunsab_console)
959 static void __init sunsab_console_init(void)
963 if (con_is_present())
966 for (i = 0; i < num_channels; i++) {
967 int this_minor = sunsab_reg.minor + i;
969 if ((this_minor - 64) == (serial_console - 1))
972 if (i == num_channels)
975 sunsab_console.index = i;
976 register_console(&sunsab_console);
979 #define SUNSAB_CONSOLE (NULL)
980 #define sunsab_console_init() do { } while (0)
983 static void __init for_each_sab_edev(void (*callback)(struct linux_ebus_device *, void *), void *arg)
985 struct linux_ebus *ebus;
986 struct linux_ebus_device *edev = NULL;
988 for_each_ebus(ebus) {
989 for_each_ebusdev(edev, ebus) {
990 if (!strcmp(edev->prom_name, "se")) {
993 } else if (!strcmp(edev->prom_name, "serial")) {
997 /* On RIO this can be an SE, check it. We could
998 * just check ebus->is_rio, but this is more portable.
1000 clen = prom_getproperty(edev->prom_node, "compatible",
1001 compat, sizeof(compat));
1003 if (strncmp(compat, "sab82532", 8) == 0) {
1004 callback(edev, arg);
1013 static void __init sab_count_callback(struct linux_ebus_device *edev, void *arg)
1020 static void __init sab_attach_callback(struct linux_ebus_device *edev, void *arg)
1022 int *instance_p = arg;
1023 struct uart_sunsab_port *up;
1024 unsigned long regs, offset;
1027 /* Note: ports are located in reverse order */
1028 regs = edev->resource[0].start;
1029 offset = sizeof(union sab82532_async_regs);
1030 for (i = 0; i < 2; i++) {
1031 up = &sunsab_ports[(*instance_p * 2) + 1 - i];
1033 memset(up, 0, sizeof(*up));
1034 up->regs = ioremap(regs + offset, sizeof(union sab82532_async_regs));
1035 up->port.irq = edev->irqs[0];
1036 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
1037 up->port.mapbase = (unsigned long)up->regs;
1038 up->port.iotype = SERIAL_IO_MEM;
1040 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
1042 offset -= sizeof(union sab82532_async_regs);
1048 static int __init probe_for_sabs(void)
1052 /* Find device instances. */
1053 for_each_sab_edev(&sab_count_callback, &this_sab);
1057 /* Allocate tables. */
1058 sunsab_ports = kmalloc(sizeof(struct uart_sunsab_port) * this_sab * 2,
1063 num_channels = this_sab * 2;
1066 for_each_sab_edev(&sab_attach_callback, &this_sab);
1070 static void __init sunsab_init_hw(void)
1074 for (i = 0; i < num_channels; i++) {
1075 struct uart_sunsab_port *up = &sunsab_ports[i];
1078 up->port.ops = &sunsab_pops;
1079 up->port.type = PORT_SUNSAB;
1080 up->port.uartclk = SAB_BASE_BAUD;
1082 up->type = readb(&up->regs->r.vstr) & 0x0f;
1083 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
1084 writeb(0xff, &up->regs->w.pim);
1085 if (up->port.line == 0) {
1086 up->pvr_dsr_bit = (1 << 0);
1087 up->pvr_dtr_bit = (1 << 1);
1089 up->pvr_dsr_bit = (1 << 3);
1090 up->pvr_dtr_bit = (1 << 2);
1092 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
1093 writeb(up->cached_pvr, &up->regs->w.pvr);
1094 up->cached_mode = readb(&up->regs->rw.mode);
1095 up->cached_mode |= SAB82532_MODE_FRTS;
1096 writeb(up->cached_mode, &up->regs->rw.mode);
1097 up->cached_mode |= SAB82532_MODE_RTS;
1098 writeb(up->cached_mode, &up->regs->rw.mode);
1100 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1101 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1103 if (!(up->port.line & 0x01)) {
1104 if (request_irq(up->port.irq, sunsab_interrupt,
1105 SA_SHIRQ, "serial(sab82532)", up)) {
1106 printk("sunsab%d: can't get IRQ %x\n",
1114 static int __init sunsab_init(void)
1116 int ret = probe_for_sabs();
1124 sunsab_reg.minor = sunserial_current_minor;
1125 sunsab_reg.nr = num_channels;
1126 sunsab_reg.cons = SUNSAB_CONSOLE;
1128 ret = uart_register_driver(&sunsab_reg);
1132 for (i = 0; i < num_channels; i++) {
1133 struct uart_sunsab_port *up = &sunsab_ports[i];
1135 if (!(up->port.line & 0x01))
1136 free_irq(up->port.irq, up);
1139 kfree(sunsab_ports);
1140 sunsab_ports = NULL;
1145 sunserial_current_minor += num_channels;
1147 sunsab_console_init();
1149 for (i = 0; i < num_channels; i++) {
1150 struct uart_sunsab_port *up = &sunsab_ports[i];
1152 uart_add_one_port(&sunsab_reg, &up->port);
1158 static void __exit sunsab_exit(void)
1162 for (i = 0; i < num_channels; i++) {
1163 struct uart_sunsab_port *up = &sunsab_ports[i];
1165 uart_remove_one_port(&sunsab_reg, &up->port);
1167 if (!(up->port.line & 0x01))
1168 free_irq(up->port.irq, up);
1172 sunserial_current_minor -= num_channels;
1173 uart_unregister_driver(&sunsab_reg);
1175 kfree(sunsab_ports);
1176 sunsab_ports = NULL;
1179 module_init(sunsab_init);
1180 module_exit(sunsab_exit);
1182 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1183 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1184 MODULE_LICENSE("GPL");