2 * mfd.c: driver for High Speed UART device of Intel Medfield platform
4 * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
6 * (C) Copyright 2010 Intel Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; version 2
15 * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
16 * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
17 * are used for RX, odd chans for TX
19 * 2. In A0 stepping, UART will not support TX half empty flag
21 * 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
22 * asserted, only when the HW is reset the DDCD and DDSR will
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/console.h>
29 #include <linux/sysrq.h>
30 #include <linux/slab.h>
31 #include <linux/serial_reg.h>
32 #include <linux/circ_buf.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/tty.h>
36 #include <linux/tty_flip.h>
37 #include <linux/serial_core.h>
38 #include <linux/serial_mfd.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/pci.h>
42 #include <linux/debugfs.h>
44 #define MFD_HSU_A0_STEPPING 1
46 #define HSU_DMA_BUF_SIZE 2048
48 #define chan_readl(chan, offset) readl(chan->reg + offset)
49 #define chan_writel(chan, offset, val) writel(val, chan->reg + offset)
51 #define mfd_readl(obj, offset) readl(obj->reg + offset)
52 #define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
54 #define HSU_DMA_TIMEOUT_CHECK_FREQ (HZ/10)
56 struct hsu_dma_buffer {
65 enum dma_data_direction dirt;
66 struct uart_hsu_port *uport;
68 struct timer_list rx_timer; /* only needed by RX channel */
71 struct uart_hsu_port {
72 struct uart_port port;
76 unsigned int lsr_break_flag;
81 struct hsu_dma_chan *txc;
82 struct hsu_dma_chan *rxc;
83 struct hsu_dma_buffer txbuf;
84 struct hsu_dma_buffer rxbuf;
85 int use_dma; /* flag for DMA/PIO */
90 /* Top level data structure of HSU */
97 struct uart_hsu_port port[3];
98 struct hsu_dma_chan chans[10];
100 struct dentry *debugfs;
103 static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
107 if (offset > UART_MSR) {
109 val = readl(up->port.membase + offset);
111 val = (unsigned int)readb(up->port.membase + offset);
116 static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
118 if (offset > UART_MSR) {
120 writel(value, up->port.membase + offset);
122 unsigned char val = value & 0xff;
123 writeb(val, up->port.membase + offset);
127 #ifdef CONFIG_DEBUG_FS
129 #define HSU_REGS_BUFSIZE 1024
131 static int hsu_show_regs_open(struct inode *inode, struct file *file)
133 file->private_data = inode->i_private;
137 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
138 size_t count, loff_t *ppos)
140 struct uart_hsu_port *up = file->private_data;
145 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
149 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
150 "MFD HSU port[%d] regs:\n", up->index);
152 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
153 "=================================\n");
154 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
155 "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
156 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
157 "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
158 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
159 "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
160 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
161 "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
162 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
163 "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
164 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
165 "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
166 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
167 "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
168 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
169 "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
170 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
171 "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
172 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
173 "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
175 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
180 static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
181 size_t count, loff_t *ppos)
183 struct hsu_dma_chan *chan = file->private_data;
188 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
192 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
193 "MFD HSU DMA channel [%d] regs:\n", chan->id);
195 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
196 "=================================\n");
197 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
198 "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
199 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
200 "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
201 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
202 "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
203 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
204 "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
205 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
206 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
207 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
208 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
209 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
210 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
211 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
212 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
213 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
214 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
215 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
216 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
217 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
218 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
219 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
220 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
222 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
227 static const struct file_operations port_regs_ops = {
228 .owner = THIS_MODULE,
229 .open = hsu_show_regs_open,
230 .read = port_show_regs,
231 .llseek = default_llseek,
234 static const struct file_operations dma_regs_ops = {
235 .owner = THIS_MODULE,
236 .open = hsu_show_regs_open,
237 .read = dma_show_regs,
238 .llseek = default_llseek,
241 static int hsu_debugfs_init(struct hsu_port *hsu)
246 hsu->debugfs = debugfs_create_dir("hsu", NULL);
250 for (i = 0; i < 3; i++) {
251 snprintf(name, sizeof(name), "port_%d_regs", i);
252 debugfs_create_file(name, S_IFREG | S_IRUGO,
253 hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
256 for (i = 0; i < 6; i++) {
257 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
258 debugfs_create_file(name, S_IFREG | S_IRUGO,
259 hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
265 static void hsu_debugfs_remove(struct hsu_port *hsu)
268 debugfs_remove_recursive(hsu->debugfs);
272 static inline int hsu_debugfs_init(struct hsu_port *hsu)
277 static inline void hsu_debugfs_remove(struct hsu_port *hsu)
280 #endif /* CONFIG_DEBUG_FS */
282 static void serial_hsu_enable_ms(struct uart_port *port)
284 struct uart_hsu_port *up =
285 container_of(port, struct uart_hsu_port, port);
287 up->ier |= UART_IER_MSI;
288 serial_out(up, UART_IER, up->ier);
291 void hsu_dma_tx(struct uart_hsu_port *up)
293 struct circ_buf *xmit = &up->port.state->xmit;
294 struct hsu_dma_buffer *dbuf = &up->txbuf;
297 /* test_and_set_bit may be better, but anyway it's in lock protected mode */
301 /* Update the circ buf info */
302 xmit->tail += dbuf->ofs;
303 xmit->tail &= UART_XMIT_SIZE - 1;
305 up->port.icount.tx += dbuf->ofs;
308 /* Disable the channel */
309 chan_writel(up->txc, HSU_CH_CR, 0x0);
311 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
312 dma_sync_single_for_device(up->port.dev,
317 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
320 /* Reprogram the channel */
321 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
322 chan_writel(up->txc, HSU_CH_D0TSR, count);
324 /* Reenable the channel */
325 chan_writel(up->txc, HSU_CH_DCR, 0x1
330 chan_writel(up->txc, HSU_CH_CR, 0x1);
333 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
334 uart_write_wakeup(&up->port);
337 /* The buffer is already cache coherent */
338 void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
342 chan_writel(rxc, HSU_CH_BSR, 32);
343 chan_writel(rxc, HSU_CH_MOTSR, 4);
345 chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
346 chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
347 chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
349 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
351 chan_writel(rxc, HSU_CH_CR, 0x3);
353 mod_timer(&rxc->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
356 /* Protected by spin_lock_irqsave(port->lock) */
357 static void serial_hsu_start_tx(struct uart_port *port)
359 struct uart_hsu_port *up =
360 container_of(port, struct uart_hsu_port, port);
364 } else if (!(up->ier & UART_IER_THRI)) {
365 up->ier |= UART_IER_THRI;
366 serial_out(up, UART_IER, up->ier);
370 static void serial_hsu_stop_tx(struct uart_port *port)
372 struct uart_hsu_port *up =
373 container_of(port, struct uart_hsu_port, port);
374 struct hsu_dma_chan *txc = up->txc;
377 chan_writel(txc, HSU_CH_CR, 0x0);
378 else if (up->ier & UART_IER_THRI) {
379 up->ier &= ~UART_IER_THRI;
380 serial_out(up, UART_IER, up->ier);
384 /* This is always called in spinlock protected mode, so
385 * modify timeout timer is safe here */
386 void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
388 struct hsu_dma_buffer *dbuf = &up->rxbuf;
389 struct hsu_dma_chan *chan = up->rxc;
390 struct uart_port *port = &up->port;
391 struct tty_struct *tty = port->state->port.tty;
398 * First need to know how many is already transferred,
399 * then check if its a timeout DMA irq, and return
400 * the trail bytes out, push them up and reenable the
404 /* Timeout IRQ, need wait some time, see Errata 2 */
408 /* Stop the channel */
409 chan_writel(chan, HSU_CH_CR, 0x0);
411 count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
413 /* Restart the channel before we leave */
414 chan_writel(chan, HSU_CH_CR, 0x3);
417 del_timer(&chan->rx_timer);
419 dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
420 dbuf->dma_size, DMA_FROM_DEVICE);
423 * Head will only wrap around when we recycle
424 * the DMA buffer, and when that happens, we
425 * explicitly set tail to 0. So head will
426 * always be greater than tail.
428 tty_insert_flip_string(tty, dbuf->buf, count);
429 port->icount.rx += count;
431 dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
432 dbuf->dma_size, DMA_FROM_DEVICE);
434 /* Reprogram the channel */
435 chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
436 chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
437 chan_writel(chan, HSU_CH_DCR, 0x1
440 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
442 tty_flip_buffer_push(tty);
444 chan_writel(chan, HSU_CH_CR, 0x3);
445 chan->rx_timer.expires = jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ;
446 add_timer(&chan->rx_timer);
450 static void serial_hsu_stop_rx(struct uart_port *port)
452 struct uart_hsu_port *up =
453 container_of(port, struct uart_hsu_port, port);
454 struct hsu_dma_chan *chan = up->rxc;
457 chan_writel(chan, HSU_CH_CR, 0x2);
459 up->ier &= ~UART_IER_RLSI;
460 up->port.read_status_mask &= ~UART_LSR_DR;
461 serial_out(up, UART_IER, up->ier);
465 static inline void receive_chars(struct uart_hsu_port *up, int *status)
467 struct tty_struct *tty = up->port.state->port.tty;
468 unsigned int ch, flag;
469 unsigned int max_count = 256;
475 ch = serial_in(up, UART_RX);
477 up->port.icount.rx++;
479 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
480 UART_LSR_FE | UART_LSR_OE))) {
482 dev_warn(up->dev, "We really rush into ERR/BI case"
483 "status = 0x%02x", *status);
484 /* For statistics only */
485 if (*status & UART_LSR_BI) {
486 *status &= ~(UART_LSR_FE | UART_LSR_PE);
487 up->port.icount.brk++;
489 * We do the SysRQ and SAK checking
490 * here because otherwise the break
491 * may get masked by ignore_status_mask
492 * or read_status_mask.
494 if (uart_handle_break(&up->port))
496 } else if (*status & UART_LSR_PE)
497 up->port.icount.parity++;
498 else if (*status & UART_LSR_FE)
499 up->port.icount.frame++;
500 if (*status & UART_LSR_OE)
501 up->port.icount.overrun++;
503 /* Mask off conditions which should be ignored. */
504 *status &= up->port.read_status_mask;
506 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
508 up->port.cons->index == up->port.line) {
509 /* Recover the break flag from console xmit */
510 *status |= up->lsr_break_flag;
511 up->lsr_break_flag = 0;
514 if (*status & UART_LSR_BI) {
516 } else if (*status & UART_LSR_PE)
518 else if (*status & UART_LSR_FE)
522 if (uart_handle_sysrq_char(&up->port, ch))
525 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
527 *status = serial_in(up, UART_LSR);
528 } while ((*status & UART_LSR_DR) && max_count--);
529 tty_flip_buffer_push(tty);
532 static void transmit_chars(struct uart_hsu_port *up)
534 struct circ_buf *xmit = &up->port.state->xmit;
537 if (up->port.x_char) {
538 serial_out(up, UART_TX, up->port.x_char);
539 up->port.icount.tx++;
543 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
544 serial_hsu_stop_tx(&up->port);
548 #ifndef MFD_HSU_A0_STEPPING
549 count = up->port.fifosize / 2;
552 * A0 only supports fully empty IRQ, and the first char written
553 * into it won't clear the EMPT bit, so we may need be cautious
554 * by useing a shorter buffer
556 count = up->port.fifosize - 4;
559 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
560 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
562 up->port.icount.tx++;
563 if (uart_circ_empty(xmit))
565 } while (--count > 0);
567 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
568 uart_write_wakeup(&up->port);
570 if (uart_circ_empty(xmit))
571 serial_hsu_stop_tx(&up->port);
574 static inline void check_modem_status(struct uart_hsu_port *up)
578 status = serial_in(up, UART_MSR);
580 if ((status & UART_MSR_ANY_DELTA) == 0)
583 if (status & UART_MSR_TERI)
584 up->port.icount.rng++;
585 if (status & UART_MSR_DDSR)
586 up->port.icount.dsr++;
587 /* We may only get DDCD when HW init and reset */
588 if (status & UART_MSR_DDCD)
589 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
590 /* Will start/stop_tx accordingly */
591 if (status & UART_MSR_DCTS)
592 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
594 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
598 * This handles the interrupt from one port.
600 static irqreturn_t port_irq(int irq, void *dev_id)
602 struct uart_hsu_port *up = dev_id;
603 unsigned int iir, lsr;
606 if (unlikely(!up->running))
609 spin_lock_irqsave(&up->port.lock, flags);
611 lsr = serial_in(up, UART_LSR);
612 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
613 UART_LSR_FE | UART_LSR_OE)))
615 "Got lsr irq while using DMA, lsr = 0x%2x\n",
617 check_modem_status(up);
618 spin_unlock_irqrestore(&up->port.lock, flags);
622 iir = serial_in(up, UART_IIR);
623 if (iir & UART_IIR_NO_INT) {
624 spin_unlock_irqrestore(&up->port.lock, flags);
628 lsr = serial_in(up, UART_LSR);
629 if (lsr & UART_LSR_DR)
630 receive_chars(up, &lsr);
631 check_modem_status(up);
633 /* lsr will be renewed during the receive_chars */
634 if (lsr & UART_LSR_THRE)
637 spin_unlock_irqrestore(&up->port.lock, flags);
641 static inline void dma_chan_irq(struct hsu_dma_chan *chan)
643 struct uart_hsu_port *up = chan->uport;
647 spin_lock_irqsave(&up->port.lock, flags);
649 if (!up->use_dma || !up->running)
653 * No matter what situation, need read clear the IRQ status
654 * There is a bug, see Errata 5, HSD 2900918
656 int_sts = chan_readl(chan, HSU_CH_SR);
659 if (chan->dirt == DMA_FROM_DEVICE)
660 hsu_dma_rx(up, int_sts);
663 if (chan->dirt == DMA_TO_DEVICE) {
664 chan_writel(chan, HSU_CH_CR, 0x0);
670 spin_unlock_irqrestore(&up->port.lock, flags);
674 static irqreturn_t dma_irq(int irq, void *dev_id)
676 struct hsu_port *hsu = dev_id;
679 int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
681 /* Currently we only have 6 channels may be used */
682 for (i = 0; i < 6; i++) {
684 dma_chan_irq(&hsu->chans[i]);
691 static unsigned int serial_hsu_tx_empty(struct uart_port *port)
693 struct uart_hsu_port *up =
694 container_of(port, struct uart_hsu_port, port);
698 spin_lock_irqsave(&up->port.lock, flags);
699 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
700 spin_unlock_irqrestore(&up->port.lock, flags);
705 static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
707 struct uart_hsu_port *up =
708 container_of(port, struct uart_hsu_port, port);
709 unsigned char status;
712 status = serial_in(up, UART_MSR);
715 if (status & UART_MSR_DCD)
717 if (status & UART_MSR_RI)
719 if (status & UART_MSR_DSR)
721 if (status & UART_MSR_CTS)
726 static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
728 struct uart_hsu_port *up =
729 container_of(port, struct uart_hsu_port, port);
730 unsigned char mcr = 0;
732 if (mctrl & TIOCM_RTS)
734 if (mctrl & TIOCM_DTR)
736 if (mctrl & TIOCM_OUT1)
737 mcr |= UART_MCR_OUT1;
738 if (mctrl & TIOCM_OUT2)
739 mcr |= UART_MCR_OUT2;
740 if (mctrl & TIOCM_LOOP)
741 mcr |= UART_MCR_LOOP;
745 serial_out(up, UART_MCR, mcr);
748 static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
750 struct uart_hsu_port *up =
751 container_of(port, struct uart_hsu_port, port);
754 spin_lock_irqsave(&up->port.lock, flags);
755 if (break_state == -1)
756 up->lcr |= UART_LCR_SBC;
758 up->lcr &= ~UART_LCR_SBC;
759 serial_out(up, UART_LCR, up->lcr);
760 spin_unlock_irqrestore(&up->port.lock, flags);
764 * What special to do:
765 * 1. chose the 64B fifo mode
766 * 2. make sure not to select half empty mode for A0 stepping
767 * 3. start dma or pio depends on configuration
768 * 4. we only allocate dma memory when needed
770 static int serial_hsu_startup(struct uart_port *port)
772 struct uart_hsu_port *up =
773 container_of(port, struct uart_hsu_port, port);
777 * Clear the FIFO buffers and disable them.
778 * (they will be reenabled in set_termios())
780 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
781 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
782 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
783 serial_out(up, UART_FCR, 0);
785 /* Clear the interrupt registers. */
786 (void) serial_in(up, UART_LSR);
787 (void) serial_in(up, UART_RX);
788 (void) serial_in(up, UART_IIR);
789 (void) serial_in(up, UART_MSR);
791 /* Now, initialize the UART, default is 8n1 */
792 serial_out(up, UART_LCR, UART_LCR_WLEN8);
794 spin_lock_irqsave(&up->port.lock, flags);
796 up->port.mctrl |= TIOCM_OUT2;
797 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
800 * Finally, enable interrupts. Note: Modem status interrupts
801 * are set via set_termios(), which will be occurring imminently
802 * anyway, so we don't enable them here.
805 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
808 serial_out(up, UART_IER, up->ier);
810 spin_unlock_irqrestore(&up->port.lock, flags);
814 struct hsu_dma_buffer *dbuf;
815 struct circ_buf *xmit = &port->state->xmit;
819 /* First allocate the RX buffer */
821 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
826 dbuf->dma_addr = dma_map_single(port->dev,
830 dbuf->dma_size = HSU_DMA_BUF_SIZE;
832 /* Start the RX channel right now */
833 hsu_dma_start_rx_chan(up->rxc, dbuf);
835 /* Next init the TX DMA */
837 dbuf->buf = xmit->buf;
838 dbuf->dma_addr = dma_map_single(port->dev,
842 dbuf->dma_size = UART_XMIT_SIZE;
844 /* This should not be changed all around */
845 chan_writel(up->txc, HSU_CH_BSR, 32);
846 chan_writel(up->txc, HSU_CH_MOTSR, 4);
851 /* And clear the interrupt registers again for luck. */
852 (void) serial_in(up, UART_LSR);
853 (void) serial_in(up, UART_RX);
854 (void) serial_in(up, UART_IIR);
855 (void) serial_in(up, UART_MSR);
861 static void serial_hsu_shutdown(struct uart_port *port)
863 struct uart_hsu_port *up =
864 container_of(port, struct uart_hsu_port, port);
867 del_timer_sync(&up->rxc->rx_timer);
869 /* Disable interrupts from this port */
871 serial_out(up, UART_IER, 0);
874 spin_lock_irqsave(&up->port.lock, flags);
875 up->port.mctrl &= ~TIOCM_OUT2;
876 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
877 spin_unlock_irqrestore(&up->port.lock, flags);
879 /* Disable break condition and FIFOs */
880 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
881 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
882 UART_FCR_CLEAR_RCVR |
883 UART_FCR_CLEAR_XMIT);
884 serial_out(up, UART_FCR, 0);
888 serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
889 struct ktermios *old)
891 struct uart_hsu_port *up =
892 container_of(port, struct uart_hsu_port, port);
893 struct tty_struct *tty = port->state->port.tty;
894 unsigned char cval, fcr = 0;
896 unsigned int baud, quot;
900 switch (termios->c_cflag & CSIZE) {
902 cval = UART_LCR_WLEN5;
905 cval = UART_LCR_WLEN6;
908 cval = UART_LCR_WLEN7;
912 cval = UART_LCR_WLEN8;
916 /* CMSPAR isn't supported by this driver */
918 tty->termios->c_cflag &= ~CMSPAR;
920 if (termios->c_cflag & CSTOPB)
921 cval |= UART_LCR_STOP;
922 if (termios->c_cflag & PARENB)
923 cval |= UART_LCR_PARITY;
924 if (!(termios->c_cflag & PARODD))
925 cval |= UART_LCR_EPAR;
928 * For those basic low baud rate we can get the direct
929 * scalar from 2746800, like 115200 = 2746800/24, for those
930 * higher baud rate, we have to handle them case by case,
931 * but DIV reg is never touched as its default value 0x3d09
933 baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
934 quot = uart_get_divisor(port, baud);
961 if ((up->port.uartclk / quot) < (2400 * 16))
962 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
963 else if ((up->port.uartclk / quot) < (230400 * 16))
964 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
966 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
968 fcr |= UART_FCR_HSU_64B_FIFO;
969 #ifdef MFD_HSU_A0_STEPPING
970 /* A0 doesn't support half empty IRQ */
971 fcr |= UART_FCR_FULL_EMPT_TXI;
975 * Ok, we're now changing the port state. Do it with
976 * interrupts disabled.
978 spin_lock_irqsave(&up->port.lock, flags);
980 /* Update the per-port timeout */
981 uart_update_timeout(port, termios->c_cflag, baud);
983 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
984 if (termios->c_iflag & INPCK)
985 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
986 if (termios->c_iflag & (BRKINT | PARMRK))
987 up->port.read_status_mask |= UART_LSR_BI;
989 /* Characters to ignore */
990 up->port.ignore_status_mask = 0;
991 if (termios->c_iflag & IGNPAR)
992 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
993 if (termios->c_iflag & IGNBRK) {
994 up->port.ignore_status_mask |= UART_LSR_BI;
996 * If we're ignoring parity and break indicators,
997 * ignore overruns too (for real raw support).
999 if (termios->c_iflag & IGNPAR)
1000 up->port.ignore_status_mask |= UART_LSR_OE;
1003 /* Ignore all characters if CREAD is not set */
1004 if ((termios->c_cflag & CREAD) == 0)
1005 up->port.ignore_status_mask |= UART_LSR_DR;
1008 * CTS flow control flag and modem status interrupts, disable
1011 up->ier &= ~UART_IER_MSI;
1012 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1013 up->ier |= UART_IER_MSI;
1015 serial_out(up, UART_IER, up->ier);
1017 if (termios->c_cflag & CRTSCTS)
1018 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1020 up->mcr &= ~UART_MCR_AFE;
1022 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1023 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
1024 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
1025 serial_out(up, UART_LCR, cval); /* reset DLAB */
1026 serial_out(up, UART_MUL, mul); /* set MUL */
1027 serial_out(up, UART_PS, ps); /* set PS */
1028 up->lcr = cval; /* Save LCR */
1029 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1030 serial_out(up, UART_FCR, fcr);
1031 spin_unlock_irqrestore(&up->port.lock, flags);
1035 serial_hsu_pm(struct uart_port *port, unsigned int state,
1036 unsigned int oldstate)
1040 static void serial_hsu_release_port(struct uart_port *port)
1044 static int serial_hsu_request_port(struct uart_port *port)
1049 static void serial_hsu_config_port(struct uart_port *port, int flags)
1051 struct uart_hsu_port *up =
1052 container_of(port, struct uart_hsu_port, port);
1053 up->port.type = PORT_MFD;
1057 serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1059 /* We don't want the core code to modify any port params */
1064 serial_hsu_type(struct uart_port *port)
1066 struct uart_hsu_port *up =
1067 container_of(port, struct uart_hsu_port, port);
1071 /* Mainly for uart console use */
1072 static struct uart_hsu_port *serial_hsu_ports[3];
1073 static struct uart_driver serial_hsu_reg;
1075 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1077 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1079 /* Wait for transmitter & holding register to empty */
1080 static inline void wait_for_xmitr(struct uart_hsu_port *up)
1082 unsigned int status, tmout = 1000;
1084 /* Wait up to 1ms for the character to be sent. */
1086 status = serial_in(up, UART_LSR);
1088 if (status & UART_LSR_BI)
1089 up->lsr_break_flag = UART_LSR_BI;
1094 } while (!(status & BOTH_EMPTY));
1096 /* Wait up to 1s for flow control if necessary */
1097 if (up->port.flags & UPF_CONS_FLOW) {
1100 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1105 static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1107 struct uart_hsu_port *up =
1108 container_of(port, struct uart_hsu_port, port);
1111 serial_out(up, UART_TX, ch);
1115 * Print a string to the serial port trying not to disturb
1116 * any possible real use of the port...
1118 * The console_lock must be held when we get here.
1121 serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1123 struct uart_hsu_port *up = serial_hsu_ports[co->index];
1124 unsigned long flags;
1128 local_irq_save(flags);
1131 else if (oops_in_progress) {
1132 locked = spin_trylock(&up->port.lock);
1134 spin_lock(&up->port.lock);
1136 /* First save the IER then disable the interrupts */
1137 ier = serial_in(up, UART_IER);
1138 serial_out(up, UART_IER, 0);
1140 uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1143 * Finally, wait for transmitter to become empty
1144 * and restore the IER
1147 serial_out(up, UART_IER, ier);
1150 spin_unlock(&up->port.lock);
1151 local_irq_restore(flags);
1154 static struct console serial_hsu_console;
1157 serial_hsu_console_setup(struct console *co, char *options)
1159 struct uart_hsu_port *up;
1166 if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1168 up = serial_hsu_ports[co->index];
1173 uart_parse_options(options, &baud, &parity, &bits, &flow);
1175 ret = uart_set_options(&up->port, co, baud, parity, bits, flow);
1180 static struct console serial_hsu_console = {
1182 .write = serial_hsu_console_write,
1183 .device = uart_console_device,
1184 .setup = serial_hsu_console_setup,
1185 .flags = CON_PRINTBUFFER,
1187 .data = &serial_hsu_reg,
1191 struct uart_ops serial_hsu_pops = {
1192 .tx_empty = serial_hsu_tx_empty,
1193 .set_mctrl = serial_hsu_set_mctrl,
1194 .get_mctrl = serial_hsu_get_mctrl,
1195 .stop_tx = serial_hsu_stop_tx,
1196 .start_tx = serial_hsu_start_tx,
1197 .stop_rx = serial_hsu_stop_rx,
1198 .enable_ms = serial_hsu_enable_ms,
1199 .break_ctl = serial_hsu_break_ctl,
1200 .startup = serial_hsu_startup,
1201 .shutdown = serial_hsu_shutdown,
1202 .set_termios = serial_hsu_set_termios,
1203 .pm = serial_hsu_pm,
1204 .type = serial_hsu_type,
1205 .release_port = serial_hsu_release_port,
1206 .request_port = serial_hsu_request_port,
1207 .config_port = serial_hsu_config_port,
1208 .verify_port = serial_hsu_verify_port,
1211 static struct uart_driver serial_hsu_reg = {
1212 .owner = THIS_MODULE,
1213 .driver_name = "MFD serial",
1214 .dev_name = "ttyMFD",
1221 static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1223 void *priv = pci_get_drvdata(pdev);
1224 struct uart_hsu_port *up;
1226 /* Make sure this is not the internal dma controller */
1227 if (priv && (pdev->device != 0x081E)) {
1229 uart_suspend_port(&serial_hsu_reg, &up->port);
1232 pci_save_state(pdev);
1233 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1237 static int serial_hsu_resume(struct pci_dev *pdev)
1239 void *priv = pci_get_drvdata(pdev);
1240 struct uart_hsu_port *up;
1243 pci_set_power_state(pdev, PCI_D0);
1244 pci_restore_state(pdev);
1246 ret = pci_enable_device(pdev);
1248 dev_warn(&pdev->dev,
1249 "HSU: can't re-enable device, try to continue\n");
1251 if (priv && (pdev->device != 0x081E)) {
1253 uart_resume_port(&serial_hsu_reg, &up->port);
1258 #define serial_hsu_suspend NULL
1259 #define serial_hsu_resume NULL
1262 /* temp global pointer before we settle down on using one or four PCI dev */
1263 static struct hsu_port *phsu;
1265 static int serial_hsu_probe(struct pci_dev *pdev,
1266 const struct pci_device_id *ent)
1268 struct uart_hsu_port *uport;
1271 printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1272 pdev->vendor, pdev->device);
1274 switch (pdev->device) {
1285 /* internal DMA controller */
1289 dev_err(&pdev->dev, "HSU: out of index!");
1293 ret = pci_enable_device(pdev);
1298 /* DMA controller */
1299 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1301 dev_err(&pdev->dev, "can not get IRQ\n");
1304 pci_set_drvdata(pdev, phsu);
1307 uport = &phsu->port[index];
1308 uport->port.irq = pdev->irq;
1309 uport->port.dev = &pdev->dev;
1310 uport->dev = &pdev->dev;
1312 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1314 dev_err(&pdev->dev, "can not get IRQ\n");
1317 uart_add_one_port(&serial_hsu_reg, &uport->port);
1319 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1321 register_console(&serial_hsu_console);
1322 uport->port.cons = &serial_hsu_console;
1325 pci_set_drvdata(pdev, uport);
1331 pci_disable_device(pdev);
1335 static void hsu_dma_rx_timeout(unsigned long data)
1337 struct hsu_dma_chan *chan = (void *)data;
1338 struct uart_hsu_port *up = chan->uport;
1339 struct hsu_dma_buffer *dbuf = &up->rxbuf;
1341 unsigned long flags;
1343 spin_lock_irqsave(&up->port.lock, flags);
1345 count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
1348 mod_timer(&chan->rx_timer, jiffies + HSU_DMA_TIMEOUT_CHECK_FREQ);
1354 spin_unlock_irqrestore(&up->port.lock, flags);
1357 static void hsu_global_init(void)
1359 struct hsu_port *hsu;
1360 struct uart_hsu_port *uport;
1361 struct hsu_dma_chan *dchan;
1364 hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1368 /* Get basic io resource and map it */
1369 hsu->paddr = 0xffa28000;
1370 hsu->iolen = 0x1000;
1372 if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1373 pr_warning("HSU: error in request mem region\n");
1375 hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1377 pr_err("HSU: error in ioremap\n");
1379 goto err_free_region;
1382 /* Initialise the 3 UART ports */
1384 for (i = 0; i < 3; i++) {
1385 uport->port.type = PORT_MFD;
1386 uport->port.iotype = UPIO_MEM;
1387 uport->port.mapbase = (resource_size_t)hsu->paddr
1388 + HSU_PORT_REG_OFFSET
1389 + i * HSU_PORT_REG_LENGTH;
1390 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1391 + i * HSU_PORT_REG_LENGTH;
1393 sprintf(uport->name, "hsu_port%d", i);
1394 uport->port.fifosize = 64;
1395 uport->port.ops = &serial_hsu_pops;
1396 uport->port.line = i;
1397 uport->port.flags = UPF_IOREMAP;
1398 /* set the scalable maxim support rate to 2746800 bps */
1399 uport->port.uartclk = 115200 * 24 * 16;
1402 uport->txc = &hsu->chans[i * 2];
1403 uport->rxc = &hsu->chans[i * 2 + 1];
1405 serial_hsu_ports[i] = uport;
1410 /* Initialise 6 dma channels */
1412 for (i = 0; i < 6; i++) {
1414 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1415 dchan->uport = &hsu->port[i/2];
1416 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1417 i * HSU_DMA_CHANS_REG_LENGTH;
1419 /* Work around for RX */
1420 if (dchan->dirt == DMA_FROM_DEVICE) {
1421 init_timer(&dchan->rx_timer);
1422 dchan->rx_timer.function = hsu_dma_rx_timeout;
1423 dchan->rx_timer.data = (unsigned long)dchan;
1429 hsu_debugfs_init(hsu);
1433 release_mem_region(hsu->paddr, hsu->iolen);
1438 static void serial_hsu_remove(struct pci_dev *pdev)
1440 void *priv = pci_get_drvdata(pdev);
1441 struct uart_hsu_port *up;
1446 /* For port 0/1/2, priv is the address of uart_hsu_port */
1447 if (pdev->device != 0x081E) {
1449 uart_remove_one_port(&serial_hsu_reg, &up->port);
1452 pci_set_drvdata(pdev, NULL);
1453 free_irq(pdev->irq, priv);
1454 pci_disable_device(pdev);
1457 /* First 3 are UART ports, and the 4th is the DMA */
1458 static const struct pci_device_id pci_ids[] __devinitdata = {
1459 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1460 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1461 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1462 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1466 static struct pci_driver hsu_pci_driver = {
1467 .name = "HSU serial",
1468 .id_table = pci_ids,
1469 .probe = serial_hsu_probe,
1470 .remove = __devexit_p(serial_hsu_remove),
1471 .suspend = serial_hsu_suspend,
1472 .resume = serial_hsu_resume,
1475 static int __init hsu_pci_init(void)
1481 ret = uart_register_driver(&serial_hsu_reg);
1485 return pci_register_driver(&hsu_pci_driver);
1488 static void __exit hsu_pci_exit(void)
1490 pci_unregister_driver(&hsu_pci_driver);
1491 uart_unregister_driver(&serial_hsu_reg);
1493 hsu_debugfs_remove(phsu);
1498 module_init(hsu_pci_init);
1499 module_exit(hsu_pci_exit);
1501 MODULE_LICENSE("GPL v2");
1502 MODULE_ALIAS("platform:medfield-hsu");