2 * Blackfin On-Chip Sport Emulated UART Driver
4 * Copyright 2006-2009 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
12 * This driver and the hardware supported are in term of EE-191 of ADI.
13 * http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf
14 * This application note describe how to implement a UART on a Sharc DSP,
15 * but this driver is implemented on Blackfin Processor.
16 * Transmit Frame Sync is not used by this driver to transfer data out.
21 #define DRV_NAME "bfin-sport-uart"
22 #define DEVICE_NAME "ttySS"
23 #define pr_fmt(fmt) DRV_NAME ": " fmt
25 #include <linux/module.h>
26 #include <linux/ioport.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/sysrq.h>
31 #include <linux/slab.h>
32 #include <linux/platform_device.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/serial_core.h>
37 #include <asm/delay.h>
38 #include <asm/portmux.h>
40 #include "bfin_sport_uart.h"
42 struct sport_uart_port {
43 struct uart_port port;
46 unsigned short rxmask;
47 unsigned short txmask1;
48 unsigned short txmask2;
50 /* unsigned char parib; */
53 static void sport_uart_tx_chars(struct sport_uart_port *up);
54 static void sport_stop_tx(struct uart_port *port);
56 static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
58 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
59 up->txmask1, up->txmask2);
61 /* Place Start and Stop bits */
62 __asm__ __volatile__ (
64 "%[val] = %[val] & %[mask1];"
65 "%[val] = %[val] | %[mask2];"
67 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
70 pr_debug("%s value:%x\n", __func__, value);
72 SPORT_PUT_TX(up, value);
75 static inline unsigned char rx_one_byte(struct sport_uart_port *up)
78 unsigned char extract;
79 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
81 if ((up->csize + up->stopb) > 7)
82 value = SPORT_GET_RX32(up);
84 value = SPORT_GET_RX(up);
86 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
87 up->csize, up->rxmask);
90 __asm__ __volatile__ (
92 "%[mask1] = %[rxmask];"
93 "%[mask2] = 0x0200(Z);"
95 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
97 "%[tmp] = extract(%[val], %[mask1].L)(Z);"
98 "%[tmp] <<= %[shift];"
99 "%[extr] = %[extr] | %[tmp];"
100 "%[mask1] = %[mask1] - %[mask2];"
103 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
104 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
105 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
106 : "ASTAT", "LB0", "LC0", "LT0"
109 pr_debug(" extract:%x\n", extract);
113 static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
115 int tclkdiv, rclkdiv;
116 unsigned int sclk = get_sclk();
118 /* Set TCR1 and TCR2, TFSR is not enabled for uart */
119 SPORT_PUT_TCR1(up, (ITFS | TLSBIT | ITCLK));
120 SPORT_PUT_TCR2(up, size + 1);
121 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
123 /* Set RCR1 and RCR2 */
124 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
125 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
126 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
128 tclkdiv = sclk / (2 * baud_rate) - 1;
129 rclkdiv = sclk / (2 * baud_rate * 2) - 1;
130 SPORT_PUT_TCLKDIV(up, tclkdiv);
131 SPORT_PUT_RCLKDIV(up, rclkdiv);
133 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
134 __func__, sclk, baud_rate, tclkdiv, rclkdiv);
139 static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
141 struct sport_uart_port *up = dev_id;
142 struct tty_struct *tty = up->port.state->port.tty;
145 spin_lock(&up->port.lock);
147 while (SPORT_GET_STAT(up) & RXNE) {
148 ch = rx_one_byte(up);
149 up->port.icount.rx++;
151 if (!uart_handle_sysrq_char(&up->port, ch))
152 tty_insert_flip_char(tty, ch, TTY_NORMAL);
154 tty_flip_buffer_push(tty);
156 spin_unlock(&up->port.lock);
161 static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
163 struct sport_uart_port *up = dev_id;
165 spin_lock(&up->port.lock);
166 sport_uart_tx_chars(up);
167 spin_unlock(&up->port.lock);
172 static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
174 struct sport_uart_port *up = dev_id;
175 struct tty_struct *tty = up->port.state->port.tty;
176 unsigned int stat = SPORT_GET_STAT(up);
178 spin_lock(&up->port.lock);
180 /* Overflow in RX FIFO */
182 up->port.icount.overrun++;
183 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
184 SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
186 /* These should not happen */
187 if (stat & (TOVF | TUVF | RUVF)) {
188 pr_err("SPORT Error:%s %s %s\n",
189 (stat & TOVF) ? "TX overflow" : "",
190 (stat & TUVF) ? "TX underflow" : "",
191 (stat & RUVF) ? "RX underflow" : "");
192 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
193 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
197 spin_unlock(&up->port.lock);
201 /* Reqeust IRQ, Setup clock */
202 static int sport_startup(struct uart_port *port)
204 struct sport_uart_port *up = (struct sport_uart_port *)port;
207 pr_debug("%s enter\n", __func__);
208 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
209 "SPORT_UART_RX", up);
211 dev_err(port->dev, "unable to request SPORT RX interrupt\n");
215 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
216 "SPORT_UART_TX", up);
218 dev_err(port->dev, "unable to request SPORT TX interrupt\n");
222 ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
223 "SPORT_UART_STATUS", up);
225 dev_err(port->dev, "unable to request SPORT status interrupt\n");
231 free_irq(up->port.irq+1, up);
233 free_irq(up->port.irq, up);
238 static void sport_uart_tx_chars(struct sport_uart_port *up)
240 struct circ_buf *xmit = &up->port.state->xmit;
242 if (SPORT_GET_STAT(up) & TXF)
245 if (up->port.x_char) {
246 tx_one_byte(up, up->port.x_char);
247 up->port.icount.tx++;
252 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
253 /* The waiting loop to stop SPORT TX from TX interrupt is
254 * too long. This may block SPORT RX interrupts and cause
255 * RX FIFO overflow. So, do stop sport TX only after the last
256 * char in TX FIFO is moved into the shift register.
258 if (SPORT_GET_STAT(up) & TXHRE)
259 sport_stop_tx(&up->port);
263 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
264 tx_one_byte(up, xmit->buf[xmit->tail]);
265 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
266 up->port.icount.tx++;
269 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
270 uart_write_wakeup(&up->port);
273 static unsigned int sport_tx_empty(struct uart_port *port)
275 struct sport_uart_port *up = (struct sport_uart_port *)port;
278 stat = SPORT_GET_STAT(up);
279 pr_debug("%s stat:%04x\n", __func__, stat);
286 static unsigned int sport_get_mctrl(struct uart_port *port)
288 pr_debug("%s enter\n", __func__);
289 return (TIOCM_CTS | TIOCM_CD | TIOCM_DSR);
292 static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
294 pr_debug("%s enter\n", __func__);
297 static void sport_stop_tx(struct uart_port *port)
299 struct sport_uart_port *up = (struct sport_uart_port *)port;
301 pr_debug("%s enter\n", __func__);
303 /* Although the hold register is empty, last byte is still in shift
304 * register and not sent out yet. So, put a dummy data into TX FIFO.
305 * Then, sport tx stops when last byte is shift out and the dummy
306 * data is moved into the shift register.
308 SPORT_PUT_TX(up, 0xffff);
309 while (!(SPORT_GET_STAT(up) & TXHRE))
312 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
318 static void sport_start_tx(struct uart_port *port)
320 struct sport_uart_port *up = (struct sport_uart_port *)port;
322 pr_debug("%s enter\n", __func__);
324 /* Write data into SPORT FIFO before enable SPROT to transmit */
325 sport_uart_tx_chars(up);
327 /* Enable transmit, then an interrupt will generated */
328 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
330 pr_debug("%s exit\n", __func__);
333 static void sport_stop_rx(struct uart_port *port)
335 struct sport_uart_port *up = (struct sport_uart_port *)port;
337 pr_debug("%s enter\n", __func__);
338 /* Disable sport to stop rx */
339 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
343 static void sport_enable_ms(struct uart_port *port)
345 pr_debug("%s enter\n", __func__);
348 static void sport_break_ctl(struct uart_port *port, int break_state)
350 pr_debug("%s enter\n", __func__);
353 static void sport_shutdown(struct uart_port *port)
355 struct sport_uart_port *up = (struct sport_uart_port *)port;
357 dev_dbg(port->dev, "%s enter\n", __func__);
360 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
361 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
364 free_irq(up->port.irq, up);
365 free_irq(up->port.irq+1, up);
366 free_irq(up->err_irq, up);
369 static const char *sport_type(struct uart_port *port)
371 struct sport_uart_port *up = (struct sport_uart_port *)port;
373 pr_debug("%s enter\n", __func__);
374 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
377 static void sport_release_port(struct uart_port *port)
379 pr_debug("%s enter\n", __func__);
382 static int sport_request_port(struct uart_port *port)
384 pr_debug("%s enter\n", __func__);
388 static void sport_config_port(struct uart_port *port, int flags)
390 struct sport_uart_port *up = (struct sport_uart_port *)port;
392 pr_debug("%s enter\n", __func__);
393 up->port.type = PORT_BFIN_SPORT;
396 static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
398 pr_debug("%s enter\n", __func__);
402 static void sport_set_termios(struct uart_port *port,
403 struct ktermios *termios, struct ktermios *old)
405 struct sport_uart_port *up = (struct sport_uart_port *)port;
409 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
411 switch (termios->c_cflag & CSIZE) {
425 pr_warning("requested word length not supported\n");
428 if (termios->c_cflag & CSTOPB) {
431 if (termios->c_cflag & PARENB) {
432 pr_warning("PAREN bits is not supported yet\n");
436 port->read_status_mask = OE;
437 if (termios->c_iflag & INPCK)
438 port->read_status_mask |= (FE | PE);
439 if (termios->c_iflag & (BRKINT | PARMRK))
440 port->read_status_mask |= BI;
443 * Characters to ignore
445 port->ignore_status_mask = 0;
446 if (termios->c_iflag & IGNPAR)
447 port->ignore_status_mask |= FE | PE;
448 if (termios->c_iflag & IGNBRK) {
449 port->ignore_status_mask |= BI;
451 * If we're ignoring parity and break indicators,
452 * ignore overruns too (for real raw support).
454 if (termios->c_iflag & IGNPAR)
455 port->ignore_status_mask |= OE;
458 /* RX extract mask */
459 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
460 /* TX masks, 8 bit data and 1 bit stop for example:
461 * mask1 = b#0111111110
462 * mask2 = b#1000000000
464 for (i = 0, up->txmask1 = 0; i < up->csize; i++)
465 up->txmask1 |= (1<<i);
466 up->txmask2 = (1<<i);
469 up->txmask2 |= (1<<i);
474 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
476 spin_lock_irqsave(&up->port.lock, flags);
479 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
480 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
482 sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
484 /* driver TX line high after config, one dummy data is
485 * necessary to stop sport after shift one byte
487 SPORT_PUT_TX(up, 0xffff);
488 SPORT_PUT_TX(up, 0xffff);
489 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
491 while (!(SPORT_GET_STAT(up) & TXHRE))
493 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
496 /* Port speed changed, update the per-port timeout. */
497 uart_update_timeout(port, termios->c_cflag, port->uartclk);
499 /* Enable sport rx */
500 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
503 spin_unlock_irqrestore(&up->port.lock, flags);
506 struct uart_ops sport_uart_ops = {
507 .tx_empty = sport_tx_empty,
508 .set_mctrl = sport_set_mctrl,
509 .get_mctrl = sport_get_mctrl,
510 .stop_tx = sport_stop_tx,
511 .start_tx = sport_start_tx,
512 .stop_rx = sport_stop_rx,
513 .enable_ms = sport_enable_ms,
514 .break_ctl = sport_break_ctl,
515 .startup = sport_startup,
516 .shutdown = sport_shutdown,
517 .set_termios = sport_set_termios,
519 .release_port = sport_release_port,
520 .request_port = sport_request_port,
521 .config_port = sport_config_port,
522 .verify_port = sport_verify_port,
525 #define BFIN_SPORT_UART_MAX_PORTS 4
527 static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
529 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
530 #define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
533 sport_uart_console_setup(struct console *co, char *options)
535 struct sport_uart_port *up;
541 /* Check whether an invalid uart number has been specified */
542 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
545 up = bfin_sport_uart_ports[co->index];
550 uart_parse_options(options, &baud, &parity, &bits, &flow);
552 return uart_set_options(&up->port, co, baud, parity, bits, flow);
555 static void sport_uart_console_putchar(struct uart_port *port, int ch)
557 struct sport_uart_port *up = (struct sport_uart_port *)port;
559 while (SPORT_GET_STAT(up) & TXF)
566 * Interrupts are disabled on entering
569 sport_uart_console_write(struct console *co, const char *s, unsigned int count)
571 struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
574 spin_lock_irqsave(&up->port.lock, flags);
576 if (SPORT_GET_TCR1(up) & TSPEN)
577 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
579 /* dummy data to start sport */
580 while (SPORT_GET_STAT(up) & TXF)
582 SPORT_PUT_TX(up, 0xffff);
583 /* Enable transmit, then an interrupt will generated */
584 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
587 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
589 /* Although the hold register is empty, last byte is still in shift
590 * register and not sent out yet. So, put a dummy data into TX FIFO.
591 * Then, sport tx stops when last byte is shift out and the dummy
592 * data is moved into the shift register.
594 while (SPORT_GET_STAT(up) & TXF)
596 SPORT_PUT_TX(up, 0xffff);
597 while (!(SPORT_GET_STAT(up) & TXHRE))
600 /* Stop sport tx transfer */
601 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
605 spin_unlock_irqrestore(&up->port.lock, flags);
608 static struct uart_driver sport_uart_reg;
610 static struct console sport_uart_console = {
612 .write = sport_uart_console_write,
613 .device = uart_console_device,
614 .setup = sport_uart_console_setup,
615 .flags = CON_PRINTBUFFER,
617 .data = &sport_uart_reg,
620 #define SPORT_UART_CONSOLE (&sport_uart_console)
622 #define SPORT_UART_CONSOLE NULL
623 #endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
626 static struct uart_driver sport_uart_reg = {
627 .owner = THIS_MODULE,
628 .driver_name = DRV_NAME,
629 .dev_name = DEVICE_NAME,
632 .nr = BFIN_SPORT_UART_MAX_PORTS,
633 .cons = SPORT_UART_CONSOLE,
637 static int sport_uart_suspend(struct device *dev)
639 struct sport_uart_port *sport = dev_get_drvdata(dev);
641 dev_dbg(dev, "%s enter\n", __func__);
643 uart_suspend_port(&sport_uart_reg, &sport->port);
648 static int sport_uart_resume(struct device *dev)
650 struct sport_uart_port *sport = dev_get_drvdata(dev);
652 dev_dbg(dev, "%s enter\n", __func__);
654 uart_resume_port(&sport_uart_reg, &sport->port);
659 static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
660 .suspend = sport_uart_suspend,
661 .resume = sport_uart_resume,
665 static int __devinit sport_uart_probe(struct platform_device *pdev)
667 struct resource *res;
668 struct sport_uart_port *sport;
671 dev_dbg(&pdev->dev, "%s enter\n", __func__);
673 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
674 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
678 if (bfin_sport_uart_ports[pdev->id] == NULL) {
679 bfin_sport_uart_ports[pdev->id] =
680 kmalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
681 sport = bfin_sport_uart_ports[pdev->id];
684 "Fail to kmalloc sport_uart_port\n");
688 ret = peripheral_request_list(
689 (unsigned short *)pdev->dev.platform_data, DRV_NAME);
692 "Fail to request SPORT peripherals\n");
693 goto out_error_free_mem;
696 spin_lock_init(&sport->port.lock);
697 sport->port.fifosize = SPORT_TX_FIFO_SIZE,
698 sport->port.ops = &sport_uart_ops;
699 sport->port.line = pdev->id;
700 sport->port.iotype = UPIO_MEM;
701 sport->port.flags = UPF_BOOT_AUTOCONF;
703 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
705 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
707 goto out_error_free_peripherals;
710 sport->port.membase = ioremap(res->start,
711 res->end - res->start);
712 if (!sport->port.membase) {
713 dev_err(&pdev->dev, "Cannot map sport IO\n");
715 goto out_error_free_peripherals;
717 sport->port.mapbase = res->start;
719 sport->port.irq = platform_get_irq(pdev, 0);
720 if (sport->port.irq < 0) {
721 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
723 goto out_error_unmap;
726 sport->err_irq = platform_get_irq(pdev, 1);
727 if (sport->err_irq < 0) {
728 dev_err(&pdev->dev, "No sport status IRQ specified\n");
730 goto out_error_unmap;
734 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
735 if (!is_early_platform_device(pdev)) {
737 sport = bfin_sport_uart_ports[pdev->id];
738 sport->port.dev = &pdev->dev;
739 dev_set_drvdata(&pdev->dev, sport);
740 ret = uart_add_one_port(&sport_uart_reg, &sport->port);
741 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
749 iounmap(sport->port.membase);
750 out_error_free_peripherals:
751 peripheral_free_list(
752 (unsigned short *)pdev->dev.platform_data);
755 bfin_sport_uart_ports[pdev->id] = NULL;
761 static int __devexit sport_uart_remove(struct platform_device *pdev)
763 struct sport_uart_port *sport = platform_get_drvdata(pdev);
765 dev_dbg(&pdev->dev, "%s enter\n", __func__);
766 dev_set_drvdata(&pdev->dev, NULL);
769 uart_remove_one_port(&sport_uart_reg, &sport->port);
770 iounmap(sport->port.membase);
771 peripheral_free_list(
772 (unsigned short *)pdev->dev.platform_data);
774 bfin_sport_uart_ports[pdev->id] = NULL;
780 static struct platform_driver sport_uart_driver = {
781 .probe = sport_uart_probe,
782 .remove = __devexit_p(sport_uart_remove),
786 .pm = &bfin_sport_uart_dev_pm_ops,
791 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
792 static __initdata struct early_platform_driver early_sport_uart_driver = {
793 .class_str = CLASS_BFIN_SPORT_CONSOLE,
794 .pdrv = &sport_uart_driver,
795 .requested_id = EARLY_PLATFORM_ID_UNSET,
798 static int __init sport_uart_rs_console_init(void)
800 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
802 early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
803 BFIN_SPORT_UART_MAX_PORTS, 0);
805 register_console(&sport_uart_console);
809 console_initcall(sport_uart_rs_console_init);
812 static int __init sport_uart_init(void)
816 pr_info("Blackfin uart over sport driver\n");
818 ret = uart_register_driver(&sport_uart_reg);
820 pr_err("failed to register %s:%d\n",
821 sport_uart_reg.driver_name, ret);
825 ret = platform_driver_register(&sport_uart_driver);
827 pr_err("failed to register sport uart driver:%d\n", ret);
828 uart_unregister_driver(&sport_uart_reg);
833 module_init(sport_uart_init);
835 static void __exit sport_uart_exit(void)
837 platform_driver_unregister(&sport_uart_driver);
838 uart_unregister_driver(&sport_uart_reg);
840 module_exit(sport_uart_exit);
842 MODULE_AUTHOR("Sonic Zhang, Roy Huang");
843 MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
844 MODULE_LICENSE("GPL");