Linux-2.6.12-rc2
[pandora-kernel.git] / drivers / serial / amba-pl011.c
1 /*
2  *  linux/drivers/char/amba.c
3  *
4  *  Driver for AMBA serial ports
5  *
6  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7  *
8  *  Copyright 1999 ARM Limited
9  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
24  *
25  *  $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
26  *
27  * This is a generic driver for ARM AMBA-type serial ports.  They
28  * have a lot of 16550-like features, but are not register compatible.
29  * Note that although they do have CTS, DCD and DSR inputs, they do
30  * not have an RI input, nor do they have DTR or RTS outputs.  If
31  * required, these have to be supplied via some other means (eg, GPIO)
32  * and hooked into this driver.
33  */
34 #include <linux/config.h>
35
36 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
37 #define SUPPORT_SYSRQ
38 #endif
39
40 #include <linux/module.h>
41 #include <linux/ioport.h>
42 #include <linux/init.h>
43 #include <linux/console.h>
44 #include <linux/sysrq.h>
45 #include <linux/device.h>
46 #include <linux/tty.h>
47 #include <linux/tty_flip.h>
48 #include <linux/serial_core.h>
49 #include <linux/serial.h>
50
51 #include <asm/io.h>
52 #include <asm/irq.h>
53 #include <asm/hardware/amba.h>
54 #include <asm/hardware/clock.h>
55 #include <asm/hardware/amba_serial.h>
56
57 #define UART_NR                 14
58
59 #define SERIAL_AMBA_MAJOR       204
60 #define SERIAL_AMBA_MINOR       64
61 #define SERIAL_AMBA_NR          UART_NR
62
63 #define AMBA_ISR_PASS_LIMIT     256
64
65 #define UART_DUMMY_RSR_RX       256
66
67 /*
68  * We wrap our port structure around the generic uart_port.
69  */
70 struct uart_amba_port {
71         struct uart_port        port;
72         struct clk              *clk;
73         unsigned int            im;     /* interrupt mask */
74         unsigned int            old_status;
75 };
76
77 static void pl011_stop_tx(struct uart_port *port, unsigned int tty_stop)
78 {
79         struct uart_amba_port *uap = (struct uart_amba_port *)port;
80
81         uap->im &= ~UART011_TXIM;
82         writew(uap->im, uap->port.membase + UART011_IMSC);
83 }
84
85 static void pl011_start_tx(struct uart_port *port, unsigned int tty_start)
86 {
87         struct uart_amba_port *uap = (struct uart_amba_port *)port;
88
89         uap->im |= UART011_TXIM;
90         writew(uap->im, uap->port.membase + UART011_IMSC);
91 }
92
93 static void pl011_stop_rx(struct uart_port *port)
94 {
95         struct uart_amba_port *uap = (struct uart_amba_port *)port;
96
97         uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
98                      UART011_PEIM|UART011_BEIM|UART011_OEIM);
99         writew(uap->im, uap->port.membase + UART011_IMSC);
100 }
101
102 static void pl011_enable_ms(struct uart_port *port)
103 {
104         struct uart_amba_port *uap = (struct uart_amba_port *)port;
105
106         uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
107         writew(uap->im, uap->port.membase + UART011_IMSC);
108 }
109
110 static void
111 #ifdef SUPPORT_SYSRQ
112 pl011_rx_chars(struct uart_amba_port *uap, struct pt_regs *regs)
113 #else
114 pl011_rx_chars(struct uart_amba_port *uap)
115 #endif
116 {
117         struct tty_struct *tty = uap->port.info->tty;
118         unsigned int status, ch, flag, rsr, max_count = 256;
119
120         status = readw(uap->port.membase + UART01x_FR);
121         while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
122                 if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
123                         if (tty->low_latency)
124                                 tty_flip_buffer_push(tty);
125                         /*
126                          * If this failed then we will throw away the
127                          * bytes but must do so to clear interrupts
128                          */
129                 }
130
131                 ch = readw(uap->port.membase + UART01x_DR);
132                 flag = TTY_NORMAL;
133                 uap->port.icount.rx++;
134
135                 /*
136                  * Note that the error handling code is
137                  * out of the main execution path
138                  */
139                 rsr = readw(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
140                 if (rsr & UART01x_RSR_ANY) {
141                         if (rsr & UART01x_RSR_BE) {
142                                 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
143                                 uap->port.icount.brk++;
144                                 if (uart_handle_break(&uap->port))
145                                         goto ignore_char;
146                         } else if (rsr & UART01x_RSR_PE)
147                                 uap->port.icount.parity++;
148                         else if (rsr & UART01x_RSR_FE)
149                                 uap->port.icount.frame++;
150                         if (rsr & UART01x_RSR_OE)
151                                 uap->port.icount.overrun++;
152
153                         rsr &= uap->port.read_status_mask;
154
155                         if (rsr & UART01x_RSR_BE)
156                                 flag = TTY_BREAK;
157                         else if (rsr & UART01x_RSR_PE)
158                                 flag = TTY_PARITY;
159                         else if (rsr & UART01x_RSR_FE)
160                                 flag = TTY_FRAME;
161                 }
162
163                 if (uart_handle_sysrq_char(&uap->port, ch, regs))
164                         goto ignore_char;
165
166                 if ((rsr & uap->port.ignore_status_mask) == 0) {
167                         tty_insert_flip_char(tty, ch, flag);
168                 }
169                 if ((rsr & UART01x_RSR_OE) &&
170                     tty->flip.count < TTY_FLIPBUF_SIZE) {
171                         /*
172                          * Overrun is special, since it's reported
173                          * immediately, and doesn't affect the current
174                          * character
175                          */
176                         tty_insert_flip_char(tty, 0, TTY_OVERRUN);
177                 }
178         ignore_char:
179                 status = readw(uap->port.membase + UART01x_FR);
180         }
181         tty_flip_buffer_push(tty);
182         return;
183 }
184
185 static void pl011_tx_chars(struct uart_amba_port *uap)
186 {
187         struct circ_buf *xmit = &uap->port.info->xmit;
188         int count;
189
190         if (uap->port.x_char) {
191                 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
192                 uap->port.icount.tx++;
193                 uap->port.x_char = 0;
194                 return;
195         }
196         if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
197                 pl011_stop_tx(&uap->port, 0);
198                 return;
199         }
200
201         count = uap->port.fifosize >> 1;
202         do {
203                 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
204                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
205                 uap->port.icount.tx++;
206                 if (uart_circ_empty(xmit))
207                         break;
208         } while (--count > 0);
209
210         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
211                 uart_write_wakeup(&uap->port);
212
213         if (uart_circ_empty(xmit))
214                 pl011_stop_tx(&uap->port, 0);
215 }
216
217 static void pl011_modem_status(struct uart_amba_port *uap)
218 {
219         unsigned int status, delta;
220
221         status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
222
223         delta = status ^ uap->old_status;
224         uap->old_status = status;
225
226         if (!delta)
227                 return;
228
229         if (delta & UART01x_FR_DCD)
230                 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
231
232         if (delta & UART01x_FR_DSR)
233                 uap->port.icount.dsr++;
234
235         if (delta & UART01x_FR_CTS)
236                 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
237
238         wake_up_interruptible(&uap->port.info->delta_msr_wait);
239 }
240
241 static irqreturn_t pl011_int(int irq, void *dev_id, struct pt_regs *regs)
242 {
243         struct uart_amba_port *uap = dev_id;
244         unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
245         int handled = 0;
246
247         spin_lock(&uap->port.lock);
248
249         status = readw(uap->port.membase + UART011_MIS);
250         if (status) {
251                 do {
252                         writew(status & ~(UART011_TXIS|UART011_RTIS|
253                                           UART011_RXIS),
254                                uap->port.membase + UART011_ICR);
255
256                         if (status & (UART011_RTIS|UART011_RXIS))
257 #ifdef SUPPORT_SYSRQ
258                                 pl011_rx_chars(uap, regs);
259 #else
260                                 pl011_rx_chars(uap);
261 #endif
262                         if (status & (UART011_DSRMIS|UART011_DCDMIS|
263                                       UART011_CTSMIS|UART011_RIMIS))
264                                 pl011_modem_status(uap);
265                         if (status & UART011_TXIS)
266                                 pl011_tx_chars(uap);
267
268                         if (pass_counter-- == 0)
269                                 break;
270
271                         status = readw(uap->port.membase + UART011_MIS);
272                 } while (status != 0);
273                 handled = 1;
274         }
275
276         spin_unlock(&uap->port.lock);
277
278         return IRQ_RETVAL(handled);
279 }
280
281 static unsigned int pl01x_tx_empty(struct uart_port *port)
282 {
283         struct uart_amba_port *uap = (struct uart_amba_port *)port;
284         unsigned int status = readw(uap->port.membase + UART01x_FR);
285         return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
286 }
287
288 static unsigned int pl01x_get_mctrl(struct uart_port *port)
289 {
290         struct uart_amba_port *uap = (struct uart_amba_port *)port;
291         unsigned int result = 0;
292         unsigned int status = readw(uap->port.membase + UART01x_FR);
293
294 #define BIT(uartbit, tiocmbit)          \
295         if (status & uartbit)           \
296                 result |= tiocmbit
297
298         BIT(UART01x_FR_DCD, TIOCM_CAR);
299         BIT(UART01x_FR_DSR, TIOCM_DSR);
300         BIT(UART01x_FR_CTS, TIOCM_CTS);
301         BIT(UART011_FR_RI, TIOCM_RNG);
302 #undef BIT
303         return result;
304 }
305
306 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
307 {
308         struct uart_amba_port *uap = (struct uart_amba_port *)port;
309         unsigned int cr;
310
311         cr = readw(uap->port.membase + UART011_CR);
312
313 #define BIT(tiocmbit, uartbit)          \
314         if (mctrl & tiocmbit)           \
315                 cr |= uartbit;          \
316         else                            \
317                 cr &= ~uartbit
318
319         BIT(TIOCM_RTS, UART011_CR_RTS);
320         BIT(TIOCM_DTR, UART011_CR_DTR);
321         BIT(TIOCM_OUT1, UART011_CR_OUT1);
322         BIT(TIOCM_OUT2, UART011_CR_OUT2);
323         BIT(TIOCM_LOOP, UART011_CR_LBE);
324 #undef BIT
325
326         writew(cr, uap->port.membase + UART011_CR);
327 }
328
329 static void pl011_break_ctl(struct uart_port *port, int break_state)
330 {
331         struct uart_amba_port *uap = (struct uart_amba_port *)port;
332         unsigned long flags;
333         unsigned int lcr_h;
334
335         spin_lock_irqsave(&uap->port.lock, flags);
336         lcr_h = readw(uap->port.membase + UART011_LCRH);
337         if (break_state == -1)
338                 lcr_h |= UART01x_LCRH_BRK;
339         else
340                 lcr_h &= ~UART01x_LCRH_BRK;
341         writew(lcr_h, uap->port.membase + UART011_LCRH);
342         spin_unlock_irqrestore(&uap->port.lock, flags);
343 }
344
345 static int pl011_startup(struct uart_port *port)
346 {
347         struct uart_amba_port *uap = (struct uart_amba_port *)port;
348         unsigned int cr;
349         int retval;
350
351         /*
352          * Try to enable the clock producer.
353          */
354         retval = clk_enable(uap->clk);
355         if (retval)
356                 goto out;
357
358         uap->port.uartclk = clk_get_rate(uap->clk);
359
360         /*
361          * Allocate the IRQ
362          */
363         retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
364         if (retval)
365                 goto clk_dis;
366
367         writew(UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
368                uap->port.membase + UART011_IFLS);
369
370         /*
371          * Provoke TX FIFO interrupt into asserting.
372          */
373         cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
374         writew(cr, uap->port.membase + UART011_CR);
375         writew(0, uap->port.membase + UART011_FBRD);
376         writew(1, uap->port.membase + UART011_IBRD);
377         writew(0, uap->port.membase + UART011_LCRH);
378         writew(0, uap->port.membase + UART01x_DR);
379         while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
380                 barrier();
381
382         cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
383         writew(cr, uap->port.membase + UART011_CR);
384
385         /*
386          * initialise the old status of the modem signals
387          */
388         uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
389
390         /*
391          * Finally, enable interrupts
392          */
393         spin_lock_irq(&uap->port.lock);
394         uap->im = UART011_RXIM | UART011_RTIM;
395         writew(uap->im, uap->port.membase + UART011_IMSC);
396         spin_unlock_irq(&uap->port.lock);
397
398         return 0;
399
400  clk_dis:
401         clk_disable(uap->clk);
402  out:
403         return retval;
404 }
405
406 static void pl011_shutdown(struct uart_port *port)
407 {
408         struct uart_amba_port *uap = (struct uart_amba_port *)port;
409         unsigned long val;
410
411         /*
412          * disable all interrupts
413          */
414         spin_lock_irq(&uap->port.lock);
415         uap->im = 0;
416         writew(uap->im, uap->port.membase + UART011_IMSC);
417         writew(0xffff, uap->port.membase + UART011_ICR);
418         spin_unlock_irq(&uap->port.lock);
419
420         /*
421          * Free the interrupt
422          */
423         free_irq(uap->port.irq, uap);
424
425         /*
426          * disable the port
427          */
428         writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR);
429
430         /*
431          * disable break condition and fifos
432          */
433         val = readw(uap->port.membase + UART011_LCRH);
434         val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
435         writew(val, uap->port.membase + UART011_LCRH);
436
437         /*
438          * Shut down the clock producer
439          */
440         clk_disable(uap->clk);
441 }
442
443 static void
444 pl011_set_termios(struct uart_port *port, struct termios *termios,
445                      struct termios *old)
446 {
447         unsigned int lcr_h, old_cr;
448         unsigned long flags;
449         unsigned int baud, quot;
450
451         /*
452          * Ask the core to calculate the divisor for us.
453          */
454         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
455         quot = port->uartclk * 4 / baud;
456
457         switch (termios->c_cflag & CSIZE) {
458         case CS5:
459                 lcr_h = UART01x_LCRH_WLEN_5;
460                 break;
461         case CS6:
462                 lcr_h = UART01x_LCRH_WLEN_6;
463                 break;
464         case CS7:
465                 lcr_h = UART01x_LCRH_WLEN_7;
466                 break;
467         default: // CS8
468                 lcr_h = UART01x_LCRH_WLEN_8;
469                 break;
470         }
471         if (termios->c_cflag & CSTOPB)
472                 lcr_h |= UART01x_LCRH_STP2;
473         if (termios->c_cflag & PARENB) {
474                 lcr_h |= UART01x_LCRH_PEN;
475                 if (!(termios->c_cflag & PARODD))
476                         lcr_h |= UART01x_LCRH_EPS;
477         }
478         if (port->fifosize > 1)
479                 lcr_h |= UART01x_LCRH_FEN;
480
481         spin_lock_irqsave(&port->lock, flags);
482
483         /*
484          * Update the per-port timeout.
485          */
486         uart_update_timeout(port, termios->c_cflag, baud);
487
488         port->read_status_mask = UART01x_RSR_OE;
489         if (termios->c_iflag & INPCK)
490                 port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
491         if (termios->c_iflag & (BRKINT | PARMRK))
492                 port->read_status_mask |= UART01x_RSR_BE;
493
494         /*
495          * Characters to ignore
496          */
497         port->ignore_status_mask = 0;
498         if (termios->c_iflag & IGNPAR)
499                 port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
500         if (termios->c_iflag & IGNBRK) {
501                 port->ignore_status_mask |= UART01x_RSR_BE;
502                 /*
503                  * If we're ignoring parity and break indicators,
504                  * ignore overruns too (for real raw support).
505                  */
506                 if (termios->c_iflag & IGNPAR)
507                         port->ignore_status_mask |= UART01x_RSR_OE;
508         }
509
510         /*
511          * Ignore all characters if CREAD is not set.
512          */
513         if ((termios->c_cflag & CREAD) == 0)
514                 port->ignore_status_mask |= UART_DUMMY_RSR_RX;
515
516         if (UART_ENABLE_MS(port, termios->c_cflag))
517                 pl011_enable_ms(port);
518
519         /* first, disable everything */
520         old_cr = readw(port->membase + UART011_CR);
521         writew(0, port->membase + UART011_CR);
522
523         /* Set baud rate */
524         writew(quot & 0x3f, port->membase + UART011_FBRD);
525         writew(quot >> 6, port->membase + UART011_IBRD);
526
527         /*
528          * ----------v----------v----------v----------v-----
529          * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
530          * ----------^----------^----------^----------^-----
531          */
532         writew(lcr_h, port->membase + UART011_LCRH);
533         writew(old_cr, port->membase + UART011_CR);
534
535         spin_unlock_irqrestore(&port->lock, flags);
536 }
537
538 static const char *pl011_type(struct uart_port *port)
539 {
540         return port->type == PORT_AMBA ? "AMBA/PL011" : NULL;
541 }
542
543 /*
544  * Release the memory region(s) being used by 'port'
545  */
546 static void pl010_release_port(struct uart_port *port)
547 {
548         release_mem_region(port->mapbase, SZ_4K);
549 }
550
551 /*
552  * Request the memory region(s) being used by 'port'
553  */
554 static int pl010_request_port(struct uart_port *port)
555 {
556         return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
557                         != NULL ? 0 : -EBUSY;
558 }
559
560 /*
561  * Configure/autoconfigure the port.
562  */
563 static void pl010_config_port(struct uart_port *port, int flags)
564 {
565         if (flags & UART_CONFIG_TYPE) {
566                 port->type = PORT_AMBA;
567                 pl010_request_port(port);
568         }
569 }
570
571 /*
572  * verify the new serial_struct (for TIOCSSERIAL).
573  */
574 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
575 {
576         int ret = 0;
577         if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
578                 ret = -EINVAL;
579         if (ser->irq < 0 || ser->irq >= NR_IRQS)
580                 ret = -EINVAL;
581         if (ser->baud_base < 9600)
582                 ret = -EINVAL;
583         return ret;
584 }
585
586 static struct uart_ops amba_pl011_pops = {
587         .tx_empty       = pl01x_tx_empty,
588         .set_mctrl      = pl011_set_mctrl,
589         .get_mctrl      = pl01x_get_mctrl,
590         .stop_tx        = pl011_stop_tx,
591         .start_tx       = pl011_start_tx,
592         .stop_rx        = pl011_stop_rx,
593         .enable_ms      = pl011_enable_ms,
594         .break_ctl      = pl011_break_ctl,
595         .startup        = pl011_startup,
596         .shutdown       = pl011_shutdown,
597         .set_termios    = pl011_set_termios,
598         .type           = pl011_type,
599         .release_port   = pl010_release_port,
600         .request_port   = pl010_request_port,
601         .config_port    = pl010_config_port,
602         .verify_port    = pl010_verify_port,
603 };
604
605 static struct uart_amba_port *amba_ports[UART_NR];
606
607 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
608
609 static inline void
610 pl011_console_write_char(struct uart_amba_port *uap, char ch)
611 {
612         unsigned int status;
613
614         do {
615                 status = readw(uap->port.membase + UART01x_FR);
616         } while (status & UART01x_FR_TXFF);
617         writew(ch, uap->port.membase + UART01x_DR);
618 }
619
620 static void
621 pl011_console_write(struct console *co, const char *s, unsigned int count)
622 {
623         struct uart_amba_port *uap = amba_ports[co->index];
624         unsigned int status, old_cr, new_cr;
625         int i;
626
627         clk_enable(uap->clk);
628
629         /*
630          *      First save the CR then disable the interrupts
631          */
632         old_cr = readw(uap->port.membase + UART011_CR);
633         new_cr = old_cr & ~UART011_CR_CTSEN;
634         new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
635         writew(new_cr, uap->port.membase + UART011_CR);
636
637         /*
638          *      Now, do each character
639          */
640         for (i = 0; i < count; i++) {
641                 pl011_console_write_char(uap, s[i]);
642                 if (s[i] == '\n')
643                         pl011_console_write_char(uap, '\r');
644         }
645
646         /*
647          *      Finally, wait for transmitter to become empty
648          *      and restore the TCR
649          */
650         do {
651                 status = readw(uap->port.membase + UART01x_FR);
652         } while (status & UART01x_FR_BUSY);
653         writew(old_cr, uap->port.membase + UART011_CR);
654
655         clk_disable(uap->clk);
656 }
657
658 static void __init
659 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
660                              int *parity, int *bits)
661 {
662         if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
663                 unsigned int lcr_h, ibrd, fbrd;
664
665                 lcr_h = readw(uap->port.membase + UART011_LCRH);
666
667                 *parity = 'n';
668                 if (lcr_h & UART01x_LCRH_PEN) {
669                         if (lcr_h & UART01x_LCRH_EPS)
670                                 *parity = 'e';
671                         else
672                                 *parity = 'o';
673                 }
674
675                 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
676                         *bits = 7;
677                 else
678                         *bits = 8;
679
680                 ibrd = readw(uap->port.membase + UART011_IBRD);
681                 fbrd = readw(uap->port.membase + UART011_FBRD);
682
683                 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
684         }
685 }
686
687 static int __init pl011_console_setup(struct console *co, char *options)
688 {
689         struct uart_amba_port *uap;
690         int baud = 38400;
691         int bits = 8;
692         int parity = 'n';
693         int flow = 'n';
694
695         /*
696          * Check whether an invalid uart number has been specified, and
697          * if so, search for the first available port that does have
698          * console support.
699          */
700         if (co->index >= UART_NR)
701                 co->index = 0;
702         uap = amba_ports[co->index];
703
704         uap->port.uartclk = clk_get_rate(uap->clk);
705
706         if (options)
707                 uart_parse_options(options, &baud, &parity, &bits, &flow);
708         else
709                 pl011_console_get_options(uap, &baud, &parity, &bits);
710
711         return uart_set_options(&uap->port, co, baud, parity, bits, flow);
712 }
713
714 extern struct uart_driver amba_reg;
715 static struct console amba_console = {
716         .name           = "ttyAMA",
717         .write          = pl011_console_write,
718         .device         = uart_console_device,
719         .setup          = pl011_console_setup,
720         .flags          = CON_PRINTBUFFER,
721         .index          = -1,
722         .data           = &amba_reg,
723 };
724
725 #define AMBA_CONSOLE    (&amba_console)
726 #else
727 #define AMBA_CONSOLE    NULL
728 #endif
729
730 static struct uart_driver amba_reg = {
731         .owner                  = THIS_MODULE,
732         .driver_name            = "ttyAMA",
733         .dev_name               = "ttyAMA",
734         .major                  = SERIAL_AMBA_MAJOR,
735         .minor                  = SERIAL_AMBA_MINOR,
736         .nr                     = UART_NR,
737         .cons                   = AMBA_CONSOLE,
738 };
739
740 static int pl011_probe(struct amba_device *dev, void *id)
741 {
742         struct uart_amba_port *uap;
743         void __iomem *base;
744         int i, ret;
745
746         for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
747                 if (amba_ports[i] == NULL)
748                         break;
749
750         if (i == ARRAY_SIZE(amba_ports)) {
751                 ret = -EBUSY;
752                 goto out;
753         }
754
755         uap = kmalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
756         if (uap == NULL) {
757                 ret = -ENOMEM;
758                 goto out;
759         }
760
761         base = ioremap(dev->res.start, PAGE_SIZE);
762         if (!base) {
763                 ret = -ENOMEM;
764                 goto free;
765         }
766
767         memset(uap, 0, sizeof(struct uart_amba_port));
768         uap->clk = clk_get(&dev->dev, "UARTCLK");
769         if (IS_ERR(uap->clk)) {
770                 ret = PTR_ERR(uap->clk);
771                 goto unmap;
772         }
773
774         ret = clk_use(uap->clk);
775         if (ret)
776                 goto putclk;
777
778         uap->port.dev = &dev->dev;
779         uap->port.mapbase = dev->res.start;
780         uap->port.membase = base;
781         uap->port.iotype = UPIO_MEM;
782         uap->port.irq = dev->irq[0];
783         uap->port.fifosize = 16;
784         uap->port.ops = &amba_pl011_pops;
785         uap->port.flags = UPF_BOOT_AUTOCONF;
786         uap->port.line = i;
787
788         amba_ports[i] = uap;
789
790         amba_set_drvdata(dev, uap);
791         ret = uart_add_one_port(&amba_reg, &uap->port);
792         if (ret) {
793                 amba_set_drvdata(dev, NULL);
794                 amba_ports[i] = NULL;
795                 clk_unuse(uap->clk);
796  putclk:
797                 clk_put(uap->clk);
798  unmap:
799                 iounmap(base);
800  free:
801                 kfree(uap);
802         }
803  out:
804         return ret;
805 }
806
807 static int pl011_remove(struct amba_device *dev)
808 {
809         struct uart_amba_port *uap = amba_get_drvdata(dev);
810         int i;
811
812         amba_set_drvdata(dev, NULL);
813
814         uart_remove_one_port(&amba_reg, &uap->port);
815
816         for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
817                 if (amba_ports[i] == uap)
818                         amba_ports[i] = NULL;
819
820         iounmap(uap->port.membase);
821         clk_unuse(uap->clk);
822         clk_put(uap->clk);
823         kfree(uap);
824         return 0;
825 }
826
827 static struct amba_id pl011_ids[] __initdata = {
828         {
829                 .id     = 0x00041011,
830                 .mask   = 0x000fffff,
831         },
832         { 0, 0 },
833 };
834
835 static struct amba_driver pl011_driver = {
836         .drv = {
837                 .name   = "uart-pl011",
838         },
839         .id_table       = pl011_ids,
840         .probe          = pl011_probe,
841         .remove         = pl011_remove,
842 };
843
844 static int __init pl011_init(void)
845 {
846         int ret;
847         printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
848
849         ret = uart_register_driver(&amba_reg);
850         if (ret == 0) {
851                 ret = amba_driver_register(&pl011_driver);
852                 if (ret)
853                         uart_unregister_driver(&amba_reg);
854         }
855         return ret;
856 }
857
858 static void __exit pl011_exit(void)
859 {
860         amba_driver_unregister(&pl011_driver);
861         uart_unregister_driver(&amba_reg);
862 }
863
864 module_init(pl011_init);
865 module_exit(pl011_exit);
866
867 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
868 MODULE_DESCRIPTION("ARM AMBA serial port driver");
869 MODULE_LICENSE("GPL");