drivers/scsi/qla4xxx/ql4_nx.c

   1 /*
   2  * QLogic iSCSI HBA Driver
   3  * Copyright (c)  2003-2009 QLogic Corporation
   4  *
   5  * See LICENSE.qla4xxx for copyright and licensing details.
   6  */
   7 #include <linux/delay.h>
   8 #include <linux/pci.h>
   9 #include "ql4_def.h"
  10 #include "ql4_glbl.h"
  11
  12 #define MASK(n)         DMA_BIT_MASK(n)
  13 #define MN_WIN(addr)    (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
  14 #define OCM_WIN(addr)   (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
  15 #define MS_WIN(addr)    (addr & 0x0ffc0000)
  16 #define QLA82XX_PCI_MN_2M       (0)
  17 #define QLA82XX_PCI_MS_2M       (0x80000)
  18 #define QLA82XX_PCI_OCM0_2M     (0xc0000)
  19 #define VALID_OCM_ADDR(addr)    (((addr) & 0x3f800) != 0x3f800)
  20 #define GET_MEM_OFFS_2M(addr)   (addr & MASK(18))
  21
  22 /* CRB window related */
  23 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  24 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  25 #define CRB_WINDOW_2M   (0x130060)
  26 #define CRB_HI(off)     ((qla4_8xxx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  27                         ((off) & 0xf0000))
  28 #define QLA82XX_PCI_CAMQM_2M_END        (0x04800800UL)
  29 #define QLA82XX_PCI_CAMQM_2M_BASE       (0x000ff800UL)
  30 #define CRB_INDIRECT_2M                 (0x1e0000UL)
  31
  32 static inline void __iomem *
  33 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
  34 {
  35         if ((off < ha->first_page_group_end) &&
  36             (off >= ha->first_page_group_start))
  37                 return (void __iomem *)(ha->nx_pcibase + off);
  38
  39         return NULL;
  40 }
  41
  42 #define MAX_CRB_XFORM 60
  43 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  44 static int qla4_8xxx_crb_table_initialized;
  45
  46 #define qla4_8xxx_crb_addr_transform(name) \
  47         (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  48          QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  49 static void
  50 qla4_8xxx_crb_addr_transform_setup(void)
  51 {
  52         qla4_8xxx_crb_addr_transform(XDMA);
  53         qla4_8xxx_crb_addr_transform(TIMR);
  54         qla4_8xxx_crb_addr_transform(SRE);
  55         qla4_8xxx_crb_addr_transform(SQN3);
  56         qla4_8xxx_crb_addr_transform(SQN2);
  57         qla4_8xxx_crb_addr_transform(SQN1);
  58         qla4_8xxx_crb_addr_transform(SQN0);
  59         qla4_8xxx_crb_addr_transform(SQS3);
  60         qla4_8xxx_crb_addr_transform(SQS2);
  61         qla4_8xxx_crb_addr_transform(SQS1);
  62         qla4_8xxx_crb_addr_transform(SQS0);
  63         qla4_8xxx_crb_addr_transform(RPMX7);
  64         qla4_8xxx_crb_addr_transform(RPMX6);
  65         qla4_8xxx_crb_addr_transform(RPMX5);
  66         qla4_8xxx_crb_addr_transform(RPMX4);
  67         qla4_8xxx_crb_addr_transform(RPMX3);
  68         qla4_8xxx_crb_addr_transform(RPMX2);
  69         qla4_8xxx_crb_addr_transform(RPMX1);
  70         qla4_8xxx_crb_addr_transform(RPMX0);
  71         qla4_8xxx_crb_addr_transform(ROMUSB);
  72         qla4_8xxx_crb_addr_transform(SN);
  73         qla4_8xxx_crb_addr_transform(QMN);
  74         qla4_8xxx_crb_addr_transform(QMS);
  75         qla4_8xxx_crb_addr_transform(PGNI);
  76         qla4_8xxx_crb_addr_transform(PGND);
  77         qla4_8xxx_crb_addr_transform(PGN3);
  78         qla4_8xxx_crb_addr_transform(PGN2);
  79         qla4_8xxx_crb_addr_transform(PGN1);
  80         qla4_8xxx_crb_addr_transform(PGN0);
  81         qla4_8xxx_crb_addr_transform(PGSI);
  82         qla4_8xxx_crb_addr_transform(PGSD);
  83         qla4_8xxx_crb_addr_transform(PGS3);
  84         qla4_8xxx_crb_addr_transform(PGS2);
  85         qla4_8xxx_crb_addr_transform(PGS1);
  86         qla4_8xxx_crb_addr_transform(PGS0);
  87         qla4_8xxx_crb_addr_transform(PS);
  88         qla4_8xxx_crb_addr_transform(PH);
  89         qla4_8xxx_crb_addr_transform(NIU);
  90         qla4_8xxx_crb_addr_transform(I2Q);
  91         qla4_8xxx_crb_addr_transform(EG);
  92         qla4_8xxx_crb_addr_transform(MN);
  93         qla4_8xxx_crb_addr_transform(MS);
  94         qla4_8xxx_crb_addr_transform(CAS2);
  95         qla4_8xxx_crb_addr_transform(CAS1);
  96         qla4_8xxx_crb_addr_transform(CAS0);
  97         qla4_8xxx_crb_addr_transform(CAM);
  98         qla4_8xxx_crb_addr_transform(C2C1);
  99         qla4_8xxx_crb_addr_transform(C2C0);
 100         qla4_8xxx_crb_addr_transform(SMB);
 101         qla4_8xxx_crb_addr_transform(OCM0);
 102         qla4_8xxx_crb_addr_transform(I2C0);
 103
 104         qla4_8xxx_crb_table_initialized = 1;
 105 }
 106
 107 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
 108         {{{0, 0,         0,         0} } },             /* 0: PCI */
 109         {{{1, 0x0100000, 0x0102000, 0x120000},  /* 1: PCIE */
 110                 {1, 0x0110000, 0x0120000, 0x130000},
 111                 {1, 0x0120000, 0x0122000, 0x124000},
 112                 {1, 0x0130000, 0x0132000, 0x126000},
 113                 {1, 0x0140000, 0x0142000, 0x128000},
 114                 {1, 0x0150000, 0x0152000, 0x12a000},
 115                 {1, 0x0160000, 0x0170000, 0x110000},
 116                 {1, 0x0170000, 0x0172000, 0x12e000},
 117                 {0, 0x0000000, 0x0000000, 0x000000},
 118                 {0, 0x0000000, 0x0000000, 0x000000},
 119                 {0, 0x0000000, 0x0000000, 0x000000},
 120                 {0, 0x0000000, 0x0000000, 0x000000},
 121                 {0, 0x0000000, 0x0000000, 0x000000},
 122                 {0, 0x0000000, 0x0000000, 0x000000},
 123                 {1, 0x01e0000, 0x01e0800, 0x122000},
 124                 {0, 0x0000000, 0x0000000, 0x000000} } },
 125         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
 126         {{{0, 0,         0,         0} } },         /* 3: */
 127         {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
 128         {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
 129         {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
 130         {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
 131         {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
 132                 {0, 0x0000000, 0x0000000, 0x000000},
 133                 {0, 0x0000000, 0x0000000, 0x000000},
 134                 {0, 0x0000000, 0x0000000, 0x000000},
 135                 {0, 0x0000000, 0x0000000, 0x000000},
 136                 {0, 0x0000000, 0x0000000, 0x000000},
 137                 {0, 0x0000000, 0x0000000, 0x000000},
 138                 {0, 0x0000000, 0x0000000, 0x000000},
 139                 {0, 0x0000000, 0x0000000, 0x000000},
 140                 {0, 0x0000000, 0x0000000, 0x000000},
 141                 {0, 0x0000000, 0x0000000, 0x000000},
 142                 {0, 0x0000000, 0x0000000, 0x000000},
 143                 {0, 0x0000000, 0x0000000, 0x000000},
 144                 {0, 0x0000000, 0x0000000, 0x000000},
 145                 {0, 0x0000000, 0x0000000, 0x000000},
 146                 {1, 0x08f0000, 0x08f2000, 0x172000} } },
 147         {{{1, 0x0900000, 0x0902000, 0x174000},  /* 9: SQM1*/
 148                 {0, 0x0000000, 0x0000000, 0x000000},
 149                 {0, 0x0000000, 0x0000000, 0x000000},
 150                 {0, 0x0000000, 0x0000000, 0x000000},
 151                 {0, 0x0000000, 0x0000000, 0x000000},
 152                 {0, 0x0000000, 0x0000000, 0x000000},
 153                 {0, 0x0000000, 0x0000000, 0x000000},
 154                 {0, 0x0000000, 0x0000000, 0x000000},
 155                 {0, 0x0000000, 0x0000000, 0x000000},
 156                 {0, 0x0000000, 0x0000000, 0x000000},
 157                 {0, 0x0000000, 0x0000000, 0x000000},
 158                 {0, 0x0000000, 0x0000000, 0x000000},
 159                 {0, 0x0000000, 0x0000000, 0x000000},
 160                 {0, 0x0000000, 0x0000000, 0x000000},
 161                 {0, 0x0000000, 0x0000000, 0x000000},
 162                 {1, 0x09f0000, 0x09f2000, 0x176000} } },
 163         {{{0, 0x0a00000, 0x0a02000, 0x178000},  /* 10: SQM2*/
 164                 {0, 0x0000000, 0x0000000, 0x000000},
 165                 {0, 0x0000000, 0x0000000, 0x000000},
 166                 {0, 0x0000000, 0x0000000, 0x000000},
 167                 {0, 0x0000000, 0x0000000, 0x000000},
 168                 {0, 0x0000000, 0x0000000, 0x000000},
 169                 {0, 0x0000000, 0x0000000, 0x000000},
 170                 {0, 0x0000000, 0x0000000, 0x000000},
 171                 {0, 0x0000000, 0x0000000, 0x000000},
 172                 {0, 0x0000000, 0x0000000, 0x000000},
 173                 {0, 0x0000000, 0x0000000, 0x000000},
 174                 {0, 0x0000000, 0x0000000, 0x000000},
 175                 {0, 0x0000000, 0x0000000, 0x000000},
 176                 {0, 0x0000000, 0x0000000, 0x000000},
 177                 {0, 0x0000000, 0x0000000, 0x000000},
 178                 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 179         {{{0, 0x0b00000, 0x0b02000, 0x17c000},  /* 11: SQM3*/
 180                 {0, 0x0000000, 0x0000000, 0x000000},
 181                 {0, 0x0000000, 0x0000000, 0x000000},
 182                 {0, 0x0000000, 0x0000000, 0x000000},
 183                 {0, 0x0000000, 0x0000000, 0x000000},
 184                 {0, 0x0000000, 0x0000000, 0x000000},
 185                 {0, 0x0000000, 0x0000000, 0x000000},
 186                 {0, 0x0000000, 0x0000000, 0x000000},
 187                 {0, 0x0000000, 0x0000000, 0x000000},
 188                 {0, 0x0000000, 0x0000000, 0x000000},
 189                 {0, 0x0000000, 0x0000000, 0x000000},
 190                 {0, 0x0000000, 0x0000000, 0x000000},
 191                 {0, 0x0000000, 0x0000000, 0x000000},
 192                 {0, 0x0000000, 0x0000000, 0x000000},
 193                 {0, 0x0000000, 0x0000000, 0x000000},
 194                 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 195         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 196         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 197         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 198         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 199         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 200         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 201         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 202         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 203         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 204         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 205         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 206         {{{0, 0,         0,         0} } },     /* 23: */
 207         {{{0, 0,         0,         0} } },     /* 24: */
 208         {{{0, 0,         0,         0} } },     /* 25: */
 209         {{{0, 0,         0,         0} } },     /* 26: */
 210         {{{0, 0,         0,         0} } },     /* 27: */
 211         {{{0, 0,         0,         0} } },     /* 28: */
 212         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 213         {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 214         {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 215         {{{0} } },                              /* 32: PCI */
 216         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 217                 {1, 0x2110000, 0x2120000, 0x130000},
 218                 {1, 0x2120000, 0x2122000, 0x124000},
 219                 {1, 0x2130000, 0x2132000, 0x126000},
 220                 {1, 0x2140000, 0x2142000, 0x128000},
 221                 {1, 0x2150000, 0x2152000, 0x12a000},
 222                 {1, 0x2160000, 0x2170000, 0x110000},
 223                 {1, 0x2170000, 0x2172000, 0x12e000},
 224                 {0, 0x0000000, 0x0000000, 0x000000},
 225                 {0, 0x0000000, 0x0000000, 0x000000},
 226                 {0, 0x0000000, 0x0000000, 0x000000},
 227                 {0, 0x0000000, 0x0000000, 0x000000},
 228                 {0, 0x0000000, 0x0000000, 0x000000},
 229                 {0, 0x0000000, 0x0000000, 0x000000},
 230                 {0, 0x0000000, 0x0000000, 0x000000},
 231                 {0, 0x0000000, 0x0000000, 0x000000} } },
 232         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 233         {{{0} } },                              /* 35: */
 234         {{{0} } },                              /* 36: */
 235         {{{0} } },                              /* 37: */
 236         {{{0} } },                              /* 38: */
 237         {{{0} } },                              /* 39: */
 238         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 239         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 240         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 241         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 242         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 243         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 244         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 245         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 246         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 247         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 248         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 249         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 250         {{{0} } },                              /* 52: */
 251         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 252         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 253         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 254         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 255         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 256         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 257         {{{0} } },                              /* 59: I2C0 */
 258         {{{0} } },                              /* 60: I2C1 */
 259         {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
 260         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 261         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 262 };
 263
 264 /*
 265  * top 12 bits of crb internal address (hub, agent)
 266  */
 267 static unsigned qla4_8xxx_crb_hub_agt[64] = {
 268         0,
 269         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 270         QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
 271         QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
 272         0,
 273         QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
 274         QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
 275         QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
 276         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
 277         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
 278         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
 279         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
 280         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 281         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 282         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 283         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
 284         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 285         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
 286         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
 287         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
 288         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
 289         QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
 290         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
 291         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
 292         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
 293         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
 294         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
 295         0,
 296         QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
 297         QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
 298         0,
 299         QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
 300         0,
 301         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 302         QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
 303         0,
 304         0,
 305         0,
 306         0,
 307         0,
 308         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 309         0,
 310         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
 311         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
 312         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
 313         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
 314         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
 315         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
 316         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
 317         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 318         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 319         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 320         0,
 321         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
 322         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
 323         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
 324         QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
 325         0,
 326         QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
 327         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
 328         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
 329         0,
 330         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
 331         0,
 332 };
 333
 334 /* Device states */
 335 static char *qdev_state[] = {
 336         "Unknown",
 337         "Cold",
 338         "Initializing",
 339         "Ready",
 340         "Need Reset",
 341         "Need Quiescent",
 342         "Failed",
 343         "Quiescent",
 344 };
 345
 346 /*
 347  * In: 'off' is offset from CRB space in 128M pci map
 348  * Out: 'off' is 2M pci map addr
 349  * side effect: lock crb window
 350  */
 351 static void
 352 qla4_8xxx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
 353 {
 354         u32 win_read;
 355
 356         ha->crb_win = CRB_HI(*off);
 357         writel(ha->crb_win,
 358                 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 359
 360         /* Read back value to make sure write has gone through before trying
 361         * to use it. */
 362         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 363         if (win_read != ha->crb_win) {
 364                 DEBUG2(ql4_printk(KERN_INFO, ha,
 365                     "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
 366                     " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
 367         }
 368         *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
 369 }
 370
 371 void
 372 qla4_8xxx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
 373 {
 374         unsigned long flags = 0;
 375         int rv;
 376
 377         rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off);
 378
 379         BUG_ON(rv == -1);
 380
 381         if (rv == 1) {
 382                 write_lock_irqsave(&ha->hw_lock, flags);
 383                 qla4_8xxx_crb_win_lock(ha);
 384                 qla4_8xxx_pci_set_crbwindow_2M(ha, &off);
 385         }
 386
 387         writel(data, (void __iomem *)off);
 388
 389         if (rv == 1) {
 390                 qla4_8xxx_crb_win_unlock(ha);
 391                 write_unlock_irqrestore(&ha->hw_lock, flags);
 392         }
 393 }
 394
 395 int
 396 qla4_8xxx_rd_32(struct scsi_qla_host *ha, ulong off)
 397 {
 398         unsigned long flags = 0;
 399         int rv;
 400         u32 data;
 401
 402         rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off);
 403
 404         BUG_ON(rv == -1);
 405
 406         if (rv == 1) {
 407                 write_lock_irqsave(&ha->hw_lock, flags);
 408                 qla4_8xxx_crb_win_lock(ha);
 409                 qla4_8xxx_pci_set_crbwindow_2M(ha, &off);
 410         }
 411         data = readl((void __iomem *)off);
 412
 413         if (rv == 1) {
 414                 qla4_8xxx_crb_win_unlock(ha);
 415                 write_unlock_irqrestore(&ha->hw_lock, flags);
 416         }
 417         return data;
 418 }
 419
 420 #define CRB_WIN_LOCK_TIMEOUT 100000000
 421
 422 int qla4_8xxx_crb_win_lock(struct scsi_qla_host *ha)
 423 {
 424         int i;
 425         int done = 0, timeout = 0;
 426
 427         while (!done) {
 428                 /* acquire semaphore3 from PCI HW block */
 429                 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
 430                 if (done == 1)
 431                         break;
 432                 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
 433                         return -1;
 434
 435                 timeout++;
 436
 437                 /* Yield CPU */
 438                 if (!in_interrupt())
 439                         schedule();
 440                 else {
 441                         for (i = 0; i < 20; i++)
 442                                 cpu_relax();    /*This a nop instr on i386*/
 443                 }
 444         }
 445         qla4_8xxx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
 446         return 0;
 447 }
 448
 449 void qla4_8xxx_crb_win_unlock(struct scsi_qla_host *ha)
 450 {
 451         qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 452 }
 453
 454 #define IDC_LOCK_TIMEOUT 100000000
 455
 456 /**
 457  * qla4_8xxx_idc_lock - hw_lock
 458  * @ha: pointer to adapter structure
 459  *
 460  * General purpose lock used to synchronize access to
 461  * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
 462  **/
 463 int qla4_8xxx_idc_lock(struct scsi_qla_host *ha)
 464 {
 465         int i;
 466         int done = 0, timeout = 0;
 467
 468         while (!done) {
 469                 /* acquire semaphore5 from PCI HW block */
 470                 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
 471                 if (done == 1)
 472                         break;
 473                 if (timeout >= IDC_LOCK_TIMEOUT)
 474                         return -1;
 475
 476                 timeout++;
 477
 478                 /* Yield CPU */
 479                 if (!in_interrupt())
 480                         schedule();
 481                 else {
 482                         for (i = 0; i < 20; i++)
 483                                 cpu_relax();    /*This a nop instr on i386*/
 484                 }
 485         }
 486         return 0;
 487 }
 488
 489 void qla4_8xxx_idc_unlock(struct scsi_qla_host *ha)
 490 {
 491         qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
 492 }
 493
 494 int
 495 qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
 496 {
 497         struct crb_128M_2M_sub_block_map *m;
 498
 499         if (*off >= QLA82XX_CRB_MAX)
 500                 return -1;
 501
 502         if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
 503                 *off = (*off - QLA82XX_PCI_CAMQM) +
 504                     QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
 505                 return 0;
 506         }
 507
 508         if (*off < QLA82XX_PCI_CRBSPACE)
 509                 return -1;
 510
 511         *off -= QLA82XX_PCI_CRBSPACE;
 512         /*
 513          * Try direct map
 514          */
 515
 516         m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
 517
 518         if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
 519                 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
 520                 return 0;
 521         }
 522
 523         /*
 524          * Not in direct map, use crb window
 525          */
 526         return 1;
 527 }
 528
 529 /*  PCI Windowing for DDR regions.  */
 530 #define QLA82XX_ADDR_IN_RANGE(addr, low, high)            \
 531         (((addr) <= (high)) && ((addr) >= (low)))
 532
 533 /*
 534 * check memory access boundary.
 535 * used by test agent. support ddr access only for now
 536 */
 537 static unsigned long
 538 qla4_8xxx_pci_mem_bound_check(struct scsi_qla_host *ha,
 539                 unsigned long long addr, int size)
 540 {
 541         if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 542             QLA82XX_ADDR_DDR_NET_MAX) ||
 543             !QLA82XX_ADDR_IN_RANGE(addr + size - 1,
 544             QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) ||
 545             ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
 546                 return 0;
 547         }
 548         return 1;
 549 }
 550
 551 static int qla4_8xxx_pci_set_window_warning_count;
 552
 553 static unsigned long
 554 qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
 555 {
 556         int window;
 557         u32 win_read;
 558
 559         if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 560             QLA82XX_ADDR_DDR_NET_MAX)) {
 561                 /* DDR network side */
 562                 window = MN_WIN(addr);
 563                 ha->ddr_mn_window = window;
 564                 qla4_8xxx_wr_32(ha, ha->mn_win_crb |
 565                     QLA82XX_PCI_CRBSPACE, window);
 566                 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb |
 567                     QLA82XX_PCI_CRBSPACE);
 568                 if ((win_read << 17) != window) {
 569                         ql4_printk(KERN_WARNING, ha,
 570                         "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
 571                         __func__, window, win_read);
 572                 }
 573                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
 574         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
 575                                 QLA82XX_ADDR_OCM0_MAX)) {
 576                 unsigned int temp1;
 577                 /* if bits 19:18&17:11 are on */
 578                 if ((addr & 0x00ff800) == 0xff800) {
 579                         printk("%s: QM access not handled.\n", __func__);
 580                         addr = -1UL;
 581                 }
 582
 583                 window = OCM_WIN(addr);
 584                 ha->ddr_mn_window = window;
 585                 qla4_8xxx_wr_32(ha, ha->mn_win_crb |
 586                     QLA82XX_PCI_CRBSPACE, window);
 587                 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb |
 588                     QLA82XX_PCI_CRBSPACE);
 589                 temp1 = ((window & 0x1FF) << 7) |
 590                     ((window & 0x0FFFE0000) >> 17);
 591                 if (win_read != temp1) {
 592                         printk("%s: Written OCMwin (0x%x) != Read"
 593                             " OCMwin (0x%x)\n", __func__, temp1, win_read);
 594                 }
 595                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
 596
 597         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
 598                                 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
 599                 /* QDR network side */
 600                 window = MS_WIN(addr);
 601                 ha->qdr_sn_window = window;
 602                 qla4_8xxx_wr_32(ha, ha->ms_win_crb |
 603                     QLA82XX_PCI_CRBSPACE, window);
 604                 win_read = qla4_8xxx_rd_32(ha,
 605                      ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
 606                 if (win_read != window) {
 607                         printk("%s: Written MSwin (0x%x) != Read "
 608                             "MSwin (0x%x)\n", __func__, window, win_read);
 609                 }
 610                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
 611
 612         } else {
 613                 /*
 614                  * peg gdb frequently accesses memory that doesn't exist,
 615                  * this limits the chit chat so debugging isn't slowed down.
 616                  */
 617                 if ((qla4_8xxx_pci_set_window_warning_count++ < 8) ||
 618                     (qla4_8xxx_pci_set_window_warning_count%64 == 0)) {
 619                         printk("%s: Warning:%s Unknown address range!\n",
 620                             __func__, DRIVER_NAME);
 621                 }
 622                 addr = -1UL;
 623         }
 624         return addr;
 625 }
 626
 627 /* check if address is in the same windows as the previous access */
 628 static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host *ha,
 629                 unsigned long long addr)
 630 {
 631         int window;
 632         unsigned long long qdr_max;
 633
 634         qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
 635
 636         if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 637             QLA82XX_ADDR_DDR_NET_MAX)) {
 638                 /* DDR network side */
 639                 BUG();  /* MN access can not come here */
 640         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
 641              QLA82XX_ADDR_OCM0_MAX)) {
 642                 return 1;
 643         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
 644              QLA82XX_ADDR_OCM1_MAX)) {
 645                 return 1;
 646         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
 647             qdr_max)) {
 648                 /* QDR network side */
 649                 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
 650                 if (ha->qdr_sn_window == window)
 651                         return 1;
 652         }
 653
 654         return 0;
 655 }
 656
 657 static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha,
 658                 u64 off, void *data, int size)
 659 {
 660         unsigned long flags;
 661         void __iomem *addr;
 662         int ret = 0;
 663         u64 start;
 664         void __iomem *mem_ptr = NULL;
 665         unsigned long mem_base;
 666         unsigned long mem_page;
 667
 668         write_lock_irqsave(&ha->hw_lock, flags);
 669
 670         /*
 671          * If attempting to access unknown address or straddle hw windows,
 672          * do not access.
 673          */
 674         start = qla4_8xxx_pci_set_window(ha, off);
 675         if ((start == -1UL) ||
 676             (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) {
 677                 write_unlock_irqrestore(&ha->hw_lock, flags);
 678                 printk(KERN_ERR"%s out of bound pci memory access. "
 679                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 680                 return -1;
 681         }
 682
 683         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 684         if (!addr) {
 685                 write_unlock_irqrestore(&ha->hw_lock, flags);
 686                 mem_base = pci_resource_start(ha->pdev, 0);
 687                 mem_page = start & PAGE_MASK;
 688                 /* Map two pages whenever user tries to access addresses in two
 689                    consecutive pages.
 690                  */
 691                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 692                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
 693                 else
 694                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 695
 696                 if (mem_ptr == NULL) {
 697                         *(u8 *)data = 0;
 698                         return -1;
 699                 }
 700                 addr = mem_ptr;
 701                 addr += start & (PAGE_SIZE - 1);
 702                 write_lock_irqsave(&ha->hw_lock, flags);
 703         }
 704
 705         switch (size) {
 706         case 1:
 707                 *(u8  *)data = readb(addr);
 708                 break;
 709         case 2:
 710                 *(u16 *)data = readw(addr);
 711                 break;
 712         case 4:
 713                 *(u32 *)data = readl(addr);
 714                 break;
 715         case 8:
 716                 *(u64 *)data = readq(addr);
 717                 break;
 718         default:
 719                 ret = -1;
 720                 break;
 721         }
 722         write_unlock_irqrestore(&ha->hw_lock, flags);
 723
 724         if (mem_ptr)
 725                 iounmap(mem_ptr);
 726         return ret;
 727 }
 728
 729 static int
 730 qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
 731                 void *data, int size)
 732 {
 733         unsigned long flags;
 734         void __iomem *addr;
 735         int ret = 0;
 736         u64 start;
 737         void __iomem *mem_ptr = NULL;
 738         unsigned long mem_base;
 739         unsigned long mem_page;
 740
 741         write_lock_irqsave(&ha->hw_lock, flags);
 742
 743         /*
 744          * If attempting to access unknown address or straddle hw windows,
 745          * do not access.
 746          */
 747         start = qla4_8xxx_pci_set_window(ha, off);
 748         if ((start == -1UL) ||
 749             (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) {
 750                 write_unlock_irqrestore(&ha->hw_lock, flags);
 751                 printk(KERN_ERR"%s out of bound pci memory access. "
 752                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 753                 return -1;
 754         }
 755
 756         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 757         if (!addr) {
 758                 write_unlock_irqrestore(&ha->hw_lock, flags);
 759                 mem_base = pci_resource_start(ha->pdev, 0);
 760                 mem_page = start & PAGE_MASK;
 761                 /* Map two pages whenever user tries to access addresses in two
 762                    consecutive pages.
 763                  */
 764                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 765                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
 766                 else
 767                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 768                 if (mem_ptr == NULL)
 769                         return -1;
 770
 771                 addr = mem_ptr;
 772                 addr += start & (PAGE_SIZE - 1);
 773                 write_lock_irqsave(&ha->hw_lock, flags);
 774         }
 775
 776         switch (size) {
 777         case 1:
 778                 writeb(*(u8 *)data, addr);
 779                 break;
 780         case 2:
 781                 writew(*(u16 *)data, addr);
 782                 break;
 783         case 4:
 784                 writel(*(u32 *)data, addr);
 785                 break;
 786         case 8:
 787                 writeq(*(u64 *)data, addr);
 788                 break;
 789         default:
 790                 ret = -1;
 791                 break;
 792         }
 793         write_unlock_irqrestore(&ha->hw_lock, flags);
 794         if (mem_ptr)
 795                 iounmap(mem_ptr);
 796         return ret;
 797 }
 798
 799 #define MTU_FUDGE_FACTOR 100
 800
 801 static unsigned long
 802 qla4_8xxx_decode_crb_addr(unsigned long addr)
 803 {
 804         int i;
 805         unsigned long base_addr, offset, pci_base;
 806
 807         if (!qla4_8xxx_crb_table_initialized)
 808                 qla4_8xxx_crb_addr_transform_setup();
 809
 810         pci_base = ADDR_ERROR;
 811         base_addr = addr & 0xfff00000;
 812         offset = addr & 0x000fffff;
 813
 814         for (i = 0; i < MAX_CRB_XFORM; i++) {
 815                 if (crb_addr_xform[i] == base_addr) {
 816                         pci_base = i << 20;
 817                         break;
 818                 }
 819         }
 820         if (pci_base == ADDR_ERROR)
 821                 return pci_base;
 822         else
 823                 return pci_base + offset;
 824 }
 825
 826 static long rom_max_timeout = 100;
 827 static long qla4_8xxx_rom_lock_timeout = 100;
 828
 829 static int
 830 qla4_8xxx_rom_lock(struct scsi_qla_host *ha)
 831 {
 832         int i;
 833         int done = 0, timeout = 0;
 834
 835         while (!done) {
 836                 /* acquire semaphore2 from PCI HW block */
 837
 838                 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
 839                 if (done == 1)
 840                         break;
 841                 if (timeout >= qla4_8xxx_rom_lock_timeout)
 842                         return -1;
 843
 844                 timeout++;
 845
 846                 /* Yield CPU */
 847                 if (!in_interrupt())
 848                         schedule();
 849                 else {
 850                         for (i = 0; i < 20; i++)
 851                                 cpu_relax();    /*This a nop instr on i386*/
 852                 }
 853         }
 854         qla4_8xxx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
 855         return 0;
 856 }
 857
 858 static void
 859 qla4_8xxx_rom_unlock(struct scsi_qla_host *ha)
 860 {
 861         qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
 862 }
 863
 864 static int
 865 qla4_8xxx_wait_rom_done(struct scsi_qla_host *ha)
 866 {
 867         long timeout = 0;
 868         long done = 0 ;
 869
 870         while (done == 0) {
 871                 done = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 872                 done &= 2;
 873                 timeout++;
 874                 if (timeout >= rom_max_timeout) {
 875                         printk("%s: Timeout reached  waiting for rom done",
 876                                         DRIVER_NAME);
 877                         return -1;
 878                 }
 879         }
 880         return 0;
 881 }
 882
 883 static int
 884 qla4_8xxx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 885 {
 886         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
 887         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 888         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
 889         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
 890         if (qla4_8xxx_wait_rom_done(ha)) {
 891                 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
 892                 return -1;
 893         }
 894         /* reset abyte_cnt and dummy_byte_cnt */
 895         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 896         udelay(10);
 897         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
 898
 899         *valp = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
 900         return 0;
 901 }
 902
 903 static int
 904 qla4_8xxx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 905 {
 906         int ret, loops = 0;
 907
 908         while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) {
 909                 udelay(100);
 910                 loops++;
 911         }
 912         if (loops >= 50000) {
 913                 printk("%s: qla4_8xxx_rom_lock failed\n", DRIVER_NAME);
 914                 return -1;
 915         }
 916         ret = qla4_8xxx_do_rom_fast_read(ha, addr, valp);
 917         qla4_8xxx_rom_unlock(ha);
 918         return ret;
 919 }
 920
 921 /**
 922  * This routine does CRB initialize sequence
 923  * to put the ISP into operational state
 924  **/
 925 static int
 926 qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
 927 {
 928         int addr, val;
 929         int i ;
 930         struct crb_addr_pair *buf;
 931         unsigned long off;
 932         unsigned offset, n;
 933
 934         struct crb_addr_pair {
 935                 long addr;
 936                 long data;
 937         };
 938
 939         /* Halt all the indiviual PEGs and other blocks of the ISP */
 940         qla4_8xxx_rom_lock(ha);
 941         if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
 942                 /* don't reset CAM block on reset */
 943                 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
 944         else
 945                 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
 946
 947         qla4_8xxx_rom_unlock(ha);
 948
 949         /* Read the signature value from the flash.
 950          * Offset 0: Contain signature (0xcafecafe)
 951          * Offset 4: Offset and number of addr/value pairs
 952          * that present in CRB initialize sequence
 953          */
 954         if (qla4_8xxx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
 955             qla4_8xxx_rom_fast_read(ha, 4, &n) != 0) {
 956                 ql4_printk(KERN_WARNING, ha,
 957                         "[ERROR] Reading crb_init area: n: %08x\n", n);
 958                 return -1;
 959         }
 960
 961         /* Offset in flash = lower 16 bits
 962          * Number of enteries = upper 16 bits
 963          */
 964         offset = n & 0xffffU;
 965         n = (n >> 16) & 0xffffU;
 966
 967         /* number of addr/value pair should not exceed 1024 enteries */
 968         if (n  >= 1024) {
 969                 ql4_printk(KERN_WARNING, ha,
 970                     "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
 971                     DRIVER_NAME, __func__, n);
 972                 return -1;
 973         }
 974
 975         ql4_printk(KERN_INFO, ha,
 976                 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
 977
 978         buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
 979         if (buf == NULL) {
 980                 ql4_printk(KERN_WARNING, ha,
 981                     "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
 982                 return -1;
 983         }
 984
 985         for (i = 0; i < n; i++) {
 986                 if (qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
 987                     qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
 988                     0) {
 989                         kfree(buf);
 990                         return -1;
 991                 }
 992
 993                 buf[i].addr = addr;
 994                 buf[i].data = val;
 995         }
 996
 997         for (i = 0; i < n; i++) {
 998                 /* Translate internal CRB initialization
 999                  * address to PCI bus address
1000                  */
1001                 off = qla4_8xxx_decode_crb_addr((unsigned long)buf[i].addr) +
1002                     QLA82XX_PCI_CRBSPACE;
1003                 /* Not all CRB  addr/value pair to be written,
1004                  * some of them are skipped
1005                  */
1006
1007                 /* skip if LS bit is set*/
1008                 if (off & 0x1) {
1009                         DEBUG2(ql4_printk(KERN_WARNING, ha,
1010                             "Skip CRB init replay for offset = 0x%lx\n", off));
1011                         continue;
1012                 }
1013
1014                 /* skipping cold reboot MAGIC */
1015                 if (off == QLA82XX_CAM_RAM(0x1fc))
1016                         continue;
1017
1018                 /* do not reset PCI */
1019                 if (off == (ROMUSB_GLB + 0xbc))
1020                         continue;
1021
1022                 /* skip core clock, so that firmware can increase the clock */
1023                 if (off == (ROMUSB_GLB + 0xc8))
1024                         continue;
1025
1026                 /* skip the function enable register */
1027                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1028                         continue;
1029
1030                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1031                         continue;
1032
1033                 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1034                         continue;
1035
1036                 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1037                         continue;
1038
1039                 if (off == ADDR_ERROR) {
1040                         ql4_printk(KERN_WARNING, ha,
1041                             "%s: [ERROR] Unknown addr: 0x%08lx\n",
1042                             DRIVER_NAME, buf[i].addr);
1043                         continue;
1044                 }
1045
1046                 qla4_8xxx_wr_32(ha, off, buf[i].data);
1047
1048                 /* ISP requires much bigger delay to settle down,
1049                  * else crb_window returns 0xffffffff
1050                  */
1051                 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1052                         msleep(1000);
1053
1054                 /* ISP requires millisec delay between
1055                  * successive CRB register updation
1056                  */
1057                 msleep(1);
1058         }
1059
1060         kfree(buf);
1061
1062         /* Resetting the data and instruction cache */
1063         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1064         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1065         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1066
1067         /* Clear all protocol processing engines */
1068         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1069         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1070         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1071         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1072         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1073         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1074         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1075         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1076
1077         return 0;
1078 }
1079
1080 static int qla4_8xxx_check_for_bad_spd(struct scsi_qla_host *ha)
1081 {
1082         u32 val = 0;
1083         val = qla4_8xxx_rd_32(ha, BOOT_LOADER_DIMM_STATUS) ;
1084         val &= QLA82XX_BOOT_LOADER_MN_ISSUE;
1085         if (val & QLA82XX_PEG_TUNE_MN_SPD_ZEROED) {
1086                 printk("Memory DIMM SPD not programmed.  Assumed valid.\n");
1087                 return 1;
1088         } else if (val) {
1089                 printk("Memory DIMM type incorrect.  Info:%08X.\n", val);
1090                 return 2;
1091         }
1092         return 0;
1093 }
1094
1095 static int
1096 qla4_8xxx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1097 {
1098         int  i;
1099         long size = 0;
1100         long flashaddr, memaddr;
1101         u64 data;
1102         u32 high, low;
1103
1104         flashaddr = memaddr = ha->hw.flt_region_bootload;
1105         size = (image_start - flashaddr)/8;
1106
1107         DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1108             ha->host_no, __func__, flashaddr, image_start));
1109
1110         for (i = 0; i < size; i++) {
1111                 if ((qla4_8xxx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1112                     (qla4_8xxx_rom_fast_read(ha, flashaddr + 4,
1113                     (int *)&high))) {
1114                         return -1;
1115                 }
1116                 data = ((u64)high << 32) | low ;
1117                 qla4_8xxx_pci_mem_write_2M(ha, memaddr, &data, 8);
1118                 flashaddr += 8;
1119                 memaddr   += 8;
1120
1121                 if (i%0x1000 == 0)
1122                         msleep(1);
1123
1124         }
1125
1126         udelay(100);
1127
1128         read_lock(&ha->hw_lock);
1129         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1130         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1131         read_unlock(&ha->hw_lock);
1132
1133         return 0;
1134 }
1135
1136 static int qla4_8xxx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1137 {
1138         u32 rst;
1139
1140         qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1141         if (qla4_8xxx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1142                 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1143                     __func__);
1144                 return QLA_ERROR;
1145         }
1146
1147         udelay(500);
1148
1149         /* at this point, QM is in reset. This could be a problem if there are
1150          * incoming d* transition queue messages. QM/PCIE could wedge.
1151          * To get around this, QM is brought out of reset.
1152          */
1153
1154         rst = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1155         /* unreset qm */
1156         rst &= ~(1 << 28);
1157         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1158
1159         if (qla4_8xxx_load_from_flash(ha, image_start)) {
1160                 printk("%s: Error trying to load fw from flash!\n", __func__);
1161                 return QLA_ERROR;
1162         }
1163
1164         return QLA_SUCCESS;
1165 }
1166
1167 int
1168 qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha,
1169                 u64 off, void *data, int size)
1170 {
1171         int i, j = 0, k, start, end, loop, sz[2], off0[2];
1172         int shift_amount;
1173         uint32_t temp;
1174         uint64_t off8, val, mem_crb, word[2] = {0, 0};
1175
1176         /*
1177          * If not MN, go check for MS or invalid.
1178          */
1179
1180         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1181                 mem_crb = QLA82XX_CRB_QDR_NET;
1182         else {
1183                 mem_crb = QLA82XX_CRB_DDR_NET;
1184                 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0)
1185                         return qla4_8xxx_pci_mem_read_direct(ha,
1186                                         off, data, size);
1187         }
1188
1189
1190         off8 = off & 0xfffffff0;
1191         off0[0] = off & 0xf;
1192         sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1193         shift_amount = 4;
1194
1195         loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1196         off0[1] = 0;
1197         sz[1] = size - sz[0];
1198
1199         for (i = 0; i < loop; i++) {
1200                 temp = off8 + (i << shift_amount);
1201                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1202                 temp = 0;
1203                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1204                 temp = MIU_TA_CTL_ENABLE;
1205                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1206                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1207                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1208
1209                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1210                         temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1211                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1212                                 break;
1213                 }
1214
1215                 if (j >= MAX_CTL_CHECK) {
1216                         if (printk_ratelimit())
1217                                 ql4_printk(KERN_ERR, ha,
1218                                     "failed to read through agent\n");
1219                         break;
1220                 }
1221
1222                 start = off0[i] >> 2;
1223                 end   = (off0[i] + sz[i] - 1) >> 2;
1224                 for (k = start; k <= end; k++) {
1225                         temp = qla4_8xxx_rd_32(ha,
1226                                 mem_crb + MIU_TEST_AGT_RDDATA(k));
1227                         word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1228                 }
1229         }
1230
1231         if (j >= MAX_CTL_CHECK)
1232                 return -1;
1233
1234         if ((off0[0] & 7) == 0) {
1235                 val = word[0];
1236         } else {
1237                 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1238                 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1239         }
1240
1241         switch (size) {
1242         case 1:
1243                 *(uint8_t  *)data = val;
1244                 break;
1245         case 2:
1246                 *(uint16_t *)data = val;
1247                 break;
1248         case 4:
1249                 *(uint32_t *)data = val;
1250                 break;
1251         case 8:
1252                 *(uint64_t *)data = val;
1253                 break;
1254         }
1255         return 0;
1256 }
1257
1258 int
1259 qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha,
1260                 u64 off, void *data, int size)
1261 {
1262         int i, j, ret = 0, loop, sz[2], off0;
1263         int scale, shift_amount, startword;
1264         uint32_t temp;
1265         uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1266
1267         /*
1268          * If not MN, go check for MS or invalid.
1269          */
1270         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1271                 mem_crb = QLA82XX_CRB_QDR_NET;
1272         else {
1273                 mem_crb = QLA82XX_CRB_DDR_NET;
1274                 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0)
1275                         return qla4_8xxx_pci_mem_write_direct(ha,
1276                                         off, data, size);
1277         }
1278
1279         off0 = off & 0x7;
1280         sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1281         sz[1] = size - sz[0];
1282
1283         off8 = off & 0xfffffff0;
1284         loop = (((off & 0xf) + size - 1) >> 4) + 1;
1285         shift_amount = 4;
1286         scale = 2;
1287         startword = (off & 0xf)/8;
1288
1289         for (i = 0; i < loop; i++) {
1290                 if (qla4_8xxx_pci_mem_read_2M(ha, off8 +
1291                     (i << shift_amount), &word[i * scale], 8))
1292                         return -1;
1293         }
1294
1295         switch (size) {
1296         case 1:
1297                 tmpw = *((uint8_t *)data);
1298                 break;
1299         case 2:
1300                 tmpw = *((uint16_t *)data);
1301                 break;
1302         case 4:
1303                 tmpw = *((uint32_t *)data);
1304                 break;
1305         case 8:
1306         default:
1307                 tmpw = *((uint64_t *)data);
1308                 break;
1309         }
1310
1311         if (sz[0] == 8)
1312                 word[startword] = tmpw;
1313         else {
1314                 word[startword] &=
1315                     ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1316                 word[startword] |= tmpw << (off0 * 8);
1317         }
1318
1319         if (sz[1] != 0) {
1320                 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1321                 word[startword+1] |= tmpw >> (sz[0] * 8);
1322         }
1323
1324         for (i = 0; i < loop; i++) {
1325                 temp = off8 + (i << shift_amount);
1326                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1327                 temp = 0;
1328                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1329                 temp = word[i * scale] & 0xffffffff;
1330                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1331                 temp = (word[i * scale] >> 32) & 0xffffffff;
1332                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1333                 temp = word[i*scale + 1] & 0xffffffff;
1334                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1335                     temp);
1336                 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1337                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1338                     temp);
1339
1340                 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1341                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1342                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1343                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1344
1345                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1346                         temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1347                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1348                                 break;
1349                 }
1350
1351                 if (j >= MAX_CTL_CHECK) {
1352                         if (printk_ratelimit())
1353                                 ql4_printk(KERN_ERR, ha,
1354                                     "failed to write through agent\n");
1355                         ret = -1;
1356                         break;
1357                 }
1358         }
1359
1360         return ret;
1361 }
1362
1363 static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1364 {
1365         u32 val = 0;
1366         int retries = 60;
1367
1368         if (!pegtune_val) {
1369                 do {
1370                         val = qla4_8xxx_rd_32(ha, CRB_CMDPEG_STATE);
1371                         if ((val == PHAN_INITIALIZE_COMPLETE) ||
1372                             (val == PHAN_INITIALIZE_ACK))
1373                                 return 0;
1374                         set_current_state(TASK_UNINTERRUPTIBLE);
1375                         schedule_timeout(500);
1376
1377                 } while (--retries);
1378
1379                 qla4_8xxx_check_for_bad_spd(ha);
1380
1381                 if (!retries) {
1382                         pegtune_val = qla4_8xxx_rd_32(ha,
1383                                 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1384                         printk(KERN_WARNING "%s: init failed, "
1385                                 "pegtune_val = %x\n", __func__, pegtune_val);
1386                         return -1;
1387                 }
1388         }
1389         return 0;
1390 }
1391
1392 static int qla4_8xxx_rcvpeg_ready(struct scsi_qla_host *ha)
1393 {
1394         uint32_t state = 0;
1395         int loops = 0;
1396
1397         /* Window 1 call */
1398         read_lock(&ha->hw_lock);
1399         state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE);
1400         read_unlock(&ha->hw_lock);
1401
1402         while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1403                 udelay(100);
1404                 /* Window 1 call */
1405                 read_lock(&ha->hw_lock);
1406                 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE);
1407                 read_unlock(&ha->hw_lock);
1408
1409                 loops++;
1410         }
1411
1412         if (loops >= 30000) {
1413                 DEBUG2(ql4_printk(KERN_INFO, ha,
1414                     "Receive Peg initialization not complete: 0x%x.\n", state));
1415                 return QLA_ERROR;
1416         }
1417
1418         return QLA_SUCCESS;
1419 }
1420
1421 static inline void
1422 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1423 {
1424         uint32_t drv_active;
1425
1426         drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1427         drv_active |= (1 << (ha->func_num * 4));
1428         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1429 }
1430
1431 void
1432 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1433 {
1434         uint32_t drv_active;
1435
1436         drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1437         drv_active &= ~(1 << (ha->func_num * 4));
1438         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1439 }
1440
1441 static inline int
1442 qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1443 {
1444         uint32_t drv_state;
1445         int rval;
1446
1447         drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1448         rval = drv_state & (1 << (ha->func_num * 4));
1449         return rval;
1450 }
1451
1452 static inline void
1453 qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1454 {
1455         uint32_t drv_state;
1456
1457         drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1458         drv_state |= (1 << (ha->func_num * 4));
1459         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1460 }
1461
1462 static inline void
1463 qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1464 {
1465         uint32_t drv_state;
1466
1467         drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1468         drv_state &= ~(1 << (ha->func_num * 4));
1469         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1470 }
1471
1472 static inline void
1473 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1474 {
1475         uint32_t qsnt_state;
1476
1477         qsnt_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1478         qsnt_state |= (2 << (ha->func_num * 4));
1479         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
1480 }
1481
1482
1483 static int
1484 qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1485 {
1486         int pcie_cap;
1487         uint16_t lnk;
1488
1489         /* scrub dma mask expansion register */
1490         qla4_8xxx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1491
1492         /* Overwrite stale initialization register values */
1493         qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1494         qla4_8xxx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1495         qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1496         qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1497
1498         if (qla4_8xxx_load_fw(ha, image_start) != QLA_SUCCESS) {
1499                 printk("%s: Error trying to start fw!\n", __func__);
1500                 return QLA_ERROR;
1501         }
1502
1503         /* Handshake with the card before we register the devices. */
1504         if (qla4_8xxx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1505                 printk("%s: Error during card handshake!\n", __func__);
1506                 return QLA_ERROR;
1507         }
1508
1509         /* Negotiated Link width */
1510         pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
1511         pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
1512         ha->link_width = (lnk >> 4) & 0x3f;
1513
1514         /* Synchronize with Receive peg */
1515         return qla4_8xxx_rcvpeg_ready(ha);
1516 }
1517
1518 static int
1519 qla4_8xxx_try_start_fw(struct scsi_qla_host *ha)
1520 {
1521         int rval = QLA_ERROR;
1522
1523         /*
1524          * FW Load priority:
1525          * 1) Operational firmware residing in flash.
1526          * 2) Fail
1527          */
1528
1529         ql4_printk(KERN_INFO, ha,
1530             "FW: Retrieving flash offsets from FLT/FDT ...\n");
1531         rval = qla4_8xxx_get_flash_info(ha);
1532         if (rval != QLA_SUCCESS)
1533                 return rval;
1534
1535         ql4_printk(KERN_INFO, ha,
1536             "FW: Attempting to load firmware from flash...\n");
1537         rval = qla4_8xxx_start_firmware(ha, ha->hw.flt_region_fw);
1538         if (rval == QLA_SUCCESS)
1539                 return rval;
1540
1541         ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash FAILED...\n");
1542
1543         return rval;
1544 }
1545
1546 /**
1547  * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
1548  * @ha: pointer to adapter structure
1549  *
1550  * Note: IDC lock must be held upon entry
1551  **/
1552 static int
1553 qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
1554 {
1555         int rval, i, timeout;
1556         uint32_t old_count, count;
1557
1558         if (qla4_8xxx_need_reset(ha))
1559                 goto dev_initialize;
1560
1561         old_count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
1562
1563         for (i = 0; i < 10; i++) {
1564                 timeout = msleep_interruptible(200);
1565                 if (timeout) {
1566                         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
1567                            QLA82XX_DEV_FAILED);
1568                         return QLA_ERROR;
1569                 }
1570
1571                 count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
1572                 if (count != old_count)
1573                         goto dev_ready;
1574         }
1575
1576 dev_initialize:
1577         /* set to DEV_INITIALIZING */
1578         ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
1579         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING);
1580
1581         /* Driver that sets device state to initializating sets IDC version */
1582         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
1583
1584         qla4_8xxx_idc_unlock(ha);
1585         rval = qla4_8xxx_try_start_fw(ha);
1586         qla4_8xxx_idc_lock(ha);
1587
1588         if (rval != QLA_SUCCESS) {
1589                 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
1590                 qla4_8xxx_clear_drv_active(ha);
1591                 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED);
1592                 return rval;
1593         }
1594
1595 dev_ready:
1596         ql4_printk(KERN_INFO, ha, "HW State: READY\n");
1597         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY);
1598
1599         return QLA_SUCCESS;
1600 }
1601
1602 /**
1603  * qla4_8xxx_need_reset_handler - Code to start reset sequence
1604  * @ha: pointer to adapter structure
1605  *
1606  * Note: IDC lock must be held upon entry
1607  **/
1608 static void
1609 qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha)
1610 {
1611         uint32_t dev_state, drv_state, drv_active;
1612         unsigned long reset_timeout;
1613
1614         ql4_printk(KERN_INFO, ha,
1615                 "Performing ISP error recovery\n");
1616
1617         if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
1618                 qla4_8xxx_idc_unlock(ha);
1619                 ha->isp_ops->disable_intrs(ha);
1620                 qla4_8xxx_idc_lock(ha);
1621         }
1622
1623         qla4_8xxx_set_rst_ready(ha);
1624
1625         /* wait for 10 seconds for reset ack from all functions */
1626         reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
1627
1628         drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1629         drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1630
1631         ql4_printk(KERN_INFO, ha,
1632                 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
1633                 __func__, ha->host_no, drv_state, drv_active);
1634
1635         while (drv_state != drv_active) {
1636                 if (time_after_eq(jiffies, reset_timeout)) {
1637                         printk("%s: RESET TIMEOUT!\n", DRIVER_NAME);
1638                         break;
1639                 }
1640
1641                 qla4_8xxx_idc_unlock(ha);
1642                 msleep(1000);
1643                 qla4_8xxx_idc_lock(ha);
1644
1645                 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1646                 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1647         }
1648
1649         dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1650         ql4_printk(KERN_INFO, ha, "3:Device state is 0x%x = %s\n", dev_state,
1651                 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1652
1653         /* Force to DEV_COLD unless someone else is starting a reset */
1654         if (dev_state != QLA82XX_DEV_INITIALIZING) {
1655                 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
1656                 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD);
1657         }
1658 }
1659
1660 /**
1661  * qla4_8xxx_need_qsnt_handler - Code to start qsnt
1662  * @ha: pointer to adapter structure
1663  **/
1664 void
1665 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
1666 {
1667         qla4_8xxx_idc_lock(ha);
1668         qla4_8xxx_set_qsnt_ready(ha);
1669         qla4_8xxx_idc_unlock(ha);
1670 }
1671
1672 /**
1673  * qla4_8xxx_device_state_handler - Adapter state machine
1674  * @ha: pointer to host adapter structure.
1675  *
1676  * Note: IDC lock must be UNLOCKED upon entry
1677  **/
1678 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
1679 {
1680         uint32_t dev_state;
1681         int rval = QLA_SUCCESS;
1682         unsigned long dev_init_timeout;
1683
1684         if (!test_bit(AF_INIT_DONE, &ha->flags))
1685                 qla4_8xxx_set_drv_active(ha);
1686
1687         dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1688         ql4_printk(KERN_INFO, ha, "1:Device state is 0x%x = %s\n", dev_state,
1689                 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1690
1691         /* wait for 30 seconds for device to go ready */
1692         dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
1693
1694         while (1) {
1695                 qla4_8xxx_idc_lock(ha);
1696
1697                 if (time_after_eq(jiffies, dev_init_timeout)) {
1698                         ql4_printk(KERN_WARNING, ha, "Device init failed!\n");
1699                         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
1700                                 QLA82XX_DEV_FAILED);
1701                 }
1702
1703                 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
1704                 ql4_printk(KERN_INFO, ha,
1705                     "2:Device state is 0x%x = %s\n", dev_state,
1706                     dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
1707
1708                 /* NOTE: Make sure idc unlocked upon exit of switch statement */
1709                 switch (dev_state) {
1710                 case QLA82XX_DEV_READY:
1711                         qla4_8xxx_idc_unlock(ha);
1712                         goto exit;
1713                 case QLA82XX_DEV_COLD:
1714                         rval = qla4_8xxx_device_bootstrap(ha);
1715                         qla4_8xxx_idc_unlock(ha);
1716                         goto exit;
1717                 case QLA82XX_DEV_INITIALIZING:
1718                         qla4_8xxx_idc_unlock(ha);
1719                         msleep(1000);
1720                         break;
1721                 case QLA82XX_DEV_NEED_RESET:
1722                         if (!ql4xdontresethba) {
1723                                 qla4_8xxx_need_reset_handler(ha);
1724                                 /* Update timeout value after need
1725                                  * reset handler */
1726                                 dev_init_timeout = jiffies +
1727                                         (ha->nx_dev_init_timeout * HZ);
1728                         }
1729                         qla4_8xxx_idc_unlock(ha);
1730                         break;
1731                 case QLA82XX_DEV_NEED_QUIESCENT:
1732                         qla4_8xxx_idc_unlock(ha);
1733                         /* idc locked/unlocked in handler */
1734                         qla4_8xxx_need_qsnt_handler(ha);
1735                         qla4_8xxx_idc_lock(ha);
1736                         /* fall thru needs idc_locked */
1737                 case QLA82XX_DEV_QUIESCENT:
1738                         qla4_8xxx_idc_unlock(ha);
1739                         msleep(1000);
1740                         break;
1741                 case QLA82XX_DEV_FAILED:
1742                         qla4_8xxx_idc_unlock(ha);
1743                         qla4xxx_dead_adapter_cleanup(ha);
1744                         rval = QLA_ERROR;
1745                         goto exit;
1746                 default:
1747                         qla4_8xxx_idc_unlock(ha);
1748                         qla4xxx_dead_adapter_cleanup(ha);
1749                         rval = QLA_ERROR;
1750                         goto exit;
1751                 }
1752         }
1753 exit:
1754         return rval;
1755 }
1756
1757 int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
1758 {
1759         int retval;
1760         retval = qla4_8xxx_device_state_handler(ha);
1761
1762         if (retval == QLA_SUCCESS &&
1763             !test_bit(AF_INIT_DONE, &ha->flags)) {
1764                 retval = qla4xxx_request_irqs(ha);
1765                 if (retval != QLA_SUCCESS) {
1766                         ql4_printk(KERN_WARNING, ha,
1767                             "Failed to reserve interrupt %d already in use.\n",
1768                             ha->pdev->irq);
1769                 } else {
1770                         set_bit(AF_IRQ_ATTACHED, &ha->flags);
1771                         ha->host->irq = ha->pdev->irq;
1772                         ql4_printk(KERN_INFO, ha, "%s: irq %d attached\n",
1773                             __func__, ha->pdev->irq);
1774                 }
1775         }
1776         return retval;
1777 }
1778
1779 /*****************************************************************************/
1780 /* Flash Manipulation Routines                                               */
1781 /*****************************************************************************/
1782
1783 #define OPTROM_BURST_SIZE       0x1000
1784 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
1785
1786 #define FARX_DATA_FLAG  BIT_31
1787 #define FARX_ACCESS_FLASH_CONF  0x7FFD0000
1788 #define FARX_ACCESS_FLASH_DATA  0x7FF00000
1789
1790 static inline uint32_t
1791 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
1792 {
1793         return hw->flash_conf_off | faddr;
1794 }
1795
1796 static inline uint32_t
1797 flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
1798 {
1799         return hw->flash_data_off | faddr;
1800 }
1801
1802 static uint32_t *
1803 qla4_8xxx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
1804     uint32_t faddr, uint32_t length)
1805 {
1806         uint32_t i;
1807         uint32_t val;
1808         int loops = 0;
1809         while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) {
1810                 udelay(100);
1811                 cond_resched();
1812                 loops++;
1813         }
1814         if (loops >= 50000) {
1815                 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
1816                 return dwptr;
1817         }
1818
1819         /* Dword reads to flash. */
1820         for (i = 0; i < length/4; i++, faddr += 4) {
1821                 if (qla4_8xxx_do_rom_fast_read(ha, faddr, &val)) {
1822                         ql4_printk(KERN_WARNING, ha,
1823                             "Do ROM fast read failed\n");
1824                         goto done_read;
1825                 }
1826                 dwptr[i] = __constant_cpu_to_le32(val);
1827         }
1828
1829 done_read:
1830         qla4_8xxx_rom_unlock(ha);
1831         return dwptr;
1832 }
1833
1834 /**
1835  * Address and length are byte address
1836  **/
1837 static uint8_t *
1838 qla4_8xxx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1839                 uint32_t offset, uint32_t length)
1840 {
1841         qla4_8xxx_read_flash_data(ha, (uint32_t *)buf, offset, length);
1842         return buf;
1843 }
1844
1845 static int
1846 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
1847 {
1848         const char *loc, *locations[] = { "DEF", "PCI" };
1849
1850         /*
1851          * FLT-location structure resides after the last PCI region.
1852          */
1853
1854         /* Begin with sane defaults. */
1855         loc = locations[0];
1856         *start = FA_FLASH_LAYOUT_ADDR_82;
1857
1858         DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
1859         return QLA_SUCCESS;
1860 }
1861
1862 static void
1863 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
1864 {
1865         const char *loc, *locations[] = { "DEF", "FLT" };
1866         uint16_t *wptr;
1867         uint16_t cnt, chksum;
1868         uint32_t start;
1869         struct qla_flt_header *flt;
1870         struct qla_flt_region *region;
1871         struct ql82xx_hw_data *hw = &ha->hw;
1872
1873         hw->flt_region_flt = flt_addr;
1874         wptr = (uint16_t *)ha->request_ring;
1875         flt = (struct qla_flt_header *)ha->request_ring;
1876         region = (struct qla_flt_region *)&flt[1];
1877         qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
1878                         flt_addr << 2, OPTROM_BURST_SIZE);
1879         if (*wptr == __constant_cpu_to_le16(0xffff))
1880                 goto no_flash_data;
1881         if (flt->version != __constant_cpu_to_le16(1)) {
1882                 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
1883                         "version=0x%x length=0x%x checksum=0x%x.\n",
1884                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
1885                         le16_to_cpu(flt->checksum)));
1886                 goto no_flash_data;
1887         }
1888
1889         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
1890         for (chksum = 0; cnt; cnt--)
1891                 chksum += le16_to_cpu(*wptr++);
1892         if (chksum) {
1893                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
1894                         "version=0x%x length=0x%x checksum=0x%x.\n",
1895                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
1896                         chksum));
1897                 goto no_flash_data;
1898         }
1899
1900         loc = locations[1];
1901         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
1902         for ( ; cnt; cnt--, region++) {
1903                 /* Store addresses as DWORD offsets. */
1904                 start = le32_to_cpu(region->start) >> 2;
1905
1906                 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
1907                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
1908                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
1909
1910                 switch (le32_to_cpu(region->code) & 0xff) {
1911                 case FLT_REG_FDT:
1912                         hw->flt_region_fdt = start;
1913                         break;
1914                 case FLT_REG_BOOT_CODE_82:
1915                         hw->flt_region_boot = start;
1916                         break;
1917                 case FLT_REG_FW_82:
1918                         hw->flt_region_fw = start;
1919                         break;
1920                 case FLT_REG_BOOTLOAD_82:
1921                         hw->flt_region_bootload = start;
1922                         break;
1923                 }
1924         }
1925         goto done;
1926
1927 no_flash_data:
1928         /* Use hardcoded defaults. */
1929         loc = locations[0];
1930
1931         hw->flt_region_fdt      = FA_FLASH_DESCR_ADDR_82;
1932         hw->flt_region_boot     = FA_BOOT_CODE_ADDR_82;
1933         hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
1934         hw->flt_region_fw       = FA_RISC_CODE_ADDR_82;
1935 done:
1936         DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x "
1937             "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt,
1938             hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload,
1939             hw->flt_region_fw));
1940 }
1941
1942 static void
1943 qla4_8xxx_get_fdt_info(struct scsi_qla_host *ha)
1944 {
1945 #define FLASH_BLK_SIZE_4K       0x1000
1946 #define FLASH_BLK_SIZE_32K      0x8000
1947 #define FLASH_BLK_SIZE_64K      0x10000
1948         const char *loc, *locations[] = { "MID", "FDT" };
1949         uint16_t cnt, chksum;
1950         uint16_t *wptr;
1951         struct qla_fdt_layout *fdt;
1952         uint16_t mid, fid;
1953         struct ql82xx_hw_data *hw = &ha->hw;
1954
1955         hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
1956         hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
1957
1958         wptr = (uint16_t *)ha->request_ring;
1959         fdt = (struct qla_fdt_layout *)ha->request_ring;
1960         qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
1961             hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
1962
1963         if (*wptr == __constant_cpu_to_le16(0xffff))
1964                 goto no_flash_data;
1965
1966         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
1967             fdt->sig[3] != 'D')
1968                 goto no_flash_data;
1969
1970         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
1971             cnt++)
1972                 chksum += le16_to_cpu(*wptr++);
1973
1974         if (chksum) {
1975                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
1976                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
1977                     le16_to_cpu(fdt->version)));
1978                 goto no_flash_data;
1979         }
1980
1981         loc = locations[1];
1982         mid = le16_to_cpu(fdt->man_id);
1983         fid = le16_to_cpu(fdt->id);
1984         hw->fdt_wrt_disable = fdt->wrt_disable_bits;
1985         hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
1986         hw->fdt_block_size = le32_to_cpu(fdt->block_size);
1987
1988         if (fdt->unprotect_sec_cmd) {
1989                 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
1990                     fdt->unprotect_sec_cmd);
1991                 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
1992                     flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
1993                     flash_conf_addr(hw, 0x0336);
1994         }
1995         goto done;
1996
1997 no_flash_data:
1998         loc = locations[0];
1999         hw->fdt_block_size = FLASH_BLK_SIZE_64K;
2000 done:
2001         DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
2002                 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
2003                 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
2004                 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
2005                 hw->fdt_block_size));
2006 }
2007
2008 static void
2009 qla4_8xxx_get_idc_param(struct scsi_qla_host *ha)
2010 {
2011 #define QLA82XX_IDC_PARAM_ADDR      0x003e885c
2012         uint32_t *wptr;
2013
2014         if (!is_qla8022(ha))
2015                 return;
2016         wptr = (uint32_t *)ha->request_ring;
2017         qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2018                         QLA82XX_IDC_PARAM_ADDR , 8);
2019
2020         if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
2021                 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
2022                 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
2023         } else {
2024                 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
2025                 ha->nx_reset_timeout = le32_to_cpu(*wptr);
2026         }
2027
2028         DEBUG2(ql4_printk(KERN_DEBUG, ha,
2029                 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
2030         DEBUG2(ql4_printk(KERN_DEBUG, ha,
2031                 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
2032         return;
2033 }
2034
2035 int
2036 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
2037 {
2038         int ret;
2039         uint32_t flt_addr;
2040
2041         ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
2042         if (ret != QLA_SUCCESS)
2043                 return ret;
2044
2045         qla4_8xxx_get_flt_info(ha, flt_addr);
2046         qla4_8xxx_get_fdt_info(ha);
2047         qla4_8xxx_get_idc_param(ha);
2048
2049         return QLA_SUCCESS;
2050 }
2051
2052 /**
2053  * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
2054  * @ha: pointer to host adapter structure.
2055  *
2056  * Remarks:
2057  * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
2058  * not be available after successful return.  Driver must cleanup potential
2059  * outstanding I/O's after calling this funcion.
2060  **/
2061 int
2062 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
2063 {
2064         int status;
2065         uint32_t mbox_cmd[MBOX_REG_COUNT];
2066         uint32_t mbox_sts[MBOX_REG_COUNT];
2067
2068         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2069         memset(&mbox_sts, 0, sizeof(mbox_sts));
2070
2071         mbox_cmd[0] = MBOX_CMD_STOP_FW;
2072         status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
2073             &mbox_cmd[0], &mbox_sts[0]);
2074
2075         DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
2076             __func__, status));
2077         return status;
2078 }
2079
2080 /**
2081  * qla4_8xxx_isp_reset - Resets ISP and aborts all outstanding commands.
2082  * @ha: pointer to host adapter structure.
2083  **/
2084 int
2085 qla4_8xxx_isp_reset(struct scsi_qla_host *ha)
2086 {
2087         int rval;
2088         uint32_t dev_state;
2089
2090         qla4_8xxx_idc_lock(ha);
2091         dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2092
2093         if (dev_state == QLA82XX_DEV_READY) {
2094                 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
2095                 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2096                     QLA82XX_DEV_NEED_RESET);
2097         } else
2098                 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
2099
2100         qla4_8xxx_idc_unlock(ha);
2101
2102         rval = qla4_8xxx_device_state_handler(ha);
2103
2104         qla4_8xxx_idc_lock(ha);
2105         qla4_8xxx_clear_rst_ready(ha);
2106         qla4_8xxx_idc_unlock(ha);
2107
2108         return rval;
2109 }
2110
2111 /**
2112  * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
2113  * @ha: pointer to host adapter structure.
2114  *
2115  **/
2116 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
2117 {
2118         uint32_t mbox_cmd[MBOX_REG_COUNT];
2119         uint32_t mbox_sts[MBOX_REG_COUNT];
2120         struct mbx_sys_info *sys_info;
2121         dma_addr_t sys_info_dma;
2122         int status = QLA_ERROR;
2123
2124         sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
2125                                       &sys_info_dma, GFP_KERNEL);
2126         if (sys_info == NULL) {
2127                 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
2128                     ha->host_no, __func__));
2129                 return status;
2130         }
2131
2132         memset(sys_info, 0, sizeof(*sys_info));
2133         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2134         memset(&mbox_sts, 0, sizeof(mbox_sts));
2135
2136         mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
2137         mbox_cmd[1] = LSDW(sys_info_dma);
2138         mbox_cmd[2] = MSDW(sys_info_dma);
2139         mbox_cmd[4] = sizeof(*sys_info);
2140
2141         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
2142             &mbox_sts[0]) != QLA_SUCCESS) {
2143                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
2144                     ha->host_no, __func__));
2145                 goto exit_validate_mac82;
2146         }
2147
2148         if (mbox_sts[4] < sizeof(*sys_info)) {
2149                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
2150                     " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
2151                 goto exit_validate_mac82;
2152
2153         }
2154
2155         /* Save M.A.C. address & serial_number */
2156         memcpy(ha->my_mac, &sys_info->mac_addr[0],
2157             min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
2158         memcpy(ha->serial_number, &sys_info->serial_number,
2159             min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
2160
2161         DEBUG2(printk("scsi%ld: %s: "
2162             "mac %02x:%02x:%02x:%02x:%02x:%02x "
2163             "serial %s\n", ha->host_no, __func__,
2164             ha->my_mac[0], ha->my_mac[1], ha->my_mac[2],
2165             ha->my_mac[3], ha->my_mac[4], ha->my_mac[5],
2166             ha->serial_number));
2167
2168         status = QLA_SUCCESS;
2169
2170 exit_validate_mac82:
2171         dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
2172                           sys_info_dma);
2173         return status;
2174 }
2175
2176 /* Interrupt handling helpers. */
2177
2178 static int
2179 qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha)
2180 {
2181         uint32_t mbox_cmd[MBOX_REG_COUNT];
2182         uint32_t mbox_sts[MBOX_REG_COUNT];
2183
2184         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
2185
2186         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2187         memset(&mbox_sts, 0, sizeof(mbox_sts));
2188         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
2189         mbox_cmd[1] = INTR_ENABLE;
2190         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2191                 &mbox_sts[0]) != QLA_SUCCESS) {
2192                 DEBUG2(ql4_printk(KERN_INFO, ha,
2193                     "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
2194                     __func__, mbox_sts[0]));
2195                 return QLA_ERROR;
2196         }
2197         return QLA_SUCCESS;
2198 }
2199
2200 static int
2201 qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha)
2202 {
2203         uint32_t mbox_cmd[MBOX_REG_COUNT];
2204         uint32_t mbox_sts[MBOX_REG_COUNT];
2205
2206         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
2207
2208         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2209         memset(&mbox_sts, 0, sizeof(mbox_sts));
2210         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
2211         mbox_cmd[1] = INTR_DISABLE;
2212         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2213             &mbox_sts[0]) != QLA_SUCCESS) {
2214                 DEBUG2(ql4_printk(KERN_INFO, ha,
2215                         "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
2216                         __func__, mbox_sts[0]));
2217                 return QLA_ERROR;
2218         }
2219
2220         return QLA_SUCCESS;
2221 }
2222
2223 void
2224 qla4_8xxx_enable_intrs(struct scsi_qla_host *ha)
2225 {
2226         qla4_8xxx_mbx_intr_enable(ha);
2227
2228         spin_lock_irq(&ha->hardware_lock);
2229         /* BIT 10 - reset */
2230         qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2231         spin_unlock_irq(&ha->hardware_lock);
2232         set_bit(AF_INTERRUPTS_ON, &ha->flags);
2233 }
2234
2235 void
2236 qla4_8xxx_disable_intrs(struct scsi_qla_host *ha)
2237 {
2238         if (test_bit(AF_INTERRUPTS_ON, &ha->flags))
2239                 qla4_8xxx_mbx_intr_disable(ha);
2240
2241         spin_lock_irq(&ha->hardware_lock);
2242         /* BIT 10 - set */
2243         qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2244         spin_unlock_irq(&ha->hardware_lock);
2245         clear_bit(AF_INTERRUPTS_ON, &ha->flags);
2246 }
2247
2248 struct ql4_init_msix_entry {
2249         uint16_t entry;
2250         uint16_t index;
2251         const char *name;
2252         irq_handler_t handler;
2253 };
2254
2255 static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = {
2256         { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT,
2257             "qla4xxx (default)",
2258             (irq_handler_t)qla4_8xxx_default_intr_handler },
2259         { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q,
2260             "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q },
2261 };
2262
2263 void
2264 qla4_8xxx_disable_msix(struct scsi_qla_host *ha)
2265 {
2266         int i;
2267         struct ql4_msix_entry *qentry;
2268
2269         for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
2270                 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
2271                 if (qentry->have_irq) {
2272                         free_irq(qentry->msix_vector, ha);
2273                         DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
2274                                 __func__, qla4_8xxx_msix_entries[i].name));
2275                 }
2276         }
2277         pci_disable_msix(ha->pdev);
2278         clear_bit(AF_MSIX_ENABLED, &ha->flags);
2279 }
2280
2281 int
2282 qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
2283 {
2284         int i, ret;
2285         struct msix_entry entries[QLA_MSIX_ENTRIES];
2286         struct ql4_msix_entry *qentry;
2287
2288         for (i = 0; i < QLA_MSIX_ENTRIES; i++)
2289                 entries[i].entry = qla4_8xxx_msix_entries[i].entry;
2290
2291         ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries));
2292         if (ret) {
2293                 ql4_printk(KERN_WARNING, ha,
2294                     "MSI-X: Failed to enable support -- %d/%d\n",
2295                     QLA_MSIX_ENTRIES, ret);
2296                 goto msix_out;
2297         }
2298         set_bit(AF_MSIX_ENABLED, &ha->flags);
2299
2300         for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
2301                 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
2302                 qentry->msix_vector = entries[i].vector;
2303                 qentry->msix_entry = entries[i].entry;
2304                 qentry->have_irq = 0;
2305                 ret = request_irq(qentry->msix_vector,
2306                     qla4_8xxx_msix_entries[i].handler, 0,
2307                     qla4_8xxx_msix_entries[i].name, ha);
2308                 if (ret) {
2309                         ql4_printk(KERN_WARNING, ha,
2310                             "MSI-X: Unable to register handler -- %x/%d.\n",
2311                             qla4_8xxx_msix_entries[i].index, ret);
2312                         qla4_8xxx_disable_msix(ha);
2313                         goto msix_out;
2314                 }
2315                 qentry->have_irq = 1;
2316                 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
2317                         __func__, qla4_8xxx_msix_entries[i].name));
2318         }
2319 msix_out:
2320         return ret;
2321 }