drivers/scsi/qla4xxx/ql4_fw.h

   1 /*
   2  * QLogic iSCSI HBA Driver
   3  * Copyright (c)  2003-2010 QLogic Corporation
   4  *
   5  * See LICENSE.qla4xxx for copyright and licensing details.
   6  */
   7
   8 #ifndef _QLA4X_FW_H
   9 #define _QLA4X_FW_H
  10
  11
  12 #define MAX_PRST_DEV_DB_ENTRIES         64
  13 #define MIN_DISC_DEV_DB_ENTRY           MAX_PRST_DEV_DB_ENTRIES
  14 #define MAX_DEV_DB_ENTRIES              512
  15
  16 /*************************************************************************
  17  *
  18  *              ISP 4010 I/O Register Set Structure and Definitions
  19  *
  20  *************************************************************************/
  21
  22 struct port_ctrl_stat_regs {
  23         __le32 ext_hw_conf;     /* 0x50  R/W */
  24         __le32 rsrvd0;          /* 0x54 */
  25         __le32 port_ctrl;       /* 0x58 */
  26         __le32 port_status;     /* 0x5c */
  27         __le32 rsrvd1[32];      /* 0x60-0xdf */
  28         __le32 gp_out;          /* 0xe0 */
  29         __le32 gp_in;           /* 0xe4 */
  30         __le32 rsrvd2[5];       /* 0xe8-0xfb */
  31         __le32 port_err_status; /* 0xfc */
  32 };
  33
  34 struct host_mem_cfg_regs {
  35         __le32 rsrvd0[12];      /* 0x50-0x79 */
  36         __le32 req_q_out;       /* 0x80 */
  37         __le32 rsrvd1[31];      /* 0x84-0xFF */
  38 };
  39
  40 /*
  41  * ISP 82xx I/O Register Set structure definitions.
  42  */
  43 struct device_reg_82xx {
  44         __le32 req_q_out;       /* 0x0000 (R): Request Queue out-Pointer. */
  45         __le32 reserve1[63];    /* Request Queue out-Pointer. (64 * 4) */
  46         __le32 rsp_q_in;        /* 0x0100 (R/W): Response Queue In-Pointer. */
  47         __le32 reserve2[63];    /* Response Queue In-Pointer. */
  48         __le32 rsp_q_out;       /* 0x0200 (R/W): Response Queue Out-Pointer. */
  49         __le32 reserve3[63];    /* Response Queue Out-Pointer. */
  50
  51         __le32 mailbox_in[8];   /* 0x0300 (R/W): Mail box In registers */
  52         __le32 reserve4[24];
  53         __le32 hint;            /* 0x0380 (R/W): Host interrupt register */
  54 #define HINT_MBX_INT_PENDING    BIT_0
  55         __le32 reserve5[31];
  56         __le32 mailbox_out[8];  /* 0x0400 (R): Mail box Out registers */
  57         __le32 reserve6[56];
  58
  59         __le32 host_status;     /* Offset 0x500 (R): host status */
  60 #define HSRX_RISC_MB_INT        BIT_0  /* RISC to Host Mailbox interrupt */
  61 #define HSRX_RISC_IOCB_INT      BIT_1  /* RISC to Host IOCB interrupt */
  62
  63         __le32 host_int;        /* Offset 0x0504 (R/W): Interrupt status. */
  64 #define ISRX_82XX_RISC_INT      BIT_0 /* RISC interrupt. */
  65 };
  66
  67 /*  remote register set (access via PCI memory read/write) */
  68 struct isp_reg {
  69 #define MBOX_REG_COUNT 8
  70         __le32 mailbox[MBOX_REG_COUNT];
  71
  72         __le32 flash_address;   /* 0x20 */
  73         __le32 flash_data;
  74         __le32 ctrl_status;
  75
  76         union {
  77                 struct {
  78                         __le32 nvram;
  79                         __le32 reserved1[2]; /* 0x30 */
  80                 } __attribute__ ((packed)) isp4010;
  81                 struct {
  82                         __le32 intr_mask;
  83                         __le32 nvram; /* 0x30 */
  84                         __le32 semaphore;
  85                 } __attribute__ ((packed)) isp4022;
  86         } u1;
  87
  88         __le32 req_q_in;    /* SCSI Request Queue Producer Index */
  89         __le32 rsp_q_out;   /* SCSI Completion Queue Consumer Index */
  90
  91         __le32 reserved2[4];    /* 0x40 */
  92
  93         union {
  94                 struct {
  95                         __le32 ext_hw_conf; /* 0x50 */
  96                         __le32 flow_ctrl;
  97                         __le32 port_ctrl;
  98                         __le32 port_status;
  99
 100                         __le32 reserved3[8]; /* 0x60 */
 101
 102                         __le32 req_q_out; /* 0x80 */
 103
 104                         __le32 reserved4[23]; /* 0x84 */
 105
 106                         __le32 gp_out; /* 0xe0 */
 107                         __le32 gp_in;
 108
 109                         __le32 reserved5[5];
 110
 111                         __le32 port_err_status; /* 0xfc */
 112                 } __attribute__ ((packed)) isp4010;
 113                 struct {
 114                         union {
 115                                 struct port_ctrl_stat_regs p0;
 116                                 struct host_mem_cfg_regs p1;
 117                         };
 118                 } __attribute__ ((packed)) isp4022;
 119         } u2;
 120 };                              /* 256 x100 */
 121
 122
 123 /* Semaphore Defines for 4010 */
 124 #define QL4010_DRVR_SEM_BITS    0x00000030
 125 #define QL4010_GPIO_SEM_BITS    0x000000c0
 126 #define QL4010_SDRAM_SEM_BITS   0x00000300
 127 #define QL4010_PHY_SEM_BITS     0x00000c00
 128 #define QL4010_NVRAM_SEM_BITS   0x00003000
 129 #define QL4010_FLASH_SEM_BITS   0x0000c000
 130
 131 #define QL4010_DRVR_SEM_MASK    0x00300000
 132 #define QL4010_GPIO_SEM_MASK    0x00c00000
 133 #define QL4010_SDRAM_SEM_MASK   0x03000000
 134 #define QL4010_PHY_SEM_MASK     0x0c000000
 135 #define QL4010_NVRAM_SEM_MASK   0x30000000
 136 #define QL4010_FLASH_SEM_MASK   0xc0000000
 137
 138 /* Semaphore Defines for 4022 */
 139 #define QL4022_RESOURCE_MASK_BASE_CODE 0x7
 140 #define QL4022_RESOURCE_BITS_BASE_CODE 0x4
 141
 142
 143 #define QL4022_DRVR_SEM_MASK    (QL4022_RESOURCE_MASK_BASE_CODE << (1+16))
 144 #define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16))
 145 #define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16))
 146 #define QL4022_NVRAM_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (10+16))
 147 #define QL4022_FLASH_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (13+16))
 148
 149
 150
 151 /* Page # defines for 4022 */
 152 #define PORT_CTRL_STAT_PAGE                     0       /* 4022 */
 153 #define HOST_MEM_CFG_PAGE                       1       /* 4022 */
 154 #define LOCAL_RAM_CFG_PAGE                      2       /* 4022 */
 155 #define PROT_STAT_PAGE                          3       /* 4022 */
 156
 157 /* Register Mask - sets corresponding mask bits in the upper word */
 158 static inline uint32_t set_rmask(uint32_t val)
 159 {
 160         return (val & 0xffff) | (val << 16);
 161 }
 162
 163
 164 static inline uint32_t clr_rmask(uint32_t val)
 165 {
 166         return 0 | (val << 16);
 167 }
 168
 169 /*  ctrl_status definitions */
 170 #define CSR_SCSI_PAGE_SELECT                    0x00000003
 171 #define CSR_SCSI_INTR_ENABLE                    0x00000004      /* 4010 */
 172 #define CSR_SCSI_RESET_INTR                     0x00000008
 173 #define CSR_SCSI_COMPLETION_INTR                0x00000010
 174 #define CSR_SCSI_PROCESSOR_INTR                 0x00000020
 175 #define CSR_INTR_RISC                           0x00000040
 176 #define CSR_BOOT_ENABLE                         0x00000080
 177 #define CSR_NET_PAGE_SELECT                     0x00000300      /* 4010 */
 178 #define CSR_FUNC_NUM                            0x00000700      /* 4022 */
 179 #define CSR_NET_RESET_INTR                      0x00000800      /* 4010 */
 180 #define CSR_FORCE_SOFT_RESET                    0x00002000      /* 4022 */
 181 #define CSR_FATAL_ERROR                         0x00004000
 182 #define CSR_SOFT_RESET                          0x00008000
 183 #define ISP_CONTROL_FN_MASK                     CSR_FUNC_NUM
 184 #define ISP_CONTROL_FN0_SCSI                    0x0500
 185 #define ISP_CONTROL_FN1_SCSI                    0x0700
 186
 187 #define INTR_PENDING                            (CSR_SCSI_COMPLETION_INTR |\
 188                                                  CSR_SCSI_PROCESSOR_INTR |\
 189                                                  CSR_SCSI_RESET_INTR)
 190
 191 /* ISP InterruptMask definitions */
 192 #define IMR_SCSI_INTR_ENABLE                    0x00000004      /* 4022 */
 193
 194 /* ISP 4022 nvram definitions */
 195 #define NVR_WRITE_ENABLE                        0x00000010      /* 4022 */
 196
 197 /*  ISP port_status definitions */
 198
 199 /*  ISP Semaphore definitions */
 200
 201 /*  ISP General Purpose Output definitions */
 202 #define GPOR_TOPCAT_RESET                       0x00000004
 203
 204 /*  shadow registers (DMA'd from HA to system memory.  read only) */
 205 struct shadow_regs {
 206         /* SCSI Request Queue Consumer Index */
 207         __le32 req_q_out;       /*  0 x0   R */
 208
 209         /* SCSI Completion Queue Producer Index */
 210         __le32 rsp_q_in;        /*  4 x4   R */
 211 };                /*  8 x8 */
 212
 213
 214 /*  External hardware configuration register */
 215 union external_hw_config_reg {
 216         struct {
 217                 /* FIXME: Do we even need this?  All values are
 218                  * referred to by 16 bit quantities.  Platform and
 219                  * endianess issues. */
 220                 __le32 bReserved0:1;
 221                 __le32 bSDRAMProtectionMethod:2;
 222                 __le32 bSDRAMBanks:1;
 223                 __le32 bSDRAMChipWidth:1;
 224                 __le32 bSDRAMChipSize:2;
 225                 __le32 bParityDisable:1;
 226                 __le32 bExternalMemoryType:1;
 227                 __le32 bFlashBIOSWriteEnable:1;
 228                 __le32 bFlashUpperBankSelect:1;
 229                 __le32 bWriteBurst:2;
 230                 __le32 bReserved1:3;
 231                 __le32 bMask:16;
 232         };
 233         uint32_t Asuint32_t;
 234 };
 235
 236 /* 82XX Support  start */
 237 /* 82xx Default FLT Addresses */
 238 #define FA_FLASH_LAYOUT_ADDR_82         0xFC400
 239 #define FA_FLASH_DESCR_ADDR_82          0xFC000
 240 #define FA_BOOT_LOAD_ADDR_82            0x04000
 241 #define FA_BOOT_CODE_ADDR_82            0x20000
 242 #define FA_RISC_CODE_ADDR_82            0x40000
 243 #define FA_GOLD_RISC_CODE_ADDR_82       0x80000
 244
 245 /* Flash Description Table */
 246 struct qla_fdt_layout {
 247         uint8_t sig[4];
 248         uint16_t version;
 249         uint16_t len;
 250         uint16_t checksum;
 251         uint8_t unused1[2];
 252         uint8_t model[16];
 253         uint16_t man_id;
 254         uint16_t id;
 255         uint8_t flags;
 256         uint8_t erase_cmd;
 257         uint8_t alt_erase_cmd;
 258         uint8_t wrt_enable_cmd;
 259         uint8_t wrt_enable_bits;
 260         uint8_t wrt_sts_reg_cmd;
 261         uint8_t unprotect_sec_cmd;
 262         uint8_t read_man_id_cmd;
 263         uint32_t block_size;
 264         uint32_t alt_block_size;
 265         uint32_t flash_size;
 266         uint32_t wrt_enable_data;
 267         uint8_t read_id_addr_len;
 268         uint8_t wrt_disable_bits;
 269         uint8_t read_dev_id_len;
 270         uint8_t chip_erase_cmd;
 271         uint16_t read_timeout;
 272         uint8_t protect_sec_cmd;
 273         uint8_t unused2[65];
 274 };
 275
 276 /* Flash Layout Table */
 277
 278 struct qla_flt_location {
 279         uint8_t sig[4];
 280         uint16_t start_lo;
 281         uint16_t start_hi;
 282         uint8_t version;
 283         uint8_t unused[5];
 284         uint16_t checksum;
 285 };
 286
 287 struct qla_flt_header {
 288         uint16_t version;
 289         uint16_t length;
 290         uint16_t checksum;
 291         uint16_t unused;
 292 };
 293
 294 /* 82xx FLT Regions */
 295 #define FLT_REG_FDT             0x1a
 296 #define FLT_REG_FLT             0x1c
 297 #define FLT_REG_BOOTLOAD_82     0x72
 298 #define FLT_REG_FW_82           0x74
 299 #define FLT_REG_GOLD_FW_82      0x75
 300 #define FLT_REG_BOOT_CODE_82    0x78
 301
 302 struct qla_flt_region {
 303         uint32_t code;
 304         uint32_t size;
 305         uint32_t start;
 306         uint32_t end;
 307 };
 308
 309 /*************************************************************************
 310  *
 311  *              Mailbox Commands Structures and Definitions
 312  *
 313  *************************************************************************/
 314
 315 /*  Mailbox command definitions */
 316 #define MBOX_CMD_ABOUT_FW                       0x0009
 317 #define MBOX_CMD_PING                           0x000B
 318 #define MBOX_CMD_ENABLE_INTRS                   0x0010
 319 #define INTR_DISABLE                            0
 320 #define INTR_ENABLE                             1
 321 #define MBOX_CMD_STOP_FW                        0x0014
 322 #define MBOX_CMD_ABORT_TASK                     0x0015
 323 #define MBOX_CMD_LUN_RESET                      0x0016
 324 #define MBOX_CMD_TARGET_WARM_RESET              0x0017
 325 #define MBOX_CMD_GET_MANAGEMENT_DATA            0x001E
 326 #define MBOX_CMD_GET_FW_STATUS                  0x001F
 327 #define MBOX_CMD_SET_ISNS_SERVICE               0x0021
 328 #define ISNS_DISABLE                            0
 329 #define ISNS_ENABLE                             1
 330 #define MBOX_CMD_COPY_FLASH                     0x0024
 331 #define MBOX_CMD_WRITE_FLASH                    0x0025
 332 #define MBOX_CMD_READ_FLASH                     0x0026
 333 #define MBOX_CMD_CLEAR_DATABASE_ENTRY           0x0031
 334 #define MBOX_CMD_CONN_OPEN                      0x0074
 335 #define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT         0x0056
 336 #define LOGOUT_OPTION_CLOSE_SESSION             0x0002
 337 #define LOGOUT_OPTION_RELOGIN                   0x0004
 338 #define LOGOUT_OPTION_FREE_DDB                  0x0008
 339 #define MBOX_CMD_EXECUTE_IOCB_A64               0x005A
 340 #define MBOX_CMD_INITIALIZE_FIRMWARE            0x0060
 341 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK         0x0061
 342 #define MBOX_CMD_REQUEST_DATABASE_ENTRY         0x0062
 343 #define MBOX_CMD_SET_DATABASE_ENTRY             0x0063
 344 #define MBOX_CMD_GET_DATABASE_ENTRY             0x0064
 345 #define DDB_DS_UNASSIGNED                       0x00
 346 #define DDB_DS_NO_CONNECTION_ACTIVE             0x01
 347 #define DDB_DS_DISCOVERY                        0x02
 348 #define DDB_DS_SESSION_ACTIVE                   0x04
 349 #define DDB_DS_SESSION_FAILED                   0x06
 350 #define DDB_DS_LOGIN_IN_PROCESS                 0x07
 351 #define MBOX_CMD_GET_FW_STATE                   0x0069
 352 #define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS 0x006A
 353 #define MBOX_CMD_GET_SYS_INFO                   0x0078
 354 #define MBOX_CMD_RESTORE_FACTORY_DEFAULTS       0x0087
 355 #define MBOX_CMD_SET_ACB                        0x0088
 356 #define MBOX_CMD_GET_ACB                        0x0089
 357 #define MBOX_CMD_DISABLE_ACB                    0x008A
 358 #define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE        0x008B
 359 #define MBOX_CMD_GET_IPV6_DEST_CACHE            0x008C
 360 #define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST       0x008D
 361 #define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST       0x008E
 362 #define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE        0x0090
 363 #define MBOX_CMD_GET_IP_ADDR_STATE              0x0091
 364 #define MBOX_CMD_SEND_IPV6_ROUTER_SOL           0x0092
 365 #define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR   0x0093
 366
 367 /* Mailbox 1 */
 368 #define FW_STATE_READY                          0x0000
 369 #define FW_STATE_CONFIG_WAIT                    0x0001
 370 #define FW_STATE_WAIT_AUTOCONNECT               0x0002
 371 #define FW_STATE_ERROR                          0x0004
 372 #define FW_STATE_CONFIGURING_IP                 0x0008
 373
 374 /* Mailbox 3 */
 375 #define FW_ADDSTATE_OPTICAL_MEDIA               0x0001
 376 #define FW_ADDSTATE_DHCPv4_ENABLED              0x0002
 377 #define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED       0x0004
 378 #define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED        0x0008
 379 #define FW_ADDSTATE_LINK_UP                     0x0010
 380 #define FW_ADDSTATE_ISNS_SVC_ENABLED            0x0020
 381
 382 #define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS    0x006B
 383 #define IPV6_DEFAULT_DDB_ENTRY                  0x0001
 384
 385 #define MBOX_CMD_CONN_OPEN_SESS_LOGIN           0x0074
 386 #define MBOX_CMD_GET_CRASH_RECORD               0x0076  /* 4010 only */
 387 #define MBOX_CMD_GET_CONN_EVENT_LOG             0x0077
 388
 389 /*  Mailbox status definitions */
 390 #define MBOX_COMPLETION_STATUS                  4
 391 #define MBOX_STS_BUSY                           0x0007
 392 #define MBOX_STS_INTERMEDIATE_COMPLETION        0x1000
 393 #define MBOX_STS_COMMAND_COMPLETE               0x4000
 394 #define MBOX_STS_COMMAND_ERROR                  0x4005
 395
 396 #define MBOX_ASYNC_EVENT_STATUS                 8
 397 #define MBOX_ASTS_SYSTEM_ERROR                  0x8002
 398 #define MBOX_ASTS_REQUEST_TRANSFER_ERROR        0x8003
 399 #define MBOX_ASTS_RESPONSE_TRANSFER_ERROR       0x8004
 400 #define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM      0x8005
 401 #define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED     0x8006
 402 #define MBOX_ASTS_LINK_UP                       0x8010
 403 #define MBOX_ASTS_LINK_DOWN                     0x8011
 404 #define MBOX_ASTS_DATABASE_CHANGED              0x8014
 405 #define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED      0x8015
 406 #define MBOX_ASTS_SELF_TEST_FAILED              0x8016
 407 #define MBOX_ASTS_LOGIN_FAILED                  0x8017
 408 #define MBOX_ASTS_DNS                           0x8018
 409 #define MBOX_ASTS_HEARTBEAT                     0x8019
 410 #define MBOX_ASTS_NVRAM_INVALID                 0x801A
 411 #define MBOX_ASTS_MAC_ADDRESS_CHANGED           0x801B
 412 #define MBOX_ASTS_IP_ADDRESS_CHANGED            0x801C
 413 #define MBOX_ASTS_DHCP_LEASE_EXPIRED            0x801D
 414 #define MBOX_ASTS_DHCP_LEASE_ACQUIRED           0x801F
 415 #define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED 0x8021
 416 #define MBOX_ASTS_DUPLICATE_IP                  0x8025
 417 #define MBOX_ASTS_ARP_COMPLETE                  0x8026
 418 #define MBOX_ASTS_SUBNET_STATE_CHANGE           0x8027
 419 #define MBOX_ASTS_RESPONSE_QUEUE_FULL           0x8028
 420 #define MBOX_ASTS_IP_ADDR_STATE_CHANGED         0x8029
 421 #define MBOX_ASTS_IPV6_PREFIX_EXPIRED           0x802B
 422 #define MBOX_ASTS_IPV6_ND_PREFIX_IGNORED        0x802C
 423 #define MBOX_ASTS_IPV6_LCL_PREFIX_IGNORED       0x802D
 424 #define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD         0x802E
 425 #define MBOX_ASTS_TXSCVR_INSERTED               0x8130
 426 #define MBOX_ASTS_TXSCVR_REMOVED                0x8131
 427
 428 #define ISNS_EVENT_DATA_RECEIVED                0x0000
 429 #define ISNS_EVENT_CONNECTION_OPENED            0x0001
 430 #define ISNS_EVENT_CONNECTION_FAILED            0x0002
 431 #define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR      0x8022
 432 #define MBOX_ASTS_SUBNET_STATE_CHANGE           0x8027
 433
 434 /* ACB State Defines */
 435 #define ACB_STATE_UNCONFIGURED  0x00
 436 #define ACB_STATE_INVALID       0x01
 437 #define ACB_STATE_ACQUIRING     0x02
 438 #define ACB_STATE_TENTATIVE     0x03
 439 #define ACB_STATE_DEPRICATED    0x04
 440 #define ACB_STATE_VALID         0x05
 441 #define ACB_STATE_DISABLING     0x06
 442
 443 /* FLASH offsets */
 444 #define FLASH_SEGMENT_IFCB      0x04000000
 445
 446 #define FLASH_OPT_RMW_HOLD      0
 447 #define FLASH_OPT_RMW_INIT      1
 448 #define FLASH_OPT_COMMIT        2
 449 #define FLASH_OPT_RMW_COMMIT    3
 450
 451 /*************************************************************************/
 452
 453 /* Host Adapter Initialization Control Block (from host) */
 454 struct addr_ctrl_blk {
 455         uint8_t version;        /* 00 */
 456 #define  IFCB_VER_MIN                   0x01
 457 #define  IFCB_VER_MAX                   0x02
 458         uint8_t control;        /* 01 */
 459
 460         uint16_t fw_options;    /* 02-03 */
 461 #define  FWOPT_HEARTBEAT_ENABLE           0x1000
 462 #define  FWOPT_SESSION_MODE               0x0040
 463 #define  FWOPT_INITIATOR_MODE             0x0020
 464 #define  FWOPT_TARGET_MODE                0x0010
 465 #define  FWOPT_ENABLE_CRBDB               0x8000
 466
 467         uint16_t exec_throttle; /* 04-05 */
 468         uint8_t zio_count;      /* 06 */
 469         uint8_t res0;   /* 07 */
 470         uint16_t eth_mtu_size;  /* 08-09 */
 471         uint16_t add_fw_options;        /* 0A-0B */
 472 #define ADFWOPT_SERIALIZE_TASK_MGMT     0x0400
 473 #define ADFWOPT_AUTOCONN_DISABLE        0x0002
 474
 475         uint8_t hb_interval;    /* 0C */
 476         uint8_t inst_num; /* 0D */
 477         uint16_t res1;          /* 0E-0F */
 478         uint16_t rqq_consumer_idx;      /* 10-11 */
 479         uint16_t compq_producer_idx;    /* 12-13 */
 480         uint16_t rqq_len;       /* 14-15 */
 481         uint16_t compq_len;     /* 16-17 */
 482         uint32_t rqq_addr_lo;   /* 18-1B */
 483         uint32_t rqq_addr_hi;   /* 1C-1F */
 484         uint32_t compq_addr_lo; /* 20-23 */
 485         uint32_t compq_addr_hi; /* 24-27 */
 486         uint32_t shdwreg_addr_lo;       /* 28-2B */
 487         uint32_t shdwreg_addr_hi;       /* 2C-2F */
 488
 489         uint16_t iscsi_opts;    /* 30-31 */
 490         uint16_t ipv4_tcp_opts; /* 32-33 */
 491 #define TCPOPT_DHCP_ENABLE              0x0200
 492         uint16_t ipv4_ip_opts;  /* 34-35 */
 493 #define IPOPT_IPV4_PROTOCOL_ENABLE      0x8000
 494 #define IPOPT_VLAN_TAGGING_ENABLE       0x2000
 495
 496         uint16_t iscsi_max_pdu_size;    /* 36-37 */
 497         uint8_t ipv4_tos;       /* 38 */
 498         uint8_t ipv4_ttl;       /* 39 */
 499         uint8_t acb_version;    /* 3A */
 500 #define ACB_NOT_SUPPORTED               0x00
 501 #define ACB_SUPPORTED                   0x02 /* Capable of ACB Version 2
 502                                                 Features */
 503
 504         uint8_t res2;   /* 3B */
 505         uint16_t def_timeout;   /* 3C-3D */
 506         uint16_t iscsi_fburst_len;      /* 3E-3F */
 507         uint16_t iscsi_def_time2wait;   /* 40-41 */
 508         uint16_t iscsi_def_time2retain; /* 42-43 */
 509         uint16_t iscsi_max_outstnd_r2t; /* 44-45 */
 510         uint16_t conn_ka_timeout;       /* 46-47 */
 511         uint16_t ipv4_port;     /* 48-49 */
 512         uint16_t iscsi_max_burst_len;   /* 4A-4B */
 513         uint32_t res5;          /* 4C-4F */
 514         uint8_t ipv4_addr[4];   /* 50-53 */
 515         uint16_t ipv4_vlan_tag; /* 54-55 */
 516         uint8_t ipv4_addr_state;        /* 56 */
 517         uint8_t ipv4_cacheid;   /* 57 */
 518         uint8_t res6[8];        /* 58-5F */
 519         uint8_t ipv4_subnet[4]; /* 60-63 */
 520         uint8_t res7[12];       /* 64-6F */
 521         uint8_t ipv4_gw_addr[4];        /* 70-73 */
 522         uint8_t res8[0xc];      /* 74-7F */
 523         uint8_t pri_dns_srvr_ip[4];/* 80-83 */
 524         uint8_t sec_dns_srvr_ip[4];/* 84-87 */
 525         uint16_t min_eph_port;  /* 88-89 */
 526         uint16_t max_eph_port;  /* 8A-8B */
 527         uint8_t res9[4];        /* 8C-8F */
 528         uint8_t iscsi_alias[32];/* 90-AF */
 529         uint8_t res9_1[0x16];   /* B0-C5 */
 530         uint16_t tgt_portal_grp;/* C6-C7 */
 531         uint8_t abort_timer;    /* C8    */
 532         uint8_t ipv4_tcp_wsf;   /* C9    */
 533         uint8_t res10[6];       /* CA-CF */
 534         uint8_t ipv4_sec_ip_addr[4];    /* D0-D3 */
 535         uint8_t ipv4_dhcp_vid_len;      /* D4 */
 536         uint8_t ipv4_dhcp_vid[11];      /* D5-DF */
 537         uint8_t res11[20];      /* E0-F3 */
 538         uint8_t ipv4_dhcp_alt_cid_len;  /* F4 */
 539         uint8_t ipv4_dhcp_alt_cid[11];  /* F5-FF */
 540         uint8_t iscsi_name[224];        /* 100-1DF */
 541         uint8_t res12[32];      /* 1E0-1FF */
 542         uint32_t cookie;        /* 200-203 */
 543         uint16_t ipv6_port;     /* 204-205 */
 544         uint16_t ipv6_opts;     /* 206-207 */
 545 #define IPV6_OPT_IPV6_PROTOCOL_ENABLE   0x8000
 546 #define IPV6_OPT_VLAN_TAGGING_ENABLE    0x2000
 547
 548         uint16_t ipv6_addtl_opts;       /* 208-209 */
 549 #define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE      0x0002 /* Pri ACB
 550                                                                   Only */
 551 #define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR          0x0001
 552
 553         uint16_t ipv6_tcp_opts; /* 20A-20B */
 554         uint8_t ipv6_tcp_wsf;   /* 20C */
 555         uint16_t ipv6_flow_lbl; /* 20D-20F */
 556         uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */
 557         uint16_t ipv6_vlan_tag; /* 220-221 */
 558         uint8_t ipv6_lnk_lcl_addr_state;/* 222 */
 559         uint8_t ipv6_addr0_state;       /* 223 */
 560         uint8_t ipv6_addr1_state;       /* 224 */
 561 #define IP_ADDRSTATE_UNCONFIGURED       0
 562 #define IP_ADDRSTATE_INVALID            1
 563 #define IP_ADDRSTATE_ACQUIRING          2
 564 #define IP_ADDRSTATE_TENTATIVE          3
 565 #define IP_ADDRSTATE_DEPRICATED         4
 566 #define IP_ADDRSTATE_PREFERRED          5
 567 #define IP_ADDRSTATE_DISABLING          6
 568
 569         uint8_t ipv6_dflt_rtr_state;    /* 225 */
 570 #define IPV6_RTRSTATE_UNKNOWN                   0
 571 #define IPV6_RTRSTATE_MANUAL                    1
 572 #define IPV6_RTRSTATE_ADVERTISED                3
 573 #define IPV6_RTRSTATE_STALE                     4
 574
 575         uint8_t ipv6_traffic_class;     /* 226 */
 576         uint8_t ipv6_hop_limit; /* 227 */
 577         uint8_t ipv6_if_id[8];  /* 228-22F */
 578         uint8_t ipv6_addr0[16]; /* 230-23F */
 579         uint8_t ipv6_addr1[16]; /* 240-24F */
 580         uint32_t ipv6_nd_reach_time;    /* 250-253 */
 581         uint32_t ipv6_nd_rexmit_timer;  /* 254-257 */
 582         uint32_t ipv6_nd_stale_timeout; /* 258-25B */
 583         uint8_t ipv6_dup_addr_detect_count;     /* 25C */
 584         uint8_t ipv6_cache_id;  /* 25D */
 585         uint8_t res13[18];      /* 25E-26F */
 586         uint32_t ipv6_gw_advrt_mtu;     /* 270-273 */
 587         uint8_t res14[140];     /* 274-2FF */
 588 };
 589
 590 struct init_fw_ctrl_blk {
 591         struct addr_ctrl_blk pri;
 592 /*      struct addr_ctrl_blk sec;*/
 593 };
 594
 595 struct addr_ctrl_blk_def {
 596         uint8_t reserved1[1];   /* 00 */
 597         uint8_t control;        /* 01 */
 598         uint8_t reserved2[11];  /* 02-0C */
 599         uint8_t inst_num;       /* 0D */
 600         uint8_t reserved3[34];  /* 0E-2F */
 601         uint16_t iscsi_opts;    /* 30-31 */
 602         uint16_t ipv4_tcp_opts; /* 32-33 */
 603         uint16_t ipv4_ip_opts;  /* 34-35 */
 604         uint16_t iscsi_max_pdu_size;    /* 36-37 */
 605         uint8_t ipv4_tos;       /* 38 */
 606         uint8_t ipv4_ttl;       /* 39 */
 607         uint8_t reserved4[2];   /* 3A-3B */
 608         uint16_t def_timeout;   /* 3C-3D */
 609         uint16_t iscsi_fburst_len;      /* 3E-3F */
 610         uint8_t reserved5[4];   /* 40-43 */
 611         uint16_t iscsi_max_outstnd_r2t; /* 44-45 */
 612         uint8_t reserved6[2];   /* 46-47 */
 613         uint16_t ipv4_port;     /* 48-49 */
 614         uint16_t iscsi_max_burst_len;   /* 4A-4B */
 615         uint8_t reserved7[4];   /* 4C-4F */
 616         uint8_t ipv4_addr[4];   /* 50-53 */
 617         uint16_t ipv4_vlan_tag; /* 54-55 */
 618         uint8_t ipv4_addr_state;        /* 56 */
 619         uint8_t ipv4_cacheid;   /* 57 */
 620         uint8_t reserved8[8];   /* 58-5F */
 621         uint8_t ipv4_subnet[4]; /* 60-63 */
 622         uint8_t reserved9[12];  /* 64-6F */
 623         uint8_t ipv4_gw_addr[4];        /* 70-73 */
 624         uint8_t reserved10[84]; /* 74-C7 */
 625         uint8_t abort_timer;    /* C8    */
 626         uint8_t ipv4_tcp_wsf;   /* C9    */
 627         uint8_t reserved11[10]; /* CA-D3 */
 628         uint8_t ipv4_dhcp_vid_len;      /* D4 */
 629         uint8_t ipv4_dhcp_vid[11];      /* D5-DF */
 630         uint8_t reserved12[20]; /* E0-F3 */
 631         uint8_t ipv4_dhcp_alt_cid_len;  /* F4 */
 632         uint8_t ipv4_dhcp_alt_cid[11];  /* F5-FF */
 633         uint8_t iscsi_name[224];        /* 100-1DF */
 634         uint8_t reserved13[32]; /* 1E0-1FF */
 635         uint32_t cookie;        /* 200-203 */
 636         uint16_t ipv6_port;     /* 204-205 */
 637         uint16_t ipv6_opts;     /* 206-207 */
 638         uint16_t ipv6_addtl_opts;       /* 208-209 */
 639         uint16_t ipv6_tcp_opts;         /* 20A-20B */
 640         uint8_t ipv6_tcp_wsf;           /* 20C */
 641         uint16_t ipv6_flow_lbl;         /* 20D-20F */
 642         uint8_t ipv6_dflt_rtr_addr[16]; /* 210-21F */
 643         uint16_t ipv6_vlan_tag;         /* 220-221 */
 644         uint8_t ipv6_lnk_lcl_addr_state;        /* 222 */
 645         uint8_t ipv6_addr0_state;       /* 223 */
 646         uint8_t ipv6_addr1_state;       /* 224 */
 647         uint8_t ipv6_dflt_rtr_state;    /* 225 */
 648         uint8_t ipv6_traffic_class;     /* 226 */
 649         uint8_t ipv6_hop_limit;         /* 227 */
 650         uint8_t ipv6_if_id[8];          /* 228-22F */
 651         uint8_t ipv6_addr0[16];         /* 230-23F */
 652         uint8_t ipv6_addr1[16];         /* 240-24F */
 653         uint32_t ipv6_nd_reach_time;    /* 250-253 */
 654         uint32_t ipv6_nd_rexmit_timer;  /* 254-257 */
 655         uint32_t ipv6_nd_stale_timeout; /* 258-25B */
 656         uint8_t ipv6_dup_addr_detect_count;     /* 25C */
 657         uint8_t ipv6_cache_id;          /* 25D */
 658         uint8_t reserved14[18];         /* 25E-26F */
 659         uint32_t ipv6_gw_advrt_mtu;     /* 270-273 */
 660         uint8_t reserved15[140];        /* 274-2FF */
 661 };
 662
 663 /*************************************************************************/
 664
 665 #define MAX_CHAP_ENTRIES_40XX   128
 666 #define MAX_CHAP_ENTRIES_82XX   1024
 667
 668 struct ql4_chap_table {
 669         uint16_t link;
 670         uint8_t flags;
 671         uint8_t secret_len;
 672 #define MIN_CHAP_SECRET_LEN     12
 673 #define MAX_CHAP_SECRET_LEN     100
 674         uint8_t secret[MAX_CHAP_SECRET_LEN];
 675 #define MAX_CHAP_NAME_LEN       256
 676         uint8_t name[MAX_CHAP_NAME_LEN];
 677         uint16_t reserved;
 678 #define CHAP_VALID_COOKIE       0x4092
 679 #define CHAP_INVALID_COOKIE     0xFFEE
 680         uint16_t cookie;
 681 };
 682
 683 struct dev_db_entry {
 684         uint16_t options;       /* 00-01 */
 685 #define DDB_OPT_DISC_SESSION  0x10
 686 #define DDB_OPT_TARGET        0x02 /* device is a target */
 687 #define DDB_OPT_IPV6_DEVICE     0x100
 688 #define DDB_OPT_AUTO_SENDTGTS_DISABLE           0x40
 689 #define DDB_OPT_IPV6_NULL_LINK_LOCAL            0x800 /* post connection */
 690 #define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL      0x800 /* pre connection */
 691
 692         uint16_t exec_throttle; /* 02-03 */
 693         uint16_t exec_count;    /* 04-05 */
 694         uint16_t res0;  /* 06-07 */
 695         uint16_t iscsi_options; /* 08-09 */
 696         uint16_t tcp_options;   /* 0A-0B */
 697         uint16_t ip_options;    /* 0C-0D */
 698         uint16_t iscsi_max_rcv_data_seg_len;    /* 0E-0F */
 699 #define BYTE_UNITS      512
 700         uint32_t res1;  /* 10-13 */
 701         uint16_t iscsi_max_snd_data_seg_len;    /* 14-15 */
 702         uint16_t iscsi_first_burst_len; /* 16-17 */
 703         uint16_t iscsi_def_time2wait;   /* 18-19 */
 704         uint16_t iscsi_def_time2retain; /* 1A-1B */
 705         uint16_t iscsi_max_outsnd_r2t;  /* 1C-1D */
 706         uint16_t ka_timeout;    /* 1E-1F */
 707         uint8_t isid[6];        /* 20-25 big-endian, must be converted
 708                                  * to little-endian */
 709         uint16_t tsid;          /* 26-27 */
 710         uint16_t port;  /* 28-29 */
 711         uint16_t iscsi_max_burst_len;   /* 2A-2B */
 712         uint16_t def_timeout;   /* 2C-2D */
 713         uint16_t res2;  /* 2E-2F */
 714         uint8_t ip_addr[0x10];  /* 30-3F */
 715         uint8_t iscsi_alias[0x20];      /* 40-5F */
 716         uint8_t tgt_addr[0x20]; /* 60-7F */
 717         uint16_t mss;   /* 80-81 */
 718         uint16_t res3;  /* 82-83 */
 719         uint16_t lcl_port;      /* 84-85 */
 720         uint8_t ipv4_tos;       /* 86 */
 721         uint16_t ipv6_flow_lbl; /* 87-89 */
 722         uint8_t res4[0x36];     /* 8A-BF */
 723         uint8_t iscsi_name[0xE0];       /* C0-19F : xxzzy Make this a
 724                                          * pointer to a string so we
 725                                          * don't have to reserve soooo
 726                                          * much RAM */
 727         uint8_t link_local_ipv6_addr[0x10]; /* 1A0-1AF */
 728         uint8_t res5[0x10];     /* 1B0-1BF */
 729         uint16_t ddb_link;      /* 1C0-1C1 */
 730         uint16_t chap_tbl_idx;  /* 1C2-1C3 */
 731         uint16_t tgt_portal_grp; /* 1C4-1C5 */
 732         uint8_t tcp_xmt_wsf;    /* 1C6 */
 733         uint8_t tcp_rcv_wsf;    /* 1C7 */
 734         uint32_t stat_sn;       /* 1C8-1CB */
 735         uint32_t exp_stat_sn;   /* 1CC-1CF */
 736         uint8_t res6[0x30];     /* 1D0-1FF */
 737 };
 738
 739 /*************************************************************************/
 740
 741 /* Flash definitions */
 742
 743 #define FLASH_OFFSET_SYS_INFO   0x02000000
 744 #define FLASH_DEFAULTBLOCKSIZE  0x20000
 745 #define FLASH_EOF_OFFSET        (FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes
 746                                                             * for EOF
 747                                                             * signature */
 748
 749 struct sys_info_phys_addr {
 750         uint8_t address[6];     /* 00-05 */
 751         uint8_t filler[2];      /* 06-07 */
 752 };
 753
 754 struct flash_sys_info {
 755         uint32_t cookie;        /* 00-03 */
 756         uint32_t physAddrCount; /* 04-07 */
 757         struct sys_info_phys_addr physAddr[4]; /* 08-27 */
 758         uint8_t vendorId[128];  /* 28-A7 */
 759         uint8_t productId[128]; /* A8-127 */
 760         uint32_t serialNumber;  /* 128-12B */
 761
 762         /*  PCI Configuration values */
 763         uint32_t pciDeviceVendor;       /* 12C-12F */
 764         uint32_t pciDeviceId;   /* 130-133 */
 765         uint32_t pciSubsysVendor;       /* 134-137 */
 766         uint32_t pciSubsysId;   /* 138-13B */
 767
 768         /*  This validates version 1. */
 769         uint32_t crumbs;        /* 13C-13F */
 770
 771         uint32_t enterpriseNumber;      /* 140-143 */
 772
 773         uint32_t mtu;           /* 144-147 */
 774         uint32_t reserved0;     /* 148-14b */
 775         uint32_t crumbs2;       /* 14c-14f */
 776         uint8_t acSerialNumber[16];     /* 150-15f */
 777         uint32_t crumbs3;       /* 160-16f */
 778
 779         /* Leave this last in the struct so it is declared invalid if
 780          * any new items are added.
 781          */
 782         uint32_t reserved1[39]; /* 170-1ff */
 783 };      /* 200 */
 784
 785 struct mbx_sys_info {
 786         uint8_t board_id_str[16];   /*  0-f  Keep board ID string first */
 787                                 /* in this structure for GUI. */
 788         uint16_t board_id;      /* 10-11 board ID code */
 789         uint16_t phys_port_cnt; /* 12-13 number of physical network ports */
 790         uint16_t port_num;      /* 14-15 network port for this PCI function */
 791                                 /* (port 0 is first port) */
 792         uint8_t mac_addr[6];    /* 16-1b MAC address for this PCI function */
 793         uint32_t iscsi_pci_func_cnt;  /* 1c-1f number of iSCSI PCI functions */
 794         uint32_t pci_func;            /* 20-23 this PCI function */
 795         unsigned char serial_number[16];  /* 24-33 serial number string */
 796         uint8_t reserved[12];             /* 34-3f */
 797 };
 798
 799 struct about_fw_info {
 800         uint16_t fw_major;              /* 00 - 01 */
 801         uint16_t fw_minor;              /* 02 - 03 */
 802         uint16_t fw_patch;              /* 04 - 05 */
 803         uint16_t fw_build;              /* 06 - 07 */
 804         uint8_t fw_build_date[16];      /* 08 - 17 ASCII String */
 805         uint8_t fw_build_time[16];      /* 18 - 27 ASCII String */
 806         uint8_t fw_build_user[16];      /* 28 - 37 ASCII String */
 807         uint16_t fw_load_source;        /* 38 - 39 */
 808                                         /* 1 = Flash Primary,
 809                                            2 = Flash Secondary,
 810                                            3 = Host Download
 811                                         */
 812         uint8_t reserved1[6];           /* 3A - 3F */
 813         uint16_t iscsi_major;           /* 40 - 41 */
 814         uint16_t iscsi_minor;           /* 42 - 43 */
 815         uint16_t bootload_major;        /* 44 - 45 */
 816         uint16_t bootload_minor;        /* 46 - 47 */
 817         uint16_t bootload_patch;        /* 48 - 49 */
 818         uint16_t bootload_build;        /* 4A - 4B */
 819         uint8_t reserved2[180];         /* 4C - FF */
 820 };
 821
 822 struct crash_record {
 823         uint16_t fw_major_version;      /* 00 - 01 */
 824         uint16_t fw_minor_version;      /* 02 - 03 */
 825         uint16_t fw_patch_version;      /* 04 - 05 */
 826         uint16_t fw_build_version;      /* 06 - 07 */
 827
 828         uint8_t build_date[16]; /* 08 - 17 */
 829         uint8_t build_time[16]; /* 18 - 27 */
 830         uint8_t build_user[16]; /* 28 - 37 */
 831         uint8_t card_serial_num[16];    /* 38 - 47 */
 832
 833         uint32_t time_of_crash_in_secs; /* 48 - 4B */
 834         uint32_t time_of_crash_in_ms;   /* 4C - 4F */
 835
 836         uint16_t out_RISC_sd_num_frames;        /* 50 - 51 */
 837         uint16_t OAP_sd_num_words;      /* 52 - 53 */
 838         uint16_t IAP_sd_num_frames;     /* 54 - 55 */
 839         uint16_t in_RISC_sd_num_words;  /* 56 - 57 */
 840
 841         uint8_t reserved1[28];  /* 58 - 7F */
 842
 843         uint8_t out_RISC_reg_dump[256]; /* 80 -17F */
 844         uint8_t in_RISC_reg_dump[256];  /*180 -27F */
 845         uint8_t in_out_RISC_stack_dump[0];      /*280 - ??? */
 846 };
 847
 848 struct conn_event_log_entry {
 849 #define MAX_CONN_EVENT_LOG_ENTRIES      100
 850         uint32_t timestamp_sec; /* 00 - 03 seconds since boot */
 851         uint32_t timestamp_ms;  /* 04 - 07 milliseconds since boot */
 852         uint16_t device_index;  /* 08 - 09  */
 853         uint16_t fw_conn_state; /* 0A - 0B  */
 854         uint8_t event_type;     /* 0C - 0C  */
 855         uint8_t error_code;     /* 0D - 0D  */
 856         uint16_t error_code_detail;     /* 0E - 0F  */
 857         uint8_t num_consecutive_events; /* 10 - 10  */
 858         uint8_t rsvd[3];        /* 11 - 13  */
 859 };
 860
 861 /*************************************************************************
 862  *
 863  *                              IOCB Commands Structures and Definitions
 864  *
 865  *************************************************************************/
 866 #define IOCB_MAX_CDB_LEN            16  /* Bytes in a CBD */
 867 #define IOCB_MAX_SENSEDATA_LEN      32  /* Bytes of sense data */
 868 #define IOCB_MAX_EXT_SENSEDATA_LEN  60  /* Bytes of extended sense data */
 869
 870 /* IOCB header structure */
 871 struct qla4_header {
 872         uint8_t entryType;
 873 #define ET_STATUS                0x03
 874 #define ET_MARKER                0x04
 875 #define ET_CONT_T1               0x0A
 876 #define ET_STATUS_CONTINUATION   0x10
 877 #define ET_CMND_T3               0x19
 878 #define ET_PASSTHRU0             0x3A
 879 #define ET_PASSTHRU_STATUS       0x3C
 880
 881         uint8_t entryStatus;
 882         uint8_t systemDefined;
 883 #define SD_ISCSI_PDU    0x01
 884         uint8_t entryCount;
 885
 886         /* SyetemDefined definition */
 887 };
 888
 889 /* Generic queue entry structure*/
 890 struct queue_entry {
 891         uint8_t data[60];
 892         uint32_t signature;
 893
 894 };
 895
 896 /* 64 bit addressing segment counts*/
 897
 898 #define COMMAND_SEG_A64   1
 899 #define CONTINUE_SEG_A64  5
 900
 901 /* 64 bit addressing segment definition*/
 902
 903 struct data_seg_a64 {
 904         struct {
 905                 uint32_t addrLow;
 906                 uint32_t addrHigh;
 907
 908         } base;
 909
 910         uint32_t count;
 911
 912 };
 913
 914 /* Command Type 3 entry structure*/
 915
 916 struct command_t3_entry {
 917         struct qla4_header hdr; /* 00-03 */
 918
 919         uint32_t handle;        /* 04-07 */
 920         uint16_t target;        /* 08-09 */
 921         uint16_t connection_id; /* 0A-0B */
 922
 923         uint8_t control_flags;  /* 0C */
 924
 925         /* data direction  (bits 5-6) */
 926 #define CF_WRITE                0x20
 927 #define CF_READ                 0x40
 928 #define CF_NO_DATA              0x00
 929
 930         /* task attributes (bits 2-0) */
 931 #define CF_HEAD_TAG             0x03
 932 #define CF_ORDERED_TAG          0x02
 933 #define CF_SIMPLE_TAG           0x01
 934
 935         /* STATE FLAGS FIELD IS A PLACE HOLDER. THE FW WILL SET BITS
 936          * IN THIS FIELD AS THE COMMAND IS PROCESSED. WHEN THE IOCB IS
 937          * CHANGED TO AN IOSB THIS FIELD WILL HAVE THE STATE FLAGS SET
 938          * PROPERLY.
 939          */
 940         uint8_t state_flags;    /* 0D */
 941         uint8_t cmdRefNum;      /* 0E */
 942         uint8_t reserved1;      /* 0F */
 943         uint8_t cdb[IOCB_MAX_CDB_LEN];  /* 10-1F */
 944         struct scsi_lun lun;    /* FCP LUN (BE). */
 945         uint32_t cmdSeqNum;     /* 28-2B */
 946         uint16_t timeout;       /* 2C-2D */
 947         uint16_t dataSegCnt;    /* 2E-2F */
 948         uint32_t ttlByteCnt;    /* 30-33 */
 949         struct data_seg_a64 dataseg[COMMAND_SEG_A64];   /* 34-3F */
 950
 951 };
 952
 953
 954 /* Continuation Type 1 entry structure*/
 955 struct continuation_t1_entry {
 956         struct qla4_header hdr;
 957
 958         struct data_seg_a64 dataseg[CONTINUE_SEG_A64];
 959
 960 };
 961
 962 /* Parameterize for 64 or 32 bits */
 963 #define COMMAND_SEG     COMMAND_SEG_A64
 964 #define CONTINUE_SEG    CONTINUE_SEG_A64
 965
 966 #define ET_COMMAND      ET_CMND_T3
 967 #define ET_CONTINUE     ET_CONT_T1
 968
 969 /* Marker entry structure*/
 970 struct qla4_marker_entry {
 971         struct qla4_header hdr; /* 00-03 */
 972
 973         uint32_t system_defined; /* 04-07 */
 974         uint16_t target;        /* 08-09 */
 975         uint16_t modifier;      /* 0A-0B */
 976 #define MM_LUN_RESET            0
 977 #define MM_TGT_WARM_RESET       1
 978
 979         uint16_t flags;         /* 0C-0D */
 980         uint16_t reserved1;     /* 0E-0F */
 981         struct scsi_lun lun;    /* FCP LUN (BE). */
 982         uint64_t reserved2;     /* 18-1F */
 983         uint64_t reserved3;     /* 20-27 */
 984         uint64_t reserved4;     /* 28-2F */
 985         uint64_t reserved5;     /* 30-37 */
 986         uint64_t reserved6;     /* 38-3F */
 987 };
 988
 989 /* Status entry structure*/
 990 struct status_entry {
 991         struct qla4_header hdr; /* 00-03 */
 992
 993         uint32_t handle;        /* 04-07 */
 994
 995         uint8_t scsiStatus;     /* 08 */
 996 #define SCSI_CHECK_CONDITION              0x02
 997
 998         uint8_t iscsiFlags;     /* 09 */
 999 #define ISCSI_FLAG_RESIDUAL_UNDER         0x02
1000 #define ISCSI_FLAG_RESIDUAL_OVER          0x04
1001
1002         uint8_t iscsiResponse;  /* 0A */
1003
1004         uint8_t completionStatus;       /* 0B */
1005 #define SCS_COMPLETE                      0x00
1006 #define SCS_INCOMPLETE                    0x01
1007 #define SCS_RESET_OCCURRED                0x04
1008 #define SCS_ABORTED                       0x05
1009 #define SCS_TIMEOUT                       0x06
1010 #define SCS_DATA_OVERRUN                  0x07
1011 #define SCS_DATA_UNDERRUN                 0x15
1012 #define SCS_QUEUE_FULL                    0x1C
1013 #define SCS_DEVICE_UNAVAILABLE            0x28
1014 #define SCS_DEVICE_LOGGED_OUT             0x29
1015
1016         uint8_t reserved1;      /* 0C */
1017
1018         /* state_flags MUST be at the same location as state_flags in
1019          * the Command_T3/4_Entry */
1020         uint8_t state_flags;    /* 0D */
1021
1022         uint16_t senseDataByteCnt;      /* 0E-0F */
1023         uint32_t residualByteCnt;       /* 10-13 */
1024         uint32_t bidiResidualByteCnt;   /* 14-17 */
1025         uint32_t expSeqNum;     /* 18-1B */
1026         uint32_t maxCmdSeqNum;  /* 1C-1F */
1027         uint8_t senseData[IOCB_MAX_SENSEDATA_LEN];      /* 20-3F */
1028
1029 };
1030
1031 /* Status Continuation entry */
1032 struct status_cont_entry {
1033        struct qla4_header hdr; /* 00-03 */
1034        uint8_t ext_sense_data[IOCB_MAX_EXT_SENSEDATA_LEN]; /* 04-63 */
1035 };
1036
1037 struct passthru0 {
1038         struct qla4_header hdr;                /* 00-03 */
1039         uint32_t handle;        /* 04-07 */
1040         uint16_t target;        /* 08-09 */
1041         uint16_t connection_id; /* 0A-0B */
1042 #define ISNS_DEFAULT_SERVER_CONN_ID     ((uint16_t)0x8000)
1043
1044         uint16_t control_flags; /* 0C-0D */
1045 #define PT_FLAG_ETHERNET_FRAME          0x8000
1046 #define PT_FLAG_ISNS_PDU                0x8000
1047 #define PT_FLAG_SEND_BUFFER             0x0200
1048 #define PT_FLAG_WAIT_4_RESPONSE         0x0100
1049 #define PT_FLAG_ISCSI_PDU               0x1000
1050
1051         uint16_t timeout;       /* 0E-0F */
1052 #define PT_DEFAULT_TIMEOUT              30 /* seconds */
1053
1054         struct data_seg_a64 out_dsd;    /* 10-1B */
1055         uint32_t res1;          /* 1C-1F */
1056         struct data_seg_a64 in_dsd;     /* 20-2B */
1057         uint8_t res2[20];       /* 2C-3F */
1058 };
1059
1060 struct passthru_status {
1061         struct qla4_header hdr;                /* 00-03 */
1062         uint32_t handle;        /* 04-07 */
1063         uint16_t target;        /* 08-09 */
1064         uint16_t connectionID;  /* 0A-0B */
1065
1066         uint8_t completionStatus;       /* 0C */
1067 #define PASSTHRU_STATUS_COMPLETE                0x01
1068
1069         uint8_t residualFlags;  /* 0D */
1070
1071         uint16_t timeout;       /* 0E-0F */
1072         uint16_t portNumber;    /* 10-11 */
1073         uint8_t res1[10];       /* 12-1B */
1074         uint32_t outResidual;   /* 1C-1F */
1075         uint8_t res2[12];       /* 20-2B */
1076         uint32_t inResidual;    /* 2C-2F */
1077         uint8_t res4[16];       /* 30-3F */
1078 };
1079
1080 /*
1081  * ISP queue - response queue entry definition.
1082  */
1083 struct response {
1084         uint8_t data[60];
1085         uint32_t signature;
1086 #define RESPONSE_PROCESSED      0xDEADDEAD      /* Signature */
1087 };
1088
1089 struct ql_iscsi_stats {
1090         uint8_t reserved1[656]; /* 0000-028F */
1091         uint32_t tx_cmd_pdu; /* 0290-0293 */
1092         uint32_t tx_resp_pdu; /* 0294-0297 */
1093         uint32_t rx_cmd_pdu; /* 0298-029B */
1094         uint32_t rx_resp_pdu; /* 029C-029F */
1095
1096         uint64_t tx_data_octets; /* 02A0-02A7 */
1097         uint64_t rx_data_octets; /* 02A8-02AF */
1098
1099         uint32_t hdr_digest_err; /* 02B0–02B3 */
1100         uint32_t data_digest_err; /* 02B4–02B7 */
1101         uint32_t conn_timeout_err; /* 02B8–02BB */
1102         uint32_t framing_err; /* 02BC–02BF */
1103
1104         uint32_t tx_nopout_pdus; /* 02C0–02C3 */
1105         uint32_t tx_scsi_cmd_pdus;  /* 02C4–02C7 */
1106         uint32_t tx_tmf_cmd_pdus; /* 02C8–02CB */
1107         uint32_t tx_login_cmd_pdus; /* 02CC–02CF */
1108         uint32_t tx_text_cmd_pdus; /* 02D0–02D3 */
1109         uint32_t tx_scsi_write_pdus; /* 02D4–02D7 */
1110         uint32_t tx_logout_cmd_pdus; /* 02D8–02DB */
1111         uint32_t tx_snack_req_pdus; /* 02DC–02DF */
1112
1113         uint32_t rx_nopin_pdus; /* 02E0–02E3 */
1114         uint32_t rx_scsi_resp_pdus; /* 02E4–02E7 */
1115         uint32_t rx_tmf_resp_pdus; /* 02E8–02EB */
1116         uint32_t rx_login_resp_pdus; /* 02EC–02EF */
1117         uint32_t rx_text_resp_pdus; /* 02F0–02F3 */
1118         uint32_t rx_scsi_read_pdus; /* 02F4–02F7 */
1119         uint32_t rx_logout_resp_pdus; /* 02F8–02FB */
1120
1121         uint32_t rx_r2t_pdus; /* 02FC–02FF */
1122         uint32_t rx_async_pdus; /* 0300–0303 */
1123         uint32_t rx_reject_pdus; /* 0304–0307 */
1124
1125         uint8_t reserved2[264]; /* 0x0308 - 0x040F */
1126 };
1127
1128 #endif /*  _QLA4X_FW_H */