drivers/scsi/qla2xxx/qla_sup.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/delay.h>
  10 #include <linux/vmalloc.h>
  11 #include <asm/uaccess.h>
  12
  13 /*
  14  * NVRAM support routines
  15  */
  16
  17 /**
  18  * qla2x00_lock_nvram_access() -
  19  * @ha: HA context
  20  */
  21 static void
  22 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
  23 {
  24         uint16_t data;
  25         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  26
  27         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  28                 data = RD_REG_WORD(&reg->nvram);
  29                 while (data & NVR_BUSY) {
  30                         udelay(100);
  31                         data = RD_REG_WORD(&reg->nvram);
  32                 }
  33
  34                 /* Lock resource */
  35                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  36                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  37                 udelay(5);
  38                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  39                 while ((data & BIT_0) == 0) {
  40                         /* Lock failed */
  41                         udelay(100);
  42                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  43                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  44                         udelay(5);
  45                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  46                 }
  47         }
  48 }
  49
  50 /**
  51  * qla2x00_unlock_nvram_access() -
  52  * @ha: HA context
  53  */
  54 static void
  55 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
  56 {
  57         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  58
  59         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  60                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  61                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  62         }
  63 }
  64
  65 /**
  66  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
  67  * @ha: HA context
  68  * @data: Serial interface selector
  69  */
  70 static void
  71 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
  72 {
  73         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  74
  75         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  76         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  77         NVRAM_DELAY();
  78         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
  79             NVR_WRT_ENABLE);
  80         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  81         NVRAM_DELAY();
  82         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  83         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  84         NVRAM_DELAY();
  85 }
  86
  87 /**
  88  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
  89  *      NVRAM.
  90  * @ha: HA context
  91  * @nv_cmd: NVRAM command
  92  *
  93  * Bit definitions for NVRAM command:
  94  *
  95  *      Bit 26     = start bit
  96  *      Bit 25, 24 = opcode
  97  *      Bit 23-16  = address
  98  *      Bit 15-0   = write data
  99  *
 100  * Returns the word read from nvram @addr.
 101  */
 102 static uint16_t
 103 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
 104 {
 105         uint8_t         cnt;
 106         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 107         uint16_t        data = 0;
 108         uint16_t        reg_data;
 109
 110         /* Send command to NVRAM. */
 111         nv_cmd <<= 5;
 112         for (cnt = 0; cnt < 11; cnt++) {
 113                 if (nv_cmd & BIT_31)
 114                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 115                 else
 116                         qla2x00_nv_write(ha, 0);
 117                 nv_cmd <<= 1;
 118         }
 119
 120         /* Read data from NVRAM. */
 121         for (cnt = 0; cnt < 16; cnt++) {
 122                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 123                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 124                 NVRAM_DELAY();
 125                 data <<= 1;
 126                 reg_data = RD_REG_WORD(&reg->nvram);
 127                 if (reg_data & NVR_DATA_IN)
 128                         data |= BIT_0;
 129                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 130                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 131                 NVRAM_DELAY();
 132         }
 133
 134         /* Deselect chip. */
 135         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 136         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 137         NVRAM_DELAY();
 138
 139         return data;
 140 }
 141
 142
 143 /**
 144  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
 145  *      request routine to get the word from NVRAM.
 146  * @ha: HA context
 147  * @addr: Address in NVRAM to read
 148  *
 149  * Returns the word read from nvram @addr.
 150  */
 151 static uint16_t
 152 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
 153 {
 154         uint16_t        data;
 155         uint32_t        nv_cmd;
 156
 157         nv_cmd = addr << 16;
 158         nv_cmd |= NV_READ_OP;
 159         data = qla2x00_nvram_request(ha, nv_cmd);
 160
 161         return (data);
 162 }
 163
 164 /**
 165  * qla2x00_nv_deselect() - Deselect NVRAM operations.
 166  * @ha: HA context
 167  */
 168 static void
 169 qla2x00_nv_deselect(struct qla_hw_data *ha)
 170 {
 171         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 172
 173         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 174         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 175         NVRAM_DELAY();
 176 }
 177
 178 /**
 179  * qla2x00_write_nvram_word() - Write NVRAM data.
 180  * @ha: HA context
 181  * @addr: Address in NVRAM to write
 182  * @data: word to program
 183  */
 184 static void
 185 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
 186 {
 187         int count;
 188         uint16_t word;
 189         uint32_t nv_cmd, wait_cnt;
 190         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 191
 192         qla2x00_nv_write(ha, NVR_DATA_OUT);
 193         qla2x00_nv_write(ha, 0);
 194         qla2x00_nv_write(ha, 0);
 195
 196         for (word = 0; word < 8; word++)
 197                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 198
 199         qla2x00_nv_deselect(ha);
 200
 201         /* Write data */
 202         nv_cmd = (addr << 16) | NV_WRITE_OP;
 203         nv_cmd |= data;
 204         nv_cmd <<= 5;
 205         for (count = 0; count < 27; count++) {
 206                 if (nv_cmd & BIT_31)
 207                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 208                 else
 209                         qla2x00_nv_write(ha, 0);
 210
 211                 nv_cmd <<= 1;
 212         }
 213
 214         qla2x00_nv_deselect(ha);
 215
 216         /* Wait for NVRAM to become ready */
 217         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 218         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 219         wait_cnt = NVR_WAIT_CNT;
 220         do {
 221                 if (!--wait_cnt) {
 222                         DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
 223                             __func__, vha->host_no));
 224                         break;
 225                 }
 226                 NVRAM_DELAY();
 227                 word = RD_REG_WORD(&reg->nvram);
 228         } while ((word & NVR_DATA_IN) == 0);
 229
 230         qla2x00_nv_deselect(ha);
 231
 232         /* Disable writes */
 233         qla2x00_nv_write(ha, NVR_DATA_OUT);
 234         for (count = 0; count < 10; count++)
 235                 qla2x00_nv_write(ha, 0);
 236
 237         qla2x00_nv_deselect(ha);
 238 }
 239
 240 static int
 241 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
 242         uint16_t data, uint32_t tmo)
 243 {
 244         int ret, count;
 245         uint16_t word;
 246         uint32_t nv_cmd;
 247         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 248
 249         ret = QLA_SUCCESS;
 250
 251         qla2x00_nv_write(ha, NVR_DATA_OUT);
 252         qla2x00_nv_write(ha, 0);
 253         qla2x00_nv_write(ha, 0);
 254
 255         for (word = 0; word < 8; word++)
 256                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 257
 258         qla2x00_nv_deselect(ha);
 259
 260         /* Write data */
 261         nv_cmd = (addr << 16) | NV_WRITE_OP;
 262         nv_cmd |= data;
 263         nv_cmd <<= 5;
 264         for (count = 0; count < 27; count++) {
 265                 if (nv_cmd & BIT_31)
 266                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 267                 else
 268                         qla2x00_nv_write(ha, 0);
 269
 270                 nv_cmd <<= 1;
 271         }
 272
 273         qla2x00_nv_deselect(ha);
 274
 275         /* Wait for NVRAM to become ready */
 276         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 277         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 278         do {
 279                 NVRAM_DELAY();
 280                 word = RD_REG_WORD(&reg->nvram);
 281                 if (!--tmo) {
 282                         ret = QLA_FUNCTION_FAILED;
 283                         break;
 284                 }
 285         } while ((word & NVR_DATA_IN) == 0);
 286
 287         qla2x00_nv_deselect(ha);
 288
 289         /* Disable writes */
 290         qla2x00_nv_write(ha, NVR_DATA_OUT);
 291         for (count = 0; count < 10; count++)
 292                 qla2x00_nv_write(ha, 0);
 293
 294         qla2x00_nv_deselect(ha);
 295
 296         return ret;
 297 }
 298
 299 /**
 300  * qla2x00_clear_nvram_protection() -
 301  * @ha: HA context
 302  */
 303 static int
 304 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
 305 {
 306         int ret, stat;
 307         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 308         uint32_t word, wait_cnt;
 309         uint16_t wprot, wprot_old;
 310
 311         /* Clear NVRAM write protection. */
 312         ret = QLA_FUNCTION_FAILED;
 313
 314         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 315         stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
 316             __constant_cpu_to_le16(0x1234), 100000);
 317         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 318         if (stat != QLA_SUCCESS || wprot != 0x1234) {
 319                 /* Write enable. */
 320                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 321                 qla2x00_nv_write(ha, 0);
 322                 qla2x00_nv_write(ha, 0);
 323                 for (word = 0; word < 8; word++)
 324                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 325
 326                 qla2x00_nv_deselect(ha);
 327
 328                 /* Enable protection register. */
 329                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 330                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 331                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 332                 for (word = 0; word < 8; word++)
 333                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 334
 335                 qla2x00_nv_deselect(ha);
 336
 337                 /* Clear protection register (ffff is cleared). */
 338                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 339                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 340                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 341                 for (word = 0; word < 8; word++)
 342                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 343
 344                 qla2x00_nv_deselect(ha);
 345
 346                 /* Wait for NVRAM to become ready. */
 347                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 348                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 349                 wait_cnt = NVR_WAIT_CNT;
 350                 do {
 351                         if (!--wait_cnt) {
 352                                 DEBUG9_10(qla_printk(
 353                                     "NVRAM didn't go ready...\n"));
 354                                 break;
 355                         }
 356                         NVRAM_DELAY();
 357                         word = RD_REG_WORD(&reg->nvram);
 358                 } while ((word & NVR_DATA_IN) == 0);
 359
 360                 if (wait_cnt)
 361                         ret = QLA_SUCCESS;
 362         } else
 363                 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
 364
 365         return ret;
 366 }
 367
 368 static void
 369 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
 370 {
 371         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 372         uint32_t word, wait_cnt;
 373
 374         if (stat != QLA_SUCCESS)
 375                 return;
 376
 377         /* Set NVRAM write protection. */
 378         /* Write enable. */
 379         qla2x00_nv_write(ha, NVR_DATA_OUT);
 380         qla2x00_nv_write(ha, 0);
 381         qla2x00_nv_write(ha, 0);
 382         for (word = 0; word < 8; word++)
 383                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 384
 385         qla2x00_nv_deselect(ha);
 386
 387         /* Enable protection register. */
 388         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 389         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 390         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 391         for (word = 0; word < 8; word++)
 392                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 393
 394         qla2x00_nv_deselect(ha);
 395
 396         /* Enable protection register. */
 397         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 398         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 399         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 400         for (word = 0; word < 8; word++)
 401                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 402
 403         qla2x00_nv_deselect(ha);
 404
 405         /* Wait for NVRAM to become ready. */
 406         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 407         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 408         wait_cnt = NVR_WAIT_CNT;
 409         do {
 410                 if (!--wait_cnt) {
 411                         DEBUG9_10(qla_printk("NVRAM didn't go ready...\n"));
 412                         break;
 413                 }
 414                 NVRAM_DELAY();
 415                 word = RD_REG_WORD(&reg->nvram);
 416         } while ((word & NVR_DATA_IN) == 0);
 417 }
 418
 419
 420 /*****************************************************************************/
 421 /* Flash Manipulation Routines                                               */
 422 /*****************************************************************************/
 423
 424 #define OPTROM_BURST_SIZE       0x1000
 425 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
 426
 427 static inline uint32_t
 428 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
 429 {
 430         return ha->flash_conf_off | faddr;
 431 }
 432
 433 static inline uint32_t
 434 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
 435 {
 436         return ha->flash_data_off | faddr;
 437 }
 438
 439 static inline uint32_t
 440 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
 441 {
 442         return ha->nvram_conf_off | naddr;
 443 }
 444
 445 static inline uint32_t
 446 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
 447 {
 448         return ha->nvram_data_off | naddr;
 449 }
 450
 451 static uint32_t
 452 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
 453 {
 454         int rval;
 455         uint32_t cnt, data;
 456         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 457
 458         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 459         /* Wait for READ cycle to complete. */
 460         rval = QLA_SUCCESS;
 461         for (cnt = 3000;
 462             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 463             rval == QLA_SUCCESS; cnt--) {
 464                 if (cnt)
 465                         udelay(10);
 466                 else
 467                         rval = QLA_FUNCTION_TIMEOUT;
 468                 cond_resched();
 469         }
 470
 471         /* TODO: What happens if we time out? */
 472         data = 0xDEADDEAD;
 473         if (rval == QLA_SUCCESS)
 474                 data = RD_REG_DWORD(&reg->flash_data);
 475
 476         return data;
 477 }
 478
 479 uint32_t *
 480 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
 481     uint32_t dwords)
 482 {
 483         uint32_t i;
 484         struct qla_hw_data *ha = vha->hw;
 485
 486         /* Dword reads to flash. */
 487         for (i = 0; i < dwords; i++, faddr++)
 488                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 489                     flash_data_addr(ha, faddr)));
 490
 491         return dwptr;
 492 }
 493
 494 static int
 495 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
 496 {
 497         int rval;
 498         uint32_t cnt;
 499         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 500
 501         WRT_REG_DWORD(&reg->flash_data, data);
 502         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 503         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 504         /* Wait for Write cycle to complete. */
 505         rval = QLA_SUCCESS;
 506         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 507             rval == QLA_SUCCESS; cnt--) {
 508                 if (cnt)
 509                         udelay(10);
 510                 else
 511                         rval = QLA_FUNCTION_TIMEOUT;
 512                 cond_resched();
 513         }
 514         return rval;
 515 }
 516
 517 static void
 518 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
 519     uint8_t *flash_id)
 520 {
 521         uint32_t ids;
 522
 523         ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
 524         *man_id = LSB(ids);
 525         *flash_id = MSB(ids);
 526
 527         /* Check if man_id and flash_id are valid. */
 528         if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
 529                 /* Read information using 0x9f opcode
 530                  * Device ID, Mfg ID would be read in the format:
 531                  *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
 532                  * Example: ATMEL 0x00 01 45 1F
 533                  * Extract MFG and Dev ID from last two bytes.
 534                  */
 535                 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
 536                 *man_id = LSB(ids);
 537                 *flash_id = MSB(ids);
 538         }
 539 }
 540
 541 static int
 542 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
 543 {
 544         const char *loc, *locations[] = { "DEF", "PCI" };
 545         uint32_t pcihdr, pcids;
 546         uint32_t *dcode;
 547         uint8_t *buf, *bcode, last_image;
 548         uint16_t cnt, chksum, *wptr;
 549         struct qla_flt_location *fltl;
 550         struct qla_hw_data *ha = vha->hw;
 551         struct req_que *req = ha->req_q_map[0];
 552
 553         /*
 554          * FLT-location structure resides after the last PCI region.
 555          */
 556
 557         /* Begin with sane defaults. */
 558         loc = locations[0];
 559         *start = 0;
 560         if (IS_QLA24XX_TYPE(ha))
 561                 *start = FA_FLASH_LAYOUT_ADDR_24;
 562         else if (IS_QLA25XX(ha))
 563                 *start = FA_FLASH_LAYOUT_ADDR;
 564         else if (IS_QLA81XX(ha))
 565                 *start = FA_FLASH_LAYOUT_ADDR_81;
 566         /* Begin with first PCI expansion ROM header. */
 567         buf = (uint8_t *)req->ring;
 568         dcode = (uint32_t *)req->ring;
 569         pcihdr = 0;
 570         last_image = 1;
 571         do {
 572                 /* Verify PCI expansion ROM header. */
 573                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
 574                 bcode = buf + (pcihdr % 4);
 575                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
 576                         goto end;
 577
 578                 /* Locate PCI data structure. */
 579                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
 580                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
 581                 bcode = buf + (pcihdr % 4);
 582
 583                 /* Validate signature of PCI data structure. */
 584                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
 585                     bcode[0x2] != 'I' || bcode[0x3] != 'R')
 586                         goto end;
 587
 588                 last_image = bcode[0x15] & BIT_7;
 589
 590                 /* Locate next PCI expansion ROM. */
 591                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
 592         } while (!last_image);
 593
 594         /* Now verify FLT-location structure. */
 595         fltl = (struct qla_flt_location *)req->ring;
 596         qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
 597             sizeof(struct qla_flt_location) >> 2);
 598         if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
 599             fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
 600                 goto end;
 601
 602         wptr = (uint16_t *)req->ring;
 603         cnt = sizeof(struct qla_flt_location) >> 1;
 604         for (chksum = 0; cnt; cnt--)
 605                 chksum += le16_to_cpu(*wptr++);
 606         if (chksum) {
 607                 qla_printk(KERN_ERR, ha,
 608                     "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
 609                 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
 610                 return QLA_FUNCTION_FAILED;
 611         }
 612
 613         /* Good data.  Use specified location. */
 614         loc = locations[1];
 615         *start = (le16_to_cpu(fltl->start_hi) << 16 |
 616             le16_to_cpu(fltl->start_lo)) >> 2;
 617 end:
 618         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
 619         return QLA_SUCCESS;
 620 }
 621
 622 static void
 623 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
 624 {
 625         const char *loc, *locations[] = { "DEF", "FLT" };
 626         const uint32_t def_fw[] =
 627                 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
 628         const uint32_t def_boot[] =
 629                 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
 630         const uint32_t def_vpd_nvram[] =
 631                 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
 632         const uint32_t def_vpd0[] =
 633                 { 0, 0, FA_VPD0_ADDR_81 };
 634         const uint32_t def_vpd1[] =
 635                 { 0, 0, FA_VPD1_ADDR_81 };
 636         const uint32_t def_nvram0[] =
 637                 { 0, 0, FA_NVRAM0_ADDR_81 };
 638         const uint32_t def_nvram1[] =
 639                 { 0, 0, FA_NVRAM1_ADDR_81 };
 640         const uint32_t def_fdt[] =
 641                 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
 642                         FA_FLASH_DESCR_ADDR_81 };
 643         const uint32_t def_npiv_conf0[] =
 644                 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
 645                         FA_NPIV_CONF0_ADDR_81 };
 646         const uint32_t def_npiv_conf1[] =
 647                 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
 648                         FA_NPIV_CONF1_ADDR_81 };
 649         uint32_t def;
 650         uint16_t *wptr;
 651         uint16_t cnt, chksum;
 652         uint32_t start;
 653         struct qla_flt_header *flt;
 654         struct qla_flt_region *region;
 655         struct qla_hw_data *ha = vha->hw;
 656         struct req_que *req = ha->req_q_map[0];
 657
 658         ha->flt_region_flt = flt_addr;
 659         wptr = (uint16_t *)req->ring;
 660         flt = (struct qla_flt_header *)req->ring;
 661         region = (struct qla_flt_region *)&flt[1];
 662         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 663             flt_addr << 2, OPTROM_BURST_SIZE);
 664         if (*wptr == __constant_cpu_to_le16(0xffff))
 665                 goto no_flash_data;
 666         if (flt->version != __constant_cpu_to_le16(1)) {
 667                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
 668                     "version=0x%x length=0x%x checksum=0x%x.\n",
 669                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 670                     le16_to_cpu(flt->checksum)));
 671                 goto no_flash_data;
 672         }
 673
 674         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
 675         for (chksum = 0; cnt; cnt--)
 676                 chksum += le16_to_cpu(*wptr++);
 677         if (chksum) {
 678                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
 679                     "version=0x%x length=0x%x checksum=0x%x.\n",
 680                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 681                     chksum));
 682                 goto no_flash_data;
 683         }
 684
 685         loc = locations[1];
 686         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
 687         for ( ; cnt; cnt--, region++) {
 688                 /* Store addresses as DWORD offsets. */
 689                 start = le32_to_cpu(region->start) >> 2;
 690
 691                 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
 692                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
 693                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
 694
 695                 switch (le32_to_cpu(region->code) & 0xff) {
 696                 case FLT_REG_FW:
 697                         ha->flt_region_fw = start;
 698                         break;
 699                 case FLT_REG_BOOT_CODE:
 700                         ha->flt_region_boot = start;
 701                         break;
 702                 case FLT_REG_VPD_0:
 703                         ha->flt_region_vpd_nvram = start;
 704                         if (!(PCI_FUNC(ha->pdev->devfn) & 1))
 705                                 ha->flt_region_vpd = start;
 706                         break;
 707                 case FLT_REG_VPD_1:
 708                         if (PCI_FUNC(ha->pdev->devfn) & 1)
 709                                 ha->flt_region_vpd = start;
 710                         break;
 711                 case FLT_REG_NVRAM_0:
 712                         if (!(PCI_FUNC(ha->pdev->devfn) & 1))
 713                                 ha->flt_region_nvram = start;
 714                         break;
 715                 case FLT_REG_NVRAM_1:
 716                         if (PCI_FUNC(ha->pdev->devfn) & 1)
 717                                 ha->flt_region_nvram = start;
 718                         break;
 719                 case FLT_REG_FDT:
 720                         ha->flt_region_fdt = start;
 721                         break;
 722                 case FLT_REG_NPIV_CONF_0:
 723                         if (!(PCI_FUNC(ha->pdev->devfn) & 1))
 724                                 ha->flt_region_npiv_conf = start;
 725                         break;
 726                 case FLT_REG_NPIV_CONF_1:
 727                         if (PCI_FUNC(ha->pdev->devfn) & 1)
 728                                 ha->flt_region_npiv_conf = start;
 729                         break;
 730                 }
 731         }
 732         goto done;
 733
 734 no_flash_data:
 735         /* Use hardcoded defaults. */
 736         loc = locations[0];
 737         def = 0;
 738         if (IS_QLA24XX_TYPE(ha))
 739                 def = 0;
 740         else if (IS_QLA25XX(ha))
 741                 def = 1;
 742         else if (IS_QLA81XX(ha))
 743                 def = 2;
 744         ha->flt_region_fw = def_fw[def];
 745         ha->flt_region_boot = def_boot[def];
 746         ha->flt_region_vpd_nvram = def_vpd_nvram[def];
 747         ha->flt_region_vpd = !(PCI_FUNC(ha->pdev->devfn) & 1) ?
 748             def_vpd0[def]: def_vpd1[def];
 749         ha->flt_region_nvram = !(PCI_FUNC(ha->pdev->devfn) & 1) ?
 750             def_nvram0[def]: def_nvram1[def];
 751         ha->flt_region_fdt = def_fdt[def];
 752         ha->flt_region_npiv_conf = !(PCI_FUNC(ha->pdev->devfn) & 1) ?
 753             def_npiv_conf0[def]: def_npiv_conf1[def];
 754 done:
 755         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
 756             "vpd_nvram=0x%x vpd=0x%x nvram=0x%x fdt=0x%x flt=0x%x "
 757             "npiv=0x%x.\n", loc, ha->flt_region_boot, ha->flt_region_fw,
 758             ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
 759             ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
 760 }
 761
 762 static void
 763 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
 764 {
 765 #define FLASH_BLK_SIZE_4K       0x1000
 766 #define FLASH_BLK_SIZE_32K      0x8000
 767 #define FLASH_BLK_SIZE_64K      0x10000
 768         const char *loc, *locations[] = { "MID", "FDT" };
 769         uint16_t cnt, chksum;
 770         uint16_t *wptr;
 771         struct qla_fdt_layout *fdt;
 772         uint8_t man_id, flash_id;
 773         uint16_t mid, fid;
 774         struct qla_hw_data *ha = vha->hw;
 775         struct req_que *req = ha->req_q_map[0];
 776
 777         wptr = (uint16_t *)req->ring;
 778         fdt = (struct qla_fdt_layout *)req->ring;
 779         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 780             ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
 781         if (*wptr == __constant_cpu_to_le16(0xffff))
 782                 goto no_flash_data;
 783         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
 784             fdt->sig[3] != 'D')
 785                 goto no_flash_data;
 786
 787         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
 788             cnt++)
 789                 chksum += le16_to_cpu(*wptr++);
 790         if (chksum) {
 791                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
 792                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
 793                     le16_to_cpu(fdt->version)));
 794                 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
 795                 goto no_flash_data;
 796         }
 797
 798         loc = locations[1];
 799         mid = le16_to_cpu(fdt->man_id);
 800         fid = le16_to_cpu(fdt->id);
 801         ha->fdt_wrt_disable = fdt->wrt_disable_bits;
 802         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
 803         ha->fdt_block_size = le32_to_cpu(fdt->block_size);
 804         if (fdt->unprotect_sec_cmd) {
 805                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
 806                     fdt->unprotect_sec_cmd);
 807                 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
 808                     flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
 809                     flash_conf_addr(ha, 0x0336);
 810         }
 811         goto done;
 812 no_flash_data:
 813         loc = locations[0];
 814         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 815         mid = man_id;
 816         fid = flash_id;
 817         ha->fdt_wrt_disable = 0x9c;
 818         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
 819         switch (man_id) {
 820         case 0xbf: /* STT flash. */
 821                 if (flash_id == 0x8e)
 822                         ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 823                 else
 824                         ha->fdt_block_size = FLASH_BLK_SIZE_32K;
 825
 826                 if (flash_id == 0x80)
 827                         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
 828                 break;
 829         case 0x13: /* ST M25P80. */
 830                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 831                 break;
 832         case 0x1f: /* Atmel 26DF081A. */
 833                 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
 834                 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
 835                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
 836                 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
 837                 break;
 838         default:
 839                 /* Default to 64 kb sector size. */
 840                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 841                 break;
 842         }
 843 done:
 844         DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
 845             "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
 846             ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
 847             ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
 848             ha->fdt_block_size));
 849 }
 850
 851 int
 852 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
 853 {
 854         int ret;
 855         uint32_t flt_addr;
 856         struct qla_hw_data *ha = vha->hw;
 857
 858         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
 859                 return QLA_SUCCESS;
 860
 861         ret = qla2xxx_find_flt_start(vha, &flt_addr);
 862         if (ret != QLA_SUCCESS)
 863                 return ret;
 864
 865         qla2xxx_get_flt_info(vha, flt_addr);
 866         qla2xxx_get_fdt_info(vha);
 867
 868         return QLA_SUCCESS;
 869 }
 870
 871 void
 872 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
 873 {
 874 #define NPIV_CONFIG_SIZE        (16*1024)
 875         void *data;
 876         uint16_t *wptr;
 877         uint16_t cnt, chksum;
 878         int i;
 879         struct qla_npiv_header hdr;
 880         struct qla_npiv_entry *entry;
 881         struct qla_hw_data *ha = vha->hw;
 882
 883         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
 884                 return;
 885
 886         ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
 887             ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
 888         if (hdr.version == __constant_cpu_to_le16(0xffff))
 889                 return;
 890         if (hdr.version != __constant_cpu_to_le16(1)) {
 891                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
 892                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
 893                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
 894                     le16_to_cpu(hdr.checksum)));
 895                 return;
 896         }
 897
 898         data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
 899         if (!data) {
 900                 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
 901                     "allocate memory.\n"));
 902                 return;
 903         }
 904
 905         ha->isp_ops->read_optrom(vha, (uint8_t *)data,
 906             ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
 907
 908         cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
 909             sizeof(struct qla_npiv_entry)) >> 1;
 910         for (wptr = data, chksum = 0; cnt; cnt--)
 911                 chksum += le16_to_cpu(*wptr++);
 912         if (chksum) {
 913                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
 914                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
 915                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
 916                     chksum));
 917                 goto done;
 918         }
 919
 920         entry = data + sizeof(struct qla_npiv_header);
 921         cnt = le16_to_cpu(hdr.entries);
 922         for (i = 0; cnt; cnt--, entry++, i++) {
 923                 uint16_t flags;
 924                 struct fc_vport_identifiers vid;
 925                 struct fc_vport *vport;
 926
 927                 flags = le16_to_cpu(entry->flags);
 928                 if (flags == 0xffff)
 929                         continue;
 930                 if ((flags & BIT_0) == 0)
 931                         continue;
 932
 933                 memset(&vid, 0, sizeof(vid));
 934                 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
 935                 vid.vport_type = FC_PORTTYPE_NPIV;
 936                 vid.disable = false;
 937                 vid.port_name = wwn_to_u64(entry->port_name);
 938                 vid.node_name = wwn_to_u64(entry->node_name);
 939
 940                 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
 941
 942                 DEBUG2(qla_printk(KERN_DEBUG, ha, "NPIV[%02x]: wwpn=%llx "
 943                         "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
 944                         vid.port_name, vid.node_name, le16_to_cpu(entry->vf_id),
 945                         entry->q_qos, entry->f_qos));
 946
 947                 if (i < QLA_PRECONFIG_VPORTS) {
 948                         vport = fc_vport_create(vha->host, 0, &vid);
 949                         if (!vport)
 950                                 qla_printk(KERN_INFO, ha,
 951                                 "NPIV-Config: Failed to create vport [%02x]: "
 952                                 "wwpn=%llx wwnn=%llx.\n", cnt,
 953                                 vid.port_name, vid.node_name);
 954                 }
 955         }
 956 done:
 957         kfree(data);
 958         ha->npiv_info = NULL;
 959 }
 960
 961 static int
 962 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
 963 {
 964         struct qla_hw_data *ha = vha->hw;
 965         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 966
 967         if (ha->flags.fac_supported)
 968                 return qla81xx_fac_do_write_enable(vha, 1);
 969
 970         /* Enable flash write. */
 971         WRT_REG_DWORD(&reg->ctrl_status,
 972             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 973         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 974
 975         if (!ha->fdt_wrt_disable)
 976                 goto done;
 977
 978         /* Disable flash write-protection, first clear SR protection bit */
 979         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
 980         /* Then write zero again to clear remaining SR bits.*/
 981         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
 982 done:
 983         return QLA_SUCCESS;
 984 }
 985
 986 static int
 987 qla24xx_protect_flash(scsi_qla_host_t *vha)
 988 {
 989         uint32_t cnt;
 990         struct qla_hw_data *ha = vha->hw;
 991         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 992
 993         if (ha->flags.fac_supported)
 994                 return qla81xx_fac_do_write_enable(vha, 0);
 995
 996         if (!ha->fdt_wrt_disable)
 997                 goto skip_wrt_protect;
 998
 999         /* Enable flash write-protection and wait for completion. */
1000         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1001             ha->fdt_wrt_disable);
1002         for (cnt = 300; cnt &&
1003             qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1004             cnt--) {
1005                 udelay(10);
1006         }
1007
1008 skip_wrt_protect:
1009         /* Disable flash write. */
1010         WRT_REG_DWORD(&reg->ctrl_status,
1011             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1012         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1013
1014         return QLA_SUCCESS;
1015 }
1016
1017 static int
1018 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1019 {
1020         struct qla_hw_data *ha = vha->hw;
1021         uint32_t start, finish;
1022
1023         if (ha->flags.fac_supported) {
1024                 start = fdata >> 2;
1025                 finish = start + (ha->fdt_block_size >> 2) - 1;
1026                 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1027                     start), flash_data_addr(ha, finish));
1028         }
1029
1030         return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1031             (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1032             ((fdata >> 16) & 0xff));
1033 }
1034
1035 static int
1036 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1037     uint32_t dwords)
1038 {
1039         int ret;
1040         uint32_t liter;
1041         uint32_t sec_mask, rest_addr;
1042         uint32_t fdata;
1043         dma_addr_t optrom_dma;
1044         void *optrom = NULL;
1045         struct qla_hw_data *ha = vha->hw;
1046
1047         /* Prepare burst-capable write on supported ISPs. */
1048         if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
1049             dwords > OPTROM_BURST_DWORDS) {
1050                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1051                     &optrom_dma, GFP_KERNEL);
1052                 if (!optrom) {
1053                         qla_printk(KERN_DEBUG, ha,
1054                             "Unable to allocate memory for optrom burst write "
1055                             "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1056                 }
1057         }
1058
1059         rest_addr = (ha->fdt_block_size >> 2) - 1;
1060         sec_mask = ~rest_addr;
1061
1062         ret = qla24xx_unprotect_flash(vha);
1063         if (ret != QLA_SUCCESS) {
1064                 qla_printk(KERN_WARNING, ha,
1065                     "Unable to unprotect flash for update.\n");
1066                 goto done;
1067         }
1068
1069         for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1070                 fdata = (faddr & sec_mask) << 2;
1071
1072                 /* Are we at the beginning of a sector? */
1073                 if ((faddr & rest_addr) == 0) {
1074                         /* Do sector unprotect. */
1075                         if (ha->fdt_unprotect_sec_cmd)
1076                                 qla24xx_write_flash_dword(ha,
1077                                     ha->fdt_unprotect_sec_cmd,
1078                                     (fdata & 0xff00) | ((fdata << 16) &
1079                                     0xff0000) | ((fdata >> 16) & 0xff));
1080                         ret = qla24xx_erase_sector(vha, fdata);
1081                         if (ret != QLA_SUCCESS) {
1082                                 DEBUG9(qla_printk("Unable to erase sector: "
1083                                     "address=%x.\n", faddr));
1084                                 break;
1085                         }
1086                 }
1087
1088                 /* Go with burst-write. */
1089                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1090                         /* Copy data to DMA'ble buffer. */
1091                         memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1092
1093                         ret = qla2x00_load_ram(vha, optrom_dma,
1094                             flash_data_addr(ha, faddr),
1095                             OPTROM_BURST_DWORDS);
1096                         if (ret != QLA_SUCCESS) {
1097                                 qla_printk(KERN_WARNING, ha,
1098                                     "Unable to burst-write optrom segment "
1099                                     "(%x/%x/%llx).\n", ret,
1100                                     flash_data_addr(ha, faddr),
1101                                     (unsigned long long)optrom_dma);
1102                                 qla_printk(KERN_WARNING, ha,
1103                                     "Reverting to slow-write.\n");
1104
1105                                 dma_free_coherent(&ha->pdev->dev,
1106                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1107                                 optrom = NULL;
1108                         } else {
1109                                 liter += OPTROM_BURST_DWORDS - 1;
1110                                 faddr += OPTROM_BURST_DWORDS - 1;
1111                                 dwptr += OPTROM_BURST_DWORDS - 1;
1112                                 continue;
1113                         }
1114                 }
1115
1116                 ret = qla24xx_write_flash_dword(ha,
1117                     flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1118                 if (ret != QLA_SUCCESS) {
1119                         DEBUG9(printk("%s(%ld) Unable to program flash "
1120                             "address=%x data=%x.\n", __func__,
1121                             vha->host_no, faddr, *dwptr));
1122                         break;
1123                 }
1124
1125                 /* Do sector protect. */
1126                 if (ha->fdt_unprotect_sec_cmd &&
1127                     ((faddr & rest_addr) == rest_addr))
1128                         qla24xx_write_flash_dword(ha,
1129                             ha->fdt_protect_sec_cmd,
1130                             (fdata & 0xff00) | ((fdata << 16) &
1131                             0xff0000) | ((fdata >> 16) & 0xff));
1132         }
1133
1134         ret = qla24xx_protect_flash(vha);
1135         if (ret != QLA_SUCCESS)
1136                 qla_printk(KERN_WARNING, ha,
1137                     "Unable to protect flash after update.\n");
1138 done:
1139         if (optrom)
1140                 dma_free_coherent(&ha->pdev->dev,
1141                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1142
1143         return ret;
1144 }
1145
1146 uint8_t *
1147 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1148     uint32_t bytes)
1149 {
1150         uint32_t i;
1151         uint16_t *wptr;
1152         struct qla_hw_data *ha = vha->hw;
1153
1154         /* Word reads to NVRAM via registers. */
1155         wptr = (uint16_t *)buf;
1156         qla2x00_lock_nvram_access(ha);
1157         for (i = 0; i < bytes >> 1; i++, naddr++)
1158                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1159                     naddr));
1160         qla2x00_unlock_nvram_access(ha);
1161
1162         return buf;
1163 }
1164
1165 uint8_t *
1166 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1167     uint32_t bytes)
1168 {
1169         uint32_t i;
1170         uint32_t *dwptr;
1171         struct qla_hw_data *ha = vha->hw;
1172
1173         /* Dword reads to flash. */
1174         dwptr = (uint32_t *)buf;
1175         for (i = 0; i < bytes >> 2; i++, naddr++)
1176                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1177                     nvram_data_addr(ha, naddr)));
1178
1179         return buf;
1180 }
1181
1182 int
1183 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1184     uint32_t bytes)
1185 {
1186         int ret, stat;
1187         uint32_t i;
1188         uint16_t *wptr;
1189         unsigned long flags;
1190         struct qla_hw_data *ha = vha->hw;
1191
1192         ret = QLA_SUCCESS;
1193
1194         spin_lock_irqsave(&ha->hardware_lock, flags);
1195         qla2x00_lock_nvram_access(ha);
1196
1197         /* Disable NVRAM write-protection. */
1198         stat = qla2x00_clear_nvram_protection(ha);
1199
1200         wptr = (uint16_t *)buf;
1201         for (i = 0; i < bytes >> 1; i++, naddr++) {
1202                 qla2x00_write_nvram_word(ha, naddr,
1203                     cpu_to_le16(*wptr));
1204                 wptr++;
1205         }
1206
1207         /* Enable NVRAM write-protection. */
1208         qla2x00_set_nvram_protection(ha, stat);
1209
1210         qla2x00_unlock_nvram_access(ha);
1211         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1212
1213         return ret;
1214 }
1215
1216 int
1217 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1218     uint32_t bytes)
1219 {
1220         int ret;
1221         uint32_t i;
1222         uint32_t *dwptr;
1223         struct qla_hw_data *ha = vha->hw;
1224         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1225
1226         ret = QLA_SUCCESS;
1227
1228         /* Enable flash write. */
1229         WRT_REG_DWORD(&reg->ctrl_status,
1230             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1231         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1232
1233         /* Disable NVRAM write-protection. */
1234         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1235         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1236
1237         /* Dword writes to flash. */
1238         dwptr = (uint32_t *)buf;
1239         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1240                 ret = qla24xx_write_flash_dword(ha,
1241                     nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1242                 if (ret != QLA_SUCCESS) {
1243                         DEBUG9(qla_printk("Unable to program nvram address=%x "
1244                             "data=%x.\n", naddr, *dwptr));
1245                         break;
1246                 }
1247         }
1248
1249         /* Enable NVRAM write-protection. */
1250         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1251
1252         /* Disable flash write. */
1253         WRT_REG_DWORD(&reg->ctrl_status,
1254             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1255         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1256
1257         return ret;
1258 }
1259
1260 uint8_t *
1261 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1262     uint32_t bytes)
1263 {
1264         uint32_t i;
1265         uint32_t *dwptr;
1266         struct qla_hw_data *ha = vha->hw;
1267
1268         /* Dword reads to flash. */
1269         dwptr = (uint32_t *)buf;
1270         for (i = 0; i < bytes >> 2; i++, naddr++)
1271                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1272                     flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1273
1274         return buf;
1275 }
1276
1277 int
1278 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1279     uint32_t bytes)
1280 {
1281         struct qla_hw_data *ha = vha->hw;
1282 #define RMW_BUFFER_SIZE (64 * 1024)
1283         uint8_t *dbuf;
1284
1285         dbuf = vmalloc(RMW_BUFFER_SIZE);
1286         if (!dbuf)
1287                 return QLA_MEMORY_ALLOC_FAILED;
1288         ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1289             RMW_BUFFER_SIZE);
1290         memcpy(dbuf + (naddr << 2), buf, bytes);
1291         ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1292             RMW_BUFFER_SIZE);
1293         vfree(dbuf);
1294
1295         return QLA_SUCCESS;
1296 }
1297
1298 static inline void
1299 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1300 {
1301         if (IS_QLA2322(ha)) {
1302                 /* Flip all colors. */
1303                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1304                         /* Turn off. */
1305                         ha->beacon_color_state = 0;
1306                         *pflags = GPIO_LED_ALL_OFF;
1307                 } else {
1308                         /* Turn on. */
1309                         ha->beacon_color_state = QLA_LED_ALL_ON;
1310                         *pflags = GPIO_LED_RGA_ON;
1311                 }
1312         } else {
1313                 /* Flip green led only. */
1314                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1315                         /* Turn off. */
1316                         ha->beacon_color_state = 0;
1317                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1318                 } else {
1319                         /* Turn on. */
1320                         ha->beacon_color_state = QLA_LED_GRN_ON;
1321                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1322                 }
1323         }
1324 }
1325
1326 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1327
1328 void
1329 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1330 {
1331         uint16_t gpio_enable;
1332         uint16_t gpio_data;
1333         uint16_t led_color = 0;
1334         unsigned long flags;
1335         struct qla_hw_data *ha = vha->hw;
1336         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1337
1338         spin_lock_irqsave(&ha->hardware_lock, flags);
1339
1340         /* Save the Original GPIOE. */
1341         if (ha->pio_address) {
1342                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1343                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1344         } else {
1345                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1346                 gpio_data = RD_REG_WORD(&reg->gpiod);
1347         }
1348
1349         /* Set the modified gpio_enable values */
1350         gpio_enable |= GPIO_LED_MASK;
1351
1352         if (ha->pio_address) {
1353                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1354         } else {
1355                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1356                 RD_REG_WORD(&reg->gpioe);
1357         }
1358
1359         qla2x00_flip_colors(ha, &led_color);
1360
1361         /* Clear out any previously set LED color. */
1362         gpio_data &= ~GPIO_LED_MASK;
1363
1364         /* Set the new input LED color to GPIOD. */
1365         gpio_data |= led_color;
1366
1367         /* Set the modified gpio_data values */
1368         if (ha->pio_address) {
1369                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1370         } else {
1371                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1372                 RD_REG_WORD(&reg->gpiod);
1373         }
1374
1375         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1376 }
1377
1378 int
1379 qla2x00_beacon_on(struct scsi_qla_host *vha)
1380 {
1381         uint16_t gpio_enable;
1382         uint16_t gpio_data;
1383         unsigned long flags;
1384         struct qla_hw_data *ha = vha->hw;
1385         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1386
1387         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1388         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1389
1390         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1391                 qla_printk(KERN_WARNING, ha,
1392                     "Unable to update fw options (beacon on).\n");
1393                 return QLA_FUNCTION_FAILED;
1394         }
1395
1396         /* Turn off LEDs. */
1397         spin_lock_irqsave(&ha->hardware_lock, flags);
1398         if (ha->pio_address) {
1399                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1400                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1401         } else {
1402                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1403                 gpio_data = RD_REG_WORD(&reg->gpiod);
1404         }
1405         gpio_enable |= GPIO_LED_MASK;
1406
1407         /* Set the modified gpio_enable values. */
1408         if (ha->pio_address) {
1409                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1410         } else {
1411                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1412                 RD_REG_WORD(&reg->gpioe);
1413         }
1414
1415         /* Clear out previously set LED colour. */
1416         gpio_data &= ~GPIO_LED_MASK;
1417         if (ha->pio_address) {
1418                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1419         } else {
1420                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1421                 RD_REG_WORD(&reg->gpiod);
1422         }
1423         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1424
1425         /*
1426          * Let the per HBA timer kick off the blinking process based on
1427          * the following flags. No need to do anything else now.
1428          */
1429         ha->beacon_blink_led = 1;
1430         ha->beacon_color_state = 0;
1431
1432         return QLA_SUCCESS;
1433 }
1434
1435 int
1436 qla2x00_beacon_off(struct scsi_qla_host *vha)
1437 {
1438         int rval = QLA_SUCCESS;
1439         struct qla_hw_data *ha = vha->hw;
1440
1441         ha->beacon_blink_led = 0;
1442
1443         /* Set the on flag so when it gets flipped it will be off. */
1444         if (IS_QLA2322(ha))
1445                 ha->beacon_color_state = QLA_LED_ALL_ON;
1446         else
1447                 ha->beacon_color_state = QLA_LED_GRN_ON;
1448
1449         ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1450
1451         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1452         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1453
1454         rval = qla2x00_set_fw_options(vha, ha->fw_options);
1455         if (rval != QLA_SUCCESS)
1456                 qla_printk(KERN_WARNING, ha,
1457                     "Unable to update fw options (beacon off).\n");
1458         return rval;
1459 }
1460
1461
1462 static inline void
1463 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1464 {
1465         /* Flip all colors. */
1466         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1467                 /* Turn off. */
1468                 ha->beacon_color_state = 0;
1469                 *pflags = 0;
1470         } else {
1471                 /* Turn on. */
1472                 ha->beacon_color_state = QLA_LED_ALL_ON;
1473                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1474         }
1475 }
1476
1477 void
1478 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1479 {
1480         uint16_t led_color = 0;
1481         uint32_t gpio_data;
1482         unsigned long flags;
1483         struct qla_hw_data *ha = vha->hw;
1484         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1485
1486         /* Save the Original GPIOD. */
1487         spin_lock_irqsave(&ha->hardware_lock, flags);
1488         gpio_data = RD_REG_DWORD(&reg->gpiod);
1489
1490         /* Enable the gpio_data reg for update. */
1491         gpio_data |= GPDX_LED_UPDATE_MASK;
1492
1493         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1494         gpio_data = RD_REG_DWORD(&reg->gpiod);
1495
1496         /* Set the color bits. */
1497         qla24xx_flip_colors(ha, &led_color);
1498
1499         /* Clear out any previously set LED color. */
1500         gpio_data &= ~GPDX_LED_COLOR_MASK;
1501
1502         /* Set the new input LED color to GPIOD. */
1503         gpio_data |= led_color;
1504
1505         /* Set the modified gpio_data values. */
1506         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1507         gpio_data = RD_REG_DWORD(&reg->gpiod);
1508         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1509 }
1510
1511 int
1512 qla24xx_beacon_on(struct scsi_qla_host *vha)
1513 {
1514         uint32_t gpio_data;
1515         unsigned long flags;
1516         struct qla_hw_data *ha = vha->hw;
1517         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1518
1519         if (ha->beacon_blink_led == 0) {
1520                 /* Enable firmware for update */
1521                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1522
1523                 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1524                         return QLA_FUNCTION_FAILED;
1525
1526                 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1527                     QLA_SUCCESS) {
1528                         qla_printk(KERN_WARNING, ha,
1529                             "Unable to update fw options (beacon on).\n");
1530                         return QLA_FUNCTION_FAILED;
1531                 }
1532
1533                 spin_lock_irqsave(&ha->hardware_lock, flags);
1534                 gpio_data = RD_REG_DWORD(&reg->gpiod);
1535
1536                 /* Enable the gpio_data reg for update. */
1537                 gpio_data |= GPDX_LED_UPDATE_MASK;
1538                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1539                 RD_REG_DWORD(&reg->gpiod);
1540
1541                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1542         }
1543
1544         /* So all colors blink together. */
1545         ha->beacon_color_state = 0;
1546
1547         /* Let the per HBA timer kick off the blinking process. */
1548         ha->beacon_blink_led = 1;
1549
1550         return QLA_SUCCESS;
1551 }
1552
1553 int
1554 qla24xx_beacon_off(struct scsi_qla_host *vha)
1555 {
1556         uint32_t gpio_data;
1557         unsigned long flags;
1558         struct qla_hw_data *ha = vha->hw;
1559         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1560
1561         ha->beacon_blink_led = 0;
1562         ha->beacon_color_state = QLA_LED_ALL_ON;
1563
1564         ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1565
1566         /* Give control back to firmware. */
1567         spin_lock_irqsave(&ha->hardware_lock, flags);
1568         gpio_data = RD_REG_DWORD(&reg->gpiod);
1569
1570         /* Disable the gpio_data reg for update. */
1571         gpio_data &= ~GPDX_LED_UPDATE_MASK;
1572         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1573         RD_REG_DWORD(&reg->gpiod);
1574         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1575
1576         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1577
1578         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1579                 qla_printk(KERN_WARNING, ha,
1580                     "Unable to update fw options (beacon off).\n");
1581                 return QLA_FUNCTION_FAILED;
1582         }
1583
1584         if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1585                 qla_printk(KERN_WARNING, ha,
1586                     "Unable to get fw options (beacon off).\n");
1587                 return QLA_FUNCTION_FAILED;
1588         }
1589
1590         return QLA_SUCCESS;
1591 }
1592
1593
1594 /*
1595  * Flash support routines
1596  */
1597
1598 /**
1599  * qla2x00_flash_enable() - Setup flash for reading and writing.
1600  * @ha: HA context
1601  */
1602 static void
1603 qla2x00_flash_enable(struct qla_hw_data *ha)
1604 {
1605         uint16_t data;
1606         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1607
1608         data = RD_REG_WORD(&reg->ctrl_status);
1609         data |= CSR_FLASH_ENABLE;
1610         WRT_REG_WORD(&reg->ctrl_status, data);
1611         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1612 }
1613
1614 /**
1615  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1616  * @ha: HA context
1617  */
1618 static void
1619 qla2x00_flash_disable(struct qla_hw_data *ha)
1620 {
1621         uint16_t data;
1622         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1623
1624         data = RD_REG_WORD(&reg->ctrl_status);
1625         data &= ~(CSR_FLASH_ENABLE);
1626         WRT_REG_WORD(&reg->ctrl_status, data);
1627         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1628 }
1629
1630 /**
1631  * qla2x00_read_flash_byte() - Reads a byte from flash
1632  * @ha: HA context
1633  * @addr: Address in flash to read
1634  *
1635  * A word is read from the chip, but, only the lower byte is valid.
1636  *
1637  * Returns the byte read from flash @addr.
1638  */
1639 static uint8_t
1640 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1641 {
1642         uint16_t data;
1643         uint16_t bank_select;
1644         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1645
1646         bank_select = RD_REG_WORD(&reg->ctrl_status);
1647
1648         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1649                 /* Specify 64K address range: */
1650                 /*  clear out Module Select and Flash Address bits [19:16]. */
1651                 bank_select &= ~0xf8;
1652                 bank_select |= addr >> 12 & 0xf0;
1653                 bank_select |= CSR_FLASH_64K_BANK;
1654                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1655                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1656
1657                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1658                 data = RD_REG_WORD(&reg->flash_data);
1659
1660                 return (uint8_t)data;
1661         }
1662
1663         /* Setup bit 16 of flash address. */
1664         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1665                 bank_select |= CSR_FLASH_64K_BANK;
1666                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1667                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1668         } else if (((addr & BIT_16) == 0) &&
1669             (bank_select & CSR_FLASH_64K_BANK)) {
1670                 bank_select &= ~(CSR_FLASH_64K_BANK);
1671                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1672                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1673         }
1674
1675         /* Always perform IO mapped accesses to the FLASH registers. */
1676         if (ha->pio_address) {
1677                 uint16_t data2;
1678
1679                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1680                 do {
1681                         data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1682                         barrier();
1683                         cpu_relax();
1684                         data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1685                 } while (data != data2);
1686         } else {
1687                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1688                 data = qla2x00_debounce_register(&reg->flash_data);
1689         }
1690
1691         return (uint8_t)data;
1692 }
1693
1694 /**
1695  * qla2x00_write_flash_byte() - Write a byte to flash
1696  * @ha: HA context
1697  * @addr: Address in flash to write
1698  * @data: Data to write
1699  */
1700 static void
1701 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1702 {
1703         uint16_t bank_select;
1704         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1705
1706         bank_select = RD_REG_WORD(&reg->ctrl_status);
1707         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1708                 /* Specify 64K address range: */
1709                 /*  clear out Module Select and Flash Address bits [19:16]. */
1710                 bank_select &= ~0xf8;
1711                 bank_select |= addr >> 12 & 0xf0;
1712                 bank_select |= CSR_FLASH_64K_BANK;
1713                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1714                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1715
1716                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1717                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1718                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1719                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1720
1721                 return;
1722         }
1723
1724         /* Setup bit 16 of flash address. */
1725         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1726                 bank_select |= CSR_FLASH_64K_BANK;
1727                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1728                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1729         } else if (((addr & BIT_16) == 0) &&
1730             (bank_select & CSR_FLASH_64K_BANK)) {
1731                 bank_select &= ~(CSR_FLASH_64K_BANK);
1732                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1733                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1734         }
1735
1736         /* Always perform IO mapped accesses to the FLASH registers. */
1737         if (ha->pio_address) {
1738                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1739                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1740         } else {
1741                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1742                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1743                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1744                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1745         }
1746 }
1747
1748 /**
1749  * qla2x00_poll_flash() - Polls flash for completion.
1750  * @ha: HA context
1751  * @addr: Address in flash to poll
1752  * @poll_data: Data to be polled
1753  * @man_id: Flash manufacturer ID
1754  * @flash_id: Flash ID
1755  *
1756  * This function polls the device until bit 7 of what is read matches data
1757  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
1758  * out (a fatal error).  The flash book recommeds reading bit 7 again after
1759  * reading bit 5 as a 1.
1760  *
1761  * Returns 0 on success, else non-zero.
1762  */
1763 static int
1764 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
1765     uint8_t man_id, uint8_t flash_id)
1766 {
1767         int status;
1768         uint8_t flash_data;
1769         uint32_t cnt;
1770
1771         status = 1;
1772
1773         /* Wait for 30 seconds for command to finish. */
1774         poll_data &= BIT_7;
1775         for (cnt = 3000000; cnt; cnt--) {
1776                 flash_data = qla2x00_read_flash_byte(ha, addr);
1777                 if ((flash_data & BIT_7) == poll_data) {
1778                         status = 0;
1779                         break;
1780                 }
1781
1782                 if (man_id != 0x40 && man_id != 0xda) {
1783                         if ((flash_data & BIT_5) && cnt > 2)
1784                                 cnt = 2;
1785                 }
1786                 udelay(10);
1787                 barrier();
1788                 cond_resched();
1789         }
1790         return status;
1791 }
1792
1793 /**
1794  * qla2x00_program_flash_address() - Programs a flash address
1795  * @ha: HA context
1796  * @addr: Address in flash to program
1797  * @data: Data to be written in flash
1798  * @man_id: Flash manufacturer ID
1799  * @flash_id: Flash ID
1800  *
1801  * Returns 0 on success, else non-zero.
1802  */
1803 static int
1804 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1805     uint8_t data, uint8_t man_id, uint8_t flash_id)
1806 {
1807         /* Write Program Command Sequence. */
1808         if (IS_OEM_001(ha)) {
1809                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1810                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1811                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1812                 qla2x00_write_flash_byte(ha, addr, data);
1813         } else {
1814                 if (man_id == 0xda && flash_id == 0xc1) {
1815                         qla2x00_write_flash_byte(ha, addr, data);
1816                         if (addr & 0x7e)
1817                                 return 0;
1818                 } else {
1819                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1820                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1821                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1822                         qla2x00_write_flash_byte(ha, addr, data);
1823                 }
1824         }
1825
1826         udelay(150);
1827
1828         /* Wait for write to complete. */
1829         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1830 }
1831
1832 /**
1833  * qla2x00_erase_flash() - Erase the flash.
1834  * @ha: HA context
1835  * @man_id: Flash manufacturer ID
1836  * @flash_id: Flash ID
1837  *
1838  * Returns 0 on success, else non-zero.
1839  */
1840 static int
1841 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
1842 {
1843         /* Individual Sector Erase Command Sequence */
1844         if (IS_OEM_001(ha)) {
1845                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1846                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1847                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1848                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1849                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1850                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1851         } else {
1852                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1853                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1854                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1855                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1856                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1857                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1858         }
1859
1860         udelay(150);
1861
1862         /* Wait for erase to complete. */
1863         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1864 }
1865
1866 /**
1867  * qla2x00_erase_flash_sector() - Erase a flash sector.
1868  * @ha: HA context
1869  * @addr: Flash sector to erase
1870  * @sec_mask: Sector address mask
1871  * @man_id: Flash manufacturer ID
1872  * @flash_id: Flash ID
1873  *
1874  * Returns 0 on success, else non-zero.
1875  */
1876 static int
1877 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
1878     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1879 {
1880         /* Individual Sector Erase Command Sequence */
1881         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1882         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1883         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1884         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1885         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1886         if (man_id == 0x1f && flash_id == 0x13)
1887                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1888         else
1889                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1890
1891         udelay(150);
1892
1893         /* Wait for erase to complete. */
1894         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1895 }
1896
1897 /**
1898  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1899  * @man_id: Flash manufacturer ID
1900  * @flash_id: Flash ID
1901  */
1902 static void
1903 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
1904     uint8_t *flash_id)
1905 {
1906         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1907         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1908         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1909         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1910         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1911         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1912         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1913         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1914 }
1915
1916 static void
1917 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1918         uint32_t saddr, uint32_t length)
1919 {
1920         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1921         uint32_t midpoint, ilength;
1922         uint8_t data;
1923
1924         midpoint = length / 2;
1925
1926         WRT_REG_WORD(&reg->nvram, 0);
1927         RD_REG_WORD(&reg->nvram);
1928         for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1929                 if (ilength == midpoint) {
1930                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1931                         RD_REG_WORD(&reg->nvram);
1932                 }
1933                 data = qla2x00_read_flash_byte(ha, saddr);
1934                 if (saddr % 100)
1935                         udelay(10);
1936                 *tmp_buf = data;
1937                 cond_resched();
1938         }
1939 }
1940
1941 static inline void
1942 qla2x00_suspend_hba(struct scsi_qla_host *vha)
1943 {
1944         int cnt;
1945         unsigned long flags;
1946         struct qla_hw_data *ha = vha->hw;
1947         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1948
1949         /* Suspend HBA. */
1950         scsi_block_requests(vha->host);
1951         ha->isp_ops->disable_intrs(ha);
1952         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1953
1954         /* Pause RISC. */
1955         spin_lock_irqsave(&ha->hardware_lock, flags);
1956         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1957         RD_REG_WORD(&reg->hccr);
1958         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1959                 for (cnt = 0; cnt < 30000; cnt++) {
1960                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1961                                 break;
1962                         udelay(100);
1963                 }
1964         } else {
1965                 udelay(10);
1966         }
1967         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1968 }
1969
1970 static inline void
1971 qla2x00_resume_hba(struct scsi_qla_host *vha)
1972 {
1973         struct qla_hw_data *ha = vha->hw;
1974
1975         /* Resume HBA. */
1976         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1977         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1978         qla2xxx_wake_dpc(vha);
1979         qla2x00_wait_for_chip_reset(vha);
1980         scsi_unblock_requests(vha->host);
1981 }
1982
1983 uint8_t *
1984 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1985     uint32_t offset, uint32_t length)
1986 {
1987         uint32_t addr, midpoint;
1988         uint8_t *data;
1989         struct qla_hw_data *ha = vha->hw;
1990         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1991
1992         /* Suspend HBA. */
1993         qla2x00_suspend_hba(vha);
1994
1995         /* Go with read. */
1996         midpoint = ha->optrom_size / 2;
1997
1998         qla2x00_flash_enable(ha);
1999         WRT_REG_WORD(&reg->nvram, 0);
2000         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
2001         for (addr = offset, data = buf; addr < length; addr++, data++) {
2002                 if (addr == midpoint) {
2003                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2004                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
2005                 }
2006
2007                 *data = qla2x00_read_flash_byte(ha, addr);
2008         }
2009         qla2x00_flash_disable(ha);
2010
2011         /* Resume HBA. */
2012         qla2x00_resume_hba(vha);
2013
2014         return buf;
2015 }
2016
2017 int
2018 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2019     uint32_t offset, uint32_t length)
2020 {
2021
2022         int rval;
2023         uint8_t man_id, flash_id, sec_number, data;
2024         uint16_t wd;
2025         uint32_t addr, liter, sec_mask, rest_addr;
2026         struct qla_hw_data *ha = vha->hw;
2027         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2028
2029         /* Suspend HBA. */
2030         qla2x00_suspend_hba(vha);
2031
2032         rval = QLA_SUCCESS;
2033         sec_number = 0;
2034
2035         /* Reset ISP chip. */
2036         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2037         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2038
2039         /* Go with write. */
2040         qla2x00_flash_enable(ha);
2041         do {    /* Loop once to provide quick error exit */
2042                 /* Structure of flash memory based on manufacturer */
2043                 if (IS_OEM_001(ha)) {
2044                         /* OEM variant with special flash part. */
2045                         man_id = flash_id = 0;
2046                         rest_addr = 0xffff;
2047                         sec_mask   = 0x10000;
2048                         goto update_flash;
2049                 }
2050                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2051                 switch (man_id) {
2052                 case 0x20: /* ST flash. */
2053                         if (flash_id == 0xd2 || flash_id == 0xe3) {
2054                                 /*
2055                                  * ST m29w008at part - 64kb sector size with
2056                                  * 32kb,8kb,8kb,16kb sectors at memory address
2057                                  * 0xf0000.
2058                                  */
2059                                 rest_addr = 0xffff;
2060                                 sec_mask = 0x10000;
2061                                 break;
2062                         }
2063                         /*
2064                          * ST m29w010b part - 16kb sector size
2065                          * Default to 16kb sectors
2066                          */
2067                         rest_addr = 0x3fff;
2068                         sec_mask = 0x1c000;
2069                         break;
2070                 case 0x40: /* Mostel flash. */
2071                         /* Mostel v29c51001 part - 512 byte sector size. */
2072                         rest_addr = 0x1ff;
2073                         sec_mask = 0x1fe00;
2074                         break;
2075                 case 0xbf: /* SST flash. */
2076                         /* SST39sf10 part - 4kb sector size. */
2077                         rest_addr = 0xfff;
2078                         sec_mask = 0x1f000;
2079                         break;
2080                 case 0xda: /* Winbond flash. */
2081                         /* Winbond W29EE011 part - 256 byte sector size. */
2082                         rest_addr = 0x7f;
2083                         sec_mask = 0x1ff80;
2084                         break;
2085                 case 0xc2: /* Macronix flash. */
2086                         /* 64k sector size. */
2087                         if (flash_id == 0x38 || flash_id == 0x4f) {
2088                                 rest_addr = 0xffff;
2089                                 sec_mask = 0x10000;
2090                                 break;
2091                         }
2092                         /* Fall through... */
2093
2094                 case 0x1f: /* Atmel flash. */
2095                         /* 512k sector size. */
2096                         if (flash_id == 0x13) {
2097                                 rest_addr = 0x7fffffff;
2098                                 sec_mask =   0x80000000;
2099                                 break;
2100                         }
2101                         /* Fall through... */
2102
2103                 case 0x01: /* AMD flash. */
2104                         if (flash_id == 0x38 || flash_id == 0x40 ||
2105                             flash_id == 0x4f) {
2106                                 /* Am29LV081 part - 64kb sector size. */
2107                                 /* Am29LV002BT part - 64kb sector size. */
2108                                 rest_addr = 0xffff;
2109                                 sec_mask = 0x10000;
2110                                 break;
2111                         } else if (flash_id == 0x3e) {
2112                                 /*
2113                                  * Am29LV008b part - 64kb sector size with
2114                                  * 32kb,8kb,8kb,16kb sector at memory address
2115                                  * h0xf0000.
2116                                  */
2117                                 rest_addr = 0xffff;
2118                                 sec_mask = 0x10000;
2119                                 break;
2120                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
2121                                 /*
2122                                  * Am29LV010 part or AM29f010 - 16kb sector
2123                                  * size.
2124                                  */
2125                                 rest_addr = 0x3fff;
2126                                 sec_mask = 0x1c000;
2127                                 break;
2128                         } else if (flash_id == 0x6d) {
2129                                 /* Am29LV001 part - 8kb sector size. */
2130                                 rest_addr = 0x1fff;
2131                                 sec_mask = 0x1e000;
2132                                 break;
2133                         }
2134                 default:
2135                         /* Default to 16 kb sector size. */
2136                         rest_addr = 0x3fff;
2137                         sec_mask = 0x1c000;
2138                         break;
2139                 }
2140
2141 update_flash:
2142                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2143                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2144                                 rval = QLA_FUNCTION_FAILED;
2145                                 break;
2146                         }
2147                 }
2148
2149                 for (addr = offset, liter = 0; liter < length; liter++,
2150                     addr++) {
2151                         data = buf[liter];
2152                         /* Are we at the beginning of a sector? */
2153                         if ((addr & rest_addr) == 0) {
2154                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2155                                         if (addr >= 0x10000UL) {
2156                                                 if (((addr >> 12) & 0xf0) &&
2157                                                     ((man_id == 0x01 &&
2158                                                         flash_id == 0x3e) ||
2159                                                      (man_id == 0x20 &&
2160                                                          flash_id == 0xd2))) {
2161                                                         sec_number++;
2162                                                         if (sec_number == 1) {
2163                                                                 rest_addr =
2164                                                                     0x7fff;
2165                                                                 sec_mask =
2166                                                                     0x18000;
2167                                                         } else if (
2168                                                             sec_number == 2 ||
2169                                                             sec_number == 3) {
2170                                                                 rest_addr =
2171                                                                     0x1fff;
2172                                                                 sec_mask =
2173                                                                     0x1e000;
2174                                                         } else if (
2175                                                             sec_number == 4) {
2176                                                                 rest_addr =
2177                                                                     0x3fff;
2178                                                                 sec_mask =
2179                                                                     0x1c000;
2180                                                         }
2181                                                 }
2182                                         }
2183                                 } else if (addr == ha->optrom_size / 2) {
2184                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2185                                         RD_REG_WORD(&reg->nvram);
2186                                 }
2187
2188                                 if (flash_id == 0xda && man_id == 0xc1) {
2189                                         qla2x00_write_flash_byte(ha, 0x5555,
2190                                             0xaa);
2191                                         qla2x00_write_flash_byte(ha, 0x2aaa,
2192                                             0x55);
2193                                         qla2x00_write_flash_byte(ha, 0x5555,
2194                                             0xa0);
2195                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2196                                         /* Then erase it */
2197                                         if (qla2x00_erase_flash_sector(ha,
2198                                             addr, sec_mask, man_id,
2199                                             flash_id)) {
2200                                                 rval = QLA_FUNCTION_FAILED;
2201                                                 break;
2202                                         }
2203                                         if (man_id == 0x01 && flash_id == 0x6d)
2204                                                 sec_number++;
2205                                 }
2206                         }
2207
2208                         if (man_id == 0x01 && flash_id == 0x6d) {
2209                                 if (sec_number == 1 &&
2210                                     addr == (rest_addr - 1)) {
2211                                         rest_addr = 0x0fff;
2212                                         sec_mask   = 0x1f000;
2213                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2214                                         rest_addr = 0x3fff;
2215                                         sec_mask   = 0x1c000;
2216                                 }
2217                         }
2218
2219                         if (qla2x00_program_flash_address(ha, addr, data,
2220                             man_id, flash_id)) {
2221                                 rval = QLA_FUNCTION_FAILED;
2222                                 break;
2223                         }
2224                         cond_resched();
2225                 }
2226         } while (0);
2227         qla2x00_flash_disable(ha);
2228
2229         /* Resume HBA. */
2230         qla2x00_resume_hba(vha);
2231
2232         return rval;
2233 }
2234
2235 uint8_t *
2236 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2237     uint32_t offset, uint32_t length)
2238 {
2239         struct qla_hw_data *ha = vha->hw;
2240
2241         /* Suspend HBA. */
2242         scsi_block_requests(vha->host);
2243         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2244
2245         /* Go with read. */
2246         qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2247
2248         /* Resume HBA. */
2249         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2250         scsi_unblock_requests(vha->host);
2251
2252         return buf;
2253 }
2254
2255 int
2256 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2257     uint32_t offset, uint32_t length)
2258 {
2259         int rval;
2260         struct qla_hw_data *ha = vha->hw;
2261
2262         /* Suspend HBA. */
2263         scsi_block_requests(vha->host);
2264         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2265
2266         /* Go with write. */
2267         rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2268             length >> 2);
2269
2270         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2271         scsi_unblock_requests(vha->host);
2272
2273         return rval;
2274 }
2275
2276 uint8_t *
2277 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2278     uint32_t offset, uint32_t length)
2279 {
2280         int rval;
2281         dma_addr_t optrom_dma;
2282         void *optrom;
2283         uint8_t *pbuf;
2284         uint32_t faddr, left, burst;
2285         struct qla_hw_data *ha = vha->hw;
2286
2287         if (offset & 0xfff)
2288                 goto slow_read;
2289         if (length < OPTROM_BURST_SIZE)
2290                 goto slow_read;
2291
2292         optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2293             &optrom_dma, GFP_KERNEL);
2294         if (!optrom) {
2295                 qla_printk(KERN_DEBUG, ha,
2296                     "Unable to allocate memory for optrom burst read "
2297                     "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2298
2299                 goto slow_read;
2300         }
2301
2302         pbuf = buf;
2303         faddr = offset >> 2;
2304         left = length >> 2;
2305         burst = OPTROM_BURST_DWORDS;
2306         while (left != 0) {
2307                 if (burst > left)
2308                         burst = left;
2309
2310                 rval = qla2x00_dump_ram(vha, optrom_dma,
2311                     flash_data_addr(ha, faddr), burst);
2312                 if (rval) {
2313                         qla_printk(KERN_WARNING, ha,
2314                             "Unable to burst-read optrom segment "
2315                             "(%x/%x/%llx).\n", rval,
2316                             flash_data_addr(ha, faddr),
2317                             (unsigned long long)optrom_dma);
2318                         qla_printk(KERN_WARNING, ha,
2319                             "Reverting to slow-read.\n");
2320
2321                         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2322                             optrom, optrom_dma);
2323                         goto slow_read;
2324                 }
2325
2326                 memcpy(pbuf, optrom, burst * 4);
2327
2328                 left -= burst;
2329                 faddr += burst;
2330                 pbuf += burst * 4;
2331         }
2332
2333         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2334             optrom_dma);
2335
2336         return buf;
2337
2338 slow_read:
2339     return qla24xx_read_optrom_data(vha, buf, offset, length);
2340 }
2341
2342 /**
2343  * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2344  * @ha: HA context
2345  * @pcids: Pointer to the FCODE PCI data structure
2346  *
2347  * The process of retrieving the FCODE version information is at best
2348  * described as interesting.
2349  *
2350  * Within the first 100h bytes of the image an ASCII string is present
2351  * which contains several pieces of information including the FCODE
2352  * version.  Unfortunately it seems the only reliable way to retrieve
2353  * the version is by scanning for another sentinel within the string,
2354  * the FCODE build date:
2355  *
2356  *      ... 2.00.02 10/17/02 ...
2357  *
2358  * Returns QLA_SUCCESS on successful retrieval of version.
2359  */
2360 static void
2361 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2362 {
2363         int ret = QLA_FUNCTION_FAILED;
2364         uint32_t istart, iend, iter, vend;
2365         uint8_t do_next, rbyte, *vbyte;
2366
2367         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2368
2369         /* Skip the PCI data structure. */
2370         istart = pcids +
2371             ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2372                 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2373         iend = istart + 0x100;
2374         do {
2375                 /* Scan for the sentinel date string...eeewww. */
2376                 do_next = 0;
2377                 iter = istart;
2378                 while ((iter < iend) && !do_next) {
2379                         iter++;
2380                         if (qla2x00_read_flash_byte(ha, iter) == '/') {
2381                                 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2382                                     '/')
2383                                         do_next++;
2384                                 else if (qla2x00_read_flash_byte(ha,
2385                                     iter + 3) == '/')
2386                                         do_next++;
2387                         }
2388                 }
2389                 if (!do_next)
2390                         break;
2391
2392                 /* Backtrack to previous ' ' (space). */
2393                 do_next = 0;
2394                 while ((iter > istart) && !do_next) {
2395                         iter--;
2396                         if (qla2x00_read_flash_byte(ha, iter) == ' ')
2397                                 do_next++;
2398                 }
2399                 if (!do_next)
2400                         break;
2401
2402                 /*
2403                  * Mark end of version tag, and find previous ' ' (space) or
2404                  * string length (recent FCODE images -- major hack ahead!!!).
2405                  */
2406                 vend = iter - 1;
2407                 do_next = 0;
2408                 while ((iter > istart) && !do_next) {
2409                         iter--;
2410                         rbyte = qla2x00_read_flash_byte(ha, iter);
2411                         if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2412                                 do_next++;
2413                 }
2414                 if (!do_next)
2415                         break;
2416
2417                 /* Mark beginning of version tag, and copy data. */
2418                 iter++;
2419                 if ((vend - iter) &&
2420                     ((vend - iter) < sizeof(ha->fcode_revision))) {
2421                         vbyte = ha->fcode_revision;
2422                         while (iter <= vend) {
2423                                 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2424                                 iter++;
2425                         }
2426                         ret = QLA_SUCCESS;
2427                 }
2428         } while (0);
2429
2430         if (ret != QLA_SUCCESS)
2431                 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2432 }
2433
2434 int
2435 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2436 {
2437         int ret = QLA_SUCCESS;
2438         uint8_t code_type, last_image;
2439         uint32_t pcihdr, pcids;
2440         uint8_t *dbyte;
2441         uint16_t *dcode;
2442         struct qla_hw_data *ha = vha->hw;
2443
2444         if (!ha->pio_address || !mbuf)
2445                 return QLA_FUNCTION_FAILED;
2446
2447         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2448         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2449         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2450         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2451
2452         qla2x00_flash_enable(ha);
2453
2454         /* Begin with first PCI expansion ROM header. */
2455         pcihdr = 0;
2456         last_image = 1;
2457         do {
2458                 /* Verify PCI expansion ROM header. */
2459                 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2460                     qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2461                         /* No signature */
2462                         DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2463                             "signature.\n"));
2464                         ret = QLA_FUNCTION_FAILED;
2465                         break;
2466                 }
2467
2468                 /* Locate PCI data structure. */
2469                 pcids = pcihdr +
2470                     ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2471                         qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2472
2473                 /* Validate signature of PCI data structure. */
2474                 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2475                     qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2476                     qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2477                     qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2478                         /* Incorrect header. */
2479                         DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2480                             "found pcir_adr=%x.\n", pcids));
2481                         ret = QLA_FUNCTION_FAILED;
2482                         break;
2483                 }
2484
2485                 /* Read version */
2486                 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2487                 switch (code_type) {
2488                 case ROM_CODE_TYPE_BIOS:
2489                         /* Intel x86, PC-AT compatible. */
2490                         ha->bios_revision[0] =
2491                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2492                         ha->bios_revision[1] =
2493                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2494                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2495                             ha->bios_revision[1], ha->bios_revision[0]));
2496                         break;
2497                 case ROM_CODE_TYPE_FCODE:
2498                         /* Open Firmware standard for PCI (FCode). */
2499                         /* Eeeewww... */
2500                         qla2x00_get_fcode_version(ha, pcids);
2501                         break;
2502                 case ROM_CODE_TYPE_EFI:
2503                         /* Extensible Firmware Interface (EFI). */
2504                         ha->efi_revision[0] =
2505                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2506                         ha->efi_revision[1] =
2507                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2508                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2509                             ha->efi_revision[1], ha->efi_revision[0]));
2510                         break;
2511                 default:
2512                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2513                             "type %x at pcids %x.\n", code_type, pcids));
2514                         break;
2515                 }
2516
2517                 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2518
2519                 /* Locate next PCI expansion ROM. */
2520                 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2521                     qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2522         } while (!last_image);
2523
2524         if (IS_QLA2322(ha)) {
2525                 /* Read firmware image information. */
2526                 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2527                 dbyte = mbuf;
2528                 memset(dbyte, 0, 8);
2529                 dcode = (uint16_t *)dbyte;
2530
2531                 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2532                     8);
2533                 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2534                     "flash:\n"));
2535                 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2536
2537                 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2538                     dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2539                     (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2540                     dcode[3] == 0)) {
2541                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2542                             "revision at %x.\n", ha->flt_region_fw * 4));
2543                 } else {
2544                         /* values are in big endian */
2545                         ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2546                         ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2547                         ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2548                 }
2549         }
2550
2551         qla2x00_flash_disable(ha);
2552
2553         return ret;
2554 }
2555
2556 int
2557 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2558 {
2559         int ret = QLA_SUCCESS;
2560         uint32_t pcihdr, pcids;
2561         uint32_t *dcode;
2562         uint8_t *bcode;
2563         uint8_t code_type, last_image;
2564         int i;
2565         struct qla_hw_data *ha = vha->hw;
2566
2567         if (!mbuf)
2568                 return QLA_FUNCTION_FAILED;
2569
2570         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2571         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2572         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2573         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2574
2575         dcode = mbuf;
2576
2577         /* Begin with first PCI expansion ROM header. */
2578         pcihdr = ha->flt_region_boot << 2;
2579         last_image = 1;
2580         do {
2581                 /* Verify PCI expansion ROM header. */
2582                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2583                 bcode = mbuf + (pcihdr % 4);
2584                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2585                         /* No signature */
2586                         DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2587                             "signature.\n"));
2588                         ret = QLA_FUNCTION_FAILED;
2589                         break;
2590                 }
2591
2592                 /* Locate PCI data structure. */
2593                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2594
2595                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2596                 bcode = mbuf + (pcihdr % 4);
2597
2598                 /* Validate signature of PCI data structure. */
2599                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2600                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2601                         /* Incorrect header. */
2602                         DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2603                             "found pcir_adr=%x.\n", pcids));
2604                         ret = QLA_FUNCTION_FAILED;
2605                         break;
2606                 }
2607
2608                 /* Read version */
2609                 code_type = bcode[0x14];
2610                 switch (code_type) {
2611                 case ROM_CODE_TYPE_BIOS:
2612                         /* Intel x86, PC-AT compatible. */
2613                         ha->bios_revision[0] = bcode[0x12];
2614                         ha->bios_revision[1] = bcode[0x13];
2615                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2616                             ha->bios_revision[1], ha->bios_revision[0]));
2617                         break;
2618                 case ROM_CODE_TYPE_FCODE:
2619                         /* Open Firmware standard for PCI (FCode). */
2620                         ha->fcode_revision[0] = bcode[0x12];
2621                         ha->fcode_revision[1] = bcode[0x13];
2622                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
2623                             ha->fcode_revision[1], ha->fcode_revision[0]));
2624                         break;
2625                 case ROM_CODE_TYPE_EFI:
2626                         /* Extensible Firmware Interface (EFI). */
2627                         ha->efi_revision[0] = bcode[0x12];
2628                         ha->efi_revision[1] = bcode[0x13];
2629                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2630                             ha->efi_revision[1], ha->efi_revision[0]));
2631                         break;
2632                 default:
2633                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2634                             "type %x at pcids %x.\n", code_type, pcids));
2635                         break;
2636                 }
2637
2638                 last_image = bcode[0x15] & BIT_7;
2639
2640                 /* Locate next PCI expansion ROM. */
2641                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2642         } while (!last_image);
2643
2644         /* Read firmware image information. */
2645         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2646         dcode = mbuf;
2647
2648         qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2649         for (i = 0; i < 4; i++)
2650                 dcode[i] = be32_to_cpu(dcode[i]);
2651
2652         if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2653             dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2654             (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2655             dcode[3] == 0)) {
2656                 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2657                     "revision at %x.\n", ha->flt_region_fw * 4));
2658         } else {
2659                 ha->fw_revision[0] = dcode[0];
2660                 ha->fw_revision[1] = dcode[1];
2661                 ha->fw_revision[2] = dcode[2];
2662                 ha->fw_revision[3] = dcode[3];
2663         }
2664
2665         return ret;
2666 }
2667
2668 static int
2669 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2670 {
2671         if (pos >= end || *pos != 0x82)
2672                 return 0;
2673
2674         pos += 3 + pos[1];
2675         if (pos >= end || *pos != 0x90)
2676                 return 0;
2677
2678         pos += 3 + pos[1];
2679         if (pos >= end || *pos != 0x78)
2680                 return 0;
2681
2682         return 1;
2683 }
2684
2685 int
2686 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2687 {
2688         struct qla_hw_data *ha = vha->hw;
2689         uint8_t *pos = ha->vpd;
2690         uint8_t *end = pos + ha->vpd_size;
2691         int len = 0;
2692
2693         if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2694                 return 0;
2695
2696         while (pos < end && *pos != 0x78) {
2697                 len = (*pos == 0x82) ? pos[1] : pos[2];
2698
2699                 if (!strncmp(pos, key, strlen(key)))
2700                         break;
2701
2702                 if (*pos != 0x90 && *pos != 0x91)
2703                         pos += len;
2704
2705                 pos += 3;
2706         }
2707
2708         if (pos < end - len && *pos != 0x78)
2709                 return snprintf(str, size, "%.*s", len, pos + 3);
2710
2711         return 0;
2712 }