drivers/scsi/qla2xxx/qla_sup.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/delay.h>
  10 #include <linux/vmalloc.h>
  11 #include <asm/uaccess.h>
  12
  13 /*
  14  * NVRAM support routines
  15  */
  16
  17 /**
  18  * qla2x00_lock_nvram_access() -
  19  * @ha: HA context
  20  */
  21 static void
  22 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
  23 {
  24         uint16_t data;
  25         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  26
  27         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  28                 data = RD_REG_WORD(&reg->nvram);
  29                 while (data & NVR_BUSY) {
  30                         udelay(100);
  31                         data = RD_REG_WORD(&reg->nvram);
  32                 }
  33
  34                 /* Lock resource */
  35                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  36                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  37                 udelay(5);
  38                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  39                 while ((data & BIT_0) == 0) {
  40                         /* Lock failed */
  41                         udelay(100);
  42                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  43                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  44                         udelay(5);
  45                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  46                 }
  47         }
  48 }
  49
  50 /**
  51  * qla2x00_unlock_nvram_access() -
  52  * @ha: HA context
  53  */
  54 static void
  55 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
  56 {
  57         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  58
  59         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  60                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  61                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  62         }
  63 }
  64
  65 /**
  66  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
  67  * @ha: HA context
  68  * @data: Serial interface selector
  69  */
  70 static void
  71 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
  72 {
  73         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  74
  75         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  76         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  77         NVRAM_DELAY();
  78         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
  79             NVR_WRT_ENABLE);
  80         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  81         NVRAM_DELAY();
  82         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  83         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  84         NVRAM_DELAY();
  85 }
  86
  87 /**
  88  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
  89  *      NVRAM.
  90  * @ha: HA context
  91  * @nv_cmd: NVRAM command
  92  *
  93  * Bit definitions for NVRAM command:
  94  *
  95  *      Bit 26     = start bit
  96  *      Bit 25, 24 = opcode
  97  *      Bit 23-16  = address
  98  *      Bit 15-0   = write data
  99  *
 100  * Returns the word read from nvram @addr.
 101  */
 102 static uint16_t
 103 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
 104 {
 105         uint8_t         cnt;
 106         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 107         uint16_t        data = 0;
 108         uint16_t        reg_data;
 109
 110         /* Send command to NVRAM. */
 111         nv_cmd <<= 5;
 112         for (cnt = 0; cnt < 11; cnt++) {
 113                 if (nv_cmd & BIT_31)
 114                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 115                 else
 116                         qla2x00_nv_write(ha, 0);
 117                 nv_cmd <<= 1;
 118         }
 119
 120         /* Read data from NVRAM. */
 121         for (cnt = 0; cnt < 16; cnt++) {
 122                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 123                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 124                 NVRAM_DELAY();
 125                 data <<= 1;
 126                 reg_data = RD_REG_WORD(&reg->nvram);
 127                 if (reg_data & NVR_DATA_IN)
 128                         data |= BIT_0;
 129                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 130                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 131                 NVRAM_DELAY();
 132         }
 133
 134         /* Deselect chip. */
 135         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 136         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 137         NVRAM_DELAY();
 138
 139         return data;
 140 }
 141
 142
 143 /**
 144  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
 145  *      request routine to get the word from NVRAM.
 146  * @ha: HA context
 147  * @addr: Address in NVRAM to read
 148  *
 149  * Returns the word read from nvram @addr.
 150  */
 151 static uint16_t
 152 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
 153 {
 154         uint16_t        data;
 155         uint32_t        nv_cmd;
 156
 157         nv_cmd = addr << 16;
 158         nv_cmd |= NV_READ_OP;
 159         data = qla2x00_nvram_request(ha, nv_cmd);
 160
 161         return (data);
 162 }
 163
 164 /**
 165  * qla2x00_nv_deselect() - Deselect NVRAM operations.
 166  * @ha: HA context
 167  */
 168 static void
 169 qla2x00_nv_deselect(struct qla_hw_data *ha)
 170 {
 171         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 172
 173         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 174         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 175         NVRAM_DELAY();
 176 }
 177
 178 /**
 179  * qla2x00_write_nvram_word() - Write NVRAM data.
 180  * @ha: HA context
 181  * @addr: Address in NVRAM to write
 182  * @data: word to program
 183  */
 184 static void
 185 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
 186 {
 187         int count;
 188         uint16_t word;
 189         uint32_t nv_cmd, wait_cnt;
 190         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 191
 192         qla2x00_nv_write(ha, NVR_DATA_OUT);
 193         qla2x00_nv_write(ha, 0);
 194         qla2x00_nv_write(ha, 0);
 195
 196         for (word = 0; word < 8; word++)
 197                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 198
 199         qla2x00_nv_deselect(ha);
 200
 201         /* Write data */
 202         nv_cmd = (addr << 16) | NV_WRITE_OP;
 203         nv_cmd |= data;
 204         nv_cmd <<= 5;
 205         for (count = 0; count < 27; count++) {
 206                 if (nv_cmd & BIT_31)
 207                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 208                 else
 209                         qla2x00_nv_write(ha, 0);
 210
 211                 nv_cmd <<= 1;
 212         }
 213
 214         qla2x00_nv_deselect(ha);
 215
 216         /* Wait for NVRAM to become ready */
 217         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 218         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 219         wait_cnt = NVR_WAIT_CNT;
 220         do {
 221                 if (!--wait_cnt) {
 222                         DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
 223                             __func__, vha->host_no));
 224                         break;
 225                 }
 226                 NVRAM_DELAY();
 227                 word = RD_REG_WORD(&reg->nvram);
 228         } while ((word & NVR_DATA_IN) == 0);
 229
 230         qla2x00_nv_deselect(ha);
 231
 232         /* Disable writes */
 233         qla2x00_nv_write(ha, NVR_DATA_OUT);
 234         for (count = 0; count < 10; count++)
 235                 qla2x00_nv_write(ha, 0);
 236
 237         qla2x00_nv_deselect(ha);
 238 }
 239
 240 static int
 241 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
 242         uint16_t data, uint32_t tmo)
 243 {
 244         int ret, count;
 245         uint16_t word;
 246         uint32_t nv_cmd;
 247         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 248
 249         ret = QLA_SUCCESS;
 250
 251         qla2x00_nv_write(ha, NVR_DATA_OUT);
 252         qla2x00_nv_write(ha, 0);
 253         qla2x00_nv_write(ha, 0);
 254
 255         for (word = 0; word < 8; word++)
 256                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 257
 258         qla2x00_nv_deselect(ha);
 259
 260         /* Write data */
 261         nv_cmd = (addr << 16) | NV_WRITE_OP;
 262         nv_cmd |= data;
 263         nv_cmd <<= 5;
 264         for (count = 0; count < 27; count++) {
 265                 if (nv_cmd & BIT_31)
 266                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 267                 else
 268                         qla2x00_nv_write(ha, 0);
 269
 270                 nv_cmd <<= 1;
 271         }
 272
 273         qla2x00_nv_deselect(ha);
 274
 275         /* Wait for NVRAM to become ready */
 276         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 277         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 278         do {
 279                 NVRAM_DELAY();
 280                 word = RD_REG_WORD(&reg->nvram);
 281                 if (!--tmo) {
 282                         ret = QLA_FUNCTION_FAILED;
 283                         break;
 284                 }
 285         } while ((word & NVR_DATA_IN) == 0);
 286
 287         qla2x00_nv_deselect(ha);
 288
 289         /* Disable writes */
 290         qla2x00_nv_write(ha, NVR_DATA_OUT);
 291         for (count = 0; count < 10; count++)
 292                 qla2x00_nv_write(ha, 0);
 293
 294         qla2x00_nv_deselect(ha);
 295
 296         return ret;
 297 }
 298
 299 /**
 300  * qla2x00_clear_nvram_protection() -
 301  * @ha: HA context
 302  */
 303 static int
 304 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
 305 {
 306         int ret, stat;
 307         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 308         uint32_t word, wait_cnt;
 309         uint16_t wprot, wprot_old;
 310
 311         /* Clear NVRAM write protection. */
 312         ret = QLA_FUNCTION_FAILED;
 313
 314         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 315         stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
 316             __constant_cpu_to_le16(0x1234), 100000);
 317         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 318         if (stat != QLA_SUCCESS || wprot != 0x1234) {
 319                 /* Write enable. */
 320                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 321                 qla2x00_nv_write(ha, 0);
 322                 qla2x00_nv_write(ha, 0);
 323                 for (word = 0; word < 8; word++)
 324                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 325
 326                 qla2x00_nv_deselect(ha);
 327
 328                 /* Enable protection register. */
 329                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 330                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 331                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 332                 for (word = 0; word < 8; word++)
 333                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 334
 335                 qla2x00_nv_deselect(ha);
 336
 337                 /* Clear protection register (ffff is cleared). */
 338                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 339                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 340                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 341                 for (word = 0; word < 8; word++)
 342                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 343
 344                 qla2x00_nv_deselect(ha);
 345
 346                 /* Wait for NVRAM to become ready. */
 347                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 348                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 349                 wait_cnt = NVR_WAIT_CNT;
 350                 do {
 351                         if (!--wait_cnt) {
 352                                 DEBUG9_10(qla_printk(
 353                                     "NVRAM didn't go ready...\n"));
 354                                 break;
 355                         }
 356                         NVRAM_DELAY();
 357                         word = RD_REG_WORD(&reg->nvram);
 358                 } while ((word & NVR_DATA_IN) == 0);
 359
 360                 if (wait_cnt)
 361                         ret = QLA_SUCCESS;
 362         } else
 363                 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
 364
 365         return ret;
 366 }
 367
 368 static void
 369 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
 370 {
 371         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 372         uint32_t word, wait_cnt;
 373
 374         if (stat != QLA_SUCCESS)
 375                 return;
 376
 377         /* Set NVRAM write protection. */
 378         /* Write enable. */
 379         qla2x00_nv_write(ha, NVR_DATA_OUT);
 380         qla2x00_nv_write(ha, 0);
 381         qla2x00_nv_write(ha, 0);
 382         for (word = 0; word < 8; word++)
 383                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 384
 385         qla2x00_nv_deselect(ha);
 386
 387         /* Enable protection register. */
 388         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 389         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 390         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 391         for (word = 0; word < 8; word++)
 392                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 393
 394         qla2x00_nv_deselect(ha);
 395
 396         /* Enable protection register. */
 397         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 398         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 399         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 400         for (word = 0; word < 8; word++)
 401                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 402
 403         qla2x00_nv_deselect(ha);
 404
 405         /* Wait for NVRAM to become ready. */
 406         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 407         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 408         wait_cnt = NVR_WAIT_CNT;
 409         do {
 410                 if (!--wait_cnt) {
 411                         DEBUG9_10(qla_printk("NVRAM didn't go ready...\n"));
 412                         break;
 413                 }
 414                 NVRAM_DELAY();
 415                 word = RD_REG_WORD(&reg->nvram);
 416         } while ((word & NVR_DATA_IN) == 0);
 417 }
 418
 419
 420 /*****************************************************************************/
 421 /* Flash Manipulation Routines                                               */
 422 /*****************************************************************************/
 423
 424 #define OPTROM_BURST_SIZE       0x1000
 425 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
 426
 427 static inline uint32_t
 428 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
 429 {
 430         return ha->flash_conf_off | faddr;
 431 }
 432
 433 static inline uint32_t
 434 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
 435 {
 436         return ha->flash_data_off | faddr;
 437 }
 438
 439 static inline uint32_t
 440 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
 441 {
 442         return ha->nvram_conf_off | naddr;
 443 }
 444
 445 static inline uint32_t
 446 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
 447 {
 448         return ha->nvram_data_off | naddr;
 449 }
 450
 451 static uint32_t
 452 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
 453 {
 454         int rval;
 455         uint32_t cnt, data;
 456         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 457
 458         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 459         /* Wait for READ cycle to complete. */
 460         rval = QLA_SUCCESS;
 461         for (cnt = 3000;
 462             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 463             rval == QLA_SUCCESS; cnt--) {
 464                 if (cnt)
 465                         udelay(10);
 466                 else
 467                         rval = QLA_FUNCTION_TIMEOUT;
 468                 cond_resched();
 469         }
 470
 471         /* TODO: What happens if we time out? */
 472         data = 0xDEADDEAD;
 473         if (rval == QLA_SUCCESS)
 474                 data = RD_REG_DWORD(&reg->flash_data);
 475
 476         return data;
 477 }
 478
 479 uint32_t *
 480 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
 481     uint32_t dwords)
 482 {
 483         uint32_t i;
 484         struct qla_hw_data *ha = vha->hw;
 485
 486         /* Dword reads to flash. */
 487         for (i = 0; i < dwords; i++, faddr++)
 488                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 489                     flash_data_addr(ha, faddr)));
 490
 491         return dwptr;
 492 }
 493
 494 static int
 495 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
 496 {
 497         int rval;
 498         uint32_t cnt;
 499         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 500
 501         WRT_REG_DWORD(&reg->flash_data, data);
 502         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 503         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 504         /* Wait for Write cycle to complete. */
 505         rval = QLA_SUCCESS;
 506         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 507             rval == QLA_SUCCESS; cnt--) {
 508                 if (cnt)
 509                         udelay(10);
 510                 else
 511                         rval = QLA_FUNCTION_TIMEOUT;
 512                 cond_resched();
 513         }
 514         return rval;
 515 }
 516
 517 static void
 518 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
 519     uint8_t *flash_id)
 520 {
 521         uint32_t ids;
 522
 523         ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
 524         *man_id = LSB(ids);
 525         *flash_id = MSB(ids);
 526
 527         /* Check if man_id and flash_id are valid. */
 528         if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
 529                 /* Read information using 0x9f opcode
 530                  * Device ID, Mfg ID would be read in the format:
 531                  *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
 532                  * Example: ATMEL 0x00 01 45 1F
 533                  * Extract MFG and Dev ID from last two bytes.
 534                  */
 535                 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
 536                 *man_id = LSB(ids);
 537                 *flash_id = MSB(ids);
 538         }
 539 }
 540
 541 static int
 542 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
 543 {
 544         const char *loc, *locations[] = { "DEF", "PCI" };
 545         uint32_t pcihdr, pcids;
 546         uint32_t *dcode;
 547         uint8_t *buf, *bcode, last_image;
 548         uint16_t cnt, chksum, *wptr;
 549         struct qla_flt_location *fltl;
 550         struct qla_hw_data *ha = vha->hw;
 551         struct req_que *req = ha->req_q_map[0];
 552
 553         /*
 554          * FLT-location structure resides after the last PCI region.
 555          */
 556
 557         /* Begin with sane defaults. */
 558         loc = locations[0];
 559         *start = 0;
 560         if (IS_QLA24XX_TYPE(ha))
 561                 *start = FA_FLASH_LAYOUT_ADDR_24;
 562         else if (IS_QLA25XX(ha))
 563                 *start = FA_FLASH_LAYOUT_ADDR;
 564         else if (IS_QLA81XX(ha))
 565                 *start = FA_FLASH_LAYOUT_ADDR_81;
 566         /* Begin with first PCI expansion ROM header. */
 567         buf = (uint8_t *)req->ring;
 568         dcode = (uint32_t *)req->ring;
 569         pcihdr = 0;
 570         last_image = 1;
 571         do {
 572                 /* Verify PCI expansion ROM header. */
 573                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
 574                 bcode = buf + (pcihdr % 4);
 575                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
 576                         goto end;
 577
 578                 /* Locate PCI data structure. */
 579                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
 580                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
 581                 bcode = buf + (pcihdr % 4);
 582
 583                 /* Validate signature of PCI data structure. */
 584                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
 585                     bcode[0x2] != 'I' || bcode[0x3] != 'R')
 586                         goto end;
 587
 588                 last_image = bcode[0x15] & BIT_7;
 589
 590                 /* Locate next PCI expansion ROM. */
 591                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
 592         } while (!last_image);
 593
 594         /* Now verify FLT-location structure. */
 595         fltl = (struct qla_flt_location *)req->ring;
 596         qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
 597             sizeof(struct qla_flt_location) >> 2);
 598         if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
 599             fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
 600                 goto end;
 601
 602         wptr = (uint16_t *)req->ring;
 603         cnt = sizeof(struct qla_flt_location) >> 1;
 604         for (chksum = 0; cnt; cnt--)
 605                 chksum += le16_to_cpu(*wptr++);
 606         if (chksum) {
 607                 qla_printk(KERN_ERR, ha,
 608                     "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
 609                 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
 610                 return QLA_FUNCTION_FAILED;
 611         }
 612
 613         /* Good data.  Use specified location. */
 614         loc = locations[1];
 615         *start = le16_to_cpu(fltl->start_hi) << 16 |
 616             le16_to_cpu(fltl->start_lo);
 617 end:
 618         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
 619         return QLA_SUCCESS;
 620 }
 621
 622 static void
 623 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
 624 {
 625         const char *loc, *locations[] = { "DEF", "FLT" };
 626         const uint32_t def_fw[] =
 627                 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
 628         const uint32_t def_boot[] =
 629                 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
 630         const uint32_t def_vpd_nvram[] =
 631                 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
 632         const uint32_t def_fdt[] =
 633                 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
 634                         FA_FLASH_DESCR_ADDR_81 };
 635         const uint32_t def_npiv_conf0[] =
 636                 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
 637                         FA_NPIV_CONF0_ADDR_81 };
 638         const uint32_t def_npiv_conf1[] =
 639                 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
 640                         FA_NPIV_CONF1_ADDR_81 };
 641         uint32_t def;
 642         uint16_t *wptr;
 643         uint16_t cnt, chksum;
 644         uint32_t start;
 645         struct qla_flt_header *flt;
 646         struct qla_flt_region *region;
 647         struct qla_hw_data *ha = vha->hw;
 648         struct req_que *req = ha->req_q_map[0];
 649
 650         ha->flt_region_flt = flt_addr;
 651         wptr = (uint16_t *)req->ring;
 652         flt = (struct qla_flt_header *)req->ring;
 653         region = (struct qla_flt_region *)&flt[1];
 654         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 655             flt_addr << 2, OPTROM_BURST_SIZE);
 656         if (*wptr == __constant_cpu_to_le16(0xffff))
 657                 goto no_flash_data;
 658         if (flt->version != __constant_cpu_to_le16(1)) {
 659                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
 660                     "version=0x%x length=0x%x checksum=0x%x.\n",
 661                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 662                     le16_to_cpu(flt->checksum)));
 663                 goto no_flash_data;
 664         }
 665
 666         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
 667         for (chksum = 0; cnt; cnt--)
 668                 chksum += le16_to_cpu(*wptr++);
 669         if (chksum) {
 670                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
 671                     "version=0x%x length=0x%x checksum=0x%x.\n",
 672                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 673                     chksum));
 674                 goto no_flash_data;
 675         }
 676
 677         loc = locations[1];
 678         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
 679         for ( ; cnt; cnt--, region++) {
 680                 /* Store addresses as DWORD offsets. */
 681                 start = le32_to_cpu(region->start) >> 2;
 682
 683                 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
 684                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
 685                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
 686
 687                 switch (le32_to_cpu(region->code) & 0xff) {
 688                 case FLT_REG_FW:
 689                         ha->flt_region_fw = start;
 690                         break;
 691                 case FLT_REG_BOOT_CODE:
 692                         ha->flt_region_boot = start;
 693                         break;
 694                 case FLT_REG_VPD_0:
 695                         ha->flt_region_vpd_nvram = start;
 696                         break;
 697                 case FLT_REG_FDT:
 698                         ha->flt_region_fdt = start;
 699                         break;
 700                 case FLT_REG_NPIV_CONF_0:
 701                         if (!(PCI_FUNC(ha->pdev->devfn) & 1))
 702                                 ha->flt_region_npiv_conf = start;
 703                         break;
 704                 case FLT_REG_NPIV_CONF_1:
 705                         if (PCI_FUNC(ha->pdev->devfn) & 1)
 706                                 ha->flt_region_npiv_conf = start;
 707                         break;
 708                 }
 709         }
 710         goto done;
 711
 712 no_flash_data:
 713         /* Use hardcoded defaults. */
 714         loc = locations[0];
 715         def = 0;
 716         if (IS_QLA24XX_TYPE(ha))
 717                 def = 0;
 718         else if (IS_QLA25XX(ha))
 719                 def = 1;
 720         else if (IS_QLA81XX(ha))
 721                 def = 2;
 722         ha->flt_region_fw = def_fw[def];
 723         ha->flt_region_boot = def_boot[def];
 724         ha->flt_region_vpd_nvram = def_vpd_nvram[def];
 725         ha->flt_region_fdt = def_fdt[def];
 726         ha->flt_region_npiv_conf = !(PCI_FUNC(ha->pdev->devfn) & 1) ?
 727             def_npiv_conf0[def]: def_npiv_conf1[def];
 728 done:
 729         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
 730             "vpd_nvram=0x%x fdt=0x%x flt=0x%x npiv=0x%x.\n", loc,
 731             ha->flt_region_boot, ha->flt_region_fw, ha->flt_region_vpd_nvram,
 732             ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
 733 }
 734
 735 static void
 736 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
 737 {
 738 #define FLASH_BLK_SIZE_4K       0x1000
 739 #define FLASH_BLK_SIZE_32K      0x8000
 740 #define FLASH_BLK_SIZE_64K      0x10000
 741         const char *loc, *locations[] = { "MID", "FDT" };
 742         uint16_t cnt, chksum;
 743         uint16_t *wptr;
 744         struct qla_fdt_layout *fdt;
 745         uint8_t man_id, flash_id;
 746         uint16_t mid, fid;
 747         struct qla_hw_data *ha = vha->hw;
 748         struct req_que *req = ha->req_q_map[0];
 749
 750         wptr = (uint16_t *)req->ring;
 751         fdt = (struct qla_fdt_layout *)req->ring;
 752         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 753             ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
 754         if (*wptr == __constant_cpu_to_le16(0xffff))
 755                 goto no_flash_data;
 756         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
 757             fdt->sig[3] != 'D')
 758                 goto no_flash_data;
 759
 760         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
 761             cnt++)
 762                 chksum += le16_to_cpu(*wptr++);
 763         if (chksum) {
 764                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
 765                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
 766                     le16_to_cpu(fdt->version)));
 767                 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
 768                 goto no_flash_data;
 769         }
 770
 771         loc = locations[1];
 772         mid = le16_to_cpu(fdt->man_id);
 773         fid = le16_to_cpu(fdt->id);
 774         ha->fdt_wrt_disable = fdt->wrt_disable_bits;
 775         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
 776         ha->fdt_block_size = le32_to_cpu(fdt->block_size);
 777         if (fdt->unprotect_sec_cmd) {
 778                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
 779                     fdt->unprotect_sec_cmd);
 780                 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
 781                     flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
 782                     flash_conf_addr(ha, 0x0336);
 783         }
 784         goto done;
 785 no_flash_data:
 786         loc = locations[0];
 787         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 788         mid = man_id;
 789         fid = flash_id;
 790         ha->fdt_wrt_disable = 0x9c;
 791         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
 792         switch (man_id) {
 793         case 0xbf: /* STT flash. */
 794                 if (flash_id == 0x8e)
 795                         ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 796                 else
 797                         ha->fdt_block_size = FLASH_BLK_SIZE_32K;
 798
 799                 if (flash_id == 0x80)
 800                         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
 801                 break;
 802         case 0x13: /* ST M25P80. */
 803                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 804                 break;
 805         case 0x1f: /* Atmel 26DF081A. */
 806                 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
 807                 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
 808                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
 809                 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
 810                 break;
 811         default:
 812                 /* Default to 64 kb sector size. */
 813                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 814                 break;
 815         }
 816 done:
 817         DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
 818             "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
 819             ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
 820             ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
 821             ha->fdt_block_size));
 822 }
 823
 824 int
 825 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
 826 {
 827         int ret;
 828         uint32_t flt_addr;
 829         struct qla_hw_data *ha = vha->hw;
 830
 831         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
 832                 return QLA_SUCCESS;
 833
 834         ret = qla2xxx_find_flt_start(vha, &flt_addr);
 835         if (ret != QLA_SUCCESS)
 836                 return ret;
 837
 838         qla2xxx_get_flt_info(vha, flt_addr);
 839         qla2xxx_get_fdt_info(vha);
 840
 841         return QLA_SUCCESS;
 842 }
 843
 844 void
 845 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
 846 {
 847 #define NPIV_CONFIG_SIZE        (16*1024)
 848         void *data;
 849         uint16_t *wptr;
 850         uint16_t cnt, chksum;
 851         int i;
 852         struct qla_npiv_header hdr;
 853         struct qla_npiv_entry *entry;
 854         struct qla_hw_data *ha = vha->hw;
 855
 856         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
 857                 return;
 858
 859         ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
 860             ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
 861         if (hdr.version == __constant_cpu_to_le16(0xffff))
 862                 return;
 863         if (hdr.version != __constant_cpu_to_le16(1)) {
 864                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
 865                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
 866                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
 867                     le16_to_cpu(hdr.checksum)));
 868                 return;
 869         }
 870
 871         data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
 872         if (!data) {
 873                 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
 874                     "allocate memory.\n"));
 875                 return;
 876         }
 877
 878         ha->isp_ops->read_optrom(vha, (uint8_t *)data,
 879             ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
 880
 881         cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
 882             sizeof(struct qla_npiv_entry)) >> 1;
 883         for (wptr = data, chksum = 0; cnt; cnt--)
 884                 chksum += le16_to_cpu(*wptr++);
 885         if (chksum) {
 886                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
 887                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
 888                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
 889                     chksum));
 890                 goto done;
 891         }
 892
 893         entry = data + sizeof(struct qla_npiv_header);
 894         cnt = le16_to_cpu(hdr.entries);
 895         for (i = 0; cnt; cnt--, entry++, i++) {
 896                 uint16_t flags;
 897                 struct fc_vport_identifiers vid;
 898                 struct fc_vport *vport;
 899
 900                 flags = le16_to_cpu(entry->flags);
 901                 if (flags == 0xffff)
 902                         continue;
 903                 if ((flags & BIT_0) == 0)
 904                         continue;
 905
 906                 memset(&vid, 0, sizeof(vid));
 907                 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
 908                 vid.vport_type = FC_PORTTYPE_NPIV;
 909                 vid.disable = false;
 910                 vid.port_name = wwn_to_u64(entry->port_name);
 911                 vid.node_name = wwn_to_u64(entry->node_name);
 912
 913                 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
 914
 915                 DEBUG2(qla_printk(KERN_DEBUG, ha, "NPIV[%02x]: wwpn=%llx "
 916                         "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
 917                         vid.port_name, vid.node_name, le16_to_cpu(entry->vf_id),
 918                         entry->q_qos, entry->f_qos));
 919
 920                 if (i < QLA_PRECONFIG_VPORTS) {
 921                         vport = fc_vport_create(vha->host, 0, &vid);
 922                         if (!vport)
 923                                 qla_printk(KERN_INFO, ha,
 924                                 "NPIV-Config: Failed to create vport [%02x]: "
 925                                 "wwpn=%llx wwnn=%llx.\n", cnt,
 926                                 vid.port_name, vid.node_name);
 927                 }
 928         }
 929 done:
 930         kfree(data);
 931         ha->npiv_info = NULL;
 932 }
 933
 934 static int
 935 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
 936 {
 937         struct qla_hw_data *ha = vha->hw;
 938         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 939
 940         if (ha->flags.fac_supported)
 941                 return qla81xx_fac_do_write_enable(vha, 1);
 942
 943         /* Enable flash write. */
 944         WRT_REG_DWORD(&reg->ctrl_status,
 945             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 946         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 947
 948         if (!ha->fdt_wrt_disable)
 949                 goto done;
 950
 951         /* Disable flash write-protection, first clear SR protection bit */
 952         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
 953         /* Then write zero again to clear remaining SR bits.*/
 954         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
 955 done:
 956         return QLA_SUCCESS;
 957 }
 958
 959 static int
 960 qla24xx_protect_flash(scsi_qla_host_t *vha)
 961 {
 962         uint32_t cnt;
 963         struct qla_hw_data *ha = vha->hw;
 964         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 965
 966         if (ha->flags.fac_supported)
 967                 return qla81xx_fac_do_write_enable(vha, 0);
 968
 969         if (!ha->fdt_wrt_disable)
 970                 goto skip_wrt_protect;
 971
 972         /* Enable flash write-protection and wait for completion. */
 973         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
 974             ha->fdt_wrt_disable);
 975         for (cnt = 300; cnt &&
 976             qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
 977             cnt--) {
 978                 udelay(10);
 979         }
 980
 981 skip_wrt_protect:
 982         /* Disable flash write. */
 983         WRT_REG_DWORD(&reg->ctrl_status,
 984             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
 985         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 986
 987         return QLA_SUCCESS;
 988 }
 989
 990 static int
 991 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
 992 {
 993         struct qla_hw_data *ha = vha->hw;
 994         uint32_t start, finish;
 995
 996         if (ha->flags.fac_supported) {
 997                 start = fdata >> 2;
 998                 finish = start + (ha->fdt_block_size >> 2) - 1;
 999                 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1000                     start), flash_data_addr(ha, finish));
1001         }
1002
1003         return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1004             (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1005             ((fdata >> 16) & 0xff));
1006 }
1007
1008 static int
1009 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1010     uint32_t dwords)
1011 {
1012         int ret;
1013         uint32_t liter;
1014         uint32_t sec_mask, rest_addr;
1015         uint32_t fdata;
1016         dma_addr_t optrom_dma;
1017         void *optrom = NULL;
1018         struct qla_hw_data *ha = vha->hw;
1019
1020         /* Prepare burst-capable write on supported ISPs. */
1021         if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
1022             dwords > OPTROM_BURST_DWORDS) {
1023                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1024                     &optrom_dma, GFP_KERNEL);
1025                 if (!optrom) {
1026                         qla_printk(KERN_DEBUG, ha,
1027                             "Unable to allocate memory for optrom burst write "
1028                             "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1029                 }
1030         }
1031
1032         rest_addr = (ha->fdt_block_size >> 2) - 1;
1033         sec_mask = ~rest_addr;
1034
1035         ret = qla24xx_unprotect_flash(vha);
1036         if (ret != QLA_SUCCESS) {
1037                 qla_printk(KERN_WARNING, ha,
1038                     "Unable to unprotect flash for update.\n");
1039                 goto done;
1040         }
1041
1042         for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1043                 fdata = (faddr & sec_mask) << 2;
1044
1045                 /* Are we at the beginning of a sector? */
1046                 if ((faddr & rest_addr) == 0) {
1047                         /* Do sector unprotect. */
1048                         if (ha->fdt_unprotect_sec_cmd)
1049                                 qla24xx_write_flash_dword(ha,
1050                                     ha->fdt_unprotect_sec_cmd,
1051                                     (fdata & 0xff00) | ((fdata << 16) &
1052                                     0xff0000) | ((fdata >> 16) & 0xff));
1053                         ret = qla24xx_erase_sector(vha, fdata);
1054                         if (ret != QLA_SUCCESS) {
1055                                 DEBUG9(qla_printk("Unable to erase sector: "
1056                                     "address=%x.\n", faddr));
1057                                 break;
1058                         }
1059                 }
1060
1061                 /* Go with burst-write. */
1062                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1063                         /* Copy data to DMA'ble buffer. */
1064                         memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1065
1066                         ret = qla2x00_load_ram(vha, optrom_dma,
1067                             flash_data_addr(ha, faddr),
1068                             OPTROM_BURST_DWORDS);
1069                         if (ret != QLA_SUCCESS) {
1070                                 qla_printk(KERN_WARNING, ha,
1071                                     "Unable to burst-write optrom segment "
1072                                     "(%x/%x/%llx).\n", ret,
1073                                     flash_data_addr(ha, faddr),
1074                                     (unsigned long long)optrom_dma);
1075                                 qla_printk(KERN_WARNING, ha,
1076                                     "Reverting to slow-write.\n");
1077
1078                                 dma_free_coherent(&ha->pdev->dev,
1079                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1080                                 optrom = NULL;
1081                         } else {
1082                                 liter += OPTROM_BURST_DWORDS - 1;
1083                                 faddr += OPTROM_BURST_DWORDS - 1;
1084                                 dwptr += OPTROM_BURST_DWORDS - 1;
1085                                 continue;
1086                         }
1087                 }
1088
1089                 ret = qla24xx_write_flash_dword(ha,
1090                     flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1091                 if (ret != QLA_SUCCESS) {
1092                         DEBUG9(printk("%s(%ld) Unable to program flash "
1093                             "address=%x data=%x.\n", __func__,
1094                             vha->host_no, faddr, *dwptr));
1095                         break;
1096                 }
1097
1098                 /* Do sector protect. */
1099                 if (ha->fdt_unprotect_sec_cmd &&
1100                     ((faddr & rest_addr) == rest_addr))
1101                         qla24xx_write_flash_dword(ha,
1102                             ha->fdt_protect_sec_cmd,
1103                             (fdata & 0xff00) | ((fdata << 16) &
1104                             0xff0000) | ((fdata >> 16) & 0xff));
1105         }
1106
1107         ret = qla24xx_protect_flash(vha);
1108         if (ret != QLA_SUCCESS)
1109                 qla_printk(KERN_WARNING, ha,
1110                     "Unable to protect flash after update.\n");
1111 done:
1112         if (optrom)
1113                 dma_free_coherent(&ha->pdev->dev,
1114                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1115
1116         return ret;
1117 }
1118
1119 uint8_t *
1120 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1121     uint32_t bytes)
1122 {
1123         uint32_t i;
1124         uint16_t *wptr;
1125         struct qla_hw_data *ha = vha->hw;
1126
1127         /* Word reads to NVRAM via registers. */
1128         wptr = (uint16_t *)buf;
1129         qla2x00_lock_nvram_access(ha);
1130         for (i = 0; i < bytes >> 1; i++, naddr++)
1131                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1132                     naddr));
1133         qla2x00_unlock_nvram_access(ha);
1134
1135         return buf;
1136 }
1137
1138 uint8_t *
1139 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1140     uint32_t bytes)
1141 {
1142         uint32_t i;
1143         uint32_t *dwptr;
1144         struct qla_hw_data *ha = vha->hw;
1145
1146         /* Dword reads to flash. */
1147         dwptr = (uint32_t *)buf;
1148         for (i = 0; i < bytes >> 2; i++, naddr++)
1149                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1150                     nvram_data_addr(ha, naddr)));
1151
1152         return buf;
1153 }
1154
1155 int
1156 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1157     uint32_t bytes)
1158 {
1159         int ret, stat;
1160         uint32_t i;
1161         uint16_t *wptr;
1162         unsigned long flags;
1163         struct qla_hw_data *ha = vha->hw;
1164
1165         ret = QLA_SUCCESS;
1166
1167         spin_lock_irqsave(&ha->hardware_lock, flags);
1168         qla2x00_lock_nvram_access(ha);
1169
1170         /* Disable NVRAM write-protection. */
1171         stat = qla2x00_clear_nvram_protection(ha);
1172
1173         wptr = (uint16_t *)buf;
1174         for (i = 0; i < bytes >> 1; i++, naddr++) {
1175                 qla2x00_write_nvram_word(ha, naddr,
1176                     cpu_to_le16(*wptr));
1177                 wptr++;
1178         }
1179
1180         /* Enable NVRAM write-protection. */
1181         qla2x00_set_nvram_protection(ha, stat);
1182
1183         qla2x00_unlock_nvram_access(ha);
1184         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1185
1186         return ret;
1187 }
1188
1189 int
1190 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1191     uint32_t bytes)
1192 {
1193         int ret;
1194         uint32_t i;
1195         uint32_t *dwptr;
1196         struct qla_hw_data *ha = vha->hw;
1197         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1198
1199         ret = QLA_SUCCESS;
1200
1201         /* Enable flash write. */
1202         WRT_REG_DWORD(&reg->ctrl_status,
1203             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1204         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1205
1206         /* Disable NVRAM write-protection. */
1207         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1208         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1209
1210         /* Dword writes to flash. */
1211         dwptr = (uint32_t *)buf;
1212         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1213                 ret = qla24xx_write_flash_dword(ha,
1214                     nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1215                 if (ret != QLA_SUCCESS) {
1216                         DEBUG9(qla_printk("Unable to program nvram address=%x "
1217                             "data=%x.\n", naddr, *dwptr));
1218                         break;
1219                 }
1220         }
1221
1222         /* Enable NVRAM write-protection. */
1223         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1224
1225         /* Disable flash write. */
1226         WRT_REG_DWORD(&reg->ctrl_status,
1227             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1228         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1229
1230         return ret;
1231 }
1232
1233 uint8_t *
1234 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1235     uint32_t bytes)
1236 {
1237         uint32_t i;
1238         uint32_t *dwptr;
1239         struct qla_hw_data *ha = vha->hw;
1240
1241         /* Dword reads to flash. */
1242         dwptr = (uint32_t *)buf;
1243         for (i = 0; i < bytes >> 2; i++, naddr++)
1244                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1245                     flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1246
1247         return buf;
1248 }
1249
1250 int
1251 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1252     uint32_t bytes)
1253 {
1254         struct qla_hw_data *ha = vha->hw;
1255 #define RMW_BUFFER_SIZE (64 * 1024)
1256         uint8_t *dbuf;
1257
1258         dbuf = vmalloc(RMW_BUFFER_SIZE);
1259         if (!dbuf)
1260                 return QLA_MEMORY_ALLOC_FAILED;
1261         ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1262             RMW_BUFFER_SIZE);
1263         memcpy(dbuf + (naddr << 2), buf, bytes);
1264         ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1265             RMW_BUFFER_SIZE);
1266         vfree(dbuf);
1267
1268         return QLA_SUCCESS;
1269 }
1270
1271 static inline void
1272 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1273 {
1274         if (IS_QLA2322(ha)) {
1275                 /* Flip all colors. */
1276                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1277                         /* Turn off. */
1278                         ha->beacon_color_state = 0;
1279                         *pflags = GPIO_LED_ALL_OFF;
1280                 } else {
1281                         /* Turn on. */
1282                         ha->beacon_color_state = QLA_LED_ALL_ON;
1283                         *pflags = GPIO_LED_RGA_ON;
1284                 }
1285         } else {
1286                 /* Flip green led only. */
1287                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1288                         /* Turn off. */
1289                         ha->beacon_color_state = 0;
1290                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1291                 } else {
1292                         /* Turn on. */
1293                         ha->beacon_color_state = QLA_LED_GRN_ON;
1294                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1295                 }
1296         }
1297 }
1298
1299 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1300
1301 void
1302 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1303 {
1304         uint16_t gpio_enable;
1305         uint16_t gpio_data;
1306         uint16_t led_color = 0;
1307         unsigned long flags;
1308         struct qla_hw_data *ha = vha->hw;
1309         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1310
1311         spin_lock_irqsave(&ha->hardware_lock, flags);
1312
1313         /* Save the Original GPIOE. */
1314         if (ha->pio_address) {
1315                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1316                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1317         } else {
1318                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1319                 gpio_data = RD_REG_WORD(&reg->gpiod);
1320         }
1321
1322         /* Set the modified gpio_enable values */
1323         gpio_enable |= GPIO_LED_MASK;
1324
1325         if (ha->pio_address) {
1326                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1327         } else {
1328                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1329                 RD_REG_WORD(&reg->gpioe);
1330         }
1331
1332         qla2x00_flip_colors(ha, &led_color);
1333
1334         /* Clear out any previously set LED color. */
1335         gpio_data &= ~GPIO_LED_MASK;
1336
1337         /* Set the new input LED color to GPIOD. */
1338         gpio_data |= led_color;
1339
1340         /* Set the modified gpio_data values */
1341         if (ha->pio_address) {
1342                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1343         } else {
1344                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1345                 RD_REG_WORD(&reg->gpiod);
1346         }
1347
1348         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1349 }
1350
1351 int
1352 qla2x00_beacon_on(struct scsi_qla_host *vha)
1353 {
1354         uint16_t gpio_enable;
1355         uint16_t gpio_data;
1356         unsigned long flags;
1357         struct qla_hw_data *ha = vha->hw;
1358         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1359
1360         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1361         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1362
1363         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1364                 qla_printk(KERN_WARNING, ha,
1365                     "Unable to update fw options (beacon on).\n");
1366                 return QLA_FUNCTION_FAILED;
1367         }
1368
1369         /* Turn off LEDs. */
1370         spin_lock_irqsave(&ha->hardware_lock, flags);
1371         if (ha->pio_address) {
1372                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1373                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1374         } else {
1375                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1376                 gpio_data = RD_REG_WORD(&reg->gpiod);
1377         }
1378         gpio_enable |= GPIO_LED_MASK;
1379
1380         /* Set the modified gpio_enable values. */
1381         if (ha->pio_address) {
1382                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1383         } else {
1384                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1385                 RD_REG_WORD(&reg->gpioe);
1386         }
1387
1388         /* Clear out previously set LED colour. */
1389         gpio_data &= ~GPIO_LED_MASK;
1390         if (ha->pio_address) {
1391                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1392         } else {
1393                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1394                 RD_REG_WORD(&reg->gpiod);
1395         }
1396         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1397
1398         /*
1399          * Let the per HBA timer kick off the blinking process based on
1400          * the following flags. No need to do anything else now.
1401          */
1402         ha->beacon_blink_led = 1;
1403         ha->beacon_color_state = 0;
1404
1405         return QLA_SUCCESS;
1406 }
1407
1408 int
1409 qla2x00_beacon_off(struct scsi_qla_host *vha)
1410 {
1411         int rval = QLA_SUCCESS;
1412         struct qla_hw_data *ha = vha->hw;
1413
1414         ha->beacon_blink_led = 0;
1415
1416         /* Set the on flag so when it gets flipped it will be off. */
1417         if (IS_QLA2322(ha))
1418                 ha->beacon_color_state = QLA_LED_ALL_ON;
1419         else
1420                 ha->beacon_color_state = QLA_LED_GRN_ON;
1421
1422         ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1423
1424         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1425         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1426
1427         rval = qla2x00_set_fw_options(vha, ha->fw_options);
1428         if (rval != QLA_SUCCESS)
1429                 qla_printk(KERN_WARNING, ha,
1430                     "Unable to update fw options (beacon off).\n");
1431         return rval;
1432 }
1433
1434
1435 static inline void
1436 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1437 {
1438         /* Flip all colors. */
1439         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1440                 /* Turn off. */
1441                 ha->beacon_color_state = 0;
1442                 *pflags = 0;
1443         } else {
1444                 /* Turn on. */
1445                 ha->beacon_color_state = QLA_LED_ALL_ON;
1446                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1447         }
1448 }
1449
1450 void
1451 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1452 {
1453         uint16_t led_color = 0;
1454         uint32_t gpio_data;
1455         unsigned long flags;
1456         struct qla_hw_data *ha = vha->hw;
1457         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1458
1459         /* Save the Original GPIOD. */
1460         spin_lock_irqsave(&ha->hardware_lock, flags);
1461         gpio_data = RD_REG_DWORD(&reg->gpiod);
1462
1463         /* Enable the gpio_data reg for update. */
1464         gpio_data |= GPDX_LED_UPDATE_MASK;
1465
1466         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1467         gpio_data = RD_REG_DWORD(&reg->gpiod);
1468
1469         /* Set the color bits. */
1470         qla24xx_flip_colors(ha, &led_color);
1471
1472         /* Clear out any previously set LED color. */
1473         gpio_data &= ~GPDX_LED_COLOR_MASK;
1474
1475         /* Set the new input LED color to GPIOD. */
1476         gpio_data |= led_color;
1477
1478         /* Set the modified gpio_data values. */
1479         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1480         gpio_data = RD_REG_DWORD(&reg->gpiod);
1481         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1482 }
1483
1484 int
1485 qla24xx_beacon_on(struct scsi_qla_host *vha)
1486 {
1487         uint32_t gpio_data;
1488         unsigned long flags;
1489         struct qla_hw_data *ha = vha->hw;
1490         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1491
1492         if (ha->beacon_blink_led == 0) {
1493                 /* Enable firmware for update */
1494                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1495
1496                 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1497                         return QLA_FUNCTION_FAILED;
1498
1499                 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1500                     QLA_SUCCESS) {
1501                         qla_printk(KERN_WARNING, ha,
1502                             "Unable to update fw options (beacon on).\n");
1503                         return QLA_FUNCTION_FAILED;
1504                 }
1505
1506                 spin_lock_irqsave(&ha->hardware_lock, flags);
1507                 gpio_data = RD_REG_DWORD(&reg->gpiod);
1508
1509                 /* Enable the gpio_data reg for update. */
1510                 gpio_data |= GPDX_LED_UPDATE_MASK;
1511                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1512                 RD_REG_DWORD(&reg->gpiod);
1513
1514                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1515         }
1516
1517         /* So all colors blink together. */
1518         ha->beacon_color_state = 0;
1519
1520         /* Let the per HBA timer kick off the blinking process. */
1521         ha->beacon_blink_led = 1;
1522
1523         return QLA_SUCCESS;
1524 }
1525
1526 int
1527 qla24xx_beacon_off(struct scsi_qla_host *vha)
1528 {
1529         uint32_t gpio_data;
1530         unsigned long flags;
1531         struct qla_hw_data *ha = vha->hw;
1532         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1533
1534         ha->beacon_blink_led = 0;
1535         ha->beacon_color_state = QLA_LED_ALL_ON;
1536
1537         ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1538
1539         /* Give control back to firmware. */
1540         spin_lock_irqsave(&ha->hardware_lock, flags);
1541         gpio_data = RD_REG_DWORD(&reg->gpiod);
1542
1543         /* Disable the gpio_data reg for update. */
1544         gpio_data &= ~GPDX_LED_UPDATE_MASK;
1545         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1546         RD_REG_DWORD(&reg->gpiod);
1547         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1548
1549         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1550
1551         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1552                 qla_printk(KERN_WARNING, ha,
1553                     "Unable to update fw options (beacon off).\n");
1554                 return QLA_FUNCTION_FAILED;
1555         }
1556
1557         if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1558                 qla_printk(KERN_WARNING, ha,
1559                     "Unable to get fw options (beacon off).\n");
1560                 return QLA_FUNCTION_FAILED;
1561         }
1562
1563         return QLA_SUCCESS;
1564 }
1565
1566
1567 /*
1568  * Flash support routines
1569  */
1570
1571 /**
1572  * qla2x00_flash_enable() - Setup flash for reading and writing.
1573  * @ha: HA context
1574  */
1575 static void
1576 qla2x00_flash_enable(struct qla_hw_data *ha)
1577 {
1578         uint16_t data;
1579         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1580
1581         data = RD_REG_WORD(&reg->ctrl_status);
1582         data |= CSR_FLASH_ENABLE;
1583         WRT_REG_WORD(&reg->ctrl_status, data);
1584         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1585 }
1586
1587 /**
1588  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1589  * @ha: HA context
1590  */
1591 static void
1592 qla2x00_flash_disable(struct qla_hw_data *ha)
1593 {
1594         uint16_t data;
1595         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1596
1597         data = RD_REG_WORD(&reg->ctrl_status);
1598         data &= ~(CSR_FLASH_ENABLE);
1599         WRT_REG_WORD(&reg->ctrl_status, data);
1600         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1601 }
1602
1603 /**
1604  * qla2x00_read_flash_byte() - Reads a byte from flash
1605  * @ha: HA context
1606  * @addr: Address in flash to read
1607  *
1608  * A word is read from the chip, but, only the lower byte is valid.
1609  *
1610  * Returns the byte read from flash @addr.
1611  */
1612 static uint8_t
1613 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1614 {
1615         uint16_t data;
1616         uint16_t bank_select;
1617         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1618
1619         bank_select = RD_REG_WORD(&reg->ctrl_status);
1620
1621         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1622                 /* Specify 64K address range: */
1623                 /*  clear out Module Select and Flash Address bits [19:16]. */
1624                 bank_select &= ~0xf8;
1625                 bank_select |= addr >> 12 & 0xf0;
1626                 bank_select |= CSR_FLASH_64K_BANK;
1627                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1628                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1629
1630                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1631                 data = RD_REG_WORD(&reg->flash_data);
1632
1633                 return (uint8_t)data;
1634         }
1635
1636         /* Setup bit 16 of flash address. */
1637         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1638                 bank_select |= CSR_FLASH_64K_BANK;
1639                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1640                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1641         } else if (((addr & BIT_16) == 0) &&
1642             (bank_select & CSR_FLASH_64K_BANK)) {
1643                 bank_select &= ~(CSR_FLASH_64K_BANK);
1644                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1645                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1646         }
1647
1648         /* Always perform IO mapped accesses to the FLASH registers. */
1649         if (ha->pio_address) {
1650                 uint16_t data2;
1651
1652                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1653                 do {
1654                         data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1655                         barrier();
1656                         cpu_relax();
1657                         data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1658                 } while (data != data2);
1659         } else {
1660                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1661                 data = qla2x00_debounce_register(&reg->flash_data);
1662         }
1663
1664         return (uint8_t)data;
1665 }
1666
1667 /**
1668  * qla2x00_write_flash_byte() - Write a byte to flash
1669  * @ha: HA context
1670  * @addr: Address in flash to write
1671  * @data: Data to write
1672  */
1673 static void
1674 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1675 {
1676         uint16_t bank_select;
1677         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1678
1679         bank_select = RD_REG_WORD(&reg->ctrl_status);
1680         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1681                 /* Specify 64K address range: */
1682                 /*  clear out Module Select and Flash Address bits [19:16]. */
1683                 bank_select &= ~0xf8;
1684                 bank_select |= addr >> 12 & 0xf0;
1685                 bank_select |= CSR_FLASH_64K_BANK;
1686                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1687                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1688
1689                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1690                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1691                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1692                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1693
1694                 return;
1695         }
1696
1697         /* Setup bit 16 of flash address. */
1698         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1699                 bank_select |= CSR_FLASH_64K_BANK;
1700                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1701                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1702         } else if (((addr & BIT_16) == 0) &&
1703             (bank_select & CSR_FLASH_64K_BANK)) {
1704                 bank_select &= ~(CSR_FLASH_64K_BANK);
1705                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1706                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1707         }
1708
1709         /* Always perform IO mapped accesses to the FLASH registers. */
1710         if (ha->pio_address) {
1711                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1712                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1713         } else {
1714                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1715                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1716                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1717                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1718         }
1719 }
1720
1721 /**
1722  * qla2x00_poll_flash() - Polls flash for completion.
1723  * @ha: HA context
1724  * @addr: Address in flash to poll
1725  * @poll_data: Data to be polled
1726  * @man_id: Flash manufacturer ID
1727  * @flash_id: Flash ID
1728  *
1729  * This function polls the device until bit 7 of what is read matches data
1730  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
1731  * out (a fatal error).  The flash book recommeds reading bit 7 again after
1732  * reading bit 5 as a 1.
1733  *
1734  * Returns 0 on success, else non-zero.
1735  */
1736 static int
1737 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
1738     uint8_t man_id, uint8_t flash_id)
1739 {
1740         int status;
1741         uint8_t flash_data;
1742         uint32_t cnt;
1743
1744         status = 1;
1745
1746         /* Wait for 30 seconds for command to finish. */
1747         poll_data &= BIT_7;
1748         for (cnt = 3000000; cnt; cnt--) {
1749                 flash_data = qla2x00_read_flash_byte(ha, addr);
1750                 if ((flash_data & BIT_7) == poll_data) {
1751                         status = 0;
1752                         break;
1753                 }
1754
1755                 if (man_id != 0x40 && man_id != 0xda) {
1756                         if ((flash_data & BIT_5) && cnt > 2)
1757                                 cnt = 2;
1758                 }
1759                 udelay(10);
1760                 barrier();
1761                 cond_resched();
1762         }
1763         return status;
1764 }
1765
1766 /**
1767  * qla2x00_program_flash_address() - Programs a flash address
1768  * @ha: HA context
1769  * @addr: Address in flash to program
1770  * @data: Data to be written in flash
1771  * @man_id: Flash manufacturer ID
1772  * @flash_id: Flash ID
1773  *
1774  * Returns 0 on success, else non-zero.
1775  */
1776 static int
1777 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1778     uint8_t data, uint8_t man_id, uint8_t flash_id)
1779 {
1780         /* Write Program Command Sequence. */
1781         if (IS_OEM_001(ha)) {
1782                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1783                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1784                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1785                 qla2x00_write_flash_byte(ha, addr, data);
1786         } else {
1787                 if (man_id == 0xda && flash_id == 0xc1) {
1788                         qla2x00_write_flash_byte(ha, addr, data);
1789                         if (addr & 0x7e)
1790                                 return 0;
1791                 } else {
1792                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1793                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1794                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1795                         qla2x00_write_flash_byte(ha, addr, data);
1796                 }
1797         }
1798
1799         udelay(150);
1800
1801         /* Wait for write to complete. */
1802         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1803 }
1804
1805 /**
1806  * qla2x00_erase_flash() - Erase the flash.
1807  * @ha: HA context
1808  * @man_id: Flash manufacturer ID
1809  * @flash_id: Flash ID
1810  *
1811  * Returns 0 on success, else non-zero.
1812  */
1813 static int
1814 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
1815 {
1816         /* Individual Sector Erase Command Sequence */
1817         if (IS_OEM_001(ha)) {
1818                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1819                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1820                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1821                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1822                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1823                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1824         } else {
1825                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1826                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1827                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1828                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1829                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1830                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1831         }
1832
1833         udelay(150);
1834
1835         /* Wait for erase to complete. */
1836         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1837 }
1838
1839 /**
1840  * qla2x00_erase_flash_sector() - Erase a flash sector.
1841  * @ha: HA context
1842  * @addr: Flash sector to erase
1843  * @sec_mask: Sector address mask
1844  * @man_id: Flash manufacturer ID
1845  * @flash_id: Flash ID
1846  *
1847  * Returns 0 on success, else non-zero.
1848  */
1849 static int
1850 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
1851     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1852 {
1853         /* Individual Sector Erase Command Sequence */
1854         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1855         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1856         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1857         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1858         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1859         if (man_id == 0x1f && flash_id == 0x13)
1860                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1861         else
1862                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1863
1864         udelay(150);
1865
1866         /* Wait for erase to complete. */
1867         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1868 }
1869
1870 /**
1871  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1872  * @man_id: Flash manufacturer ID
1873  * @flash_id: Flash ID
1874  */
1875 static void
1876 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
1877     uint8_t *flash_id)
1878 {
1879         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1880         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1881         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1882         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1883         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1884         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1885         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1886         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1887 }
1888
1889 static void
1890 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1891         uint32_t saddr, uint32_t length)
1892 {
1893         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1894         uint32_t midpoint, ilength;
1895         uint8_t data;
1896
1897         midpoint = length / 2;
1898
1899         WRT_REG_WORD(&reg->nvram, 0);
1900         RD_REG_WORD(&reg->nvram);
1901         for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1902                 if (ilength == midpoint) {
1903                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1904                         RD_REG_WORD(&reg->nvram);
1905                 }
1906                 data = qla2x00_read_flash_byte(ha, saddr);
1907                 if (saddr % 100)
1908                         udelay(10);
1909                 *tmp_buf = data;
1910                 cond_resched();
1911         }
1912 }
1913
1914 static inline void
1915 qla2x00_suspend_hba(struct scsi_qla_host *vha)
1916 {
1917         int cnt;
1918         unsigned long flags;
1919         struct qla_hw_data *ha = vha->hw;
1920         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1921
1922         /* Suspend HBA. */
1923         scsi_block_requests(vha->host);
1924         ha->isp_ops->disable_intrs(ha);
1925         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1926
1927         /* Pause RISC. */
1928         spin_lock_irqsave(&ha->hardware_lock, flags);
1929         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1930         RD_REG_WORD(&reg->hccr);
1931         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1932                 for (cnt = 0; cnt < 30000; cnt++) {
1933                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1934                                 break;
1935                         udelay(100);
1936                 }
1937         } else {
1938                 udelay(10);
1939         }
1940         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1941 }
1942
1943 static inline void
1944 qla2x00_resume_hba(struct scsi_qla_host *vha)
1945 {
1946         struct qla_hw_data *ha = vha->hw;
1947
1948         /* Resume HBA. */
1949         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1950         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1951         qla2xxx_wake_dpc(vha);
1952         qla2x00_wait_for_chip_reset(vha);
1953         scsi_unblock_requests(vha->host);
1954 }
1955
1956 uint8_t *
1957 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1958     uint32_t offset, uint32_t length)
1959 {
1960         uint32_t addr, midpoint;
1961         uint8_t *data;
1962         struct qla_hw_data *ha = vha->hw;
1963         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1964
1965         /* Suspend HBA. */
1966         qla2x00_suspend_hba(vha);
1967
1968         /* Go with read. */
1969         midpoint = ha->optrom_size / 2;
1970
1971         qla2x00_flash_enable(ha);
1972         WRT_REG_WORD(&reg->nvram, 0);
1973         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
1974         for (addr = offset, data = buf; addr < length; addr++, data++) {
1975                 if (addr == midpoint) {
1976                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1977                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
1978                 }
1979
1980                 *data = qla2x00_read_flash_byte(ha, addr);
1981         }
1982         qla2x00_flash_disable(ha);
1983
1984         /* Resume HBA. */
1985         qla2x00_resume_hba(vha);
1986
1987         return buf;
1988 }
1989
1990 int
1991 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1992     uint32_t offset, uint32_t length)
1993 {
1994
1995         int rval;
1996         uint8_t man_id, flash_id, sec_number, data;
1997         uint16_t wd;
1998         uint32_t addr, liter, sec_mask, rest_addr;
1999         struct qla_hw_data *ha = vha->hw;
2000         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2001
2002         /* Suspend HBA. */
2003         qla2x00_suspend_hba(vha);
2004
2005         rval = QLA_SUCCESS;
2006         sec_number = 0;
2007
2008         /* Reset ISP chip. */
2009         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2010         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2011
2012         /* Go with write. */
2013         qla2x00_flash_enable(ha);
2014         do {    /* Loop once to provide quick error exit */
2015                 /* Structure of flash memory based on manufacturer */
2016                 if (IS_OEM_001(ha)) {
2017                         /* OEM variant with special flash part. */
2018                         man_id = flash_id = 0;
2019                         rest_addr = 0xffff;
2020                         sec_mask   = 0x10000;
2021                         goto update_flash;
2022                 }
2023                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2024                 switch (man_id) {
2025                 case 0x20: /* ST flash. */
2026                         if (flash_id == 0xd2 || flash_id == 0xe3) {
2027                                 /*
2028                                  * ST m29w008at part - 64kb sector size with
2029                                  * 32kb,8kb,8kb,16kb sectors at memory address
2030                                  * 0xf0000.
2031                                  */
2032                                 rest_addr = 0xffff;
2033                                 sec_mask = 0x10000;
2034                                 break;
2035                         }
2036                         /*
2037                          * ST m29w010b part - 16kb sector size
2038                          * Default to 16kb sectors
2039                          */
2040                         rest_addr = 0x3fff;
2041                         sec_mask = 0x1c000;
2042                         break;
2043                 case 0x40: /* Mostel flash. */
2044                         /* Mostel v29c51001 part - 512 byte sector size. */
2045                         rest_addr = 0x1ff;
2046                         sec_mask = 0x1fe00;
2047                         break;
2048                 case 0xbf: /* SST flash. */
2049                         /* SST39sf10 part - 4kb sector size. */
2050                         rest_addr = 0xfff;
2051                         sec_mask = 0x1f000;
2052                         break;
2053                 case 0xda: /* Winbond flash. */
2054                         /* Winbond W29EE011 part - 256 byte sector size. */
2055                         rest_addr = 0x7f;
2056                         sec_mask = 0x1ff80;
2057                         break;
2058                 case 0xc2: /* Macronix flash. */
2059                         /* 64k sector size. */
2060                         if (flash_id == 0x38 || flash_id == 0x4f) {
2061                                 rest_addr = 0xffff;
2062                                 sec_mask = 0x10000;
2063                                 break;
2064                         }
2065                         /* Fall through... */
2066
2067                 case 0x1f: /* Atmel flash. */
2068                         /* 512k sector size. */
2069                         if (flash_id == 0x13) {
2070                                 rest_addr = 0x7fffffff;
2071                                 sec_mask =   0x80000000;
2072                                 break;
2073                         }
2074                         /* Fall through... */
2075
2076                 case 0x01: /* AMD flash. */
2077                         if (flash_id == 0x38 || flash_id == 0x40 ||
2078                             flash_id == 0x4f) {
2079                                 /* Am29LV081 part - 64kb sector size. */
2080                                 /* Am29LV002BT part - 64kb sector size. */
2081                                 rest_addr = 0xffff;
2082                                 sec_mask = 0x10000;
2083                                 break;
2084                         } else if (flash_id == 0x3e) {
2085                                 /*
2086                                  * Am29LV008b part - 64kb sector size with
2087                                  * 32kb,8kb,8kb,16kb sector at memory address
2088                                  * h0xf0000.
2089                                  */
2090                                 rest_addr = 0xffff;
2091                                 sec_mask = 0x10000;
2092                                 break;
2093                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
2094                                 /*
2095                                  * Am29LV010 part or AM29f010 - 16kb sector
2096                                  * size.
2097                                  */
2098                                 rest_addr = 0x3fff;
2099                                 sec_mask = 0x1c000;
2100                                 break;
2101                         } else if (flash_id == 0x6d) {
2102                                 /* Am29LV001 part - 8kb sector size. */
2103                                 rest_addr = 0x1fff;
2104                                 sec_mask = 0x1e000;
2105                                 break;
2106                         }
2107                 default:
2108                         /* Default to 16 kb sector size. */
2109                         rest_addr = 0x3fff;
2110                         sec_mask = 0x1c000;
2111                         break;
2112                 }
2113
2114 update_flash:
2115                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2116                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2117                                 rval = QLA_FUNCTION_FAILED;
2118                                 break;
2119                         }
2120                 }
2121
2122                 for (addr = offset, liter = 0; liter < length; liter++,
2123                     addr++) {
2124                         data = buf[liter];
2125                         /* Are we at the beginning of a sector? */
2126                         if ((addr & rest_addr) == 0) {
2127                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2128                                         if (addr >= 0x10000UL) {
2129                                                 if (((addr >> 12) & 0xf0) &&
2130                                                     ((man_id == 0x01 &&
2131                                                         flash_id == 0x3e) ||
2132                                                      (man_id == 0x20 &&
2133                                                          flash_id == 0xd2))) {
2134                                                         sec_number++;
2135                                                         if (sec_number == 1) {
2136                                                                 rest_addr =
2137                                                                     0x7fff;
2138                                                                 sec_mask =
2139                                                                     0x18000;
2140                                                         } else if (
2141                                                             sec_number == 2 ||
2142                                                             sec_number == 3) {
2143                                                                 rest_addr =
2144                                                                     0x1fff;
2145                                                                 sec_mask =
2146                                                                     0x1e000;
2147                                                         } else if (
2148                                                             sec_number == 4) {
2149                                                                 rest_addr =
2150                                                                     0x3fff;
2151                                                                 sec_mask =
2152                                                                     0x1c000;
2153                                                         }
2154                                                 }
2155                                         }
2156                                 } else if (addr == ha->optrom_size / 2) {
2157                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2158                                         RD_REG_WORD(&reg->nvram);
2159                                 }
2160
2161                                 if (flash_id == 0xda && man_id == 0xc1) {
2162                                         qla2x00_write_flash_byte(ha, 0x5555,
2163                                             0xaa);
2164                                         qla2x00_write_flash_byte(ha, 0x2aaa,
2165                                             0x55);
2166                                         qla2x00_write_flash_byte(ha, 0x5555,
2167                                             0xa0);
2168                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2169                                         /* Then erase it */
2170                                         if (qla2x00_erase_flash_sector(ha,
2171                                             addr, sec_mask, man_id,
2172                                             flash_id)) {
2173                                                 rval = QLA_FUNCTION_FAILED;
2174                                                 break;
2175                                         }
2176                                         if (man_id == 0x01 && flash_id == 0x6d)
2177                                                 sec_number++;
2178                                 }
2179                         }
2180
2181                         if (man_id == 0x01 && flash_id == 0x6d) {
2182                                 if (sec_number == 1 &&
2183                                     addr == (rest_addr - 1)) {
2184                                         rest_addr = 0x0fff;
2185                                         sec_mask   = 0x1f000;
2186                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2187                                         rest_addr = 0x3fff;
2188                                         sec_mask   = 0x1c000;
2189                                 }
2190                         }
2191
2192                         if (qla2x00_program_flash_address(ha, addr, data,
2193                             man_id, flash_id)) {
2194                                 rval = QLA_FUNCTION_FAILED;
2195                                 break;
2196                         }
2197                         cond_resched();
2198                 }
2199         } while (0);
2200         qla2x00_flash_disable(ha);
2201
2202         /* Resume HBA. */
2203         qla2x00_resume_hba(vha);
2204
2205         return rval;
2206 }
2207
2208 uint8_t *
2209 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2210     uint32_t offset, uint32_t length)
2211 {
2212         struct qla_hw_data *ha = vha->hw;
2213
2214         /* Suspend HBA. */
2215         scsi_block_requests(vha->host);
2216         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2217
2218         /* Go with read. */
2219         qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2220
2221         /* Resume HBA. */
2222         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2223         scsi_unblock_requests(vha->host);
2224
2225         return buf;
2226 }
2227
2228 int
2229 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2230     uint32_t offset, uint32_t length)
2231 {
2232         int rval;
2233         struct qla_hw_data *ha = vha->hw;
2234
2235         /* Suspend HBA. */
2236         scsi_block_requests(vha->host);
2237         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2238
2239         /* Go with write. */
2240         rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2241             length >> 2);
2242
2243         /* Resume HBA -- RISC reset needed. */
2244         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2245         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2246         qla2xxx_wake_dpc(vha);
2247         qla2x00_wait_for_hba_online(vha);
2248         scsi_unblock_requests(vha->host);
2249
2250         return rval;
2251 }
2252
2253 uint8_t *
2254 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2255     uint32_t offset, uint32_t length)
2256 {
2257         int rval;
2258         dma_addr_t optrom_dma;
2259         void *optrom;
2260         uint8_t *pbuf;
2261         uint32_t faddr, left, burst;
2262         struct qla_hw_data *ha = vha->hw;
2263
2264         if (offset & 0xfff)
2265                 goto slow_read;
2266         if (length < OPTROM_BURST_SIZE)
2267                 goto slow_read;
2268
2269         optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2270             &optrom_dma, GFP_KERNEL);
2271         if (!optrom) {
2272                 qla_printk(KERN_DEBUG, ha,
2273                     "Unable to allocate memory for optrom burst read "
2274                     "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2275
2276                 goto slow_read;
2277         }
2278
2279         pbuf = buf;
2280         faddr = offset >> 2;
2281         left = length >> 2;
2282         burst = OPTROM_BURST_DWORDS;
2283         while (left != 0) {
2284                 if (burst > left)
2285                         burst = left;
2286
2287                 rval = qla2x00_dump_ram(vha, optrom_dma,
2288                     flash_data_addr(ha, faddr), burst);
2289                 if (rval) {
2290                         qla_printk(KERN_WARNING, ha,
2291                             "Unable to burst-read optrom segment "
2292                             "(%x/%x/%llx).\n", rval,
2293                             flash_data_addr(ha, faddr),
2294                             (unsigned long long)optrom_dma);
2295                         qla_printk(KERN_WARNING, ha,
2296                             "Reverting to slow-read.\n");
2297
2298                         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2299                             optrom, optrom_dma);
2300                         goto slow_read;
2301                 }
2302
2303                 memcpy(pbuf, optrom, burst * 4);
2304
2305                 left -= burst;
2306                 faddr += burst;
2307                 pbuf += burst * 4;
2308         }
2309
2310         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2311             optrom_dma);
2312
2313         return buf;
2314
2315 slow_read:
2316     return qla24xx_read_optrom_data(vha, buf, offset, length);
2317 }
2318
2319 /**
2320  * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2321  * @ha: HA context
2322  * @pcids: Pointer to the FCODE PCI data structure
2323  *
2324  * The process of retrieving the FCODE version information is at best
2325  * described as interesting.
2326  *
2327  * Within the first 100h bytes of the image an ASCII string is present
2328  * which contains several pieces of information including the FCODE
2329  * version.  Unfortunately it seems the only reliable way to retrieve
2330  * the version is by scanning for another sentinel within the string,
2331  * the FCODE build date:
2332  *
2333  *      ... 2.00.02 10/17/02 ...
2334  *
2335  * Returns QLA_SUCCESS on successful retrieval of version.
2336  */
2337 static void
2338 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2339 {
2340         int ret = QLA_FUNCTION_FAILED;
2341         uint32_t istart, iend, iter, vend;
2342         uint8_t do_next, rbyte, *vbyte;
2343
2344         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2345
2346         /* Skip the PCI data structure. */
2347         istart = pcids +
2348             ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2349                 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2350         iend = istart + 0x100;
2351         do {
2352                 /* Scan for the sentinel date string...eeewww. */
2353                 do_next = 0;
2354                 iter = istart;
2355                 while ((iter < iend) && !do_next) {
2356                         iter++;
2357                         if (qla2x00_read_flash_byte(ha, iter) == '/') {
2358                                 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2359                                     '/')
2360                                         do_next++;
2361                                 else if (qla2x00_read_flash_byte(ha,
2362                                     iter + 3) == '/')
2363                                         do_next++;
2364                         }
2365                 }
2366                 if (!do_next)
2367                         break;
2368
2369                 /* Backtrack to previous ' ' (space). */
2370                 do_next = 0;
2371                 while ((iter > istart) && !do_next) {
2372                         iter--;
2373                         if (qla2x00_read_flash_byte(ha, iter) == ' ')
2374                                 do_next++;
2375                 }
2376                 if (!do_next)
2377                         break;
2378
2379                 /*
2380                  * Mark end of version tag, and find previous ' ' (space) or
2381                  * string length (recent FCODE images -- major hack ahead!!!).
2382                  */
2383                 vend = iter - 1;
2384                 do_next = 0;
2385                 while ((iter > istart) && !do_next) {
2386                         iter--;
2387                         rbyte = qla2x00_read_flash_byte(ha, iter);
2388                         if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2389                                 do_next++;
2390                 }
2391                 if (!do_next)
2392                         break;
2393
2394                 /* Mark beginning of version tag, and copy data. */
2395                 iter++;
2396                 if ((vend - iter) &&
2397                     ((vend - iter) < sizeof(ha->fcode_revision))) {
2398                         vbyte = ha->fcode_revision;
2399                         while (iter <= vend) {
2400                                 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2401                                 iter++;
2402                         }
2403                         ret = QLA_SUCCESS;
2404                 }
2405         } while (0);
2406
2407         if (ret != QLA_SUCCESS)
2408                 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2409 }
2410
2411 int
2412 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2413 {
2414         int ret = QLA_SUCCESS;
2415         uint8_t code_type, last_image;
2416         uint32_t pcihdr, pcids;
2417         uint8_t *dbyte;
2418         uint16_t *dcode;
2419         struct qla_hw_data *ha = vha->hw;
2420
2421         if (!ha->pio_address || !mbuf)
2422                 return QLA_FUNCTION_FAILED;
2423
2424         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2425         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2426         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2427         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2428
2429         qla2x00_flash_enable(ha);
2430
2431         /* Begin with first PCI expansion ROM header. */
2432         pcihdr = 0;
2433         last_image = 1;
2434         do {
2435                 /* Verify PCI expansion ROM header. */
2436                 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2437                     qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2438                         /* No signature */
2439                         DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2440                             "signature.\n"));
2441                         ret = QLA_FUNCTION_FAILED;
2442                         break;
2443                 }
2444
2445                 /* Locate PCI data structure. */
2446                 pcids = pcihdr +
2447                     ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2448                         qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2449
2450                 /* Validate signature of PCI data structure. */
2451                 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2452                     qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2453                     qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2454                     qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2455                         /* Incorrect header. */
2456                         DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2457                             "found pcir_adr=%x.\n", pcids));
2458                         ret = QLA_FUNCTION_FAILED;
2459                         break;
2460                 }
2461
2462                 /* Read version */
2463                 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2464                 switch (code_type) {
2465                 case ROM_CODE_TYPE_BIOS:
2466                         /* Intel x86, PC-AT compatible. */
2467                         ha->bios_revision[0] =
2468                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2469                         ha->bios_revision[1] =
2470                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2471                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2472                             ha->bios_revision[1], ha->bios_revision[0]));
2473                         break;
2474                 case ROM_CODE_TYPE_FCODE:
2475                         /* Open Firmware standard for PCI (FCode). */
2476                         /* Eeeewww... */
2477                         qla2x00_get_fcode_version(ha, pcids);
2478                         break;
2479                 case ROM_CODE_TYPE_EFI:
2480                         /* Extensible Firmware Interface (EFI). */
2481                         ha->efi_revision[0] =
2482                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2483                         ha->efi_revision[1] =
2484                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2485                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2486                             ha->efi_revision[1], ha->efi_revision[0]));
2487                         break;
2488                 default:
2489                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2490                             "type %x at pcids %x.\n", code_type, pcids));
2491                         break;
2492                 }
2493
2494                 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2495
2496                 /* Locate next PCI expansion ROM. */
2497                 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2498                     qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2499         } while (!last_image);
2500
2501         if (IS_QLA2322(ha)) {
2502                 /* Read firmware image information. */
2503                 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2504                 dbyte = mbuf;
2505                 memset(dbyte, 0, 8);
2506                 dcode = (uint16_t *)dbyte;
2507
2508                 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2509                     8);
2510                 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2511                     "flash:\n"));
2512                 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2513
2514                 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2515                     dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2516                     (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2517                     dcode[3] == 0)) {
2518                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2519                             "revision at %x.\n", ha->flt_region_fw * 4));
2520                 } else {
2521                         /* values are in big endian */
2522                         ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2523                         ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2524                         ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2525                 }
2526         }
2527
2528         qla2x00_flash_disable(ha);
2529
2530         return ret;
2531 }
2532
2533 int
2534 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2535 {
2536         int ret = QLA_SUCCESS;
2537         uint32_t pcihdr, pcids;
2538         uint32_t *dcode;
2539         uint8_t *bcode;
2540         uint8_t code_type, last_image;
2541         int i;
2542         struct qla_hw_data *ha = vha->hw;
2543
2544         if (!mbuf)
2545                 return QLA_FUNCTION_FAILED;
2546
2547         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2548         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2549         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2550         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2551
2552         dcode = mbuf;
2553
2554         /* Begin with first PCI expansion ROM header. */
2555         pcihdr = ha->flt_region_boot << 2;
2556         last_image = 1;
2557         do {
2558                 /* Verify PCI expansion ROM header. */
2559                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2560                 bcode = mbuf + (pcihdr % 4);
2561                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2562                         /* No signature */
2563                         DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2564                             "signature.\n"));
2565                         ret = QLA_FUNCTION_FAILED;
2566                         break;
2567                 }
2568
2569                 /* Locate PCI data structure. */
2570                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2571
2572                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2573                 bcode = mbuf + (pcihdr % 4);
2574
2575                 /* Validate signature of PCI data structure. */
2576                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2577                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2578                         /* Incorrect header. */
2579                         DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2580                             "found pcir_adr=%x.\n", pcids));
2581                         ret = QLA_FUNCTION_FAILED;
2582                         break;
2583                 }
2584
2585                 /* Read version */
2586                 code_type = bcode[0x14];
2587                 switch (code_type) {
2588                 case ROM_CODE_TYPE_BIOS:
2589                         /* Intel x86, PC-AT compatible. */
2590                         ha->bios_revision[0] = bcode[0x12];
2591                         ha->bios_revision[1] = bcode[0x13];
2592                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2593                             ha->bios_revision[1], ha->bios_revision[0]));
2594                         break;
2595                 case ROM_CODE_TYPE_FCODE:
2596                         /* Open Firmware standard for PCI (FCode). */
2597                         ha->fcode_revision[0] = bcode[0x12];
2598                         ha->fcode_revision[1] = bcode[0x13];
2599                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
2600                             ha->fcode_revision[1], ha->fcode_revision[0]));
2601                         break;
2602                 case ROM_CODE_TYPE_EFI:
2603                         /* Extensible Firmware Interface (EFI). */
2604                         ha->efi_revision[0] = bcode[0x12];
2605                         ha->efi_revision[1] = bcode[0x13];
2606                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2607                             ha->efi_revision[1], ha->efi_revision[0]));
2608                         break;
2609                 default:
2610                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2611                             "type %x at pcids %x.\n", code_type, pcids));
2612                         break;
2613                 }
2614
2615                 last_image = bcode[0x15] & BIT_7;
2616
2617                 /* Locate next PCI expansion ROM. */
2618                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2619         } while (!last_image);
2620
2621         /* Read firmware image information. */
2622         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2623         dcode = mbuf;
2624
2625         qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2626         for (i = 0; i < 4; i++)
2627                 dcode[i] = be32_to_cpu(dcode[i]);
2628
2629         if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2630             dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2631             (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2632             dcode[3] == 0)) {
2633                 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2634                     "revision at %x.\n", ha->flt_region_fw * 4));
2635         } else {
2636                 ha->fw_revision[0] = dcode[0];
2637                 ha->fw_revision[1] = dcode[1];
2638                 ha->fw_revision[2] = dcode[2];
2639                 ha->fw_revision[3] = dcode[3];
2640         }
2641
2642         return ret;
2643 }
2644
2645 static int
2646 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2647 {
2648         if (pos >= end || *pos != 0x82)
2649                 return 0;
2650
2651         pos += 3 + pos[1];
2652         if (pos >= end || *pos != 0x90)
2653                 return 0;
2654
2655         pos += 3 + pos[1];
2656         if (pos >= end || *pos != 0x78)
2657                 return 0;
2658
2659         return 1;
2660 }
2661
2662 int
2663 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2664 {
2665         struct qla_hw_data *ha = vha->hw;
2666         uint8_t *pos = ha->vpd;
2667         uint8_t *end = pos + ha->vpd_size;
2668         int len = 0;
2669
2670         if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2671                 return 0;
2672
2673         while (pos < end && *pos != 0x78) {
2674                 len = (*pos == 0x82) ? pos[1] : pos[2];
2675
2676                 if (!strncmp(pos, key, strlen(key)))
2677                         break;
2678
2679                 if (*pos != 0x90 && *pos != 0x91)
2680                         pos += len;
2681
2682                 pos += 3;
2683         }
2684
2685         if (pos < end - len && *pos != 0x78)
2686                 return snprintf(str, size, "%.*s", len, pos + 3);
2687
2688         return 0;
2689 }