drivers/scsi/qla2xxx/qla_sup.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/delay.h>
  10 #include <linux/vmalloc.h>
  11 #include <asm/uaccess.h>
  12
  13 /*
  14  * NVRAM support routines
  15  */
  16
  17 /**
  18  * qla2x00_lock_nvram_access() -
  19  * @ha: HA context
  20  */
  21 static void
  22 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
  23 {
  24         uint16_t data;
  25         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  26
  27         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  28                 data = RD_REG_WORD(&reg->nvram);
  29                 while (data & NVR_BUSY) {
  30                         udelay(100);
  31                         data = RD_REG_WORD(&reg->nvram);
  32                 }
  33
  34                 /* Lock resource */
  35                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  36                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  37                 udelay(5);
  38                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  39                 while ((data & BIT_0) == 0) {
  40                         /* Lock failed */
  41                         udelay(100);
  42                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  43                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  44                         udelay(5);
  45                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  46                 }
  47         }
  48 }
  49
  50 /**
  51  * qla2x00_unlock_nvram_access() -
  52  * @ha: HA context
  53  */
  54 static void
  55 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
  56 {
  57         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  58
  59         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  60                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  61                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  62         }
  63 }
  64
  65 /**
  66  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
  67  * @ha: HA context
  68  * @data: Serial interface selector
  69  */
  70 static void
  71 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
  72 {
  73         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  74
  75         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  76         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  77         NVRAM_DELAY();
  78         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
  79             NVR_WRT_ENABLE);
  80         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  81         NVRAM_DELAY();
  82         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  83         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  84         NVRAM_DELAY();
  85 }
  86
  87 /**
  88  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
  89  *      NVRAM.
  90  * @ha: HA context
  91  * @nv_cmd: NVRAM command
  92  *
  93  * Bit definitions for NVRAM command:
  94  *
  95  *      Bit 26     = start bit
  96  *      Bit 25, 24 = opcode
  97  *      Bit 23-16  = address
  98  *      Bit 15-0   = write data
  99  *
 100  * Returns the word read from nvram @addr.
 101  */
 102 static uint16_t
 103 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
 104 {
 105         uint8_t         cnt;
 106         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 107         uint16_t        data = 0;
 108         uint16_t        reg_data;
 109
 110         /* Send command to NVRAM. */
 111         nv_cmd <<= 5;
 112         for (cnt = 0; cnt < 11; cnt++) {
 113                 if (nv_cmd & BIT_31)
 114                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 115                 else
 116                         qla2x00_nv_write(ha, 0);
 117                 nv_cmd <<= 1;
 118         }
 119
 120         /* Read data from NVRAM. */
 121         for (cnt = 0; cnt < 16; cnt++) {
 122                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 123                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 124                 NVRAM_DELAY();
 125                 data <<= 1;
 126                 reg_data = RD_REG_WORD(&reg->nvram);
 127                 if (reg_data & NVR_DATA_IN)
 128                         data |= BIT_0;
 129                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 130                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 131                 NVRAM_DELAY();
 132         }
 133
 134         /* Deselect chip. */
 135         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 136         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 137         NVRAM_DELAY();
 138
 139         return data;
 140 }
 141
 142
 143 /**
 144  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
 145  *      request routine to get the word from NVRAM.
 146  * @ha: HA context
 147  * @addr: Address in NVRAM to read
 148  *
 149  * Returns the word read from nvram @addr.
 150  */
 151 static uint16_t
 152 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
 153 {
 154         uint16_t        data;
 155         uint32_t        nv_cmd;
 156
 157         nv_cmd = addr << 16;
 158         nv_cmd |= NV_READ_OP;
 159         data = qla2x00_nvram_request(ha, nv_cmd);
 160
 161         return (data);
 162 }
 163
 164 /**
 165  * qla2x00_nv_deselect() - Deselect NVRAM operations.
 166  * @ha: HA context
 167  */
 168 static void
 169 qla2x00_nv_deselect(struct qla_hw_data *ha)
 170 {
 171         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 172
 173         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 174         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 175         NVRAM_DELAY();
 176 }
 177
 178 /**
 179  * qla2x00_write_nvram_word() - Write NVRAM data.
 180  * @ha: HA context
 181  * @addr: Address in NVRAM to write
 182  * @data: word to program
 183  */
 184 static void
 185 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
 186 {
 187         int count;
 188         uint16_t word;
 189         uint32_t nv_cmd, wait_cnt;
 190         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 191
 192         qla2x00_nv_write(ha, NVR_DATA_OUT);
 193         qla2x00_nv_write(ha, 0);
 194         qla2x00_nv_write(ha, 0);
 195
 196         for (word = 0; word < 8; word++)
 197                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 198
 199         qla2x00_nv_deselect(ha);
 200
 201         /* Write data */
 202         nv_cmd = (addr << 16) | NV_WRITE_OP;
 203         nv_cmd |= data;
 204         nv_cmd <<= 5;
 205         for (count = 0; count < 27; count++) {
 206                 if (nv_cmd & BIT_31)
 207                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 208                 else
 209                         qla2x00_nv_write(ha, 0);
 210
 211                 nv_cmd <<= 1;
 212         }
 213
 214         qla2x00_nv_deselect(ha);
 215
 216         /* Wait for NVRAM to become ready */
 217         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 218         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 219         wait_cnt = NVR_WAIT_CNT;
 220         do {
 221                 if (!--wait_cnt) {
 222                         DEBUG9_10(qla_printk(KERN_WARNING, ha,
 223                             "NVRAM didn't go ready...\n"));
 224                         break;
 225                 }
 226                 NVRAM_DELAY();
 227                 word = RD_REG_WORD(&reg->nvram);
 228         } while ((word & NVR_DATA_IN) == 0);
 229
 230         qla2x00_nv_deselect(ha);
 231
 232         /* Disable writes */
 233         qla2x00_nv_write(ha, NVR_DATA_OUT);
 234         for (count = 0; count < 10; count++)
 235                 qla2x00_nv_write(ha, 0);
 236
 237         qla2x00_nv_deselect(ha);
 238 }
 239
 240 static int
 241 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
 242         uint16_t data, uint32_t tmo)
 243 {
 244         int ret, count;
 245         uint16_t word;
 246         uint32_t nv_cmd;
 247         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 248
 249         ret = QLA_SUCCESS;
 250
 251         qla2x00_nv_write(ha, NVR_DATA_OUT);
 252         qla2x00_nv_write(ha, 0);
 253         qla2x00_nv_write(ha, 0);
 254
 255         for (word = 0; word < 8; word++)
 256                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 257
 258         qla2x00_nv_deselect(ha);
 259
 260         /* Write data */
 261         nv_cmd = (addr << 16) | NV_WRITE_OP;
 262         nv_cmd |= data;
 263         nv_cmd <<= 5;
 264         for (count = 0; count < 27; count++) {
 265                 if (nv_cmd & BIT_31)
 266                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 267                 else
 268                         qla2x00_nv_write(ha, 0);
 269
 270                 nv_cmd <<= 1;
 271         }
 272
 273         qla2x00_nv_deselect(ha);
 274
 275         /* Wait for NVRAM to become ready */
 276         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 277         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 278         do {
 279                 NVRAM_DELAY();
 280                 word = RD_REG_WORD(&reg->nvram);
 281                 if (!--tmo) {
 282                         ret = QLA_FUNCTION_FAILED;
 283                         break;
 284                 }
 285         } while ((word & NVR_DATA_IN) == 0);
 286
 287         qla2x00_nv_deselect(ha);
 288
 289         /* Disable writes */
 290         qla2x00_nv_write(ha, NVR_DATA_OUT);
 291         for (count = 0; count < 10; count++)
 292                 qla2x00_nv_write(ha, 0);
 293
 294         qla2x00_nv_deselect(ha);
 295
 296         return ret;
 297 }
 298
 299 /**
 300  * qla2x00_clear_nvram_protection() -
 301  * @ha: HA context
 302  */
 303 static int
 304 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
 305 {
 306         int ret, stat;
 307         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 308         uint32_t word, wait_cnt;
 309         uint16_t wprot, wprot_old;
 310
 311         /* Clear NVRAM write protection. */
 312         ret = QLA_FUNCTION_FAILED;
 313
 314         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 315         stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
 316             __constant_cpu_to_le16(0x1234), 100000);
 317         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 318         if (stat != QLA_SUCCESS || wprot != 0x1234) {
 319                 /* Write enable. */
 320                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 321                 qla2x00_nv_write(ha, 0);
 322                 qla2x00_nv_write(ha, 0);
 323                 for (word = 0; word < 8; word++)
 324                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 325
 326                 qla2x00_nv_deselect(ha);
 327
 328                 /* Enable protection register. */
 329                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 330                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 331                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 332                 for (word = 0; word < 8; word++)
 333                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 334
 335                 qla2x00_nv_deselect(ha);
 336
 337                 /* Clear protection register (ffff is cleared). */
 338                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 339                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 340                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 341                 for (word = 0; word < 8; word++)
 342                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 343
 344                 qla2x00_nv_deselect(ha);
 345
 346                 /* Wait for NVRAM to become ready. */
 347                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 348                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 349                 wait_cnt = NVR_WAIT_CNT;
 350                 do {
 351                         if (!--wait_cnt) {
 352                                 DEBUG9_10(qla_printk(KERN_WARNING, ha,
 353                                     "NVRAM didn't go ready...\n"));
 354                                 break;
 355                         }
 356                         NVRAM_DELAY();
 357                         word = RD_REG_WORD(&reg->nvram);
 358                 } while ((word & NVR_DATA_IN) == 0);
 359
 360                 if (wait_cnt)
 361                         ret = QLA_SUCCESS;
 362         } else
 363                 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
 364
 365         return ret;
 366 }
 367
 368 static void
 369 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
 370 {
 371         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 372         uint32_t word, wait_cnt;
 373
 374         if (stat != QLA_SUCCESS)
 375                 return;
 376
 377         /* Set NVRAM write protection. */
 378         /* Write enable. */
 379         qla2x00_nv_write(ha, NVR_DATA_OUT);
 380         qla2x00_nv_write(ha, 0);
 381         qla2x00_nv_write(ha, 0);
 382         for (word = 0; word < 8; word++)
 383                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 384
 385         qla2x00_nv_deselect(ha);
 386
 387         /* Enable protection register. */
 388         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 389         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 390         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 391         for (word = 0; word < 8; word++)
 392                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 393
 394         qla2x00_nv_deselect(ha);
 395
 396         /* Enable protection register. */
 397         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 398         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 399         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 400         for (word = 0; word < 8; word++)
 401                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 402
 403         qla2x00_nv_deselect(ha);
 404
 405         /* Wait for NVRAM to become ready. */
 406         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 407         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 408         wait_cnt = NVR_WAIT_CNT;
 409         do {
 410                 if (!--wait_cnt) {
 411                         DEBUG9_10(qla_printk(KERN_WARNING, ha,
 412                             "NVRAM didn't go ready...\n"));
 413                         break;
 414                 }
 415                 NVRAM_DELAY();
 416                 word = RD_REG_WORD(&reg->nvram);
 417         } while ((word & NVR_DATA_IN) == 0);
 418 }
 419
 420
 421 /*****************************************************************************/
 422 /* Flash Manipulation Routines                                               */
 423 /*****************************************************************************/
 424
 425 #define OPTROM_BURST_SIZE       0x1000
 426 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
 427
 428 static inline uint32_t
 429 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
 430 {
 431         return ha->flash_conf_off | faddr;
 432 }
 433
 434 static inline uint32_t
 435 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
 436 {
 437         return ha->flash_data_off | faddr;
 438 }
 439
 440 static inline uint32_t
 441 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
 442 {
 443         return ha->nvram_conf_off | naddr;
 444 }
 445
 446 static inline uint32_t
 447 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
 448 {
 449         return ha->nvram_data_off | naddr;
 450 }
 451
 452 static uint32_t
 453 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
 454 {
 455         int rval;
 456         uint32_t cnt, data;
 457         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 458
 459         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 460         /* Wait for READ cycle to complete. */
 461         rval = QLA_SUCCESS;
 462         for (cnt = 3000;
 463             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 464             rval == QLA_SUCCESS; cnt--) {
 465                 if (cnt)
 466                         udelay(10);
 467                 else
 468                         rval = QLA_FUNCTION_TIMEOUT;
 469                 cond_resched();
 470         }
 471
 472         /* TODO: What happens if we time out? */
 473         data = 0xDEADDEAD;
 474         if (rval == QLA_SUCCESS)
 475                 data = RD_REG_DWORD(&reg->flash_data);
 476
 477         return data;
 478 }
 479
 480 uint32_t *
 481 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
 482     uint32_t dwords)
 483 {
 484         uint32_t i;
 485         struct qla_hw_data *ha = vha->hw;
 486
 487         /* Dword reads to flash. */
 488         for (i = 0; i < dwords; i++, faddr++)
 489                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 490                     flash_data_addr(ha, faddr)));
 491
 492         return dwptr;
 493 }
 494
 495 static int
 496 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
 497 {
 498         int rval;
 499         uint32_t cnt;
 500         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 501
 502         WRT_REG_DWORD(&reg->flash_data, data);
 503         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 504         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 505         /* Wait for Write cycle to complete. */
 506         rval = QLA_SUCCESS;
 507         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 508             rval == QLA_SUCCESS; cnt--) {
 509                 if (cnt)
 510                         udelay(10);
 511                 else
 512                         rval = QLA_FUNCTION_TIMEOUT;
 513                 cond_resched();
 514         }
 515         return rval;
 516 }
 517
 518 static void
 519 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
 520     uint8_t *flash_id)
 521 {
 522         uint32_t ids;
 523
 524         ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
 525         *man_id = LSB(ids);
 526         *flash_id = MSB(ids);
 527
 528         /* Check if man_id and flash_id are valid. */
 529         if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
 530                 /* Read information using 0x9f opcode
 531                  * Device ID, Mfg ID would be read in the format:
 532                  *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
 533                  * Example: ATMEL 0x00 01 45 1F
 534                  * Extract MFG and Dev ID from last two bytes.
 535                  */
 536                 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
 537                 *man_id = LSB(ids);
 538                 *flash_id = MSB(ids);
 539         }
 540 }
 541
 542 static int
 543 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
 544 {
 545         const char *loc, *locations[] = { "DEF", "PCI" };
 546         uint32_t pcihdr, pcids;
 547         uint32_t *dcode;
 548         uint8_t *buf, *bcode, last_image;
 549         uint16_t cnt, chksum, *wptr;
 550         struct qla_flt_location *fltl;
 551         struct qla_hw_data *ha = vha->hw;
 552         struct req_que *req = ha->req_q_map[0];
 553
 554         /*
 555          * FLT-location structure resides after the last PCI region.
 556          */
 557
 558         /* Begin with sane defaults. */
 559         loc = locations[0];
 560         *start = 0;
 561         if (IS_QLA24XX_TYPE(ha))
 562                 *start = FA_FLASH_LAYOUT_ADDR_24;
 563         else if (IS_QLA25XX(ha))
 564                 *start = FA_FLASH_LAYOUT_ADDR;
 565         else if (IS_QLA81XX(ha))
 566                 *start = FA_FLASH_LAYOUT_ADDR_81;
 567         /* Begin with first PCI expansion ROM header. */
 568         buf = (uint8_t *)req->ring;
 569         dcode = (uint32_t *)req->ring;
 570         pcihdr = 0;
 571         last_image = 1;
 572         do {
 573                 /* Verify PCI expansion ROM header. */
 574                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
 575                 bcode = buf + (pcihdr % 4);
 576                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
 577                         goto end;
 578
 579                 /* Locate PCI data structure. */
 580                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
 581                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
 582                 bcode = buf + (pcihdr % 4);
 583
 584                 /* Validate signature of PCI data structure. */
 585                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
 586                     bcode[0x2] != 'I' || bcode[0x3] != 'R')
 587                         goto end;
 588
 589                 last_image = bcode[0x15] & BIT_7;
 590
 591                 /* Locate next PCI expansion ROM. */
 592                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
 593         } while (!last_image);
 594
 595         /* Now verify FLT-location structure. */
 596         fltl = (struct qla_flt_location *)req->ring;
 597         qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
 598             sizeof(struct qla_flt_location) >> 2);
 599         if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
 600             fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
 601                 goto end;
 602
 603         wptr = (uint16_t *)req->ring;
 604         cnt = sizeof(struct qla_flt_location) >> 1;
 605         for (chksum = 0; cnt; cnt--)
 606                 chksum += le16_to_cpu(*wptr++);
 607         if (chksum) {
 608                 qla_printk(KERN_ERR, ha,
 609                     "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
 610                 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
 611                 return QLA_FUNCTION_FAILED;
 612         }
 613
 614         /* Good data.  Use specified location. */
 615         loc = locations[1];
 616         *start = (le16_to_cpu(fltl->start_hi) << 16 |
 617             le16_to_cpu(fltl->start_lo)) >> 2;
 618 end:
 619         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
 620         return QLA_SUCCESS;
 621 }
 622
 623 static void
 624 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
 625 {
 626         const char *loc, *locations[] = { "DEF", "FLT" };
 627         const uint32_t def_fw[] =
 628                 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
 629         const uint32_t def_boot[] =
 630                 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
 631         const uint32_t def_vpd_nvram[] =
 632                 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
 633         const uint32_t def_vpd0[] =
 634                 { 0, 0, FA_VPD0_ADDR_81 };
 635         const uint32_t def_vpd1[] =
 636                 { 0, 0, FA_VPD1_ADDR_81 };
 637         const uint32_t def_nvram0[] =
 638                 { 0, 0, FA_NVRAM0_ADDR_81 };
 639         const uint32_t def_nvram1[] =
 640                 { 0, 0, FA_NVRAM1_ADDR_81 };
 641         const uint32_t def_fdt[] =
 642                 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
 643                         FA_FLASH_DESCR_ADDR_81 };
 644         const uint32_t def_npiv_conf0[] =
 645                 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
 646                         FA_NPIV_CONF0_ADDR_81 };
 647         const uint32_t def_npiv_conf1[] =
 648                 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
 649                         FA_NPIV_CONF1_ADDR_81 };
 650         uint32_t def;
 651         uint16_t *wptr;
 652         uint16_t cnt, chksum;
 653         uint32_t start;
 654         struct qla_flt_header *flt;
 655         struct qla_flt_region *region;
 656         struct qla_hw_data *ha = vha->hw;
 657         struct req_que *req = ha->req_q_map[0];
 658
 659         ha->flt_region_flt = flt_addr;
 660         wptr = (uint16_t *)req->ring;
 661         flt = (struct qla_flt_header *)req->ring;
 662         region = (struct qla_flt_region *)&flt[1];
 663         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 664             flt_addr << 2, OPTROM_BURST_SIZE);
 665         if (*wptr == __constant_cpu_to_le16(0xffff))
 666                 goto no_flash_data;
 667         if (flt->version != __constant_cpu_to_le16(1)) {
 668                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
 669                     "version=0x%x length=0x%x checksum=0x%x.\n",
 670                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 671                     le16_to_cpu(flt->checksum)));
 672                 goto no_flash_data;
 673         }
 674
 675         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
 676         for (chksum = 0; cnt; cnt--)
 677                 chksum += le16_to_cpu(*wptr++);
 678         if (chksum) {
 679                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
 680                     "version=0x%x length=0x%x checksum=0x%x.\n",
 681                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 682                     chksum));
 683                 goto no_flash_data;
 684         }
 685
 686         loc = locations[1];
 687         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
 688         for ( ; cnt; cnt--, region++) {
 689                 /* Store addresses as DWORD offsets. */
 690                 start = le32_to_cpu(region->start) >> 2;
 691
 692                 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
 693                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
 694                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
 695
 696                 switch (le32_to_cpu(region->code) & 0xff) {
 697                 case FLT_REG_FW:
 698                         ha->flt_region_fw = start;
 699                         break;
 700                 case FLT_REG_BOOT_CODE:
 701                         ha->flt_region_boot = start;
 702                         break;
 703                 case FLT_REG_VPD_0:
 704                         ha->flt_region_vpd_nvram = start;
 705                         if (ha->flags.port0)
 706                                 ha->flt_region_vpd = start;
 707                         break;
 708                 case FLT_REG_VPD_1:
 709                         if (!ha->flags.port0)
 710                                 ha->flt_region_vpd = start;
 711                         break;
 712                 case FLT_REG_NVRAM_0:
 713                         if (ha->flags.port0)
 714                                 ha->flt_region_nvram = start;
 715                         break;
 716                 case FLT_REG_NVRAM_1:
 717                         if (!ha->flags.port0)
 718                                 ha->flt_region_nvram = start;
 719                         break;
 720                 case FLT_REG_FDT:
 721                         ha->flt_region_fdt = start;
 722                         break;
 723                 case FLT_REG_NPIV_CONF_0:
 724                         if (ha->flags.port0)
 725                                 ha->flt_region_npiv_conf = start;
 726                         break;
 727                 case FLT_REG_NPIV_CONF_1:
 728                         if (!ha->flags.port0)
 729                                 ha->flt_region_npiv_conf = start;
 730                         break;
 731                 case FLT_REG_GOLD_FW:
 732                         ha->flt_region_gold_fw = start;
 733                         break;
 734                 }
 735         }
 736         goto done;
 737
 738 no_flash_data:
 739         /* Use hardcoded defaults. */
 740         loc = locations[0];
 741         def = 0;
 742         if (IS_QLA24XX_TYPE(ha))
 743                 def = 0;
 744         else if (IS_QLA25XX(ha))
 745                 def = 1;
 746         else if (IS_QLA81XX(ha))
 747                 def = 2;
 748         ha->flt_region_fw = def_fw[def];
 749         ha->flt_region_boot = def_boot[def];
 750         ha->flt_region_vpd_nvram = def_vpd_nvram[def];
 751         ha->flt_region_vpd = ha->flags.port0 ?
 752             def_vpd0[def]: def_vpd1[def];
 753         ha->flt_region_nvram = ha->flags.port0 ?
 754             def_nvram0[def]: def_nvram1[def];
 755         ha->flt_region_fdt = def_fdt[def];
 756         ha->flt_region_npiv_conf = ha->flags.port0 ?
 757             def_npiv_conf0[def]: def_npiv_conf1[def];
 758 done:
 759         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
 760             "vpd_nvram=0x%x vpd=0x%x nvram=0x%x fdt=0x%x flt=0x%x "
 761             "npiv=0x%x.\n", loc, ha->flt_region_boot, ha->flt_region_fw,
 762             ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
 763             ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
 764 }
 765
 766 static void
 767 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
 768 {
 769 #define FLASH_BLK_SIZE_4K       0x1000
 770 #define FLASH_BLK_SIZE_32K      0x8000
 771 #define FLASH_BLK_SIZE_64K      0x10000
 772         const char *loc, *locations[] = { "MID", "FDT" };
 773         uint16_t cnt, chksum;
 774         uint16_t *wptr;
 775         struct qla_fdt_layout *fdt;
 776         uint8_t man_id, flash_id;
 777         uint16_t mid, fid;
 778         struct qla_hw_data *ha = vha->hw;
 779         struct req_que *req = ha->req_q_map[0];
 780
 781         wptr = (uint16_t *)req->ring;
 782         fdt = (struct qla_fdt_layout *)req->ring;
 783         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 784             ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
 785         if (*wptr == __constant_cpu_to_le16(0xffff))
 786                 goto no_flash_data;
 787         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
 788             fdt->sig[3] != 'D')
 789                 goto no_flash_data;
 790
 791         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
 792             cnt++)
 793                 chksum += le16_to_cpu(*wptr++);
 794         if (chksum) {
 795                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
 796                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
 797                     le16_to_cpu(fdt->version)));
 798                 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
 799                 goto no_flash_data;
 800         }
 801
 802         loc = locations[1];
 803         mid = le16_to_cpu(fdt->man_id);
 804         fid = le16_to_cpu(fdt->id);
 805         ha->fdt_wrt_disable = fdt->wrt_disable_bits;
 806         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
 807         ha->fdt_block_size = le32_to_cpu(fdt->block_size);
 808         if (fdt->unprotect_sec_cmd) {
 809                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
 810                     fdt->unprotect_sec_cmd);
 811                 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
 812                     flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
 813                     flash_conf_addr(ha, 0x0336);
 814         }
 815         goto done;
 816 no_flash_data:
 817         loc = locations[0];
 818         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 819         mid = man_id;
 820         fid = flash_id;
 821         ha->fdt_wrt_disable = 0x9c;
 822         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
 823         switch (man_id) {
 824         case 0xbf: /* STT flash. */
 825                 if (flash_id == 0x8e)
 826                         ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 827                 else
 828                         ha->fdt_block_size = FLASH_BLK_SIZE_32K;
 829
 830                 if (flash_id == 0x80)
 831                         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
 832                 break;
 833         case 0x13: /* ST M25P80. */
 834                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 835                 break;
 836         case 0x1f: /* Atmel 26DF081A. */
 837                 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
 838                 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
 839                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
 840                 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
 841                 break;
 842         default:
 843                 /* Default to 64 kb sector size. */
 844                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 845                 break;
 846         }
 847 done:
 848         DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
 849             "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
 850             ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
 851             ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
 852             ha->fdt_block_size));
 853 }
 854
 855 int
 856 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
 857 {
 858         int ret;
 859         uint32_t flt_addr;
 860         struct qla_hw_data *ha = vha->hw;
 861
 862         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
 863                 return QLA_SUCCESS;
 864
 865         ret = qla2xxx_find_flt_start(vha, &flt_addr);
 866         if (ret != QLA_SUCCESS)
 867                 return ret;
 868
 869         qla2xxx_get_flt_info(vha, flt_addr);
 870         qla2xxx_get_fdt_info(vha);
 871
 872         return QLA_SUCCESS;
 873 }
 874
 875 void
 876 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
 877 {
 878 #define NPIV_CONFIG_SIZE        (16*1024)
 879         void *data;
 880         uint16_t *wptr;
 881         uint16_t cnt, chksum;
 882         int i;
 883         struct qla_npiv_header hdr;
 884         struct qla_npiv_entry *entry;
 885         struct qla_hw_data *ha = vha->hw;
 886
 887         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
 888                 return;
 889
 890         ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
 891             ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
 892         if (hdr.version == __constant_cpu_to_le16(0xffff))
 893                 return;
 894         if (hdr.version != __constant_cpu_to_le16(1)) {
 895                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
 896                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
 897                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
 898                     le16_to_cpu(hdr.checksum)));
 899                 return;
 900         }
 901
 902         data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
 903         if (!data) {
 904                 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
 905                     "allocate memory.\n"));
 906                 return;
 907         }
 908
 909         ha->isp_ops->read_optrom(vha, (uint8_t *)data,
 910             ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
 911
 912         cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
 913             sizeof(struct qla_npiv_entry)) >> 1;
 914         for (wptr = data, chksum = 0; cnt; cnt--)
 915                 chksum += le16_to_cpu(*wptr++);
 916         if (chksum) {
 917                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
 918                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
 919                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
 920                     chksum));
 921                 goto done;
 922         }
 923
 924         entry = data + sizeof(struct qla_npiv_header);
 925         cnt = le16_to_cpu(hdr.entries);
 926         for (i = 0; cnt; cnt--, entry++, i++) {
 927                 uint16_t flags;
 928                 struct fc_vport_identifiers vid;
 929                 struct fc_vport *vport;
 930
 931                 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
 932
 933                 flags = le16_to_cpu(entry->flags);
 934                 if (flags == 0xffff)
 935                         continue;
 936                 if ((flags & BIT_0) == 0)
 937                         continue;
 938
 939                 memset(&vid, 0, sizeof(vid));
 940                 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
 941                 vid.vport_type = FC_PORTTYPE_NPIV;
 942                 vid.disable = false;
 943                 vid.port_name = wwn_to_u64(entry->port_name);
 944                 vid.node_name = wwn_to_u64(entry->node_name);
 945
 946                 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV[%02x]: wwpn=%llx "
 947                         "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
 948                         (unsigned long long)vid.port_name,
 949                         (unsigned long long)vid.node_name,
 950                         le16_to_cpu(entry->vf_id),
 951                         entry->q_qos, entry->f_qos));
 952
 953                 if (i < QLA_PRECONFIG_VPORTS) {
 954                         vport = fc_vport_create(vha->host, 0, &vid);
 955                         if (!vport)
 956                                 qla_printk(KERN_INFO, ha,
 957                                 "NPIV-Config: Failed to create vport [%02x]: "
 958                                 "wwpn=%llx wwnn=%llx.\n", cnt,
 959                                 (unsigned long long)vid.port_name,
 960                                 (unsigned long long)vid.node_name);
 961                 }
 962         }
 963 done:
 964         kfree(data);
 965 }
 966
 967 static int
 968 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
 969 {
 970         struct qla_hw_data *ha = vha->hw;
 971         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 972
 973         if (ha->flags.fac_supported)
 974                 return qla81xx_fac_do_write_enable(vha, 1);
 975
 976         /* Enable flash write. */
 977         WRT_REG_DWORD(&reg->ctrl_status,
 978             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 979         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 980
 981         if (!ha->fdt_wrt_disable)
 982                 goto done;
 983
 984         /* Disable flash write-protection, first clear SR protection bit */
 985         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
 986         /* Then write zero again to clear remaining SR bits.*/
 987         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
 988 done:
 989         return QLA_SUCCESS;
 990 }
 991
 992 static int
 993 qla24xx_protect_flash(scsi_qla_host_t *vha)
 994 {
 995         uint32_t cnt;
 996         struct qla_hw_data *ha = vha->hw;
 997         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 998
 999         if (ha->flags.fac_supported)
1000                 return qla81xx_fac_do_write_enable(vha, 0);
1001
1002         if (!ha->fdt_wrt_disable)
1003                 goto skip_wrt_protect;
1004
1005         /* Enable flash write-protection and wait for completion. */
1006         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1007             ha->fdt_wrt_disable);
1008         for (cnt = 300; cnt &&
1009             qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1010             cnt--) {
1011                 udelay(10);
1012         }
1013
1014 skip_wrt_protect:
1015         /* Disable flash write. */
1016         WRT_REG_DWORD(&reg->ctrl_status,
1017             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1018         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1019
1020         return QLA_SUCCESS;
1021 }
1022
1023 static int
1024 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1025 {
1026         struct qla_hw_data *ha = vha->hw;
1027         uint32_t start, finish;
1028
1029         if (ha->flags.fac_supported) {
1030                 start = fdata >> 2;
1031                 finish = start + (ha->fdt_block_size >> 2) - 1;
1032                 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1033                     start), flash_data_addr(ha, finish));
1034         }
1035
1036         return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1037             (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1038             ((fdata >> 16) & 0xff));
1039 }
1040
1041 static int
1042 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1043     uint32_t dwords)
1044 {
1045         int ret;
1046         uint32_t liter;
1047         uint32_t sec_mask, rest_addr;
1048         uint32_t fdata;
1049         dma_addr_t optrom_dma;
1050         void *optrom = NULL;
1051         struct qla_hw_data *ha = vha->hw;
1052
1053         /* Prepare burst-capable write on supported ISPs. */
1054         if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
1055             dwords > OPTROM_BURST_DWORDS) {
1056                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1057                     &optrom_dma, GFP_KERNEL);
1058                 if (!optrom) {
1059                         qla_printk(KERN_DEBUG, ha,
1060                             "Unable to allocate memory for optrom burst write "
1061                             "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1062                 }
1063         }
1064
1065         rest_addr = (ha->fdt_block_size >> 2) - 1;
1066         sec_mask = ~rest_addr;
1067
1068         ret = qla24xx_unprotect_flash(vha);
1069         if (ret != QLA_SUCCESS) {
1070                 qla_printk(KERN_WARNING, ha,
1071                     "Unable to unprotect flash for update.\n");
1072                 goto done;
1073         }
1074
1075         for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1076                 fdata = (faddr & sec_mask) << 2;
1077
1078                 /* Are we at the beginning of a sector? */
1079                 if ((faddr & rest_addr) == 0) {
1080                         /* Do sector unprotect. */
1081                         if (ha->fdt_unprotect_sec_cmd)
1082                                 qla24xx_write_flash_dword(ha,
1083                                     ha->fdt_unprotect_sec_cmd,
1084                                     (fdata & 0xff00) | ((fdata << 16) &
1085                                     0xff0000) | ((fdata >> 16) & 0xff));
1086                         ret = qla24xx_erase_sector(vha, fdata);
1087                         if (ret != QLA_SUCCESS) {
1088                                 DEBUG9(qla_printk(KERN_WARNING, ha,
1089                                     "Unable to erase sector: address=%x.\n",
1090                                     faddr));
1091                                 break;
1092                         }
1093                 }
1094
1095                 /* Go with burst-write. */
1096                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1097                         /* Copy data to DMA'ble buffer. */
1098                         memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1099
1100                         ret = qla2x00_load_ram(vha, optrom_dma,
1101                             flash_data_addr(ha, faddr),
1102                             OPTROM_BURST_DWORDS);
1103                         if (ret != QLA_SUCCESS) {
1104                                 qla_printk(KERN_WARNING, ha,
1105                                     "Unable to burst-write optrom segment "
1106                                     "(%x/%x/%llx).\n", ret,
1107                                     flash_data_addr(ha, faddr),
1108                                     (unsigned long long)optrom_dma);
1109                                 qla_printk(KERN_WARNING, ha,
1110                                     "Reverting to slow-write.\n");
1111
1112                                 dma_free_coherent(&ha->pdev->dev,
1113                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1114                                 optrom = NULL;
1115                         } else {
1116                                 liter += OPTROM_BURST_DWORDS - 1;
1117                                 faddr += OPTROM_BURST_DWORDS - 1;
1118                                 dwptr += OPTROM_BURST_DWORDS - 1;
1119                                 continue;
1120                         }
1121                 }
1122
1123                 ret = qla24xx_write_flash_dword(ha,
1124                     flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1125                 if (ret != QLA_SUCCESS) {
1126                         DEBUG9(printk("%s(%ld) Unable to program flash "
1127                             "address=%x data=%x.\n", __func__,
1128                             vha->host_no, faddr, *dwptr));
1129                         break;
1130                 }
1131
1132                 /* Do sector protect. */
1133                 if (ha->fdt_unprotect_sec_cmd &&
1134                     ((faddr & rest_addr) == rest_addr))
1135                         qla24xx_write_flash_dword(ha,
1136                             ha->fdt_protect_sec_cmd,
1137                             (fdata & 0xff00) | ((fdata << 16) &
1138                             0xff0000) | ((fdata >> 16) & 0xff));
1139         }
1140
1141         ret = qla24xx_protect_flash(vha);
1142         if (ret != QLA_SUCCESS)
1143                 qla_printk(KERN_WARNING, ha,
1144                     "Unable to protect flash after update.\n");
1145 done:
1146         if (optrom)
1147                 dma_free_coherent(&ha->pdev->dev,
1148                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1149
1150         return ret;
1151 }
1152
1153 uint8_t *
1154 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1155     uint32_t bytes)
1156 {
1157         uint32_t i;
1158         uint16_t *wptr;
1159         struct qla_hw_data *ha = vha->hw;
1160
1161         /* Word reads to NVRAM via registers. */
1162         wptr = (uint16_t *)buf;
1163         qla2x00_lock_nvram_access(ha);
1164         for (i = 0; i < bytes >> 1; i++, naddr++)
1165                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1166                     naddr));
1167         qla2x00_unlock_nvram_access(ha);
1168
1169         return buf;
1170 }
1171
1172 uint8_t *
1173 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1174     uint32_t bytes)
1175 {
1176         uint32_t i;
1177         uint32_t *dwptr;
1178         struct qla_hw_data *ha = vha->hw;
1179
1180         /* Dword reads to flash. */
1181         dwptr = (uint32_t *)buf;
1182         for (i = 0; i < bytes >> 2; i++, naddr++)
1183                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1184                     nvram_data_addr(ha, naddr)));
1185
1186         return buf;
1187 }
1188
1189 int
1190 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1191     uint32_t bytes)
1192 {
1193         int ret, stat;
1194         uint32_t i;
1195         uint16_t *wptr;
1196         unsigned long flags;
1197         struct qla_hw_data *ha = vha->hw;
1198
1199         ret = QLA_SUCCESS;
1200
1201         spin_lock_irqsave(&ha->hardware_lock, flags);
1202         qla2x00_lock_nvram_access(ha);
1203
1204         /* Disable NVRAM write-protection. */
1205         stat = qla2x00_clear_nvram_protection(ha);
1206
1207         wptr = (uint16_t *)buf;
1208         for (i = 0; i < bytes >> 1; i++, naddr++) {
1209                 qla2x00_write_nvram_word(ha, naddr,
1210                     cpu_to_le16(*wptr));
1211                 wptr++;
1212         }
1213
1214         /* Enable NVRAM write-protection. */
1215         qla2x00_set_nvram_protection(ha, stat);
1216
1217         qla2x00_unlock_nvram_access(ha);
1218         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1219
1220         return ret;
1221 }
1222
1223 int
1224 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1225     uint32_t bytes)
1226 {
1227         int ret;
1228         uint32_t i;
1229         uint32_t *dwptr;
1230         struct qla_hw_data *ha = vha->hw;
1231         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1232
1233         ret = QLA_SUCCESS;
1234
1235         /* Enable flash write. */
1236         WRT_REG_DWORD(&reg->ctrl_status,
1237             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1238         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1239
1240         /* Disable NVRAM write-protection. */
1241         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1242         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1243
1244         /* Dword writes to flash. */
1245         dwptr = (uint32_t *)buf;
1246         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1247                 ret = qla24xx_write_flash_dword(ha,
1248                     nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1249                 if (ret != QLA_SUCCESS) {
1250                         DEBUG9(qla_printk(KERN_WARNING, ha,
1251                             "Unable to program nvram address=%x data=%x.\n",
1252                             naddr, *dwptr));
1253                         break;
1254                 }
1255         }
1256
1257         /* Enable NVRAM write-protection. */
1258         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1259
1260         /* Disable flash write. */
1261         WRT_REG_DWORD(&reg->ctrl_status,
1262             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1263         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1264
1265         return ret;
1266 }
1267
1268 uint8_t *
1269 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1270     uint32_t bytes)
1271 {
1272         uint32_t i;
1273         uint32_t *dwptr;
1274         struct qla_hw_data *ha = vha->hw;
1275
1276         /* Dword reads to flash. */
1277         dwptr = (uint32_t *)buf;
1278         for (i = 0; i < bytes >> 2; i++, naddr++)
1279                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1280                     flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1281
1282         return buf;
1283 }
1284
1285 int
1286 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1287     uint32_t bytes)
1288 {
1289         struct qla_hw_data *ha = vha->hw;
1290 #define RMW_BUFFER_SIZE (64 * 1024)
1291         uint8_t *dbuf;
1292
1293         dbuf = vmalloc(RMW_BUFFER_SIZE);
1294         if (!dbuf)
1295                 return QLA_MEMORY_ALLOC_FAILED;
1296         ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1297             RMW_BUFFER_SIZE);
1298         memcpy(dbuf + (naddr << 2), buf, bytes);
1299         ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1300             RMW_BUFFER_SIZE);
1301         vfree(dbuf);
1302
1303         return QLA_SUCCESS;
1304 }
1305
1306 static inline void
1307 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1308 {
1309         if (IS_QLA2322(ha)) {
1310                 /* Flip all colors. */
1311                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1312                         /* Turn off. */
1313                         ha->beacon_color_state = 0;
1314                         *pflags = GPIO_LED_ALL_OFF;
1315                 } else {
1316                         /* Turn on. */
1317                         ha->beacon_color_state = QLA_LED_ALL_ON;
1318                         *pflags = GPIO_LED_RGA_ON;
1319                 }
1320         } else {
1321                 /* Flip green led only. */
1322                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1323                         /* Turn off. */
1324                         ha->beacon_color_state = 0;
1325                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1326                 } else {
1327                         /* Turn on. */
1328                         ha->beacon_color_state = QLA_LED_GRN_ON;
1329                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1330                 }
1331         }
1332 }
1333
1334 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1335
1336 void
1337 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1338 {
1339         uint16_t gpio_enable;
1340         uint16_t gpio_data;
1341         uint16_t led_color = 0;
1342         unsigned long flags;
1343         struct qla_hw_data *ha = vha->hw;
1344         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1345
1346         spin_lock_irqsave(&ha->hardware_lock, flags);
1347
1348         /* Save the Original GPIOE. */
1349         if (ha->pio_address) {
1350                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1351                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1352         } else {
1353                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1354                 gpio_data = RD_REG_WORD(&reg->gpiod);
1355         }
1356
1357         /* Set the modified gpio_enable values */
1358         gpio_enable |= GPIO_LED_MASK;
1359
1360         if (ha->pio_address) {
1361                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1362         } else {
1363                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1364                 RD_REG_WORD(&reg->gpioe);
1365         }
1366
1367         qla2x00_flip_colors(ha, &led_color);
1368
1369         /* Clear out any previously set LED color. */
1370         gpio_data &= ~GPIO_LED_MASK;
1371
1372         /* Set the new input LED color to GPIOD. */
1373         gpio_data |= led_color;
1374
1375         /* Set the modified gpio_data values */
1376         if (ha->pio_address) {
1377                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1378         } else {
1379                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1380                 RD_REG_WORD(&reg->gpiod);
1381         }
1382
1383         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1384 }
1385
1386 int
1387 qla2x00_beacon_on(struct scsi_qla_host *vha)
1388 {
1389         uint16_t gpio_enable;
1390         uint16_t gpio_data;
1391         unsigned long flags;
1392         struct qla_hw_data *ha = vha->hw;
1393         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1394
1395         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1396         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1397
1398         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1399                 qla_printk(KERN_WARNING, ha,
1400                     "Unable to update fw options (beacon on).\n");
1401                 return QLA_FUNCTION_FAILED;
1402         }
1403
1404         /* Turn off LEDs. */
1405         spin_lock_irqsave(&ha->hardware_lock, flags);
1406         if (ha->pio_address) {
1407                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1408                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1409         } else {
1410                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1411                 gpio_data = RD_REG_WORD(&reg->gpiod);
1412         }
1413         gpio_enable |= GPIO_LED_MASK;
1414
1415         /* Set the modified gpio_enable values. */
1416         if (ha->pio_address) {
1417                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1418         } else {
1419                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1420                 RD_REG_WORD(&reg->gpioe);
1421         }
1422
1423         /* Clear out previously set LED colour. */
1424         gpio_data &= ~GPIO_LED_MASK;
1425         if (ha->pio_address) {
1426                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1427         } else {
1428                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1429                 RD_REG_WORD(&reg->gpiod);
1430         }
1431         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1432
1433         /*
1434          * Let the per HBA timer kick off the blinking process based on
1435          * the following flags. No need to do anything else now.
1436          */
1437         ha->beacon_blink_led = 1;
1438         ha->beacon_color_state = 0;
1439
1440         return QLA_SUCCESS;
1441 }
1442
1443 int
1444 qla2x00_beacon_off(struct scsi_qla_host *vha)
1445 {
1446         int rval = QLA_SUCCESS;
1447         struct qla_hw_data *ha = vha->hw;
1448
1449         ha->beacon_blink_led = 0;
1450
1451         /* Set the on flag so when it gets flipped it will be off. */
1452         if (IS_QLA2322(ha))
1453                 ha->beacon_color_state = QLA_LED_ALL_ON;
1454         else
1455                 ha->beacon_color_state = QLA_LED_GRN_ON;
1456
1457         ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1458
1459         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1460         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1461
1462         rval = qla2x00_set_fw_options(vha, ha->fw_options);
1463         if (rval != QLA_SUCCESS)
1464                 qla_printk(KERN_WARNING, ha,
1465                     "Unable to update fw options (beacon off).\n");
1466         return rval;
1467 }
1468
1469
1470 static inline void
1471 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1472 {
1473         /* Flip all colors. */
1474         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1475                 /* Turn off. */
1476                 ha->beacon_color_state = 0;
1477                 *pflags = 0;
1478         } else {
1479                 /* Turn on. */
1480                 ha->beacon_color_state = QLA_LED_ALL_ON;
1481                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1482         }
1483 }
1484
1485 void
1486 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1487 {
1488         uint16_t led_color = 0;
1489         uint32_t gpio_data;
1490         unsigned long flags;
1491         struct qla_hw_data *ha = vha->hw;
1492         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1493
1494         /* Save the Original GPIOD. */
1495         spin_lock_irqsave(&ha->hardware_lock, flags);
1496         gpio_data = RD_REG_DWORD(&reg->gpiod);
1497
1498         /* Enable the gpio_data reg for update. */
1499         gpio_data |= GPDX_LED_UPDATE_MASK;
1500
1501         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1502         gpio_data = RD_REG_DWORD(&reg->gpiod);
1503
1504         /* Set the color bits. */
1505         qla24xx_flip_colors(ha, &led_color);
1506
1507         /* Clear out any previously set LED color. */
1508         gpio_data &= ~GPDX_LED_COLOR_MASK;
1509
1510         /* Set the new input LED color to GPIOD. */
1511         gpio_data |= led_color;
1512
1513         /* Set the modified gpio_data values. */
1514         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1515         gpio_data = RD_REG_DWORD(&reg->gpiod);
1516         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1517 }
1518
1519 int
1520 qla24xx_beacon_on(struct scsi_qla_host *vha)
1521 {
1522         uint32_t gpio_data;
1523         unsigned long flags;
1524         struct qla_hw_data *ha = vha->hw;
1525         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1526
1527         if (ha->beacon_blink_led == 0) {
1528                 /* Enable firmware for update */
1529                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1530
1531                 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1532                         return QLA_FUNCTION_FAILED;
1533
1534                 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1535                     QLA_SUCCESS) {
1536                         qla_printk(KERN_WARNING, ha,
1537                             "Unable to update fw options (beacon on).\n");
1538                         return QLA_FUNCTION_FAILED;
1539                 }
1540
1541                 spin_lock_irqsave(&ha->hardware_lock, flags);
1542                 gpio_data = RD_REG_DWORD(&reg->gpiod);
1543
1544                 /* Enable the gpio_data reg for update. */
1545                 gpio_data |= GPDX_LED_UPDATE_MASK;
1546                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1547                 RD_REG_DWORD(&reg->gpiod);
1548
1549                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1550         }
1551
1552         /* So all colors blink together. */
1553         ha->beacon_color_state = 0;
1554
1555         /* Let the per HBA timer kick off the blinking process. */
1556         ha->beacon_blink_led = 1;
1557
1558         return QLA_SUCCESS;
1559 }
1560
1561 int
1562 qla24xx_beacon_off(struct scsi_qla_host *vha)
1563 {
1564         uint32_t gpio_data;
1565         unsigned long flags;
1566         struct qla_hw_data *ha = vha->hw;
1567         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1568
1569         ha->beacon_blink_led = 0;
1570         ha->beacon_color_state = QLA_LED_ALL_ON;
1571
1572         ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1573
1574         /* Give control back to firmware. */
1575         spin_lock_irqsave(&ha->hardware_lock, flags);
1576         gpio_data = RD_REG_DWORD(&reg->gpiod);
1577
1578         /* Disable the gpio_data reg for update. */
1579         gpio_data &= ~GPDX_LED_UPDATE_MASK;
1580         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1581         RD_REG_DWORD(&reg->gpiod);
1582         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1583
1584         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1585
1586         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1587                 qla_printk(KERN_WARNING, ha,
1588                     "Unable to update fw options (beacon off).\n");
1589                 return QLA_FUNCTION_FAILED;
1590         }
1591
1592         if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1593                 qla_printk(KERN_WARNING, ha,
1594                     "Unable to get fw options (beacon off).\n");
1595                 return QLA_FUNCTION_FAILED;
1596         }
1597
1598         return QLA_SUCCESS;
1599 }
1600
1601
1602 /*
1603  * Flash support routines
1604  */
1605
1606 /**
1607  * qla2x00_flash_enable() - Setup flash for reading and writing.
1608  * @ha: HA context
1609  */
1610 static void
1611 qla2x00_flash_enable(struct qla_hw_data *ha)
1612 {
1613         uint16_t data;
1614         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1615
1616         data = RD_REG_WORD(&reg->ctrl_status);
1617         data |= CSR_FLASH_ENABLE;
1618         WRT_REG_WORD(&reg->ctrl_status, data);
1619         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1620 }
1621
1622 /**
1623  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1624  * @ha: HA context
1625  */
1626 static void
1627 qla2x00_flash_disable(struct qla_hw_data *ha)
1628 {
1629         uint16_t data;
1630         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1631
1632         data = RD_REG_WORD(&reg->ctrl_status);
1633         data &= ~(CSR_FLASH_ENABLE);
1634         WRT_REG_WORD(&reg->ctrl_status, data);
1635         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1636 }
1637
1638 /**
1639  * qla2x00_read_flash_byte() - Reads a byte from flash
1640  * @ha: HA context
1641  * @addr: Address in flash to read
1642  *
1643  * A word is read from the chip, but, only the lower byte is valid.
1644  *
1645  * Returns the byte read from flash @addr.
1646  */
1647 static uint8_t
1648 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1649 {
1650         uint16_t data;
1651         uint16_t bank_select;
1652         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1653
1654         bank_select = RD_REG_WORD(&reg->ctrl_status);
1655
1656         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1657                 /* Specify 64K address range: */
1658                 /*  clear out Module Select and Flash Address bits [19:16]. */
1659                 bank_select &= ~0xf8;
1660                 bank_select |= addr >> 12 & 0xf0;
1661                 bank_select |= CSR_FLASH_64K_BANK;
1662                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1663                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1664
1665                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1666                 data = RD_REG_WORD(&reg->flash_data);
1667
1668                 return (uint8_t)data;
1669         }
1670
1671         /* Setup bit 16 of flash address. */
1672         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1673                 bank_select |= CSR_FLASH_64K_BANK;
1674                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1675                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1676         } else if (((addr & BIT_16) == 0) &&
1677             (bank_select & CSR_FLASH_64K_BANK)) {
1678                 bank_select &= ~(CSR_FLASH_64K_BANK);
1679                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1680                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1681         }
1682
1683         /* Always perform IO mapped accesses to the FLASH registers. */
1684         if (ha->pio_address) {
1685                 uint16_t data2;
1686
1687                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1688                 do {
1689                         data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1690                         barrier();
1691                         cpu_relax();
1692                         data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1693                 } while (data != data2);
1694         } else {
1695                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1696                 data = qla2x00_debounce_register(&reg->flash_data);
1697         }
1698
1699         return (uint8_t)data;
1700 }
1701
1702 /**
1703  * qla2x00_write_flash_byte() - Write a byte to flash
1704  * @ha: HA context
1705  * @addr: Address in flash to write
1706  * @data: Data to write
1707  */
1708 static void
1709 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1710 {
1711         uint16_t bank_select;
1712         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1713
1714         bank_select = RD_REG_WORD(&reg->ctrl_status);
1715         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1716                 /* Specify 64K address range: */
1717                 /*  clear out Module Select and Flash Address bits [19:16]. */
1718                 bank_select &= ~0xf8;
1719                 bank_select |= addr >> 12 & 0xf0;
1720                 bank_select |= CSR_FLASH_64K_BANK;
1721                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1722                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1723
1724                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1725                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1726                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1727                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1728
1729                 return;
1730         }
1731
1732         /* Setup bit 16 of flash address. */
1733         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1734                 bank_select |= CSR_FLASH_64K_BANK;
1735                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1736                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1737         } else if (((addr & BIT_16) == 0) &&
1738             (bank_select & CSR_FLASH_64K_BANK)) {
1739                 bank_select &= ~(CSR_FLASH_64K_BANK);
1740                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1741                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1742         }
1743
1744         /* Always perform IO mapped accesses to the FLASH registers. */
1745         if (ha->pio_address) {
1746                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1747                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1748         } else {
1749                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1750                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1751                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1752                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1753         }
1754 }
1755
1756 /**
1757  * qla2x00_poll_flash() - Polls flash for completion.
1758  * @ha: HA context
1759  * @addr: Address in flash to poll
1760  * @poll_data: Data to be polled
1761  * @man_id: Flash manufacturer ID
1762  * @flash_id: Flash ID
1763  *
1764  * This function polls the device until bit 7 of what is read matches data
1765  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
1766  * out (a fatal error).  The flash book recommeds reading bit 7 again after
1767  * reading bit 5 as a 1.
1768  *
1769  * Returns 0 on success, else non-zero.
1770  */
1771 static int
1772 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
1773     uint8_t man_id, uint8_t flash_id)
1774 {
1775         int status;
1776         uint8_t flash_data;
1777         uint32_t cnt;
1778
1779         status = 1;
1780
1781         /* Wait for 30 seconds for command to finish. */
1782         poll_data &= BIT_7;
1783         for (cnt = 3000000; cnt; cnt--) {
1784                 flash_data = qla2x00_read_flash_byte(ha, addr);
1785                 if ((flash_data & BIT_7) == poll_data) {
1786                         status = 0;
1787                         break;
1788                 }
1789
1790                 if (man_id != 0x40 && man_id != 0xda) {
1791                         if ((flash_data & BIT_5) && cnt > 2)
1792                                 cnt = 2;
1793                 }
1794                 udelay(10);
1795                 barrier();
1796                 cond_resched();
1797         }
1798         return status;
1799 }
1800
1801 /**
1802  * qla2x00_program_flash_address() - Programs a flash address
1803  * @ha: HA context
1804  * @addr: Address in flash to program
1805  * @data: Data to be written in flash
1806  * @man_id: Flash manufacturer ID
1807  * @flash_id: Flash ID
1808  *
1809  * Returns 0 on success, else non-zero.
1810  */
1811 static int
1812 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1813     uint8_t data, uint8_t man_id, uint8_t flash_id)
1814 {
1815         /* Write Program Command Sequence. */
1816         if (IS_OEM_001(ha)) {
1817                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1818                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1819                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1820                 qla2x00_write_flash_byte(ha, addr, data);
1821         } else {
1822                 if (man_id == 0xda && flash_id == 0xc1) {
1823                         qla2x00_write_flash_byte(ha, addr, data);
1824                         if (addr & 0x7e)
1825                                 return 0;
1826                 } else {
1827                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1828                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1829                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1830                         qla2x00_write_flash_byte(ha, addr, data);
1831                 }
1832         }
1833
1834         udelay(150);
1835
1836         /* Wait for write to complete. */
1837         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1838 }
1839
1840 /**
1841  * qla2x00_erase_flash() - Erase the flash.
1842  * @ha: HA context
1843  * @man_id: Flash manufacturer ID
1844  * @flash_id: Flash ID
1845  *
1846  * Returns 0 on success, else non-zero.
1847  */
1848 static int
1849 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
1850 {
1851         /* Individual Sector Erase Command Sequence */
1852         if (IS_OEM_001(ha)) {
1853                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1854                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1855                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1856                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1857                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1858                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1859         } else {
1860                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1861                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1862                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1863                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1864                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1865                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1866         }
1867
1868         udelay(150);
1869
1870         /* Wait for erase to complete. */
1871         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1872 }
1873
1874 /**
1875  * qla2x00_erase_flash_sector() - Erase a flash sector.
1876  * @ha: HA context
1877  * @addr: Flash sector to erase
1878  * @sec_mask: Sector address mask
1879  * @man_id: Flash manufacturer ID
1880  * @flash_id: Flash ID
1881  *
1882  * Returns 0 on success, else non-zero.
1883  */
1884 static int
1885 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
1886     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1887 {
1888         /* Individual Sector Erase Command Sequence */
1889         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1890         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1891         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1892         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1893         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1894         if (man_id == 0x1f && flash_id == 0x13)
1895                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1896         else
1897                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1898
1899         udelay(150);
1900
1901         /* Wait for erase to complete. */
1902         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1903 }
1904
1905 /**
1906  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1907  * @man_id: Flash manufacturer ID
1908  * @flash_id: Flash ID
1909  */
1910 static void
1911 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
1912     uint8_t *flash_id)
1913 {
1914         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1915         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1916         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1917         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1918         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1919         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1920         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1921         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1922 }
1923
1924 static void
1925 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1926         uint32_t saddr, uint32_t length)
1927 {
1928         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1929         uint32_t midpoint, ilength;
1930         uint8_t data;
1931
1932         midpoint = length / 2;
1933
1934         WRT_REG_WORD(&reg->nvram, 0);
1935         RD_REG_WORD(&reg->nvram);
1936         for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1937                 if (ilength == midpoint) {
1938                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1939                         RD_REG_WORD(&reg->nvram);
1940                 }
1941                 data = qla2x00_read_flash_byte(ha, saddr);
1942                 if (saddr % 100)
1943                         udelay(10);
1944                 *tmp_buf = data;
1945                 cond_resched();
1946         }
1947 }
1948
1949 static inline void
1950 qla2x00_suspend_hba(struct scsi_qla_host *vha)
1951 {
1952         int cnt;
1953         unsigned long flags;
1954         struct qla_hw_data *ha = vha->hw;
1955         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1956
1957         /* Suspend HBA. */
1958         scsi_block_requests(vha->host);
1959         ha->isp_ops->disable_intrs(ha);
1960         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1961
1962         /* Pause RISC. */
1963         spin_lock_irqsave(&ha->hardware_lock, flags);
1964         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1965         RD_REG_WORD(&reg->hccr);
1966         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1967                 for (cnt = 0; cnt < 30000; cnt++) {
1968                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1969                                 break;
1970                         udelay(100);
1971                 }
1972         } else {
1973                 udelay(10);
1974         }
1975         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1976 }
1977
1978 static inline void
1979 qla2x00_resume_hba(struct scsi_qla_host *vha)
1980 {
1981         struct qla_hw_data *ha = vha->hw;
1982
1983         /* Resume HBA. */
1984         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1985         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1986         qla2xxx_wake_dpc(vha);
1987         qla2x00_wait_for_chip_reset(vha);
1988         scsi_unblock_requests(vha->host);
1989 }
1990
1991 uint8_t *
1992 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1993     uint32_t offset, uint32_t length)
1994 {
1995         uint32_t addr, midpoint;
1996         uint8_t *data;
1997         struct qla_hw_data *ha = vha->hw;
1998         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1999
2000         /* Suspend HBA. */
2001         qla2x00_suspend_hba(vha);
2002
2003         /* Go with read. */
2004         midpoint = ha->optrom_size / 2;
2005
2006         qla2x00_flash_enable(ha);
2007         WRT_REG_WORD(&reg->nvram, 0);
2008         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
2009         for (addr = offset, data = buf; addr < length; addr++, data++) {
2010                 if (addr == midpoint) {
2011                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2012                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
2013                 }
2014
2015                 *data = qla2x00_read_flash_byte(ha, addr);
2016         }
2017         qla2x00_flash_disable(ha);
2018
2019         /* Resume HBA. */
2020         qla2x00_resume_hba(vha);
2021
2022         return buf;
2023 }
2024
2025 int
2026 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2027     uint32_t offset, uint32_t length)
2028 {
2029
2030         int rval;
2031         uint8_t man_id, flash_id, sec_number, data;
2032         uint16_t wd;
2033         uint32_t addr, liter, sec_mask, rest_addr;
2034         struct qla_hw_data *ha = vha->hw;
2035         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2036
2037         /* Suspend HBA. */
2038         qla2x00_suspend_hba(vha);
2039
2040         rval = QLA_SUCCESS;
2041         sec_number = 0;
2042
2043         /* Reset ISP chip. */
2044         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2045         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2046
2047         /* Go with write. */
2048         qla2x00_flash_enable(ha);
2049         do {    /* Loop once to provide quick error exit */
2050                 /* Structure of flash memory based on manufacturer */
2051                 if (IS_OEM_001(ha)) {
2052                         /* OEM variant with special flash part. */
2053                         man_id = flash_id = 0;
2054                         rest_addr = 0xffff;
2055                         sec_mask   = 0x10000;
2056                         goto update_flash;
2057                 }
2058                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2059                 switch (man_id) {
2060                 case 0x20: /* ST flash. */
2061                         if (flash_id == 0xd2 || flash_id == 0xe3) {
2062                                 /*
2063                                  * ST m29w008at part - 64kb sector size with
2064                                  * 32kb,8kb,8kb,16kb sectors at memory address
2065                                  * 0xf0000.
2066                                  */
2067                                 rest_addr = 0xffff;
2068                                 sec_mask = 0x10000;
2069                                 break;
2070                         }
2071                         /*
2072                          * ST m29w010b part - 16kb sector size
2073                          * Default to 16kb sectors
2074                          */
2075                         rest_addr = 0x3fff;
2076                         sec_mask = 0x1c000;
2077                         break;
2078                 case 0x40: /* Mostel flash. */
2079                         /* Mostel v29c51001 part - 512 byte sector size. */
2080                         rest_addr = 0x1ff;
2081                         sec_mask = 0x1fe00;
2082                         break;
2083                 case 0xbf: /* SST flash. */
2084                         /* SST39sf10 part - 4kb sector size. */
2085                         rest_addr = 0xfff;
2086                         sec_mask = 0x1f000;
2087                         break;
2088                 case 0xda: /* Winbond flash. */
2089                         /* Winbond W29EE011 part - 256 byte sector size. */
2090                         rest_addr = 0x7f;
2091                         sec_mask = 0x1ff80;
2092                         break;
2093                 case 0xc2: /* Macronix flash. */
2094                         /* 64k sector size. */
2095                         if (flash_id == 0x38 || flash_id == 0x4f) {
2096                                 rest_addr = 0xffff;
2097                                 sec_mask = 0x10000;
2098                                 break;
2099                         }
2100                         /* Fall through... */
2101
2102                 case 0x1f: /* Atmel flash. */
2103                         /* 512k sector size. */
2104                         if (flash_id == 0x13) {
2105                                 rest_addr = 0x7fffffff;
2106                                 sec_mask =   0x80000000;
2107                                 break;
2108                         }
2109                         /* Fall through... */
2110
2111                 case 0x01: /* AMD flash. */
2112                         if (flash_id == 0x38 || flash_id == 0x40 ||
2113                             flash_id == 0x4f) {
2114                                 /* Am29LV081 part - 64kb sector size. */
2115                                 /* Am29LV002BT part - 64kb sector size. */
2116                                 rest_addr = 0xffff;
2117                                 sec_mask = 0x10000;
2118                                 break;
2119                         } else if (flash_id == 0x3e) {
2120                                 /*
2121                                  * Am29LV008b part - 64kb sector size with
2122                                  * 32kb,8kb,8kb,16kb sector at memory address
2123                                  * h0xf0000.
2124                                  */
2125                                 rest_addr = 0xffff;
2126                                 sec_mask = 0x10000;
2127                                 break;
2128                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
2129                                 /*
2130                                  * Am29LV010 part or AM29f010 - 16kb sector
2131                                  * size.
2132                                  */
2133                                 rest_addr = 0x3fff;
2134                                 sec_mask = 0x1c000;
2135                                 break;
2136                         } else if (flash_id == 0x6d) {
2137                                 /* Am29LV001 part - 8kb sector size. */
2138                                 rest_addr = 0x1fff;
2139                                 sec_mask = 0x1e000;
2140                                 break;
2141                         }
2142                 default:
2143                         /* Default to 16 kb sector size. */
2144                         rest_addr = 0x3fff;
2145                         sec_mask = 0x1c000;
2146                         break;
2147                 }
2148
2149 update_flash:
2150                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2151                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2152                                 rval = QLA_FUNCTION_FAILED;
2153                                 break;
2154                         }
2155                 }
2156
2157                 for (addr = offset, liter = 0; liter < length; liter++,
2158                     addr++) {
2159                         data = buf[liter];
2160                         /* Are we at the beginning of a sector? */
2161                         if ((addr & rest_addr) == 0) {
2162                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2163                                         if (addr >= 0x10000UL) {
2164                                                 if (((addr >> 12) & 0xf0) &&
2165                                                     ((man_id == 0x01 &&
2166                                                         flash_id == 0x3e) ||
2167                                                      (man_id == 0x20 &&
2168                                                          flash_id == 0xd2))) {
2169                                                         sec_number++;
2170                                                         if (sec_number == 1) {
2171                                                                 rest_addr =
2172                                                                     0x7fff;
2173                                                                 sec_mask =
2174                                                                     0x18000;
2175                                                         } else if (
2176                                                             sec_number == 2 ||
2177                                                             sec_number == 3) {
2178                                                                 rest_addr =
2179                                                                     0x1fff;
2180                                                                 sec_mask =
2181                                                                     0x1e000;
2182                                                         } else if (
2183                                                             sec_number == 4) {
2184                                                                 rest_addr =
2185                                                                     0x3fff;
2186                                                                 sec_mask =
2187                                                                     0x1c000;
2188                                                         }
2189                                                 }
2190                                         }
2191                                 } else if (addr == ha->optrom_size / 2) {
2192                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2193                                         RD_REG_WORD(&reg->nvram);
2194                                 }
2195
2196                                 if (flash_id == 0xda && man_id == 0xc1) {
2197                                         qla2x00_write_flash_byte(ha, 0x5555,
2198                                             0xaa);
2199                                         qla2x00_write_flash_byte(ha, 0x2aaa,
2200                                             0x55);
2201                                         qla2x00_write_flash_byte(ha, 0x5555,
2202                                             0xa0);
2203                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2204                                         /* Then erase it */
2205                                         if (qla2x00_erase_flash_sector(ha,
2206                                             addr, sec_mask, man_id,
2207                                             flash_id)) {
2208                                                 rval = QLA_FUNCTION_FAILED;
2209                                                 break;
2210                                         }
2211                                         if (man_id == 0x01 && flash_id == 0x6d)
2212                                                 sec_number++;
2213                                 }
2214                         }
2215
2216                         if (man_id == 0x01 && flash_id == 0x6d) {
2217                                 if (sec_number == 1 &&
2218                                     addr == (rest_addr - 1)) {
2219                                         rest_addr = 0x0fff;
2220                                         sec_mask   = 0x1f000;
2221                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2222                                         rest_addr = 0x3fff;
2223                                         sec_mask   = 0x1c000;
2224                                 }
2225                         }
2226
2227                         if (qla2x00_program_flash_address(ha, addr, data,
2228                             man_id, flash_id)) {
2229                                 rval = QLA_FUNCTION_FAILED;
2230                                 break;
2231                         }
2232                         cond_resched();
2233                 }
2234         } while (0);
2235         qla2x00_flash_disable(ha);
2236
2237         /* Resume HBA. */
2238         qla2x00_resume_hba(vha);
2239
2240         return rval;
2241 }
2242
2243 uint8_t *
2244 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2245     uint32_t offset, uint32_t length)
2246 {
2247         struct qla_hw_data *ha = vha->hw;
2248
2249         /* Suspend HBA. */
2250         scsi_block_requests(vha->host);
2251         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2252
2253         /* Go with read. */
2254         qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2255
2256         /* Resume HBA. */
2257         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2258         scsi_unblock_requests(vha->host);
2259
2260         return buf;
2261 }
2262
2263 int
2264 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2265     uint32_t offset, uint32_t length)
2266 {
2267         int rval;
2268         struct qla_hw_data *ha = vha->hw;
2269
2270         /* Suspend HBA. */
2271         scsi_block_requests(vha->host);
2272         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2273
2274         /* Go with write. */
2275         rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2276             length >> 2);
2277
2278         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2279         scsi_unblock_requests(vha->host);
2280
2281         return rval;
2282 }
2283
2284 uint8_t *
2285 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2286     uint32_t offset, uint32_t length)
2287 {
2288         int rval;
2289         dma_addr_t optrom_dma;
2290         void *optrom;
2291         uint8_t *pbuf;
2292         uint32_t faddr, left, burst;
2293         struct qla_hw_data *ha = vha->hw;
2294
2295         if (IS_QLA25XX(ha) || IS_QLA81XX(ha))
2296                 goto try_fast;
2297         if (offset & 0xfff)
2298                 goto slow_read;
2299         if (length < OPTROM_BURST_SIZE)
2300                 goto slow_read;
2301
2302 try_fast:
2303         optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2304             &optrom_dma, GFP_KERNEL);
2305         if (!optrom) {
2306                 qla_printk(KERN_DEBUG, ha,
2307                     "Unable to allocate memory for optrom burst read "
2308                     "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2309
2310                 goto slow_read;
2311         }
2312
2313         pbuf = buf;
2314         faddr = offset >> 2;
2315         left = length >> 2;
2316         burst = OPTROM_BURST_DWORDS;
2317         while (left != 0) {
2318                 if (burst > left)
2319                         burst = left;
2320
2321                 rval = qla2x00_dump_ram(vha, optrom_dma,
2322                     flash_data_addr(ha, faddr), burst);
2323                 if (rval) {
2324                         qla_printk(KERN_WARNING, ha,
2325                             "Unable to burst-read optrom segment "
2326                             "(%x/%x/%llx).\n", rval,
2327                             flash_data_addr(ha, faddr),
2328                             (unsigned long long)optrom_dma);
2329                         qla_printk(KERN_WARNING, ha,
2330                             "Reverting to slow-read.\n");
2331
2332                         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2333                             optrom, optrom_dma);
2334                         goto slow_read;
2335                 }
2336
2337                 memcpy(pbuf, optrom, burst * 4);
2338
2339                 left -= burst;
2340                 faddr += burst;
2341                 pbuf += burst * 4;
2342         }
2343
2344         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2345             optrom_dma);
2346
2347         return buf;
2348
2349 slow_read:
2350     return qla24xx_read_optrom_data(vha, buf, offset, length);
2351 }
2352
2353 /**
2354  * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2355  * @ha: HA context
2356  * @pcids: Pointer to the FCODE PCI data structure
2357  *
2358  * The process of retrieving the FCODE version information is at best
2359  * described as interesting.
2360  *
2361  * Within the first 100h bytes of the image an ASCII string is present
2362  * which contains several pieces of information including the FCODE
2363  * version.  Unfortunately it seems the only reliable way to retrieve
2364  * the version is by scanning for another sentinel within the string,
2365  * the FCODE build date:
2366  *
2367  *      ... 2.00.02 10/17/02 ...
2368  *
2369  * Returns QLA_SUCCESS on successful retrieval of version.
2370  */
2371 static void
2372 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2373 {
2374         int ret = QLA_FUNCTION_FAILED;
2375         uint32_t istart, iend, iter, vend;
2376         uint8_t do_next, rbyte, *vbyte;
2377
2378         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2379
2380         /* Skip the PCI data structure. */
2381         istart = pcids +
2382             ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2383                 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2384         iend = istart + 0x100;
2385         do {
2386                 /* Scan for the sentinel date string...eeewww. */
2387                 do_next = 0;
2388                 iter = istart;
2389                 while ((iter < iend) && !do_next) {
2390                         iter++;
2391                         if (qla2x00_read_flash_byte(ha, iter) == '/') {
2392                                 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2393                                     '/')
2394                                         do_next++;
2395                                 else if (qla2x00_read_flash_byte(ha,
2396                                     iter + 3) == '/')
2397                                         do_next++;
2398                         }
2399                 }
2400                 if (!do_next)
2401                         break;
2402
2403                 /* Backtrack to previous ' ' (space). */
2404                 do_next = 0;
2405                 while ((iter > istart) && !do_next) {
2406                         iter--;
2407                         if (qla2x00_read_flash_byte(ha, iter) == ' ')
2408                                 do_next++;
2409                 }
2410                 if (!do_next)
2411                         break;
2412
2413                 /*
2414                  * Mark end of version tag, and find previous ' ' (space) or
2415                  * string length (recent FCODE images -- major hack ahead!!!).
2416                  */
2417                 vend = iter - 1;
2418                 do_next = 0;
2419                 while ((iter > istart) && !do_next) {
2420                         iter--;
2421                         rbyte = qla2x00_read_flash_byte(ha, iter);
2422                         if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2423                                 do_next++;
2424                 }
2425                 if (!do_next)
2426                         break;
2427
2428                 /* Mark beginning of version tag, and copy data. */
2429                 iter++;
2430                 if ((vend - iter) &&
2431                     ((vend - iter) < sizeof(ha->fcode_revision))) {
2432                         vbyte = ha->fcode_revision;
2433                         while (iter <= vend) {
2434                                 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2435                                 iter++;
2436                         }
2437                         ret = QLA_SUCCESS;
2438                 }
2439         } while (0);
2440
2441         if (ret != QLA_SUCCESS)
2442                 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2443 }
2444
2445 int
2446 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2447 {
2448         int ret = QLA_SUCCESS;
2449         uint8_t code_type, last_image;
2450         uint32_t pcihdr, pcids;
2451         uint8_t *dbyte;
2452         uint16_t *dcode;
2453         struct qla_hw_data *ha = vha->hw;
2454
2455         if (!ha->pio_address || !mbuf)
2456                 return QLA_FUNCTION_FAILED;
2457
2458         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2459         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2460         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2461         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2462
2463         qla2x00_flash_enable(ha);
2464
2465         /* Begin with first PCI expansion ROM header. */
2466         pcihdr = 0;
2467         last_image = 1;
2468         do {
2469                 /* Verify PCI expansion ROM header. */
2470                 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2471                     qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2472                         /* No signature */
2473                         DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2474                             "signature.\n"));
2475                         ret = QLA_FUNCTION_FAILED;
2476                         break;
2477                 }
2478
2479                 /* Locate PCI data structure. */
2480                 pcids = pcihdr +
2481                     ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2482                         qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2483
2484                 /* Validate signature of PCI data structure. */
2485                 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2486                     qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2487                     qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2488                     qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2489                         /* Incorrect header. */
2490                         DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2491                             "found pcir_adr=%x.\n", pcids));
2492                         ret = QLA_FUNCTION_FAILED;
2493                         break;
2494                 }
2495
2496                 /* Read version */
2497                 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2498                 switch (code_type) {
2499                 case ROM_CODE_TYPE_BIOS:
2500                         /* Intel x86, PC-AT compatible. */
2501                         ha->bios_revision[0] =
2502                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2503                         ha->bios_revision[1] =
2504                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2505                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2506                             ha->bios_revision[1], ha->bios_revision[0]));
2507                         break;
2508                 case ROM_CODE_TYPE_FCODE:
2509                         /* Open Firmware standard for PCI (FCode). */
2510                         /* Eeeewww... */
2511                         qla2x00_get_fcode_version(ha, pcids);
2512                         break;
2513                 case ROM_CODE_TYPE_EFI:
2514                         /* Extensible Firmware Interface (EFI). */
2515                         ha->efi_revision[0] =
2516                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2517                         ha->efi_revision[1] =
2518                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2519                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2520                             ha->efi_revision[1], ha->efi_revision[0]));
2521                         break;
2522                 default:
2523                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2524                             "type %x at pcids %x.\n", code_type, pcids));
2525                         break;
2526                 }
2527
2528                 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2529
2530                 /* Locate next PCI expansion ROM. */
2531                 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2532                     qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2533         } while (!last_image);
2534
2535         if (IS_QLA2322(ha)) {
2536                 /* Read firmware image information. */
2537                 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2538                 dbyte = mbuf;
2539                 memset(dbyte, 0, 8);
2540                 dcode = (uint16_t *)dbyte;
2541
2542                 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2543                     8);
2544                 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2545                     "flash:\n"));
2546                 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2547
2548                 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2549                     dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2550                     (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2551                     dcode[3] == 0)) {
2552                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2553                             "revision at %x.\n", ha->flt_region_fw * 4));
2554                 } else {
2555                         /* values are in big endian */
2556                         ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2557                         ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2558                         ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2559                 }
2560         }
2561
2562         qla2x00_flash_disable(ha);
2563
2564         return ret;
2565 }
2566
2567 int
2568 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2569 {
2570         int ret = QLA_SUCCESS;
2571         uint32_t pcihdr, pcids;
2572         uint32_t *dcode;
2573         uint8_t *bcode;
2574         uint8_t code_type, last_image;
2575         int i;
2576         struct qla_hw_data *ha = vha->hw;
2577
2578         if (!mbuf)
2579                 return QLA_FUNCTION_FAILED;
2580
2581         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2582         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2583         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2584         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2585
2586         dcode = mbuf;
2587
2588         /* Begin with first PCI expansion ROM header. */
2589         pcihdr = ha->flt_region_boot << 2;
2590         last_image = 1;
2591         do {
2592                 /* Verify PCI expansion ROM header. */
2593                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2594                 bcode = mbuf + (pcihdr % 4);
2595                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2596                         /* No signature */
2597                         DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2598                             "signature.\n"));
2599                         ret = QLA_FUNCTION_FAILED;
2600                         break;
2601                 }
2602
2603                 /* Locate PCI data structure. */
2604                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2605
2606                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2607                 bcode = mbuf + (pcihdr % 4);
2608
2609                 /* Validate signature of PCI data structure. */
2610                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2611                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2612                         /* Incorrect header. */
2613                         DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2614                             "found pcir_adr=%x.\n", pcids));
2615                         ret = QLA_FUNCTION_FAILED;
2616                         break;
2617                 }
2618
2619                 /* Read version */
2620                 code_type = bcode[0x14];
2621                 switch (code_type) {
2622                 case ROM_CODE_TYPE_BIOS:
2623                         /* Intel x86, PC-AT compatible. */
2624                         ha->bios_revision[0] = bcode[0x12];
2625                         ha->bios_revision[1] = bcode[0x13];
2626                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2627                             ha->bios_revision[1], ha->bios_revision[0]));
2628                         break;
2629                 case ROM_CODE_TYPE_FCODE:
2630                         /* Open Firmware standard for PCI (FCode). */
2631                         ha->fcode_revision[0] = bcode[0x12];
2632                         ha->fcode_revision[1] = bcode[0x13];
2633                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
2634                             ha->fcode_revision[1], ha->fcode_revision[0]));
2635                         break;
2636                 case ROM_CODE_TYPE_EFI:
2637                         /* Extensible Firmware Interface (EFI). */
2638                         ha->efi_revision[0] = bcode[0x12];
2639                         ha->efi_revision[1] = bcode[0x13];
2640                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2641                             ha->efi_revision[1], ha->efi_revision[0]));
2642                         break;
2643                 default:
2644                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2645                             "type %x at pcids %x.\n", code_type, pcids));
2646                         break;
2647                 }
2648
2649                 last_image = bcode[0x15] & BIT_7;
2650
2651                 /* Locate next PCI expansion ROM. */
2652                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2653         } while (!last_image);
2654
2655         /* Read firmware image information. */
2656         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2657         dcode = mbuf;
2658
2659         qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2660         for (i = 0; i < 4; i++)
2661                 dcode[i] = be32_to_cpu(dcode[i]);
2662
2663         if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2664             dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2665             (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2666             dcode[3] == 0)) {
2667                 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2668                     "revision at %x.\n", ha->flt_region_fw * 4));
2669         } else {
2670                 ha->fw_revision[0] = dcode[0];
2671                 ha->fw_revision[1] = dcode[1];
2672                 ha->fw_revision[2] = dcode[2];
2673                 ha->fw_revision[3] = dcode[3];
2674         }
2675
2676         return ret;
2677 }
2678
2679 static int
2680 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2681 {
2682         if (pos >= end || *pos != 0x82)
2683                 return 0;
2684
2685         pos += 3 + pos[1];
2686         if (pos >= end || *pos != 0x90)
2687                 return 0;
2688
2689         pos += 3 + pos[1];
2690         if (pos >= end || *pos != 0x78)
2691                 return 0;
2692
2693         return 1;
2694 }
2695
2696 int
2697 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2698 {
2699         struct qla_hw_data *ha = vha->hw;
2700         uint8_t *pos = ha->vpd;
2701         uint8_t *end = pos + ha->vpd_size;
2702         int len = 0;
2703
2704         if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2705                 return 0;
2706
2707         while (pos < end && *pos != 0x78) {
2708                 len = (*pos == 0x82) ? pos[1] : pos[2];
2709
2710                 if (!strncmp(pos, key, strlen(key)))
2711                         break;
2712
2713                 if (*pos != 0x90 && *pos != 0x91)
2714                         pos += len;
2715
2716                 pos += 3;
2717         }
2718
2719         if (pos < end - len && *pos != 0x78)
2720                 return snprintf(str, size, "%.*s", len, pos + 3);
2721
2722         return 0;
2723 }