2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/sched.h>
18 #include <linux/slab.h>
19 #include <linux/dmapool.h>
20 #include <linux/mempool.h>
21 #include <linux/spinlock.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/workqueue.h>
25 #include <linux/firmware.h>
26 #include <linux/aer.h>
27 #include <linux/mutex.h>
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34 #include <scsi/scsi_bsg_fc.h>
37 #define QLA2XXX_DRIVER_NAME "qla2xxx"
40 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
41 * but that's fine as we don't look at the last 24 ones for
44 #define MAILBOX_REGISTER_COUNT_2100 8
45 #define MAILBOX_REGISTER_COUNT 32
47 #define QLA2200A_RISC_ROM_VER 4
51 #include "qla_settings.h"
54 * Data bit definitions
72 #define BIT_16 0x10000
73 #define BIT_17 0x20000
74 #define BIT_18 0x40000
75 #define BIT_19 0x80000
76 #define BIT_20 0x100000
77 #define BIT_21 0x200000
78 #define BIT_22 0x400000
79 #define BIT_23 0x800000
80 #define BIT_24 0x1000000
81 #define BIT_25 0x2000000
82 #define BIT_26 0x4000000
83 #define BIT_27 0x8000000
84 #define BIT_28 0x10000000
85 #define BIT_29 0x20000000
86 #define BIT_30 0x40000000
87 #define BIT_31 0x80000000
89 #define LSB(x) ((uint8_t)(x))
90 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
92 #define LSW(x) ((uint16_t)(x))
93 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
95 #define LSD(x) ((uint32_t)((uint64_t)(x)))
96 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
98 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
104 #define RD_REG_BYTE(addr) readb(addr)
105 #define RD_REG_WORD(addr) readw(addr)
106 #define RD_REG_DWORD(addr) readl(addr)
107 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
108 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
109 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
110 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
111 #define WRT_REG_WORD(addr, data) writew(data,addr)
112 #define WRT_REG_DWORD(addr, data) writel(data,addr)
115 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
118 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
119 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
122 * Fibre Channel device definitions.
124 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
125 #define MAX_FIBRE_DEVICES 512
126 #define MAX_FIBRE_LUNS 0xFFFF
127 #define MAX_RSCN_COUNT 32
128 #define MAX_HOST_COUNT 16
131 * Host adapter default definitions.
133 #define MAX_BUSES 1 /* We only have one bus today */
134 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
135 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
137 #define MAX_LUNS MAX_FIBRE_LUNS
138 #define MAX_CMDS_PER_LUN 255
141 * Fibre Channel device definitions.
143 #define SNS_LAST_LOOP_ID_2100 0xfe
144 #define SNS_LAST_LOOP_ID_2300 0x7ff
146 #define LAST_LOCAL_LOOP_ID 0x7d
147 #define SNS_FL_PORT 0x7e
148 #define FABRIC_CONTROLLER 0x7f
149 #define SIMPLE_NAME_SERVER 0x80
150 #define SNS_FIRST_LOOP_ID 0x81
151 #define MANAGEMENT_SERVER 0xfe
152 #define BROADCAST 0xff
155 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
156 * valid range of an N-PORT id is 0 through 0x7ef.
158 #define NPH_LAST_HANDLE 0x7ef
159 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
160 #define NPH_SNS 0x7fc /* FFFFFC */
161 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
162 #define NPH_F_PORT 0x7fe /* FFFFFE */
163 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
165 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
169 * Timeout timer counts in seconds
171 #define PORT_RETRY_TIME 1
172 #define LOOP_DOWN_TIMEOUT 60
173 #define LOOP_DOWN_TIME 255 /* 240 */
174 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
176 /* Maximum outstanding commands in ISP queues (1-65535) */
177 #define MAX_OUTSTANDING_COMMANDS 1024
179 /* ISP request and response entry counts (37-65535) */
180 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
181 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
182 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
183 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
184 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
185 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
193 struct fc_port *fcport;
196 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
200 uint32_t request_sense_length;
201 uint8_t *request_sense_ptr;
207 * SRB flag definitions
209 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
215 #define SRB_LOGIN_CMD 1
216 #define SRB_LOGOUT_CMD 2
218 struct timer_list timer;
220 void (*free)(srb_t *sp);
221 void (*timeout)(srb_t *sp);
227 #define SRB_LOGIN_RETRIED BIT_0
228 #define SRB_LOGIN_COND_PLOGI BIT_1
229 #define SRB_LOGIN_SKIP_PRLI BIT_2
234 #define SRB_ELS_CMD_RPT 3
235 #define SRB_ELS_CMD_HST 4
241 struct srb_bsg_ctx ctx;
242 struct fc_bsg_job *bsg_job;
251 uint32_t transfer_size;
255 * ISP I/O Register Set structure definitions.
257 struct device_reg_2xxx {
258 uint16_t flash_address; /* Flash BIOS address */
259 uint16_t flash_data; /* Flash BIOS data */
260 uint16_t unused_1[1]; /* Gap */
261 uint16_t ctrl_status; /* Control/Status */
262 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
263 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
264 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
266 uint16_t ictrl; /* Interrupt control */
267 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
268 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
270 uint16_t istatus; /* Interrupt status */
271 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
273 uint16_t semaphore; /* Semaphore */
274 uint16_t nvram; /* NVRAM register. */
275 #define NVR_DESELECT 0
276 #define NVR_BUSY BIT_15
277 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
278 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
279 #define NVR_DATA_IN BIT_3
280 #define NVR_DATA_OUT BIT_2
281 #define NVR_SELECT BIT_1
282 #define NVR_CLOCK BIT_0
284 #define NVR_WAIT_CNT 20000
296 uint16_t unused_2[59]; /* Gap */
297 } __attribute__((packed)) isp2100;
300 uint16_t req_q_in; /* In-Pointer */
301 uint16_t req_q_out; /* Out-Pointer */
303 uint16_t rsp_q_in; /* In-Pointer */
304 uint16_t rsp_q_out; /* Out-Pointer */
306 /* RISC to Host Status */
307 uint32_t host_status;
308 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
309 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
311 /* Host to Host Semaphore */
312 uint16_t host_semaphore;
313 uint16_t unused_3[17]; /* Gap */
347 uint16_t unused_4[10]; /* Gap */
348 } __attribute__((packed)) isp2300;
351 uint16_t fpm_diag_config;
352 uint16_t unused_5[0x4]; /* Gap */
354 uint16_t unused_5_1; /* Gap */
355 uint16_t pcr; /* Processor Control Register. */
356 uint16_t unused_6[0x5]; /* Gap */
357 uint16_t mctr; /* Memory Configuration and Timing. */
358 uint16_t unused_7[0x3]; /* Gap */
359 uint16_t fb_cmd_2100; /* Unused on 23XX */
360 uint16_t unused_8[0x3]; /* Gap */
361 uint16_t hccr; /* Host command & control register. */
362 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
363 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
365 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
366 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
367 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
368 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
369 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
370 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
371 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
372 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
374 uint16_t unused_9[5]; /* Gap */
375 uint16_t gpiod; /* GPIO Data register. */
376 uint16_t gpioe; /* GPIO Enable register. */
377 #define GPIO_LED_MASK 0x00C0
378 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
379 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
380 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
381 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
382 #define GPIO_LED_ALL_OFF 0x0000
383 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
384 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
388 uint16_t unused_10[8]; /* Gap */
404 uint16_t mailbox23; /* Also probe reg. */
405 } __attribute__((packed)) isp2200;
409 struct device_reg_25xxmq {
417 struct device_reg_2xxx isp;
418 struct device_reg_24xx isp24;
419 struct device_reg_25xxmq isp25mq;
422 #define ISP_REQ_Q_IN(ha, reg) \
423 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
424 &(reg)->u.isp2100.mailbox4 : \
425 &(reg)->u.isp2300.req_q_in)
426 #define ISP_REQ_Q_OUT(ha, reg) \
427 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
428 &(reg)->u.isp2100.mailbox4 : \
429 &(reg)->u.isp2300.req_q_out)
430 #define ISP_RSP_Q_IN(ha, reg) \
431 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
432 &(reg)->u.isp2100.mailbox5 : \
433 &(reg)->u.isp2300.rsp_q_in)
434 #define ISP_RSP_Q_OUT(ha, reg) \
435 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
436 &(reg)->u.isp2100.mailbox5 : \
437 &(reg)->u.isp2300.rsp_q_out)
439 #define MAILBOX_REG(ha, reg, num) \
440 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
442 &(reg)->u.isp2100.mailbox0 + (num) : \
443 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
444 &(reg)->u.isp2300.mailbox0 + (num))
445 #define RD_MAILBOX_REG(ha, reg, num) \
446 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
447 #define WRT_MAILBOX_REG(ha, reg, num, data) \
448 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
450 #define FB_CMD_REG(ha, reg) \
451 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
452 &(reg)->fb_cmd_2100 : \
453 &(reg)->u.isp2300.fb_cmd)
454 #define RD_FB_CMD_REG(ha, reg) \
455 RD_REG_WORD(FB_CMD_REG(ha, reg))
456 #define WRT_FB_CMD_REG(ha, reg, data) \
457 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
460 uint32_t out_mb; /* outbound from driver */
461 uint32_t in_mb; /* Incoming from RISC */
462 uint16_t mb[MAILBOX_REGISTER_COUNT];
467 #define MBX_DMA_IN BIT_0
468 #define MBX_DMA_OUT BIT_1
469 #define IOCTL_CMD BIT_2
472 #define MBX_TOV_SECONDS 30
475 * ISP product identification definitions in mailboxes after reset.
477 #define PROD_ID_1 0x4953
478 #define PROD_ID_2 0x0000
479 #define PROD_ID_2a 0x5020
480 #define PROD_ID_3 0x2020
483 * ISP mailbox Self-Test status codes
485 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
486 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
487 #define MBS_BUSY 4 /* Busy. */
490 * ISP mailbox command complete status codes
492 #define MBS_COMMAND_COMPLETE 0x4000
493 #define MBS_INVALID_COMMAND 0x4001
494 #define MBS_HOST_INTERFACE_ERROR 0x4002
495 #define MBS_TEST_FAILED 0x4003
496 #define MBS_COMMAND_ERROR 0x4005
497 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
498 #define MBS_PORT_ID_USED 0x4007
499 #define MBS_LOOP_ID_USED 0x4008
500 #define MBS_ALL_IDS_IN_USE 0x4009
501 #define MBS_NOT_LOGGED_IN 0x400A
502 #define MBS_LINK_DOWN_ERROR 0x400B
503 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
506 * ISP mailbox asynchronous event status codes
508 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
509 #define MBA_RESET 0x8001 /* Reset Detected. */
510 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
511 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
512 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
513 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
514 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
516 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
517 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
518 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
519 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
520 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
521 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
522 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
523 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
524 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
525 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
526 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
527 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
528 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
529 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
530 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
531 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
533 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
534 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
535 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
536 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
537 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
538 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
539 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
540 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
541 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
542 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
543 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
544 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
545 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
546 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
548 /* ISP mailbox loopback echo diagnostic error code */
549 #define MBS_LB_RESET 0x17
551 * Firmware options 1, 2, 3.
553 #define FO1_AE_ON_LIPF8 BIT_0
554 #define FO1_AE_ALL_LIP_RESET BIT_1
555 #define FO1_CTIO_RETRY BIT_3
556 #define FO1_DISABLE_LIP_F7_SW BIT_4
557 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
558 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
559 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
560 #define FO1_SET_EMPHASIS_SWING BIT_8
561 #define FO1_AE_AUTO_BYPASS BIT_9
562 #define FO1_ENABLE_PURE_IOCB BIT_10
563 #define FO1_AE_PLOGI_RJT BIT_11
564 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
565 #define FO1_AE_QUEUE_FULL BIT_13
567 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
568 #define FO2_REV_LOOPBACK BIT_1
570 #define FO3_ENABLE_EMERG_IOCB BIT_0
571 #define FO3_AE_RND_ERROR BIT_1
573 /* 24XX additional firmware options */
574 #define ADD_FO_COUNT 3
575 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
576 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
578 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
580 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
583 * ISP mailbox commands
585 #define MBC_LOAD_RAM 1 /* Load RAM. */
586 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
587 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
588 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
589 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
590 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
591 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
592 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
593 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
594 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
595 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
596 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
597 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
598 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
599 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
600 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
601 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
602 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
603 #define MBC_RESET 0x18 /* Reset. */
604 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
605 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
606 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
607 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
608 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
609 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
610 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
611 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
612 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
613 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
614 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
615 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
616 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
617 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
618 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
619 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
620 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
621 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
622 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
623 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
624 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
625 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
626 /* Initialization Procedure */
627 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
628 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
629 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
630 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
631 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
632 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
633 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
634 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
635 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
636 #define MBC_LIP_RESET 0x6c /* LIP reset. */
637 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
639 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
640 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
641 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
642 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
643 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
644 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
645 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
646 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
647 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
648 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
649 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
652 * ISP24xx mailbox commands
654 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
655 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
656 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
657 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
658 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
659 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
660 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
661 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
662 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
663 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
664 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
665 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
666 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
667 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
668 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
669 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
671 /* Firmware return data sizes */
672 #define FCAL_MAP_SIZE 128
674 /* Mailbox bit definitions for out_mb and in_mb */
675 #define MBX_31 BIT_31
676 #define MBX_30 BIT_30
677 #define MBX_29 BIT_29
678 #define MBX_28 BIT_28
679 #define MBX_27 BIT_27
680 #define MBX_26 BIT_26
681 #define MBX_25 BIT_25
682 #define MBX_24 BIT_24
683 #define MBX_23 BIT_23
684 #define MBX_22 BIT_22
685 #define MBX_21 BIT_21
686 #define MBX_20 BIT_20
687 #define MBX_19 BIT_19
688 #define MBX_18 BIT_18
689 #define MBX_17 BIT_17
690 #define MBX_16 BIT_16
691 #define MBX_15 BIT_15
692 #define MBX_14 BIT_14
693 #define MBX_13 BIT_13
694 #define MBX_12 BIT_12
695 #define MBX_11 BIT_11
696 #define MBX_10 BIT_10
709 * Firmware state codes from get firmware state mailbox command
711 #define FSTATE_CONFIG_WAIT 0
712 #define FSTATE_WAIT_AL_PA 1
713 #define FSTATE_WAIT_LOGIN 2
714 #define FSTATE_READY 3
715 #define FSTATE_LOSS_OF_SYNC 4
716 #define FSTATE_ERROR 5
717 #define FSTATE_REINIT 6
718 #define FSTATE_NON_PART 7
720 #define FSTATE_CONFIG_CORRECT 0
721 #define FSTATE_P2P_RCV_LIP 1
722 #define FSTATE_P2P_CHOOSE_LOOP 2
723 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
724 #define FSTATE_FATAL_ERROR 4
725 #define FSTATE_LOOP_BACK_CONN 5
728 * Port Database structure definition
729 * Little endian except where noted.
731 #define PORT_DATABASE_SIZE 128 /* bytes */
735 uint8_t master_state;
738 uint8_t hard_address;
741 uint8_t node_name[WWN_SIZE];
742 uint8_t port_name[WWN_SIZE];
743 uint16_t execution_throttle;
744 uint16_t execution_count;
747 uint16_t resource_allocation;
748 uint16_t current_allocation;
751 uint16_t transmit_execution_list_next;
752 uint16_t transmit_execution_list_previous;
753 uint16_t common_features;
754 uint16_t total_concurrent_sequences;
755 uint16_t RO_by_information_category;
758 uint16_t receive_data_size;
759 uint16_t concurrent_sequences;
760 uint16_t open_sequences_per_exchange;
761 uint16_t lun_abort_flags;
762 uint16_t lun_stop_flags;
763 uint16_t stop_queue_head;
764 uint16_t stop_queue_tail;
765 uint16_t port_retry_timer;
766 uint16_t next_sequence_id;
767 uint16_t frame_count;
768 uint16_t PRLI_payload_length;
769 uint8_t prli_svc_param_word_0[2]; /* Big endian */
770 /* Bits 15-0 of word 0 */
771 uint8_t prli_svc_param_word_3[2]; /* Big endian */
772 /* Bits 15-0 of word 3 */
774 uint16_t extended_lun_info_list_pointer;
775 uint16_t extended_lun_stop_list_pointer;
779 * Port database slave/master states
781 #define PD_STATE_DISCOVERY 0
782 #define PD_STATE_WAIT_DISCOVERY_ACK 1
783 #define PD_STATE_PORT_LOGIN 2
784 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
785 #define PD_STATE_PROCESS_LOGIN 4
786 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
787 #define PD_STATE_PORT_LOGGED_IN 6
788 #define PD_STATE_PORT_UNAVAILABLE 7
789 #define PD_STATE_PROCESS_LOGOUT 8
790 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
791 #define PD_STATE_PORT_LOGOUT 10
792 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
795 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
796 #define QLA_ZIO_DISABLED 0
797 #define QLA_ZIO_DEFAULT_TIMER 2
800 * ISP Initialization Control Block.
801 * Little endian except where noted.
803 #define ICB_VERSION 1
809 * LSB BIT 0 = Enable Hard Loop Id
810 * LSB BIT 1 = Enable Fairness
811 * LSB BIT 2 = Enable Full-Duplex
812 * LSB BIT 3 = Enable Fast Posting
813 * LSB BIT 4 = Enable Target Mode
814 * LSB BIT 5 = Disable Initiator Mode
815 * LSB BIT 6 = Enable ADISC
816 * LSB BIT 7 = Enable Target Inquiry Data
818 * MSB BIT 0 = Enable PDBC Notify
819 * MSB BIT 1 = Non Participating LIP
820 * MSB BIT 2 = Descending Loop ID Search
821 * MSB BIT 3 = Acquire Loop ID in LIPA
822 * MSB BIT 4 = Stop PortQ on Full Status
823 * MSB BIT 5 = Full Login after LIP
824 * MSB BIT 6 = Node Name Option
825 * MSB BIT 7 = Ext IFWCB enable bit
827 uint8_t firmware_options[2];
829 uint16_t frame_payload_size;
830 uint16_t max_iocb_allocation;
831 uint16_t execution_throttle;
833 uint8_t retry_delay; /* unused */
834 uint8_t port_name[WWN_SIZE]; /* Big endian. */
835 uint16_t hard_address;
836 uint8_t inquiry_data;
837 uint8_t login_timeout;
838 uint8_t node_name[WWN_SIZE]; /* Big endian. */
840 uint16_t request_q_outpointer;
841 uint16_t response_q_inpointer;
842 uint16_t request_q_length;
843 uint16_t response_q_length;
844 uint32_t request_q_address[2];
845 uint32_t response_q_address[2];
847 uint16_t lun_enables;
848 uint8_t command_resource_count;
849 uint8_t immediate_notify_resource_count;
851 uint8_t reserved_2[2];
854 * LSB BIT 0 = Timer Operation mode bit 0
855 * LSB BIT 1 = Timer Operation mode bit 1
856 * LSB BIT 2 = Timer Operation mode bit 2
857 * LSB BIT 3 = Timer Operation mode bit 3
858 * LSB BIT 4 = Init Config Mode bit 0
859 * LSB BIT 5 = Init Config Mode bit 1
860 * LSB BIT 6 = Init Config Mode bit 2
861 * LSB BIT 7 = Enable Non part on LIHA failure
863 * MSB BIT 0 = Enable class 2
864 * MSB BIT 1 = Enable ACK0
867 * MSB BIT 4 = FC Tape Enable
868 * MSB BIT 5 = Enable FC Confirm
869 * MSB BIT 6 = Enable command queuing in target mode
870 * MSB BIT 7 = No Logo On Link Down
872 uint8_t add_firmware_options[2];
874 uint8_t response_accumulation_timer;
875 uint8_t interrupt_delay_timer;
878 * LSB BIT 0 = Enable Read xfr_rdy
879 * LSB BIT 1 = Soft ID only
882 * LSB BIT 4 = FCP RSP Payload [0]
883 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
884 * LSB BIT 6 = Enable Out-of-Order frame handling
885 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
887 * MSB BIT 0 = Sbus enable - 2300
891 * MSB BIT 4 = LED mode
892 * MSB BIT 5 = enable 50 ohm termination
893 * MSB BIT 6 = Data Rate (2300 only)
894 * MSB BIT 7 = Data Rate (2300 only)
896 uint8_t special_options[2];
898 uint8_t reserved_3[26];
902 * Get Link Status mailbox command return buffer.
904 #define GLSO_SEND_RPS BIT_0
905 #define GLSO_USE_DID BIT_3
907 struct link_statistics {
908 uint32_t link_fail_cnt;
909 uint32_t loss_sync_cnt;
910 uint32_t loss_sig_cnt;
911 uint32_t prim_seq_err_cnt;
912 uint32_t inval_xmit_word_cnt;
913 uint32_t inval_crc_cnt;
915 uint32_t unused1[0x1a];
918 uint32_t dumped_frames;
924 * NVRAM Command values.
926 #define NV_START_BIT BIT_2
927 #define NV_WRITE_OP (BIT_26+BIT_24)
928 #define NV_READ_OP (BIT_26+BIT_25)
929 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
930 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
931 #define NV_DELAY_COUNT 10
934 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
941 uint8_t nvram_version;
945 * NVRAM RISC parameter block
947 uint8_t parameter_block_version;
951 * LSB BIT 0 = Enable Hard Loop Id
952 * LSB BIT 1 = Enable Fairness
953 * LSB BIT 2 = Enable Full-Duplex
954 * LSB BIT 3 = Enable Fast Posting
955 * LSB BIT 4 = Enable Target Mode
956 * LSB BIT 5 = Disable Initiator Mode
957 * LSB BIT 6 = Enable ADISC
958 * LSB BIT 7 = Enable Target Inquiry Data
960 * MSB BIT 0 = Enable PDBC Notify
961 * MSB BIT 1 = Non Participating LIP
962 * MSB BIT 2 = Descending Loop ID Search
963 * MSB BIT 3 = Acquire Loop ID in LIPA
964 * MSB BIT 4 = Stop PortQ on Full Status
965 * MSB BIT 5 = Full Login after LIP
966 * MSB BIT 6 = Node Name Option
967 * MSB BIT 7 = Ext IFWCB enable bit
969 uint8_t firmware_options[2];
971 uint16_t frame_payload_size;
972 uint16_t max_iocb_allocation;
973 uint16_t execution_throttle;
975 uint8_t retry_delay; /* unused */
976 uint8_t port_name[WWN_SIZE]; /* Big endian. */
977 uint16_t hard_address;
978 uint8_t inquiry_data;
979 uint8_t login_timeout;
980 uint8_t node_name[WWN_SIZE]; /* Big endian. */
983 * LSB BIT 0 = Timer Operation mode bit 0
984 * LSB BIT 1 = Timer Operation mode bit 1
985 * LSB BIT 2 = Timer Operation mode bit 2
986 * LSB BIT 3 = Timer Operation mode bit 3
987 * LSB BIT 4 = Init Config Mode bit 0
988 * LSB BIT 5 = Init Config Mode bit 1
989 * LSB BIT 6 = Init Config Mode bit 2
990 * LSB BIT 7 = Enable Non part on LIHA failure
992 * MSB BIT 0 = Enable class 2
993 * MSB BIT 1 = Enable ACK0
996 * MSB BIT 4 = FC Tape Enable
997 * MSB BIT 5 = Enable FC Confirm
998 * MSB BIT 6 = Enable command queuing in target mode
999 * MSB BIT 7 = No Logo On Link Down
1001 uint8_t add_firmware_options[2];
1003 uint8_t response_accumulation_timer;
1004 uint8_t interrupt_delay_timer;
1007 * LSB BIT 0 = Enable Read xfr_rdy
1008 * LSB BIT 1 = Soft ID only
1011 * LSB BIT 4 = FCP RSP Payload [0]
1012 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1013 * LSB BIT 6 = Enable Out-of-Order frame handling
1014 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1016 * MSB BIT 0 = Sbus enable - 2300
1020 * MSB BIT 4 = LED mode
1021 * MSB BIT 5 = enable 50 ohm termination
1022 * MSB BIT 6 = Data Rate (2300 only)
1023 * MSB BIT 7 = Data Rate (2300 only)
1025 uint8_t special_options[2];
1027 /* Reserved for expanded RISC parameter block */
1028 uint8_t reserved_2[22];
1031 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1032 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1033 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1034 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1035 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1036 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1037 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1038 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1040 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1041 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1042 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1043 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1044 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1045 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1046 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1047 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1049 * LSB BIT 0 = Output Swing 1G bit 0
1050 * LSB BIT 1 = Output Swing 1G bit 1
1051 * LSB BIT 2 = Output Swing 1G bit 2
1052 * LSB BIT 3 = Output Emphasis 1G bit 0
1053 * LSB BIT 4 = Output Emphasis 1G bit 1
1054 * LSB BIT 5 = Output Swing 2G bit 0
1055 * LSB BIT 6 = Output Swing 2G bit 1
1056 * LSB BIT 7 = Output Swing 2G bit 2
1058 * MSB BIT 0 = Output Emphasis 2G bit 0
1059 * MSB BIT 1 = Output Emphasis 2G bit 1
1060 * MSB BIT 2 = Output Enable
1067 uint8_t seriallink_options[4];
1070 * NVRAM host parameter block
1072 * LSB BIT 0 = Enable spinup delay
1073 * LSB BIT 1 = Disable BIOS
1074 * LSB BIT 2 = Enable Memory Map BIOS
1075 * LSB BIT 3 = Enable Selectable Boot
1076 * LSB BIT 4 = Disable RISC code load
1077 * LSB BIT 5 = Set cache line size 1
1078 * LSB BIT 6 = PCI Parity Disable
1079 * LSB BIT 7 = Enable extended logging
1081 * MSB BIT 0 = Enable 64bit addressing
1082 * MSB BIT 1 = Enable lip reset
1083 * MSB BIT 2 = Enable lip full login
1084 * MSB BIT 3 = Enable target reset
1085 * MSB BIT 4 = Enable database storage
1086 * MSB BIT 5 = Enable cache flush read
1087 * MSB BIT 6 = Enable database load
1088 * MSB BIT 7 = Enable alternate WWN
1092 uint8_t boot_node_name[WWN_SIZE];
1093 uint8_t boot_lun_number;
1094 uint8_t reset_delay;
1095 uint8_t port_down_retry_count;
1096 uint8_t boot_id_number;
1097 uint16_t max_luns_per_target;
1098 uint8_t fcode_boot_port_name[WWN_SIZE];
1099 uint8_t alternate_port_name[WWN_SIZE];
1100 uint8_t alternate_node_name[WWN_SIZE];
1103 * BIT 0 = Selective Login
1104 * BIT 1 = Alt-Boot Enable
1106 * BIT 3 = Boot Order List
1108 * BIT 5 = Selective LUN
1112 uint8_t efi_parameters;
1114 uint8_t link_down_timeout;
1116 uint8_t adapter_id[16];
1118 uint8_t alt1_boot_node_name[WWN_SIZE];
1119 uint16_t alt1_boot_lun_number;
1120 uint8_t alt2_boot_node_name[WWN_SIZE];
1121 uint16_t alt2_boot_lun_number;
1122 uint8_t alt3_boot_node_name[WWN_SIZE];
1123 uint16_t alt3_boot_lun_number;
1124 uint8_t alt4_boot_node_name[WWN_SIZE];
1125 uint16_t alt4_boot_lun_number;
1126 uint8_t alt5_boot_node_name[WWN_SIZE];
1127 uint16_t alt5_boot_lun_number;
1128 uint8_t alt6_boot_node_name[WWN_SIZE];
1129 uint16_t alt6_boot_lun_number;
1130 uint8_t alt7_boot_node_name[WWN_SIZE];
1131 uint16_t alt7_boot_lun_number;
1133 uint8_t reserved_3[2];
1135 /* Offset 200-215 : Model Number */
1136 uint8_t model_number[16];
1138 /* OEM related items */
1139 uint8_t oem_specific[16];
1142 * NVRAM Adapter Features offset 232-239
1144 * LSB BIT 0 = External GBIC
1145 * LSB BIT 1 = Risc RAM parity
1146 * LSB BIT 2 = Buffer Plus Module
1147 * LSB BIT 3 = Multi Chip Adapter
1148 * LSB BIT 4 = Internal connector
1162 uint8_t adapter_features[2];
1164 uint8_t reserved_4[16];
1166 /* Subsystem vendor ID for ISP2200 */
1167 uint16_t subsystem_vendor_id_2200;
1169 /* Subsystem device ID for ISP2200 */
1170 uint16_t subsystem_device_id_2200;
1177 * ISP queue - response queue entry definition.
1182 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1193 #define SET_TARGET_ID(ha, to, from) \
1195 if (HAS_EXTENDED_IDS(ha)) \
1196 to.extended = cpu_to_le16(from); \
1198 to.id.standard = (uint8_t)from; \
1202 * ISP queue - command entry structure definition.
1204 #define COMMAND_TYPE 0x11 /* Command entry */
1206 uint8_t entry_type; /* Entry type. */
1207 uint8_t entry_count; /* Entry count. */
1208 uint8_t sys_define; /* System defined. */
1209 uint8_t entry_status; /* Entry Status. */
1210 uint32_t handle; /* System handle. */
1211 target_id_t target; /* SCSI ID */
1212 uint16_t lun; /* SCSI LUN */
1213 uint16_t control_flags; /* Control flags. */
1214 #define CF_WRITE BIT_6
1215 #define CF_READ BIT_5
1216 #define CF_SIMPLE_TAG BIT_3
1217 #define CF_ORDERED_TAG BIT_2
1218 #define CF_HEAD_TAG BIT_1
1219 uint16_t reserved_1;
1220 uint16_t timeout; /* Command timeout. */
1221 uint16_t dseg_count; /* Data segment count. */
1222 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1223 uint32_t byte_count; /* Total byte count. */
1224 uint32_t dseg_0_address; /* Data segment 0 address. */
1225 uint32_t dseg_0_length; /* Data segment 0 length. */
1226 uint32_t dseg_1_address; /* Data segment 1 address. */
1227 uint32_t dseg_1_length; /* Data segment 1 length. */
1228 uint32_t dseg_2_address; /* Data segment 2 address. */
1229 uint32_t dseg_2_length; /* Data segment 2 length. */
1233 * ISP queue - 64-Bit addressing, command entry structure definition.
1235 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1237 uint8_t entry_type; /* Entry type. */
1238 uint8_t entry_count; /* Entry count. */
1239 uint8_t sys_define; /* System defined. */
1240 uint8_t entry_status; /* Entry Status. */
1241 uint32_t handle; /* System handle. */
1242 target_id_t target; /* SCSI ID */
1243 uint16_t lun; /* SCSI LUN */
1244 uint16_t control_flags; /* Control flags. */
1245 uint16_t reserved_1;
1246 uint16_t timeout; /* Command timeout. */
1247 uint16_t dseg_count; /* Data segment count. */
1248 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1249 uint32_t byte_count; /* Total byte count. */
1250 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1251 uint32_t dseg_0_length; /* Data segment 0 length. */
1252 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1253 uint32_t dseg_1_length; /* Data segment 1 length. */
1254 } cmd_a64_entry_t, request_t;
1257 * ISP queue - continuation entry structure definition.
1259 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1261 uint8_t entry_type; /* Entry type. */
1262 uint8_t entry_count; /* Entry count. */
1263 uint8_t sys_define; /* System defined. */
1264 uint8_t entry_status; /* Entry Status. */
1266 uint32_t dseg_0_address; /* Data segment 0 address. */
1267 uint32_t dseg_0_length; /* Data segment 0 length. */
1268 uint32_t dseg_1_address; /* Data segment 1 address. */
1269 uint32_t dseg_1_length; /* Data segment 1 length. */
1270 uint32_t dseg_2_address; /* Data segment 2 address. */
1271 uint32_t dseg_2_length; /* Data segment 2 length. */
1272 uint32_t dseg_3_address; /* Data segment 3 address. */
1273 uint32_t dseg_3_length; /* Data segment 3 length. */
1274 uint32_t dseg_4_address; /* Data segment 4 address. */
1275 uint32_t dseg_4_length; /* Data segment 4 length. */
1276 uint32_t dseg_5_address; /* Data segment 5 address. */
1277 uint32_t dseg_5_length; /* Data segment 5 length. */
1278 uint32_t dseg_6_address; /* Data segment 6 address. */
1279 uint32_t dseg_6_length; /* Data segment 6 length. */
1283 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1285 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1287 uint8_t entry_type; /* Entry type. */
1288 uint8_t entry_count; /* Entry count. */
1289 uint8_t sys_define; /* System defined. */
1290 uint8_t entry_status; /* Entry Status. */
1291 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1292 uint32_t dseg_0_length; /* Data segment 0 length. */
1293 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1294 uint32_t dseg_1_length; /* Data segment 1 length. */
1295 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1296 uint32_t dseg_2_length; /* Data segment 2 length. */
1297 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1298 uint32_t dseg_3_length; /* Data segment 3 length. */
1299 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1300 uint32_t dseg_4_length; /* Data segment 4 length. */
1304 * ISP queue - status entry structure definition.
1306 #define STATUS_TYPE 0x03 /* Status entry. */
1308 uint8_t entry_type; /* Entry type. */
1309 uint8_t entry_count; /* Entry count. */
1310 uint8_t sys_define; /* System defined. */
1311 uint8_t entry_status; /* Entry Status. */
1312 uint32_t handle; /* System handle. */
1313 uint16_t scsi_status; /* SCSI status. */
1314 uint16_t comp_status; /* Completion status. */
1315 uint16_t state_flags; /* State flags. */
1316 uint16_t status_flags; /* Status flags. */
1317 uint16_t rsp_info_len; /* Response Info Length. */
1318 uint16_t req_sense_length; /* Request sense data length. */
1319 uint32_t residual_length; /* Residual transfer length. */
1320 uint8_t rsp_info[8]; /* FCP response information. */
1321 uint8_t req_sense_data[32]; /* Request sense data. */
1325 * Status entry entry status
1327 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1328 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1329 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1330 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1331 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1332 #define RF_BUSY BIT_1 /* Busy */
1333 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1334 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1335 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1339 * Status entry SCSI status bit definitions.
1341 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1342 #define SS_RESIDUAL_UNDER BIT_11
1343 #define SS_RESIDUAL_OVER BIT_10
1344 #define SS_SENSE_LEN_VALID BIT_9
1345 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1347 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1348 #define SS_BUSY_CONDITION BIT_3
1349 #define SS_CONDITION_MET BIT_2
1350 #define SS_CHECK_CONDITION BIT_1
1353 * Status entry completion status
1355 #define CS_COMPLETE 0x0 /* No errors */
1356 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1357 #define CS_DMA 0x2 /* A DMA direction error. */
1358 #define CS_TRANSPORT 0x3 /* Transport error. */
1359 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1360 #define CS_ABORTED 0x5 /* System aborted command. */
1361 #define CS_TIMEOUT 0x6 /* Timeout error. */
1362 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1364 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1365 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1366 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1367 /* (selection timeout) */
1368 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1369 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1370 #define CS_PORT_BUSY 0x2B /* Port Busy */
1371 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1372 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1373 #define CS_UNKNOWN 0x81 /* Driver defined */
1374 #define CS_RETRY 0x82 /* Driver defined */
1375 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1378 * Status entry status flags
1380 #define SF_ABTS_TERMINATED BIT_10
1381 #define SF_LOGOUT_SENT BIT_13
1384 * ISP queue - status continuation entry structure definition.
1386 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1388 uint8_t entry_type; /* Entry type. */
1389 uint8_t entry_count; /* Entry count. */
1390 uint8_t sys_define; /* System defined. */
1391 uint8_t entry_status; /* Entry Status. */
1392 uint8_t data[60]; /* data */
1396 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1397 * structure definition.
1399 #define STATUS_TYPE_21 0x21 /* Status entry. */
1401 uint8_t entry_type; /* Entry type. */
1402 uint8_t entry_count; /* Entry count. */
1403 uint8_t handle_count; /* Handle count. */
1404 uint8_t entry_status; /* Entry Status. */
1405 uint32_t handle[15]; /* System handles. */
1409 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1410 * structure definition.
1412 #define STATUS_TYPE_22 0x22 /* Status entry. */
1414 uint8_t entry_type; /* Entry type. */
1415 uint8_t entry_count; /* Entry count. */
1416 uint8_t handle_count; /* Handle count. */
1417 uint8_t entry_status; /* Entry Status. */
1418 uint16_t handle[30]; /* System handles. */
1422 * ISP queue - marker entry structure definition.
1424 #define MARKER_TYPE 0x04 /* Marker entry. */
1426 uint8_t entry_type; /* Entry type. */
1427 uint8_t entry_count; /* Entry count. */
1428 uint8_t handle_count; /* Handle count. */
1429 uint8_t entry_status; /* Entry Status. */
1430 uint32_t sys_define_2; /* System defined. */
1431 target_id_t target; /* SCSI ID */
1432 uint8_t modifier; /* Modifier (7-0). */
1433 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1434 #define MK_SYNC_ID 1 /* Synchronize ID */
1435 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1436 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1437 /* clear port changed, */
1438 /* use sequence number. */
1440 uint16_t sequence_number; /* Sequence number of event */
1441 uint16_t lun; /* SCSI LUN */
1442 uint8_t reserved_2[48];
1446 * ISP queue - Management Server entry structure definition.
1448 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1450 uint8_t entry_type; /* Entry type. */
1451 uint8_t entry_count; /* Entry count. */
1452 uint8_t handle_count; /* Handle count. */
1453 uint8_t entry_status; /* Entry Status. */
1454 uint32_t handle1; /* System handle. */
1455 target_id_t loop_id;
1457 uint16_t control_flags; /* Control flags. */
1460 uint16_t cmd_dsd_count;
1461 uint16_t total_dsd_count;
1467 uint32_t rsp_bytecount;
1468 uint32_t req_bytecount;
1469 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1470 uint32_t dseg_req_length; /* Data segment 0 length. */
1471 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1472 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1477 * ISP queue - Mailbox Command entry structure definition.
1479 #define MBX_IOCB_TYPE 0x39
1482 uint8_t entry_count;
1483 uint8_t sys_define1;
1484 /* Use sys_define1 for source type */
1485 #define SOURCE_SCSI 0x00
1486 #define SOURCE_IP 0x01
1487 #define SOURCE_VI 0x02
1488 #define SOURCE_SCTP 0x03
1489 #define SOURCE_MP 0x04
1490 #define SOURCE_MPIOCTL 0x05
1491 #define SOURCE_ASYNC_IOCB 0x07
1493 uint8_t entry_status;
1496 target_id_t loop_id;
1499 uint16_t state_flags;
1500 uint16_t status_flags;
1502 uint32_t sys_define2[2];
1512 uint32_t reserved_2[2];
1513 uint8_t node_name[WWN_SIZE];
1514 uint8_t port_name[WWN_SIZE];
1518 * ISP request and response queue entry sizes
1520 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1521 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1525 * 24 bit port ID type definition.
1535 #elif defined(__LITTLE_ENDIAN)
1540 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1545 #define INVALID_PORT_ID 0xFFFFFF
1548 * Switch info gathering structure.
1552 uint8_t node_name[WWN_SIZE];
1553 uint8_t port_name[WWN_SIZE];
1554 uint8_t fabric_port_name[WWN_SIZE];
1559 * Fibre channel port type.
1571 * Fibre channel port structure.
1573 typedef struct fc_port {
1574 struct list_head list;
1575 struct scsi_qla_host *vha;
1577 uint8_t node_name[WWN_SIZE];
1578 uint8_t port_name[WWN_SIZE];
1581 uint16_t old_loop_id;
1585 uint8_t fabric_port_name[WWN_SIZE];
1588 fc_port_type_t port_type;
1593 int port_login_retry_count;
1595 atomic_t port_down_timer;
1597 struct fc_rport *rport, *drport;
1598 u32 supported_classes;
1604 * Fibre channel port/lun states.
1606 #define FCS_UNCONFIGURED 1
1607 #define FCS_DEVICE_DEAD 2
1608 #define FCS_DEVICE_LOST 3
1609 #define FCS_ONLINE 4
1614 #define FCF_FABRIC_DEVICE BIT_0
1615 #define FCF_LOGIN_NEEDED BIT_1
1616 #define FCF_FCP2_DEVICE BIT_2
1618 /* No loop ID flag. */
1619 #define FC_NO_LOOP_ID 0x1000
1624 * NOTE: All structures are big-endian in form.
1627 #define CT_REJECT_RESPONSE 0x8001
1628 #define CT_ACCEPT_RESPONSE 0x8002
1629 #define CT_REASON_INVALID_COMMAND_CODE 0x01
1630 #define CT_REASON_CANNOT_PERFORM 0x09
1631 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1632 #define CT_EXPL_ALREADY_REGISTERED 0x10
1634 #define NS_N_PORT_TYPE 0x01
1635 #define NS_NL_PORT_TYPE 0x02
1636 #define NS_NX_PORT_TYPE 0x7F
1638 #define GA_NXT_CMD 0x100
1639 #define GA_NXT_REQ_SIZE (16 + 4)
1640 #define GA_NXT_RSP_SIZE (16 + 620)
1642 #define GID_PT_CMD 0x1A1
1643 #define GID_PT_REQ_SIZE (16 + 4)
1644 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1646 #define GPN_ID_CMD 0x112
1647 #define GPN_ID_REQ_SIZE (16 + 4)
1648 #define GPN_ID_RSP_SIZE (16 + 8)
1650 #define GNN_ID_CMD 0x113
1651 #define GNN_ID_REQ_SIZE (16 + 4)
1652 #define GNN_ID_RSP_SIZE (16 + 8)
1654 #define GFT_ID_CMD 0x117
1655 #define GFT_ID_REQ_SIZE (16 + 4)
1656 #define GFT_ID_RSP_SIZE (16 + 32)
1658 #define RFT_ID_CMD 0x217
1659 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1660 #define RFT_ID_RSP_SIZE 16
1662 #define RFF_ID_CMD 0x21F
1663 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1664 #define RFF_ID_RSP_SIZE 16
1666 #define RNN_ID_CMD 0x213
1667 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1668 #define RNN_ID_RSP_SIZE 16
1670 #define RSNN_NN_CMD 0x239
1671 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1672 #define RSNN_NN_RSP_SIZE 16
1674 #define GFPN_ID_CMD 0x11C
1675 #define GFPN_ID_REQ_SIZE (16 + 4)
1676 #define GFPN_ID_RSP_SIZE (16 + 8)
1678 #define GPSC_CMD 0x127
1679 #define GPSC_REQ_SIZE (16 + 8)
1680 #define GPSC_RSP_SIZE (16 + 2 + 2)
1684 * HBA attribute types.
1686 #define FDMI_HBA_ATTR_COUNT 9
1687 #define FDMI_HBA_NODE_NAME 1
1688 #define FDMI_HBA_MANUFACTURER 2
1689 #define FDMI_HBA_SERIAL_NUMBER 3
1690 #define FDMI_HBA_MODEL 4
1691 #define FDMI_HBA_MODEL_DESCRIPTION 5
1692 #define FDMI_HBA_HARDWARE_VERSION 6
1693 #define FDMI_HBA_DRIVER_VERSION 7
1694 #define FDMI_HBA_OPTION_ROM_VERSION 8
1695 #define FDMI_HBA_FIRMWARE_VERSION 9
1696 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1697 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1699 struct ct_fdmi_hba_attr {
1703 uint8_t node_name[WWN_SIZE];
1704 uint8_t manufacturer[32];
1705 uint8_t serial_num[8];
1707 uint8_t model_desc[80];
1708 uint8_t hw_version[16];
1709 uint8_t driver_version[32];
1710 uint8_t orom_version[16];
1711 uint8_t fw_version[16];
1712 uint8_t os_version[128];
1713 uint8_t max_ct_len[4];
1717 struct ct_fdmi_hba_attributes {
1719 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1723 * Port attribute types.
1725 #define FDMI_PORT_ATTR_COUNT 6
1726 #define FDMI_PORT_FC4_TYPES 1
1727 #define FDMI_PORT_SUPPORT_SPEED 2
1728 #define FDMI_PORT_CURRENT_SPEED 3
1729 #define FDMI_PORT_MAX_FRAME_SIZE 4
1730 #define FDMI_PORT_OS_DEVICE_NAME 5
1731 #define FDMI_PORT_HOST_NAME 6
1733 #define FDMI_PORT_SPEED_1GB 0x1
1734 #define FDMI_PORT_SPEED_2GB 0x2
1735 #define FDMI_PORT_SPEED_10GB 0x4
1736 #define FDMI_PORT_SPEED_4GB 0x8
1737 #define FDMI_PORT_SPEED_8GB 0x10
1738 #define FDMI_PORT_SPEED_16GB 0x20
1739 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
1741 struct ct_fdmi_port_attr {
1745 uint8_t fc4_types[32];
1748 uint32_t max_frame_size;
1749 uint8_t os_dev_name[32];
1750 uint8_t host_name[32];
1755 * Port Attribute Block.
1757 struct ct_fdmi_port_attributes {
1759 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1762 /* FDMI definitions. */
1763 #define GRHL_CMD 0x100
1764 #define GHAT_CMD 0x101
1765 #define GRPL_CMD 0x102
1766 #define GPAT_CMD 0x110
1768 #define RHBA_CMD 0x200
1769 #define RHBA_RSP_SIZE 16
1771 #define RHAT_CMD 0x201
1772 #define RPRT_CMD 0x210
1774 #define RPA_CMD 0x211
1775 #define RPA_RSP_SIZE 16
1777 #define DHBA_CMD 0x300
1778 #define DHBA_REQ_SIZE (16 + 8)
1779 #define DHBA_RSP_SIZE 16
1781 #define DHAT_CMD 0x301
1782 #define DPRT_CMD 0x310
1783 #define DPA_CMD 0x311
1785 /* CT command header -- request/response common fields */
1795 /* CT command request */
1797 struct ct_cmd_hdr header;
1799 uint16_t max_rsp_size;
1800 uint8_t fragment_id;
1801 uint8_t reserved[3];
1804 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
1820 uint8_t fc4_types[32];
1827 uint8_t fc4_feature;
1834 uint8_t node_name[8];
1838 uint8_t node_name[8];
1840 uint8_t sym_node_name[255];
1844 uint8_t hba_indentifier[8];
1848 uint8_t hba_identifier[8];
1849 uint32_t entry_count;
1850 uint8_t port_name[8];
1851 struct ct_fdmi_hba_attributes attrs;
1855 uint8_t hba_identifier[8];
1856 struct ct_fdmi_hba_attributes attrs;
1860 uint8_t port_name[8];
1861 struct ct_fdmi_port_attributes attrs;
1865 uint8_t port_name[8];
1869 uint8_t port_name[8];
1873 uint8_t port_name[8];
1877 uint8_t port_name[8];
1881 uint8_t port_name[8];
1886 /* CT command response header */
1888 struct ct_cmd_hdr header;
1891 uint8_t fragment_id;
1892 uint8_t reason_code;
1893 uint8_t explanation_code;
1894 uint8_t vendor_unique;
1897 struct ct_sns_gid_pt_data {
1898 uint8_t control_byte;
1903 struct ct_rsp_hdr header;
1909 uint8_t port_name[8];
1910 uint8_t sym_port_name_len;
1911 uint8_t sym_port_name[255];
1912 uint8_t node_name[8];
1913 uint8_t sym_node_name_len;
1914 uint8_t sym_node_name[255];
1915 uint8_t init_proc_assoc[8];
1916 uint8_t node_ip_addr[16];
1917 uint8_t class_of_service[4];
1918 uint8_t fc4_types[32];
1919 uint8_t ip_address[16];
1920 uint8_t fabric_port_name[8];
1922 uint8_t hard_address[3];
1926 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1930 uint8_t port_name[8];
1934 uint8_t node_name[8];
1938 uint8_t fc4_types[32];
1942 uint32_t entry_count;
1943 uint8_t port_name[8];
1944 struct ct_fdmi_hba_attributes attrs;
1948 uint8_t port_name[8];
1960 struct ct_sns_req req;
1961 struct ct_sns_rsp rsp;
1966 * SNS command structures -- for 2200 compatability.
1968 #define RFT_ID_SNS_SCMD_LEN 22
1969 #define RFT_ID_SNS_CMD_SIZE 60
1970 #define RFT_ID_SNS_DATA_SIZE 16
1972 #define RNN_ID_SNS_SCMD_LEN 10
1973 #define RNN_ID_SNS_CMD_SIZE 36
1974 #define RNN_ID_SNS_DATA_SIZE 16
1976 #define GA_NXT_SNS_SCMD_LEN 6
1977 #define GA_NXT_SNS_CMD_SIZE 28
1978 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
1980 #define GID_PT_SNS_SCMD_LEN 6
1981 #define GID_PT_SNS_CMD_SIZE 28
1982 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1984 #define GPN_ID_SNS_SCMD_LEN 6
1985 #define GPN_ID_SNS_CMD_SIZE 28
1986 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
1988 #define GNN_ID_SNS_SCMD_LEN 6
1989 #define GNN_ID_SNS_CMD_SIZE 28
1990 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
1992 struct sns_cmd_pkt {
1995 uint16_t buffer_length;
1996 uint16_t reserved_1;
1997 uint32_t buffer_address[2];
1998 uint16_t subcommand_length;
1999 uint16_t reserved_2;
2000 uint16_t subcommand;
2002 uint32_t reserved_3;
2006 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2007 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2008 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2009 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2010 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2011 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2018 const struct firmware *fw;
2021 /* Return data from MBC_GET_ID_LIST call. */
2022 struct gid_list_info {
2026 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2027 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2028 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2030 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2033 typedef struct vport_info {
2034 uint8_t port_name[WWN_SIZE];
2035 uint8_t node_name[WWN_SIZE];
2038 unsigned long host_no;
2043 typedef struct vport_params {
2044 uint8_t port_name[WWN_SIZE];
2045 uint8_t node_name[WWN_SIZE];
2047 #define VP_OPTS_RETRY_ENABLE BIT_0
2048 #define VP_OPTS_VP_DISABLE BIT_1
2051 /* NPIV - return codes of VP create and modify */
2052 #define VP_RET_CODE_OK 0
2053 #define VP_RET_CODE_FATAL 1
2054 #define VP_RET_CODE_WRONG_ID 2
2055 #define VP_RET_CODE_WWPN 3
2056 #define VP_RET_CODE_RESOURCES 4
2057 #define VP_RET_CODE_NO_MEM 5
2058 #define VP_RET_CODE_NOT_FOUND 6
2065 struct isp_operations {
2067 int (*pci_config) (struct scsi_qla_host *);
2068 void (*reset_chip) (struct scsi_qla_host *);
2069 int (*chip_diag) (struct scsi_qla_host *);
2070 void (*config_rings) (struct scsi_qla_host *);
2071 void (*reset_adapter) (struct scsi_qla_host *);
2072 int (*nvram_config) (struct scsi_qla_host *);
2073 void (*update_fw_options) (struct scsi_qla_host *);
2074 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2076 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2077 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2079 irq_handler_t intr_handler;
2080 void (*enable_intrs) (struct qla_hw_data *);
2081 void (*disable_intrs) (struct qla_hw_data *);
2083 int (*abort_command) (srb_t *);
2084 int (*target_reset) (struct fc_port *, unsigned int, int);
2085 int (*lun_reset) (struct fc_port *, unsigned int, int);
2086 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2087 uint8_t, uint8_t, uint16_t *, uint8_t);
2088 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2091 uint16_t (*calc_req_entries) (uint16_t);
2092 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2093 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2094 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2097 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2098 uint32_t, uint32_t);
2099 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2102 void (*fw_dump) (struct scsi_qla_host *, int);
2104 int (*beacon_on) (struct scsi_qla_host *);
2105 int (*beacon_off) (struct scsi_qla_host *);
2106 void (*beacon_blink) (struct scsi_qla_host *);
2108 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2109 uint32_t, uint32_t);
2110 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2113 int (*get_flash_version) (struct scsi_qla_host *, void *);
2114 int (*start_scsi) (srb_t *);
2117 /* MSI-X Support *************************************************************/
2119 #define QLA_MSIX_CHIP_REV_24XX 3
2120 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2121 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2123 #define QLA_MSIX_DEFAULT 0x00
2124 #define QLA_MSIX_RSP_Q 0x01
2126 #define QLA_MIDX_DEFAULT 0
2127 #define QLA_MIDX_RSP_Q 1
2128 #define QLA_PCI_MSIX_CONTROL 0xa2
2130 struct scsi_qla_host;
2132 struct qla_msix_entry {
2136 struct rsp_que *rsp;
2139 #define WATCH_INTERVAL 1 /* number of seconds */
2142 enum qla_work_type {
2145 QLA_EVT_ASYNC_LOGIN,
2146 QLA_EVT_ASYNC_LOGIN_DONE,
2147 QLA_EVT_ASYNC_LOGOUT,
2148 QLA_EVT_ASYNC_LOGOUT_DONE,
2153 struct qla_work_evt {
2154 struct list_head list;
2155 enum qla_work_type type;
2157 #define QLA_EVT_FLAG_FREE 0x1
2161 enum fc_host_event_code code;
2165 #define QLA_IDC_ACK_REGS 7
2166 uint16_t mb[QLA_IDC_ACK_REGS];
2169 struct fc_port *fcport;
2170 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
2175 #define QLA_UEVENT_CODE_FW_DUMP 0
2180 struct qla_chip_state_84xx {
2181 struct list_head list;
2185 spinlock_t access_lock;
2186 struct mutex fw_update_mutex;
2188 uint32_t op_fw_version;
2189 uint32_t op_fw_size;
2190 uint32_t op_fw_seq_size;
2191 uint32_t diag_fw_version;
2192 uint32_t gold_fw_version;
2195 struct qla_statistics {
2196 uint32_t total_isp_aborts;
2197 uint64_t input_bytes;
2198 uint64_t output_bytes;
2201 /* Multi queue support */
2202 #define MBC_INITIALIZE_MULTIQ 0x1f
2203 #define QLA_QUE_PAGE 0X1000
2204 #define QLA_MQ_SIZE 32
2205 #define QLA_MAX_QUEUES 256
2206 #define ISP_QUE_REG(ha, id) \
2208 ((void *)(ha->mqiobase) +\
2209 (QLA_QUE_PAGE * id)) :\
2210 ((void *)(ha->iobase)))
2211 #define QLA_REQ_QUE_ID(tag) \
2212 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2213 #define QLA_DEFAULT_QUE_QOS 5
2214 #define QLA_PRECONFIG_VPORTS 32
2215 #define QLA_MAX_VPORTS_QLA24XX 128
2216 #define QLA_MAX_VPORTS_QLA25XX 256
2217 /* Response queue data structure */
2221 response_t *ring_ptr;
2222 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */
2223 uint32_t __iomem *rsp_q_out;
2224 uint16_t ring_index;
2231 struct qla_hw_data *hw;
2232 struct qla_msix_entry *msix;
2233 struct req_que *req;
2234 srb_t *status_srb; /* status continuation entry */
2235 struct work_struct q_work;
2238 /* Request queue data structure */
2242 request_t *ring_ptr;
2243 uint32_t __iomem *req_q_in; /* FWI2-capable only. */
2244 uint32_t __iomem *req_q_out;
2245 uint16_t ring_index;
2254 struct rsp_que *rsp;
2255 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2256 uint32_t current_outstanding_cmd;
2260 /* Place holder for FW buffer parameters */
2268 * Qlogic host adapter specific data structure.
2270 struct qla_hw_data {
2271 struct pci_dev *pdev;
2273 #define SRB_MIN_REQ 128
2274 mempool_t *srb_mempool;
2277 uint32_t mbox_int :1;
2278 uint32_t mbox_busy :1;
2280 uint32_t disable_risc_code_load :1;
2281 uint32_t enable_64bit_addressing :1;
2282 uint32_t enable_lip_reset :1;
2283 uint32_t enable_target_reset :1;
2284 uint32_t enable_lip_full_login :1;
2285 uint32_t enable_led_scheme :1;
2286 uint32_t inta_enabled :1;
2287 uint32_t msi_enabled :1;
2288 uint32_t msix_enabled :1;
2289 uint32_t disable_serdes :1;
2290 uint32_t gpsc_supported :1;
2291 uint32_t npiv_supported :1;
2292 uint32_t pci_channel_io_perm_failure :1;
2293 uint32_t fce_enabled :1;
2294 uint32_t fac_supported :1;
2295 uint32_t chip_reset_done :1;
2297 uint32_t running_gold_fw :1;
2298 uint32_t eeh_busy :1;
2299 uint32_t cpu_affinity_enabled :1;
2300 uint32_t disable_msix_handshake :1;
2301 uint32_t fcp_prio_enabled :1;
2304 /* This spinlock is used to protect "io transactions", you must
2305 * acquire it before doing any IO to the card, eg with RD_REG*() and
2306 * WRT_REG*() for the duration of your entire commandtransaction.
2308 * This spinlock is of lower priority than the io request lock.
2311 spinlock_t hardware_lock ____cacheline_aligned;
2314 device_reg_t __iomem *iobase; /* Base I/O address */
2315 resource_size_t pio_address;
2317 #define MIN_IOBASE_LEN 0x100
2318 /* Multi queue data structs */
2319 device_reg_t __iomem *mqiobase;
2320 uint16_t msix_count;
2322 struct req_que **req_q_map;
2323 struct rsp_que **rsp_q_map;
2324 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2325 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2326 uint8_t max_req_queues;
2327 uint8_t max_rsp_queues;
2328 struct qla_npiv_entry *npiv_info;
2329 uint16_t nvram_npiv_size;
2331 uint16_t switch_cap;
2332 #define FLOGI_SEQ_DEL BIT_8
2333 #define FLOGI_MID_SUPPORT BIT_10
2334 #define FLOGI_VSAN_SUPPORT BIT_12
2335 #define FLOGI_SP_SUPPORT BIT_13
2337 uint8_t port_no; /* Physical port of adapter */
2339 /* Timeout timers. */
2340 uint8_t loop_down_abort_time; /* port down timer */
2341 atomic_t loop_down_timer; /* loop down timer */
2342 uint8_t link_down_timeout; /* link down timeout */
2343 uint16_t max_loop_id;
2346 uint16_t min_external_loopid; /* First external loop Id */
2348 #define PORT_SPEED_UNKNOWN 0xFFFF
2349 #define PORT_SPEED_1GB 0x00
2350 #define PORT_SPEED_2GB 0x01
2351 #define PORT_SPEED_4GB 0x03
2352 #define PORT_SPEED_8GB 0x04
2353 #define PORT_SPEED_10GB 0x13
2354 uint16_t link_data_rate; /* F/W operating speed */
2356 uint8_t current_topology;
2357 uint8_t prev_topology;
2358 #define ISP_CFG_NL 1
2360 #define ISP_CFG_FL 4
2363 uint8_t operating_mode; /* F/W operating mode */
2368 uint8_t interrupts_on;
2369 uint32_t isp_abort_cnt;
2371 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2372 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2373 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2374 uint32_t device_type;
2375 #define DT_ISP2100 BIT_0
2376 #define DT_ISP2200 BIT_1
2377 #define DT_ISP2300 BIT_2
2378 #define DT_ISP2312 BIT_3
2379 #define DT_ISP2322 BIT_4
2380 #define DT_ISP6312 BIT_5
2381 #define DT_ISP6322 BIT_6
2382 #define DT_ISP2422 BIT_7
2383 #define DT_ISP2432 BIT_8
2384 #define DT_ISP5422 BIT_9
2385 #define DT_ISP5432 BIT_10
2386 #define DT_ISP2532 BIT_11
2387 #define DT_ISP8432 BIT_12
2388 #define DT_ISP8001 BIT_13
2389 #define DT_ISP_LAST (DT_ISP8001 << 1)
2391 #define DT_IIDMA BIT_26
2392 #define DT_FWI2 BIT_27
2393 #define DT_ZIO_SUPPORTED BIT_28
2394 #define DT_OEM_001 BIT_29
2395 #define DT_ISP2200A BIT_30
2396 #define DT_EXTENDED_IDS BIT_31
2397 #define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2398 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2399 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2400 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2401 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2402 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2403 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2404 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2405 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2406 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2407 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2408 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2409 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2410 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2411 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2413 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2414 IS_QLA6312(ha) || IS_QLA6322(ha))
2415 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2416 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2417 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
2418 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
2419 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2421 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
2422 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2423 IS_QLA25XX(ha) || IS_QLA81XX(ha))
2424 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha))
2425 #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \
2426 (ha)->flags.msix_enabled)
2427 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha))
2428 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha))
2429 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
2431 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2432 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2433 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2434 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2435 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2437 /* HBA serial number */
2442 /* NVRAM configuration data */
2443 #define MAX_NVRAM_SIZE 4096
2444 #define VPD_OFFSET MAX_NVRAM_SIZE / 2
2445 uint16_t nvram_size;
2446 uint16_t nvram_base;
2452 uint16_t loop_reset_delay;
2453 uint8_t retry_count;
2454 uint8_t login_timeout;
2456 int port_down_retry_count;
2459 uint32_t login_retry_count;
2460 /* SNS command interfaces. */
2461 ms_iocb_entry_t *ms_iocb;
2462 dma_addr_t ms_iocb_dma;
2463 struct ct_sns_pkt *ct_sns;
2464 dma_addr_t ct_sns_dma;
2465 /* SNS command interfaces for 2200. */
2466 struct sns_cmd_pkt *sns_cmd;
2467 dma_addr_t sns_cmd_dma;
2469 #define SFP_DEV_SIZE 256
2470 #define SFP_BLOCK_SIZE 64
2472 dma_addr_t sfp_data_dma;
2475 dma_addr_t edc_data_dma;
2476 uint16_t edc_data_len;
2478 #define XGMAC_DATA_SIZE 4096
2480 dma_addr_t xgmac_data_dma;
2482 #define DCBX_TLV_DATA_SIZE 4096
2484 dma_addr_t dcbx_tlv_dma;
2486 struct task_struct *dpc_thread;
2487 uint8_t dpc_active; /* DPC routine is active */
2489 dma_addr_t gid_list_dma;
2490 struct gid_list_info *gid_list;
2491 int gid_list_info_size;
2493 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2494 #define DMA_POOL_SIZE 256
2495 struct dma_pool *s_dma_pool;
2497 dma_addr_t init_cb_dma;
2500 dma_addr_t ex_init_cb_dma;
2501 struct ex_init_cb_81xx *ex_init_cb;
2503 /* These are used by mailbox operations. */
2504 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2507 unsigned long mbx_cmd_flags;
2508 #define MBX_INTERRUPT 1
2509 #define MBX_INTR_WAIT 2
2510 #define MBX_UPDATE_FLASH_ACTIVE 3
2512 struct mutex vport_lock; /* Virtual port synchronization */
2513 struct completion mbx_cmd_comp; /* Serialize mbx access */
2514 struct completion mbx_intr_comp; /* Used for completion notification */
2516 /* Basic firmware related information. */
2517 uint16_t fw_major_version;
2518 uint16_t fw_minor_version;
2519 uint16_t fw_subminor_version;
2520 uint16_t fw_attributes;
2521 uint32_t fw_memory_size;
2522 uint32_t fw_transfer_size;
2523 uint32_t fw_srisc_address;
2524 #define RISC_START_ADDRESS_2100 0x1000
2525 #define RISC_START_ADDRESS_2300 0x800
2526 #define RISC_START_ADDRESS_2400 0x100000
2527 uint16_t fw_xcb_count;
2529 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2530 uint8_t fw_seriallink_options[4];
2531 uint16_t fw_seriallink_options24[4];
2533 uint8_t mpi_version[3];
2534 uint32_t mpi_capabilities;
2535 uint8_t phy_version[3];
2537 /* Firmware dump information. */
2538 struct qla2xxx_fw_dump *fw_dump;
2539 uint32_t fw_dump_len;
2541 int fw_dump_reading;
2545 uint32_t chain_offset;
2546 struct dentry *dfs_dir;
2547 struct dentry *dfs_fce;
2552 uint64_t fce_wr, fce_rd;
2553 struct mutex fce_mutex;
2556 uint16_t chip_revision;
2558 uint16_t product_id[4];
2560 uint8_t model_number[16+1];
2561 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2562 char model_desc[80];
2563 uint8_t adapter_id[16+1];
2565 /* Option ROM information. */
2566 char *optrom_buffer;
2567 uint32_t optrom_size;
2569 #define QLA_SWAITING 0
2570 #define QLA_SREADING 1
2571 #define QLA_SWRITING 2
2572 uint32_t optrom_region_start;
2573 uint32_t optrom_region_size;
2575 /* PCI expansion ROM image information. */
2576 #define ROM_CODE_TYPE_BIOS 0
2577 #define ROM_CODE_TYPE_FCODE 1
2578 #define ROM_CODE_TYPE_EFI 3
2579 uint8_t bios_revision[2];
2580 uint8_t efi_revision[2];
2581 uint8_t fcode_revision[16];
2582 uint32_t fw_revision[4];
2584 /* Offsets for flash/nvram access (set to ~0 if not used). */
2585 uint32_t flash_conf_off;
2586 uint32_t flash_data_off;
2587 uint32_t nvram_conf_off;
2588 uint32_t nvram_data_off;
2590 uint32_t fdt_wrt_disable;
2591 uint32_t fdt_erase_cmd;
2592 uint32_t fdt_block_size;
2593 uint32_t fdt_unprotect_sec_cmd;
2594 uint32_t fdt_protect_sec_cmd;
2596 uint32_t flt_region_flt;
2597 uint32_t flt_region_fdt;
2598 uint32_t flt_region_boot;
2599 uint32_t flt_region_fw;
2600 uint32_t flt_region_vpd_nvram;
2601 uint32_t flt_region_vpd;
2602 uint32_t flt_region_nvram;
2603 uint32_t flt_region_npiv_conf;
2604 uint32_t flt_region_gold_fw;
2605 uint32_t flt_region_fcp_prio;
2607 /* Needed for BEACON */
2608 uint16_t beacon_blink_led;
2609 uint8_t beacon_color_state;
2610 #define QLA_LED_GRN_ON 0x01
2611 #define QLA_LED_YLW_ON 0x02
2612 #define QLA_LED_ABR_ON 0x04
2613 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
2614 /* ISP2322: red, green, amber. */
2617 struct fc_host_statistics fc_host_stat;
2619 struct qla_msix_entry *msix_entries;
2621 struct list_head vp_list; /* list of VP */
2622 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
2623 sizeof(unsigned long)];
2624 uint16_t num_vhosts; /* number of vports created */
2625 uint16_t num_vsans; /* number of vsan created */
2626 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
2627 int cur_vport_count;
2629 struct qla_chip_state_84xx *cs84xx;
2630 struct qla_statistics qla_stats;
2631 struct isp_operations *isp_ops;
2632 struct workqueue_struct *wq;
2633 struct qlfc_fw fw_buf;
2635 /* FCP_CMND priority support */
2636 struct qla_fcp_prio_cfg *fcp_prio_cfg;
2640 * Qlogic scsi host structure
2642 typedef struct scsi_qla_host {
2643 struct list_head list;
2644 struct list_head vp_fcports; /* list of fcports */
2645 struct list_head work_list;
2646 spinlock_t work_lock;
2648 /* Commonly used flags and state information. */
2649 struct Scsi_Host *host;
2650 unsigned long host_no;
2651 uint8_t host_str[16];
2654 uint32_t init_done :1;
2656 uint32_t rscn_queue_overflow :1;
2657 uint32_t reset_active :1;
2659 uint32_t management_server_logged_in :1;
2660 uint32_t process_response_queue :1;
2663 atomic_t loop_state;
2664 #define LOOP_TIMEOUT 1
2667 #define LOOP_UPDATE 4
2668 #define LOOP_READY 5
2671 unsigned long dpc_flags;
2672 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2673 #define RESET_ACTIVE 1
2674 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2675 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2676 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2677 #define LOOP_RESYNC_ACTIVE 5
2678 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2679 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2680 #define RELOGIN_NEEDED 8
2681 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
2682 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
2683 #define BEACON_BLINK_NEEDED 11
2684 #define REGISTER_FDMI_NEEDED 12
2685 #define FCPORT_UPDATE_NEEDED 13
2686 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
2687 #define UNLOADING 15
2688 #define NPIV_CONFIG_NEEDED 16
2690 uint32_t device_flags;
2691 #define SWITCH_FOUND BIT_0
2692 #define DFLG_NO_CABLE BIT_1
2694 /* ISP configuration data. */
2695 uint16_t loop_id; /* Host adapter loop id */
2697 port_id_t d_id; /* Host adapter port id */
2698 uint8_t marker_needed;
2699 uint16_t mgmt_svr_loop_id;
2704 uint32_t rscn_queue[MAX_RSCN_COUNT];
2705 uint8_t rscn_in_ptr;
2706 uint8_t rscn_out_ptr;
2708 /* Timeout timers. */
2709 uint8_t loop_down_abort_time; /* port down timer */
2710 atomic_t loop_down_timer; /* loop down timer */
2711 uint8_t link_down_timeout; /* link down timeout */
2713 uint32_t timer_active;
2714 struct timer_list timer;
2716 uint8_t node_name[WWN_SIZE];
2717 uint8_t port_name[WWN_SIZE];
2718 uint8_t fabric_node_name[WWN_SIZE];
2720 uint16_t fcoe_vlan_id;
2721 uint16_t fcoe_fcf_idx;
2722 uint8_t fcoe_vn_port_mac[6];
2724 uint32_t vp_abort_cnt;
2726 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
2727 uint16_t vp_idx; /* vport ID */
2729 unsigned long vp_flags;
2730 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
2731 #define VP_CREATE_NEEDED 1
2732 #define VP_BIND_NEEDED 2
2733 #define VP_DELETE_NEEDED 3
2734 #define VP_SCR_NEEDED 4 /* State Change Request registration */
2736 #define VP_OFFLINE 0
2739 // #define VP_DISABLE 3
2740 uint16_t vp_err_state;
2741 uint16_t vp_prev_err_state;
2742 #define VP_ERR_UNKWN 0
2743 #define VP_ERR_PORTDWN 1
2744 #define VP_ERR_FAB_UNSUPPORTED 2
2745 #define VP_ERR_FAB_NORESOURCES 3
2746 #define VP_ERR_FAB_LOGOUT 4
2747 #define VP_ERR_ADAP_NORESOURCES 5
2748 struct qla_hw_data *hw;
2749 struct req_que *req;
2753 * Macros to help code, maintain, etc.
2755 #define LOOP_TRANSITION(ha) \
2756 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2757 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2758 atomic_read(&ha->loop_state) == LOOP_DOWN)
2760 #define qla_printk(level, ha, format, arg...) \
2761 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2764 * qla2x00 local function return status codes
2766 #define MBS_MASK 0x3fff
2768 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2769 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2770 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2771 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2772 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2773 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2774 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2775 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2776 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2777 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2779 #define QLA_FUNCTION_TIMEOUT 0x100
2780 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2781 #define QLA_FUNCTION_FAILED 0x102
2782 #define QLA_MEMORY_ALLOC_FAILED 0x103
2783 #define QLA_LOCK_TIMEOUT 0x104
2784 #define QLA_ABORTED 0x105
2785 #define QLA_SUSPENDED 0x106
2786 #define QLA_BUSY 0x107
2787 #define QLA_RSCNS_HANDLED 0x108
2788 #define QLA_ALREADY_REGISTERED 0x109
2790 #define NVRAM_DELAY() udelay(10)
2792 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2795 * Flash support definitions
2797 #define OPTROM_SIZE_2300 0x20000
2798 #define OPTROM_SIZE_2322 0x100000
2799 #define OPTROM_SIZE_24XX 0x100000
2800 #define OPTROM_SIZE_25XX 0x200000
2801 #define OPTROM_SIZE_81XX 0x400000
2803 #include "qla_gbl.h"
2804 #include "qla_dbg.h"
2805 #include "qla_inline.h"
2807 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)