2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
40 #ifndef _PMC8001_REG_H_
41 #define _PMC8001_REG_H_
43 #include <linux/types.h>
44 #include <scsi/libsas.h>
47 /* for Request Opcode of IOMB */
48 #define OPC_INB_ECHO 1 /* 0x000 */
49 #define OPC_INB_PHYSTART 4 /* 0x004 */
50 #define OPC_INB_PHYSTOP 5 /* 0x005 */
51 #define OPC_INB_SSPINIIOSTART 6 /* 0x006 */
52 #define OPC_INB_SSPINITMSTART 7 /* 0x007 */
53 #define OPC_INB_SSPINIEXTIOSTART 8 /* 0x008 */
54 #define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */
55 #define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */
56 #define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */
57 #define OPC_INB_SSPINIEDCIOSTART 12 /* 0x00C */
58 #define OPC_INB_SSPINIEXTEDCIOSTART 13 /* 0x00D */
59 #define OPC_INB_SSPTGTEDCIOSTART 14 /* 0x00E */
60 #define OPC_INB_SSP_ABORT 15 /* 0x00F */
61 #define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */
62 #define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */
63 #define OPC_INB_SMP_REQUEST 18 /* 0x012 */
64 /* SMP_RESPONSE is removed */
65 #define OPC_INB_SMP_RESPONSE 19 /* 0x013 */
66 #define OPC_INB_SMP_ABORT 20 /* 0x014 */
67 #define OPC_INB_REG_DEV 22 /* 0x016 */
68 #define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */
69 #define OPC_INB_SATA_ABORT 24 /* 0x018 */
70 #define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */
71 #define OPC_INB_GET_DEV_INFO 26 /* 0x01A */
72 #define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */
73 #define OPC_INB_GPIO 34 /* 0x022 */
74 #define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */
75 #define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */
76 #define OPC_INB_SAS_HW_EVENT_ACK 37 /* 0x025 */
77 #define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */
78 #define OPC_INB_PORT_CONTROL 39 /* 0x027 */
79 #define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */
80 #define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */
81 #define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */
82 #define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */
83 #define OPC_INB_SET_DEV_INFO 44 /* 0x02C */
84 #define OPC_INB_SAS_RE_INITIALIZE 45 /* 0x02D */
86 /* for Response Opcode of IOMB */
87 #define OPC_OUB_ECHO 1 /* 0x001 */
88 #define OPC_OUB_HW_EVENT 4 /* 0x004 */
89 #define OPC_OUB_SSP_COMP 5 /* 0x005 */
90 #define OPC_OUB_SMP_COMP 6 /* 0x006 */
91 #define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */
92 #define OPC_OUB_DEV_REGIST 10 /* 0x00A */
93 #define OPC_OUB_DEREG_DEV 11 /* 0x00B */
94 #define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */
95 #define OPC_OUB_SATA_COMP 13 /* 0x00D */
96 #define OPC_OUB_SATA_EVENT 14 /* 0x00E */
97 #define OPC_OUB_SSP_EVENT 15 /* 0x00F */
98 #define OPC_OUB_DEV_HANDLE_ARRIV 16 /* 0x010 */
99 /* SMP_RECEIVED Notification is removed */
100 #define OPC_OUB_SMP_RECV_EVENT 17 /* 0x011 */
101 #define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */
102 #define OPC_OUB_DEV_INFO 19 /* 0x013 */
103 #define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */
104 #define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */
105 #define OPC_OUB_GPIO_EVENT 23 /* 0x017 */
106 #define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */
107 #define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */
108 #define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */
109 #define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */
110 #define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */
111 #define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */
112 #define OPC_OUB_SAS_HW_EVENT_ACK 31 /* 0x01F */
113 #define OPC_OUB_PORT_CONTROL 32 /* 0x020 */
114 #define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */
115 #define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */
116 #define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */
117 #define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */
118 #define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */
119 #define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */
120 #define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */
121 #define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */
122 #define OPC_OUB_SAS_RE_INITIALIZE 41 /* 0x029 */
125 #define SPINHOLD_DISABLE (0x00 << 14)
126 #define SPINHOLD_ENABLE (0x01 << 14)
127 #define LINKMODE_SAS (0x01 << 12)
128 #define LINKMODE_DSATA (0x02 << 12)
129 #define LINKMODE_AUTO (0x03 << 12)
130 #define LINKRATE_15 (0x01 << 8)
131 #define LINKRATE_30 (0x02 << 8)
132 #define LINKRATE_60 (0x04 << 8)
135 __le32 header; /* Bits [11:0] - Message operation code */
136 /* Bits [15:12] - Message Category */
137 /* Bits [21:16] - Outboundqueue ID for the
138 operation completion message */
139 /* Bits [23:22] - Reserved */
140 /* Bits [28:24] - Buffer Count, indicates how
141 many buffer are allocated for the massage */
142 /* Bits [30:29] - Reserved */
143 /* Bits [31] - Message Valid bit */
144 } __attribute__((packed, aligned(4)));
148 * brief the data structure of PHY Start Command
149 * use to describe enable the phy (64 bytes)
151 struct phy_start_req {
153 __le32 ase_sh_lm_slr_phyid;
154 struct sas_identify_frame sas_identify;
156 } __attribute__((packed, aligned(4)));
160 * brief the data structure of PHY Start Command
161 * use to disable the phy (64 bytes)
163 struct phy_stop_req {
167 } __attribute__((packed, aligned(4)));
170 /* set device bits fis - device to host */
171 struct set_dev_bits_fis {
172 u8 fis_type; /* 0xA1*/
174 /* b7 : n Bit. Notification bit. If set device needs attention. */
175 /* b6 : i Bit. Interrupt Bit */
176 /* b5-b4: reserved2 */
181 } __attribute__ ((packed));
182 /* PIO setup FIS - device to host */
183 struct pio_setup_fis {
184 u8 fis_type; /* 0x5f */
187 /* b6 : i bit. Interrupt bit */
188 /* b5 : d bit. data transfer direction. set to 1 for device to host
208 } __attribute__ ((packed));
211 * brief the data structure of SATA Completion Response
212 * use to discribe the sata task response (64 bytes)
214 struct sata_completion_resp {
219 } __attribute__((packed, aligned(4)));
223 * brief the data structure of SAS HW Event Notification
224 * use to alert the host about the hardware event(64 bytes)
226 struct hw_event_resp {
227 __le32 lr_evt_status_phyid_portid;
229 __le32 npip_portstate;
230 struct sas_identify_frame sas_identify;
231 struct dev_to_host_fis sata_fis;
232 } __attribute__((packed, aligned(4)));
236 * brief the data structure of REGISTER DEVICE Command
237 * use to describe MPI REGISTER DEVICE Command (64 bytes)
243 __le32 dtype_dlr_retry;
244 __le32 firstburstsize_ITNexustimeout;
247 __le32 upper_device_id;
249 } __attribute__((packed, aligned(4)));
253 * brief the data structure of DEREGISTER DEVICE Command
254 * use to request spc to remove all internal resources associated
255 * with the device id (64 bytes)
258 struct dereg_dev_req {
262 } __attribute__((packed, aligned(4)));
266 * brief the data structure of DEVICE_REGISTRATION Response
267 * use to notify the completion of the device registration (64 bytes)
270 struct dev_reg_resp {
275 } __attribute__((packed, aligned(4)));
279 * brief the data structure of Local PHY Control Command
280 * use to issue PHY CONTROL to local phy (64 bytes)
282 struct local_phy_ctl_req {
286 } __attribute__((packed, aligned(4)));
290 * brief the data structure of Local Phy Control Response
291 * use to describe MPI Local Phy Control Response (64 bytes)
293 struct local_phy_ctl_resp {
298 } __attribute__((packed, aligned(4)));
301 #define OP_BITS 0x0000FF00
302 #define ID_BITS 0x0000000F
305 * brief the data structure of PORT Control Command
306 * use to control port properties (64 bytes)
309 struct port_ctl_req {
311 __le32 portop_portid;
315 } __attribute__((packed, aligned(4)));
319 * brief the data structure of HW Event Ack Command
320 * use to acknowledge receive HW event (64 bytes)
323 struct hw_event_ack_req {
325 __le32 sea_phyid_portid;
329 } __attribute__((packed, aligned(4)));
333 * brief the data structure of SSP Completion Response
334 * use to indicate a SSP Completion (n bytes)
336 struct ssp_completion_resp {
340 __le32 ssptag_rescv_rescpad;
341 struct ssp_response_iu ssp_resp_iu;
342 __le32 residual_count;
343 } __attribute__((packed, aligned(4)));
346 #define SSP_RESCV_BIT 0x00010000
349 * brief the data structure of SATA EVNET esponse
350 * use to indicate a SATA Completion (64 bytes)
353 struct sata_event_resp {
359 } __attribute__((packed, aligned(4)));
362 * brief the data structure of SSP EVNET esponse
363 * use to indicate a SSP Completion (64 bytes)
366 struct ssp_event_resp {
372 } __attribute__((packed, aligned(4)));
375 * brief the data structure of General Event Notification Response
376 * use to describe MPI General Event Notification Response (64 bytes)
378 struct general_event_resp {
380 __le32 inb_IOMB_payload[14];
381 } __attribute__((packed, aligned(4)));
384 #define GENERAL_EVENT_PAYLOAD 14
385 #define OPCODE_BITS 0x00000fff
388 * brief the data structure of SMP Request Command
389 * use to describe MPI SMP REQUEST Command (64 bytes)
395 /* Bits [0] - Indirect response */
396 /* Bits [1] - Indirect Payload */
397 /* Bits [15:2] - Reserved */
398 /* Bits [23:16] - direct payload Len */
399 /* Bits [31:24] - Reserved */
404 __le64 long_req_addr;/* sg dma address, LE */
405 __le32 long_req_size;/* LE */
407 __le64 long_resp_addr;/* sg dma address, LE */
408 __le32 long_resp_size;/* LE */
410 } long_smp_req;/* sequencer extension */
412 } __attribute__((packed, aligned(4)));
414 * brief the data structure of SMP Completion Response
415 * use to describe MPI SMP Completion Response (64 bytes)
417 struct smp_completion_resp {
422 } __attribute__((packed, aligned(4)));
425 *brief the data structure of SSP SMP SATA Abort Command
426 * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
428 struct task_abort_req {
434 } __attribute__((packed, aligned(4)));
436 /* These flags used for SSP SMP & SATA Abort */
437 #define ABORT_MASK 0x3
438 #define ABORT_SINGLE 0x0
439 #define ABORT_ALL 0x1
442 * brief the data structure of SSP SATA SMP Abort Response
443 * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
445 struct task_abort_resp {
450 } __attribute__((packed, aligned(4)));
454 * brief the data structure of SAS Diagnostic Start/End Command
455 * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
457 struct sas_diag_start_end_req {
459 __le32 operation_phyid;
461 } __attribute__((packed, aligned(4)));
465 * brief the data structure of SAS Diagnostic Execute Command
466 * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
468 struct sas_diag_execute_req{
470 __le32 cmdtype_cmddesc_phyid;
473 __le32 codepat_errmsk;
477 } __attribute__((packed, aligned(4)));
480 #define SAS_DIAG_PARAM_BYTES 24
483 * brief the data structure of Set Device State Command
484 * use to describe MPI Set Device State Command (64 bytes)
486 struct set_dev_state_req {
491 } __attribute__((packed, aligned(4)));
494 * brief the data structure of sas_re_initialization
496 struct sas_re_initialization_req {
499 __le32 SSAHOLT;/* bit29-set max port;
500 ** bit28-set open reject cmd retries.
501 ** bit27-set open reject data retries.
502 ** bit26-set open reject option, remap:1 or not:0.
503 ** bit25-set sata head of line time out.
505 __le32 reserved_maxPorts;
506 __le32 open_reject_cmdretries_data_retries;/* cmd retries: 31-bit16;
507 * data retries: bit15-bit0.
511 } __attribute__((packed, aligned(4)));
514 * brief the data structure of SATA Start Command
515 * use to describe MPI SATA IO Start Command (64 bytes)
518 struct sata_start_req {
522 __le32 ncqtag_atap_dir_m;
523 struct host_to_dev_fis sata_fis;
530 } __attribute__((packed, aligned(4)));
533 * brief the data structure of SSP INI TM Start Command
534 * use to describe MPI SSP INI TM Start Command (64 bytes)
536 struct ssp_ini_tm_start_req {
544 } __attribute__((packed, aligned(4)));
547 struct ssp_info_unit {
548 u8 lun[8];/* SCSI Logical Unit Number */
549 u8 reserved1;/* reserved */
551 /* B7 : enabledFirstBurst */
552 /* B6-3 : taskPriority */
553 /* B2-0 : taskAttribute */
554 u8 reserved2; /* reserved */
555 u8 additional_cdb_len;
556 /* B7-2 : additional_cdb_len */
557 /* B1-0 : reserved */
558 u8 cdb[16];/* The SCSI CDB up to 16 bytes length */
559 } __attribute__((packed, aligned(4)));
563 * brief the data structure of SSP INI IO Start Command
564 * use to describe MPI SSP INI IO Start Command (64 bytes)
566 struct ssp_ini_io_start_req {
571 struct ssp_info_unit ssp_iu;
576 } __attribute__((packed, aligned(4)));
580 * brief the data structure of Firmware download
581 * use to describe MPI FW DOWNLOAD Command (64 bytes)
583 struct fw_flash_Update_req {
585 __le32 cur_image_offset;
586 __le32 cur_image_len;
587 __le32 total_image_len;
593 } __attribute__((packed, aligned(4)));
596 #define FWFLASH_IOMB_RESERVED_LEN 0x07
598 * brief the data structure of FW_FLASH_UPDATE Response
599 * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
602 struct fw_flash_Update_resp {
606 } __attribute__((packed, aligned(4)));
610 * brief the data structure of Get NVM Data Command
611 * use to get data from NVM in HBA(64 bytes)
613 struct get_nvm_data_req {
622 } __attribute__((packed, aligned(4)));
625 struct set_nvm_data_req {
634 } __attribute__((packed, aligned(4)));
637 #define TWI_DEVICE 0x0
638 #define C_SEEPROM 0x1
639 #define VPD_FLASH 0x4
640 #define AAP1_RDUMP 0x5
641 #define IOP_RDUMP 0x6
642 #define EXPAN_ROM 0x7
644 #define IPMode 0x80000000
645 #define NVMD_TYPE 0x0000000F
646 #define NVMD_STAT 0x0000FFFF
647 #define NVMD_LEN 0xFF000000
649 * brief the data structure of Get NVMD Data Response
650 * use to describe MPI Get NVMD Data Response (64 bytes)
652 struct get_nvm_data_resp {
654 __le32 ir_tda_bn_dps_das_nvm;
657 } __attribute__((packed, aligned(4)));
661 * brief the data structure of SAS Diagnostic Start/End Response
662 * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
665 struct sas_diag_start_end_resp {
669 } __attribute__((packed, aligned(4)));
673 * brief the data structure of SAS Diagnostic Execute Response
674 * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
677 struct sas_diag_execute_resp {
679 __le32 cmdtype_cmddesc_phyid;
683 } __attribute__((packed, aligned(4)));
687 * brief the data structure of Set Device State Response
688 * use to describe MPI Set Device State Response (64 bytes)
691 struct set_dev_state_resp {
697 } __attribute__((packed, aligned(4)));
700 #define NDS_BITS 0x0F
701 #define PDS_BITS 0xF0
707 #define HW_EVENT_RESET_START 0x01
708 #define HW_EVENT_CHIP_RESET_COMPLETE 0x02
709 #define HW_EVENT_PHY_STOP_STATUS 0x03
710 #define HW_EVENT_SAS_PHY_UP 0x04
711 #define HW_EVENT_SATA_PHY_UP 0x05
712 #define HW_EVENT_SATA_SPINUP_HOLD 0x06
713 #define HW_EVENT_PHY_DOWN 0x07
714 #define HW_EVENT_PORT_INVALID 0x08
715 #define HW_EVENT_BROADCAST_CHANGE 0x09
716 #define HW_EVENT_PHY_ERROR 0x0A
717 #define HW_EVENT_BROADCAST_SES 0x0B
718 #define HW_EVENT_INBOUND_CRC_ERROR 0x0C
719 #define HW_EVENT_HARD_RESET_RECEIVED 0x0D
720 #define HW_EVENT_MALFUNCTION 0x0E
721 #define HW_EVENT_ID_FRAME_TIMEOUT 0x0F
722 #define HW_EVENT_BROADCAST_EXP 0x10
723 #define HW_EVENT_PHY_START_STATUS 0x11
724 #define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12
725 #define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13
726 #define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14
727 #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15
728 #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16
729 #define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
730 #define HW_EVENT_PORT_RECOVER 0x18
731 #define HW_EVENT_PORT_RESET_TIMER_TMO 0x19
732 #define HW_EVENT_PORT_RESET_COMPLETE 0x20
733 #define EVENT_BROADCAST_ASYNCH_EVENT 0x21
736 #define PORT_NOT_ESTABLISHED 0x00
737 #define PORT_VALID 0x01
738 #define PORT_LOSTCOMM 0x02
739 #define PORT_IN_RESET 0x04
740 #define PORT_INVALID 0x08
743 * SSP/SMP/SATA IO Completion Status values
746 #define IO_SUCCESS 0x00
747 #define IO_ABORTED 0x01
748 #define IO_OVERFLOW 0x02
749 #define IO_UNDERFLOW 0x03
750 #define IO_FAILED 0x04
751 #define IO_ABORT_RESET 0x05
752 #define IO_NOT_VALID 0x06
753 #define IO_NO_DEVICE 0x07
754 #define IO_ILLEGAL_PARAMETER 0x08
755 #define IO_LINK_FAILURE 0x09
756 #define IO_PROG_ERROR 0x0A
757 #define IO_EDC_IN_ERROR 0x0B
758 #define IO_EDC_OUT_ERROR 0x0C
759 #define IO_ERROR_HW_TIMEOUT 0x0D
760 #define IO_XFER_ERROR_BREAK 0x0E
761 #define IO_XFER_ERROR_PHY_NOT_READY 0x0F
762 #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10
763 #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
764 #define IO_OPEN_CNX_ERROR_BREAK 0x12
765 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
766 #define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14
767 #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
768 #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
769 #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
770 #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
771 #define IO_XFER_ERROR_NAK_RECEIVED 0x19
772 #define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
773 #define IO_XFER_ERROR_PEER_ABORTED 0x1B
774 #define IO_XFER_ERROR_RX_FRAME 0x1C
775 #define IO_XFER_ERROR_DMA 0x1D
776 #define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E
777 #define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
778 #define IO_XFER_ERROR_SATA 0x20
779 #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
780 #define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21
781 #define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23
782 #define IO_XFER_OPEN_RETRY_TIMEOUT 0x24
783 #define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25
784 #define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26
785 #define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27
786 #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28
788 #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
789 #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31
790 #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
792 #define IO_XFER_ERROR_OFFSET_MISMATCH 0x34
793 #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35
794 #define IO_XFER_CMD_FRAME_ISSUED 0x36
795 #define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37
796 #define IO_PORT_IN_RESET 0x38
797 #define IO_DS_NON_OPERATIONAL 0x39
798 #define IO_DS_IN_RECOVERY 0x3A
799 #define IO_TM_TAG_NOT_FOUND 0x3B
800 #define IO_XFER_PIO_SETUP_ERROR 0x3C
801 #define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
802 #define IO_DS_IN_ERROR 0x3E
803 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
804 #define IO_ABORT_IN_PROGRESS 0x40
805 #define IO_ABORT_DELAYED 0x41
806 #define IO_INVALID_LENGTH 0x42
808 /* WARNING: This error code must always be the last number.
809 * If you add error code, modify this code also
810 * It is used as an index
812 #define IO_ERROR_UNKNOWN_GENERIC 0x43
814 /* MSGU CONFIGURATION TABLE*/
816 #define SPC_MSGU_CFG_TABLE_UPDATE 0x01/* Inbound doorbell bit0 */
817 #define SPC_MSGU_CFG_TABLE_RESET 0x02/* Inbound doorbell bit1 */
818 #define SPC_MSGU_CFG_TABLE_FREEZE 0x04/* Inbound doorbell bit2 */
819 #define SPC_MSGU_CFG_TABLE_UNFREEZE 0x08/* Inbound doorbell bit4 */
820 #define MSGU_IBDB_SET 0x04
821 #define MSGU_HOST_INT_STATUS 0x08
822 #define MSGU_HOST_INT_MASK 0x0C
823 #define MSGU_IOPIB_INT_STATUS 0x18
824 #define MSGU_IOPIB_INT_MASK 0x1C
825 #define MSGU_IBDB_CLEAR 0x20/* RevB - Host not use */
826 #define MSGU_MSGU_CONTROL 0x24
827 #define MSGU_ODR 0x3C/* RevB */
828 #define MSGU_ODCR 0x40/* RevB */
829 #define MSGU_SCRATCH_PAD_0 0x44
830 #define MSGU_SCRATCH_PAD_1 0x48
831 #define MSGU_SCRATCH_PAD_2 0x4C
832 #define MSGU_SCRATCH_PAD_3 0x50
833 #define MSGU_HOST_SCRATCH_PAD_0 0x54
834 #define MSGU_HOST_SCRATCH_PAD_1 0x58
835 #define MSGU_HOST_SCRATCH_PAD_2 0x5C
836 #define MSGU_HOST_SCRATCH_PAD_3 0x60
837 #define MSGU_HOST_SCRATCH_PAD_4 0x64
838 #define MSGU_HOST_SCRATCH_PAD_5 0x68
839 #define MSGU_HOST_SCRATCH_PAD_6 0x6C
840 #define MSGU_HOST_SCRATCH_PAD_7 0x70
841 #define MSGU_ODMR 0x74/* RevB */
843 /* bit definition for ODMR register */
844 #define ODMR_MASK_ALL 0xFFFFFFFF/* mask all
846 #define ODMR_CLEAR_ALL 0/* clear all
848 /* bit definition for ODCR register */
849 #define ODCR_CLEAR_ALL 0xFFFFFFFF /* mask all
852 #define MSIX_TABLE_OFFSET 0x2000
853 #define MSIX_TABLE_ELEMENT_SIZE 0x10
854 #define MSIX_INTERRUPT_CONTROL_OFFSET 0xC
855 #define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + MSIX_INTERRUPT_CONTROL_OFFSET)
856 #define MSIX_INTERRUPT_DISABLE 0x1
857 #define MSIX_INTERRUPT_ENABLE 0x0
860 /* state definition for Scratch Pad1 register */
861 #define SCRATCH_PAD1_POR 0x00 /* power on reset state */
862 #define SCRATCH_PAD1_SFR 0x01 /* soft reset state */
863 #define SCRATCH_PAD1_ERR 0x02 /* error state */
864 #define SCRATCH_PAD1_RDY 0x03 /* ready state */
865 #define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */
866 #define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */
867 #define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0 /* ScratchPad1
868 Mask, bit1-0 State, bit2 Soft Reset, bit3 FW RDY for Soft Reset */
869 #define SCRATCH_PAD1_RESERVED 0x000003F8 /* Scratch Pad1
870 Reserved bit 3 to 9 */
872 /* state definition for Scratch Pad2 register */
873 #define SCRATCH_PAD2_POR 0x00 /* power on state */
874 #define SCRATCH_PAD2_SFR 0x01 /* soft reset state */
875 #define SCRATCH_PAD2_ERR 0x02 /* error state */
876 #define SCRATCH_PAD2_RDY 0x03 /* ready state */
877 #define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset flag*/
878 #define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */
879 #define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF4 /* ScratchPad 2
880 Mask, bit1-0 State */
881 #define SCRATCH_PAD2_RESERVED 0x000003FC /* Scratch Pad1
882 Reserved bit 2 to 9 */
884 #define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */
885 #define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */
887 /* main configuration offset - byte offset */
888 #define MAIN_SIGNATURE_OFFSET 0x00/* DWORD 0x00 */
889 #define MAIN_INTERFACE_REVISION 0x04/* DWORD 0x01 */
890 #define MAIN_FW_REVISION 0x08/* DWORD 0x02 */
891 #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C/* DWORD 0x03 */
892 #define MAIN_MAX_SGL_OFFSET 0x10/* DWORD 0x04 */
893 #define MAIN_CNTRL_CAP_OFFSET 0x14/* DWORD 0x05 */
894 #define MAIN_GST_OFFSET 0x18/* DWORD 0x06 */
895 #define MAIN_IBQ_OFFSET 0x1C/* DWORD 0x07 */
896 #define MAIN_OBQ_OFFSET 0x20/* DWORD 0x08 */
897 #define MAIN_IQNPPD_HPPD_OFFSET 0x24/* DWORD 0x09 */
898 #define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28/* DWORD 0x0A */
899 #define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C/* DWORD 0x0B */
900 #define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30/* DWORD 0x0C */
901 #define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34/* DWORD 0x0D */
902 #define MAIN_TITNX_EVENT_PID03_OFFSET 0x38/* DWORD 0x0E */
903 #define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C/* DWORD 0x0F */
904 #define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40/* DWORD 0x10 */
905 #define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44/* DWORD 0x11 */
906 #define MAIN_OB_SMP_EVENT_PID03_OFFSET 0x48/* DWORD 0x12 */
907 #define MAIN_OB_SMP_EVENT_PID47_OFFSET 0x4C/* DWORD 0x13 */
908 #define MAIN_EVENT_LOG_ADDR_HI 0x50/* DWORD 0x14 */
909 #define MAIN_EVENT_LOG_ADDR_LO 0x54/* DWORD 0x15 */
910 #define MAIN_EVENT_LOG_BUFF_SIZE 0x58/* DWORD 0x16 */
911 #define MAIN_EVENT_LOG_OPTION 0x5C/* DWORD 0x17 */
912 #define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60/* DWORD 0x18 */
913 #define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64/* DWORD 0x19 */
914 #define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68/* DWORD 0x1A */
915 #define MAIN_IOP_EVENT_LOG_OPTION 0x6C/* DWORD 0x1B */
916 #define MAIN_FATAL_ERROR_INTERRUPT 0x70/* DWORD 0x1C */
917 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74/* DWORD 0x1D */
918 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78/* DWORD 0x1E */
919 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C/* DWORD 0x1F */
920 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80/* DWORD 0x20 */
921 #define MAIN_HDA_FLAGS_OFFSET 0x84/* DWORD 0x21 */
922 #define MAIN_ANALOG_SETUP_OFFSET 0x88/* DWORD 0x22 */
924 /* Gereral Status Table offset - byte offset */
925 #define GST_GSTLEN_MPIS_OFFSET 0x00
926 #define GST_IQ_FREEZE_STATE0_OFFSET 0x04
927 #define GST_IQ_FREEZE_STATE1_OFFSET 0x08
928 #define GST_MSGUTCNT_OFFSET 0x0C
929 #define GST_IOPTCNT_OFFSET 0x10
930 #define GST_PHYSTATE_OFFSET 0x18
931 #define GST_PHYSTATE0_OFFSET 0x18
932 #define GST_PHYSTATE1_OFFSET 0x1C
933 #define GST_PHYSTATE2_OFFSET 0x20
934 #define GST_PHYSTATE3_OFFSET 0x24
935 #define GST_PHYSTATE4_OFFSET 0x28
936 #define GST_PHYSTATE5_OFFSET 0x2C
937 #define GST_PHYSTATE6_OFFSET 0x30
938 #define GST_PHYSTATE7_OFFSET 0x34
939 #define GST_RERRINFO_OFFSET 0x44
941 /* General Status Table - MPI state */
942 #define GST_MPI_STATE_UNINIT 0x00
943 #define GST_MPI_STATE_INIT 0x01
944 #define GST_MPI_STATE_TERMINATION 0x02
945 #define GST_MPI_STATE_ERROR 0x03
946 #define GST_MPI_STATE_MASK 0x07
948 #define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
949 #define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
950 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
951 #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
952 #define PCIE_EVENT_INTERRUPT 0x003044
953 #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
954 #define PCIE_ERROR_INTERRUPT 0x00304C
955 /* signature defintion for host scratch pad0 register */
956 #define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
957 /* Signature for Soft Reset */
959 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
960 #define SPC_REG_RESET 0x000000/* reset register */
962 /* bit difination for SPC_RESET register */
963 #define SPC_REG_RESET_OSSP 0x00000001
964 #define SPC_REG_RESET_RAAE 0x00000002
965 #define SPC_REG_RESET_PCS_SPBC 0x00000004
966 #define SPC_REG_RESET_PCS_IOP_SS 0x00000008
967 #define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
968 #define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
969 #define SPC_REG_RESET_PCS_LM 0x00000040
970 #define SPC_REG_RESET_PCS 0x00000080
971 #define SPC_REG_RESET_GSM 0x00000100
972 #define SPC_REG_RESET_DDR2 0x00010000
973 #define SPC_REG_RESET_BDMA_CORE 0x00020000
974 #define SPC_REG_RESET_BDMA_SXCBI 0x00040000
975 #define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
976 #define SPC_REG_RESET_PCIE_PWR 0x00100000
977 #define SPC_REG_RESET_PCIE_SFT 0x00200000
978 #define SPC_REG_RESET_PCS_SXCBI 0x00400000
979 #define SPC_REG_RESET_LMS_SXCBI 0x00800000
980 #define SPC_REG_RESET_PMIC_SXCBI 0x01000000
981 #define SPC_REG_RESET_PMIC_CORE 0x02000000
982 #define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
983 #define SPC_REG_RESET_DEVICE 0x80000000
985 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
986 #define SPC_IBW_AXI_TRANSLATION_LOW 0x003258
988 #define MBIC_AAP1_ADDR_BASE 0x060000
989 #define MBIC_IOP_ADDR_BASE 0x070000
990 #define GSM_ADDR_BASE 0x0700000
991 /* Dynamic map through Bar4 - 0x00700000 */
992 #define GSM_CONFIG_RESET 0x00000000
993 #define RAM_ECC_DB_ERR 0x00000018
994 #define GSM_READ_ADDR_PARITY_INDIC 0x00000058
995 #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
996 #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
997 #define GSM_READ_ADDR_PARITY_CHECK 0x00000038
998 #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
999 #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
1001 #define RB6_ACCESS_REG 0x6A0000
1002 #define HDAC_EXEC_CMD 0x0002
1003 #define HDA_C_PA 0xcb
1004 #define HDA_SEQ_ID_BITS 0x00ff0000
1005 #define HDA_GSM_OFFSET_BITS 0x00FFFFFF
1006 #define MBIC_AAP1_ADDR_BASE 0x060000
1007 #define MBIC_IOP_ADDR_BASE 0x070000
1008 #define GSM_ADDR_BASE 0x0700000
1009 #define SPC_TOP_LEVEL_ADDR_BASE 0x000000
1010 #define GSM_CONFIG_RESET_VALUE 0x00003b00
1011 #define GPIO_ADDR_BASE 0x00090000
1012 #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
1015 #define SPC_RB6_OFFSET 0x80C0
1016 /* Magic number of soft reset for RB6 */
1017 #define RB6_MAGIC_NUMBER_RST 0x1234
1019 /* Device Register status */
1020 #define DEVREG_SUCCESS 0x00
1021 #define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01
1022 #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02
1023 #define DEVREG_FAILURE_INVALID_PHY_ID 0x03
1024 #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04
1025 #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05
1026 #define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06
1027 #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07