drivers/scsi/pm8001/pm8001_hwi.c

   1 /*
   2  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include <linux/slab.h>
  41  #include "pm8001_sas.h"
  42  #include "pm8001_hwi.h"
  43  #include "pm8001_chips.h"
  44  #include "pm8001_ctl.h"
  45
  46 /**
  47  * read_main_config_table - read the configure table and save it.
  48  * @pm8001_ha: our hba card information
  49  */
  50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  51 {
  52         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  53         pm8001_ha->main_cfg_tbl.signature       = pm8001_mr32(address, 0x00);
  54         pm8001_ha->main_cfg_tbl.interface_rev   = pm8001_mr32(address, 0x04);
  55         pm8001_ha->main_cfg_tbl.firmware_rev    = pm8001_mr32(address, 0x08);
  56         pm8001_ha->main_cfg_tbl.max_out_io      = pm8001_mr32(address, 0x0C);
  57         pm8001_ha->main_cfg_tbl.max_sgl         = pm8001_mr32(address, 0x10);
  58         pm8001_ha->main_cfg_tbl.ctrl_cap_flag   = pm8001_mr32(address, 0x14);
  59         pm8001_ha->main_cfg_tbl.gst_offset      = pm8001_mr32(address, 0x18);
  60         pm8001_ha->main_cfg_tbl.inbound_queue_offset =
  61                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
  62         pm8001_ha->main_cfg_tbl.outbound_queue_offset =
  63                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
  64         pm8001_ha->main_cfg_tbl.hda_mode_flag   =
  65                 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  66
  67         /* read analog Setting offset from the configuration table */
  68         pm8001_ha->main_cfg_tbl.anolog_setup_table_offset =
  69                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  70
  71         /* read Error Dump Offset and Length */
  72         pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 =
  73                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  74         pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 =
  75                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  76         pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 =
  77                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  78         pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 =
  79                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  80 }
  81
  82 /**
  83  * read_general_status_table - read the general status table and save it.
  84  * @pm8001_ha: our hba card information
  85  */
  86 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  87 {
  88         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  89         pm8001_ha->gs_tbl.gst_len_mpistate      = pm8001_mr32(address, 0x00);
  90         pm8001_ha->gs_tbl.iq_freeze_state0      = pm8001_mr32(address, 0x04);
  91         pm8001_ha->gs_tbl.iq_freeze_state1      = pm8001_mr32(address, 0x08);
  92         pm8001_ha->gs_tbl.msgu_tcnt             = pm8001_mr32(address, 0x0C);
  93         pm8001_ha->gs_tbl.iop_tcnt              = pm8001_mr32(address, 0x10);
  94         pm8001_ha->gs_tbl.reserved              = pm8001_mr32(address, 0x14);
  95         pm8001_ha->gs_tbl.phy_state[0]  = pm8001_mr32(address, 0x18);
  96         pm8001_ha->gs_tbl.phy_state[1]  = pm8001_mr32(address, 0x1C);
  97         pm8001_ha->gs_tbl.phy_state[2]  = pm8001_mr32(address, 0x20);
  98         pm8001_ha->gs_tbl.phy_state[3]  = pm8001_mr32(address, 0x24);
  99         pm8001_ha->gs_tbl.phy_state[4]  = pm8001_mr32(address, 0x28);
 100         pm8001_ha->gs_tbl.phy_state[5]  = pm8001_mr32(address, 0x2C);
 101         pm8001_ha->gs_tbl.phy_state[6]  = pm8001_mr32(address, 0x30);
 102         pm8001_ha->gs_tbl.phy_state[7]  = pm8001_mr32(address, 0x34);
 103         pm8001_ha->gs_tbl.reserved1             = pm8001_mr32(address, 0x38);
 104         pm8001_ha->gs_tbl.reserved2             = pm8001_mr32(address, 0x3C);
 105         pm8001_ha->gs_tbl.reserved3             = pm8001_mr32(address, 0x40);
 106         pm8001_ha->gs_tbl.recover_err_info[0]   = pm8001_mr32(address, 0x44);
 107         pm8001_ha->gs_tbl.recover_err_info[1]   = pm8001_mr32(address, 0x48);
 108         pm8001_ha->gs_tbl.recover_err_info[2]   = pm8001_mr32(address, 0x4C);
 109         pm8001_ha->gs_tbl.recover_err_info[3]   = pm8001_mr32(address, 0x50);
 110         pm8001_ha->gs_tbl.recover_err_info[4]   = pm8001_mr32(address, 0x54);
 111         pm8001_ha->gs_tbl.recover_err_info[5]   = pm8001_mr32(address, 0x58);
 112         pm8001_ha->gs_tbl.recover_err_info[6]   = pm8001_mr32(address, 0x5C);
 113         pm8001_ha->gs_tbl.recover_err_info[7]   = pm8001_mr32(address, 0x60);
 114 }
 115
 116 /**
 117  * read_inbnd_queue_table - read the inbound queue table and save it.
 118  * @pm8001_ha: our hba card information
 119  */
 120 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 121 {
 122         int inbQ_num = 1;
 123         int i;
 124         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 125         for (i = 0; i < inbQ_num; i++) {
 126                 u32 offset = i * 0x20;
 127                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 128                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 129                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 130                         pm8001_mr32(address, (offset + 0x18));
 131         }
 132 }
 133
 134 /**
 135  * read_outbnd_queue_table - read the outbound queue table and save it.
 136  * @pm8001_ha: our hba card information
 137  */
 138 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 139 {
 140         int outbQ_num = 1;
 141         int i;
 142         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 143         for (i = 0; i < outbQ_num; i++) {
 144                 u32 offset = i * 0x24;
 145                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 146                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 147                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 148                         pm8001_mr32(address, (offset + 0x18));
 149         }
 150 }
 151
 152 /**
 153  * init_default_table_values - init the default table.
 154  * @pm8001_ha: our hba card information
 155  */
 156 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 157 {
 158         int qn = 1;
 159         int i;
 160         u32 offsetib, offsetob;
 161         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 162         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 163
 164         pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd                     = 0;
 165         pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3                = 0;
 166         pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7                = 0;
 167         pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3               = 0;
 168         pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7               = 0;
 169         pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3       = 0;
 170         pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7       = 0;
 171         pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3   = 0;
 172         pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7   = 0;
 173         pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3   = 0;
 174         pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7   = 0;
 175
 176         pm8001_ha->main_cfg_tbl.upper_event_log_addr            =
 177                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 178         pm8001_ha->main_cfg_tbl.lower_event_log_addr            =
 179                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 180         pm8001_ha->main_cfg_tbl.event_log_size  = PM8001_EVENT_LOG_SIZE;
 181         pm8001_ha->main_cfg_tbl.event_log_option                = 0x01;
 182         pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr        =
 183                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 184         pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr        =
 185                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 186         pm8001_ha->main_cfg_tbl.iop_event_log_size      = PM8001_EVENT_LOG_SIZE;
 187         pm8001_ha->main_cfg_tbl.iop_event_log_option            = 0x01;
 188         pm8001_ha->main_cfg_tbl.fatal_err_interrupt             = 0x01;
 189         for (i = 0; i < qn; i++) {
 190                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 191                         PM8001_MPI_QUEUE | (64 << 16) | (0x00<<30);
 192                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 193                         pm8001_ha->memoryMap.region[IB].phys_addr_hi;
 194                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 195                 pm8001_ha->memoryMap.region[IB].phys_addr_lo;
 196                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 197                         (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr;
 198                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 199                         pm8001_ha->memoryMap.region[IB].total_len;
 200                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 201                         pm8001_ha->memoryMap.region[CI].phys_addr_hi;
 202                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 203                         pm8001_ha->memoryMap.region[CI].phys_addr_lo;
 204                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 205                         pm8001_ha->memoryMap.region[CI].virt_ptr;
 206                 offsetib = i * 0x20;
 207                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 208                         get_pci_bar_index(pm8001_mr32(addressib,
 209                                 (offsetib + 0x14)));
 210                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 211                         pm8001_mr32(addressib, (offsetib + 0x18));
 212                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 213                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 214         }
 215         for (i = 0; i < qn; i++) {
 216                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 217                         PM8001_MPI_QUEUE | (64 << 16) | (0x01<<30);
 218                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 219                         pm8001_ha->memoryMap.region[OB].phys_addr_hi;
 220                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 221                         pm8001_ha->memoryMap.region[OB].phys_addr_lo;
 222                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 223                         (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr;
 224                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 225                         pm8001_ha->memoryMap.region[OB].total_len;
 226                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 227                         pm8001_ha->memoryMap.region[PI].phys_addr_hi;
 228                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 229                         pm8001_ha->memoryMap.region[PI].phys_addr_lo;
 230                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay       =
 231                         0 | (10 << 16) | (0 << 24);
 232                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 233                         pm8001_ha->memoryMap.region[PI].virt_ptr;
 234                 offsetob = i * 0x24;
 235                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 236                         get_pci_bar_index(pm8001_mr32(addressob,
 237                         offsetob + 0x14));
 238                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 239                         pm8001_mr32(addressob, (offsetob + 0x18));
 240                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 241                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 242         }
 243 }
 244
 245 /**
 246  * update_main_config_table - update the main default table to the HBA.
 247  * @pm8001_ha: our hba card information
 248  */
 249 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 250 {
 251         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 252         pm8001_mw32(address, 0x24,
 253                 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd);
 254         pm8001_mw32(address, 0x28,
 255                 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3);
 256         pm8001_mw32(address, 0x2C,
 257                 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7);
 258         pm8001_mw32(address, 0x30,
 259                 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3);
 260         pm8001_mw32(address, 0x34,
 261                 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7);
 262         pm8001_mw32(address, 0x38,
 263                 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3);
 264         pm8001_mw32(address, 0x3C,
 265                 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7);
 266         pm8001_mw32(address, 0x40,
 267                 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3);
 268         pm8001_mw32(address, 0x44,
 269                 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7);
 270         pm8001_mw32(address, 0x48,
 271                 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3);
 272         pm8001_mw32(address, 0x4C,
 273                 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7);
 274         pm8001_mw32(address, 0x50,
 275                 pm8001_ha->main_cfg_tbl.upper_event_log_addr);
 276         pm8001_mw32(address, 0x54,
 277                 pm8001_ha->main_cfg_tbl.lower_event_log_addr);
 278         pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size);
 279         pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option);
 280         pm8001_mw32(address, 0x60,
 281                 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr);
 282         pm8001_mw32(address, 0x64,
 283                 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr);
 284         pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size);
 285         pm8001_mw32(address, 0x6C,
 286                 pm8001_ha->main_cfg_tbl.iop_event_log_option);
 287         pm8001_mw32(address, 0x70,
 288                 pm8001_ha->main_cfg_tbl.fatal_err_interrupt);
 289 }
 290
 291 /**
 292  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 293  * @pm8001_ha: our hba card information
 294  */
 295 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 296                                      int number)
 297 {
 298         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 299         u16 offset = number * 0x20;
 300         pm8001_mw32(address, offset + 0x00,
 301                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 302         pm8001_mw32(address, offset + 0x04,
 303                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 304         pm8001_mw32(address, offset + 0x08,
 305                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 306         pm8001_mw32(address, offset + 0x0C,
 307                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 308         pm8001_mw32(address, offset + 0x10,
 309                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 310 }
 311
 312 /**
 313  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 314  * @pm8001_ha: our hba card information
 315  */
 316 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 317                                       int number)
 318 {
 319         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 320         u16 offset = number * 0x24;
 321         pm8001_mw32(address, offset + 0x00,
 322                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 323         pm8001_mw32(address, offset + 0x04,
 324                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 325         pm8001_mw32(address, offset + 0x08,
 326                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 327         pm8001_mw32(address, offset + 0x0C,
 328                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 329         pm8001_mw32(address, offset + 0x10,
 330                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 331         pm8001_mw32(address, offset + 0x1C,
 332                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 333 }
 334
 335 /**
 336  * pm8001_bar4_shift - function is called to shift BAR base address
 337  * @pm8001_ha : our hba card infomation
 338  * @shiftValue : shifting value in memory bar.
 339  */
 340 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
 341 {
 342         u32 regVal;
 343         unsigned long start;
 344
 345         /* program the inbound AXI translation Lower Address */
 346         pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
 347
 348         /* confirm the setting is written */
 349         start = jiffies + HZ; /* 1 sec */
 350         do {
 351                 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
 352         } while ((regVal != shiftValue) && time_before(jiffies, start));
 353
 354         if (regVal != shiftValue) {
 355                 PM8001_INIT_DBG(pm8001_ha,
 356                         pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
 357                         " = 0x%x\n", regVal));
 358                 return -1;
 359         }
 360         return 0;
 361 }
 362
 363 /**
 364  * mpi_set_phys_g3_with_ssc
 365  * @pm8001_ha: our hba card information
 366  * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
 367  */
 368 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
 369                                      u32 SSCbit)
 370 {
 371         u32 value, offset, i;
 372         unsigned long flags;
 373
 374 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
 375 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
 376 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
 377 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
 378 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
 379 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
 380 #define SNW3_PHY_CAPABILITIES_PARITY 31
 381
 382    /*
 383     * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
 384     * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
 385     */
 386         spin_lock_irqsave(&pm8001_ha->lock, flags);
 387         if (-1 == pm8001_bar4_shift(pm8001_ha,
 388                                 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
 389                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 390                 return;
 391         }
 392
 393         for (i = 0; i < 4; i++) {
 394                 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
 395                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 396         }
 397         /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
 398         if (-1 == pm8001_bar4_shift(pm8001_ha,
 399                                 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
 400                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 401                 return;
 402         }
 403         for (i = 4; i < 8; i++) {
 404                 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 405                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 406         }
 407         /*************************************************************
 408         Change the SSC upspreading value to 0x0 so that upspreading is disabled.
 409         Device MABC SMOD0 Controls
 410         Address: (via MEMBASE-III):
 411         Using shifted destination address 0x0_0000: with Offset 0xD8
 412
 413         31:28 R/W Reserved Do not change
 414         27:24 R/W SAS_SMOD_SPRDUP 0000
 415         23:20 R/W SAS_SMOD_SPRDDN 0000
 416         19:0  R/W  Reserved Do not change
 417         Upon power-up this register will read as 0x8990c016,
 418         and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
 419         so that the written value will be 0x8090c016.
 420         This will ensure only down-spreading SSC is enabled on the SPC.
 421         *************************************************************/
 422         value = pm8001_cr32(pm8001_ha, 2, 0xd8);
 423         pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
 424
 425         /*set the shifted destination address to 0x0 to avoid error operation */
 426         pm8001_bar4_shift(pm8001_ha, 0x0);
 427         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 428         return;
 429 }
 430
 431 /**
 432  * mpi_set_open_retry_interval_reg
 433  * @pm8001_ha: our hba card information
 434  * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
 435  */
 436 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
 437                                             u32 interval)
 438 {
 439         u32 offset;
 440         u32 value;
 441         u32 i;
 442         unsigned long flags;
 443
 444 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
 445 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
 446 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
 447 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
 448 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
 449
 450         value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
 451         spin_lock_irqsave(&pm8001_ha->lock, flags);
 452         /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
 453         if (-1 == pm8001_bar4_shift(pm8001_ha,
 454                              OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
 455                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 456                 return;
 457         }
 458         for (i = 0; i < 4; i++) {
 459                 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
 460                 pm8001_cw32(pm8001_ha, 2, offset, value);
 461         }
 462
 463         if (-1 == pm8001_bar4_shift(pm8001_ha,
 464                              OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
 465                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 466                 return;
 467         }
 468         for (i = 4; i < 8; i++) {
 469                 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 470                 pm8001_cw32(pm8001_ha, 2, offset, value);
 471         }
 472         /*set the shifted destination address to 0x0 to avoid error operation */
 473         pm8001_bar4_shift(pm8001_ha, 0x0);
 474         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 475         return;
 476 }
 477
 478 /**
 479  * mpi_init_check - check firmware initialization status.
 480  * @pm8001_ha: our hba card information
 481  */
 482 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 483 {
 484         u32 max_wait_count;
 485         u32 value;
 486         u32 gst_len_mpistate;
 487         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 488         table is updated */
 489         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
 490         /* wait until Inbound DoorBell Clear Register toggled */
 491         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 492         do {
 493                 udelay(1);
 494                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 495                 value &= SPC_MSGU_CFG_TABLE_UPDATE;
 496         } while ((value != 0) && (--max_wait_count));
 497
 498         if (!max_wait_count)
 499                 return -1;
 500         /* check the MPI-State for initialization */
 501         gst_len_mpistate =
 502                 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 503                 GST_GSTLEN_MPIS_OFFSET);
 504         if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
 505                 return -1;
 506         /* check MPI Initialization error */
 507         gst_len_mpistate = gst_len_mpistate >> 16;
 508         if (0x0000 != gst_len_mpistate)
 509                 return -1;
 510         return 0;
 511 }
 512
 513 /**
 514  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 515  * @pm8001_ha: our hba card information
 516  */
 517 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 518 {
 519         u32 value, value1;
 520         u32 max_wait_count;
 521         /* check error state */
 522         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 523         value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 524         /* check AAP error */
 525         if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
 526                 /* error state */
 527                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 528                 return -1;
 529         }
 530
 531         /* check IOP error */
 532         if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
 533                 /* error state */
 534                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 535                 return -1;
 536         }
 537
 538         /* bit 4-31 of scratch pad1 should be zeros if it is not
 539         in error state*/
 540         if (value & SCRATCH_PAD1_STATE_MASK) {
 541                 /* error case */
 542                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 543                 return -1;
 544         }
 545
 546         /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
 547         in error state */
 548         if (value1 & SCRATCH_PAD2_STATE_MASK) {
 549                 /* error case */
 550                 return -1;
 551         }
 552
 553         max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
 554
 555         /* wait until scratch pad 1 and 2 registers in ready state  */
 556         do {
 557                 udelay(1);
 558                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 559                         & SCRATCH_PAD1_RDY;
 560                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 561                         & SCRATCH_PAD2_RDY;
 562                 if ((--max_wait_count) == 0)
 563                         return -1;
 564         } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
 565         return 0;
 566 }
 567
 568 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 569 {
 570         void __iomem *base_addr;
 571         u32     value;
 572         u32     offset;
 573         u32     pcibar;
 574         u32     pcilogic;
 575
 576         value = pm8001_cr32(pm8001_ha, 0, 0x44);
 577         offset = value & 0x03FFFFFF;
 578         PM8001_INIT_DBG(pm8001_ha,
 579                 pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
 580         pcilogic = (value & 0xFC000000) >> 26;
 581         pcibar = get_pci_bar_index(pcilogic);
 582         PM8001_INIT_DBG(pm8001_ha,
 583                 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
 584         pm8001_ha->main_cfg_tbl_addr = base_addr =
 585                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 586         pm8001_ha->general_stat_tbl_addr =
 587                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
 588         pm8001_ha->inbnd_q_tbl_addr =
 589                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
 590         pm8001_ha->outbnd_q_tbl_addr =
 591                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
 592 }
 593
 594 /**
 595  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 596  * @pm8001_ha: our hba card information
 597  */
 598 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
 599 {
 600         /* check the firmware status */
 601         if (-1 == check_fw_ready(pm8001_ha)) {
 602                 PM8001_FAIL_DBG(pm8001_ha,
 603                         pm8001_printk("Firmware is not ready!\n"));
 604                 return -EBUSY;
 605         }
 606
 607         /* Initialize pci space address eg: mpi offset */
 608         init_pci_device_addresses(pm8001_ha);
 609         init_default_table_values(pm8001_ha);
 610         read_main_config_table(pm8001_ha);
 611         read_general_status_table(pm8001_ha);
 612         read_inbnd_queue_table(pm8001_ha);
 613         read_outbnd_queue_table(pm8001_ha);
 614         /* update main config table ,inbound table and outbound table */
 615         update_main_config_table(pm8001_ha);
 616         update_inbnd_queue_table(pm8001_ha, 0);
 617         update_outbnd_queue_table(pm8001_ha, 0);
 618         mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
 619         /* 7->130ms, 34->500ms, 119->1.5s */
 620         mpi_set_open_retry_interval_reg(pm8001_ha, 119);
 621         /* notify firmware update finished and check initialization status */
 622         if (0 == mpi_init_check(pm8001_ha)) {
 623                 PM8001_INIT_DBG(pm8001_ha,
 624                         pm8001_printk("MPI initialize successful!\n"));
 625         } else
 626                 return -EBUSY;
 627         /*This register is a 16-bit timer with a resolution of 1us. This is the
 628         timer used for interrupt delay/coalescing in the PCIe Application Layer.
 629         Zero is not a valid value. A value of 1 in the register will cause the
 630         interrupts to be normal. A value greater than 1 will cause coalescing
 631         delays.*/
 632         pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
 633         pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
 634         return 0;
 635 }
 636
 637 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
 638 {
 639         u32 max_wait_count;
 640         u32 value;
 641         u32 gst_len_mpistate;
 642         init_pci_device_addresses(pm8001_ha);
 643         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
 644         table is stop */
 645         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
 646
 647         /* wait until Inbound DoorBell Clear Register toggled */
 648         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 649         do {
 650                 udelay(1);
 651                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 652                 value &= SPC_MSGU_CFG_TABLE_RESET;
 653         } while ((value != 0) && (--max_wait_count));
 654
 655         if (!max_wait_count) {
 656                 PM8001_FAIL_DBG(pm8001_ha,
 657                         pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
 658                 return -1;
 659         }
 660
 661         /* check the MPI-State for termination in progress */
 662         /* wait until Inbound DoorBell Clear Register toggled */
 663         max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 664         do {
 665                 udelay(1);
 666                 gst_len_mpistate =
 667                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 668                         GST_GSTLEN_MPIS_OFFSET);
 669                 if (GST_MPI_STATE_UNINIT ==
 670                         (gst_len_mpistate & GST_MPI_STATE_MASK))
 671                         break;
 672         } while (--max_wait_count);
 673         if (!max_wait_count) {
 674                 PM8001_FAIL_DBG(pm8001_ha,
 675                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
 676                                 gst_len_mpistate & GST_MPI_STATE_MASK));
 677                 return -1;
 678         }
 679         return 0;
 680 }
 681
 682 /**
 683  * soft_reset_ready_check - Function to check FW is ready for soft reset.
 684  * @pm8001_ha: our hba card information
 685  */
 686 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
 687 {
 688         u32 regVal, regVal1, regVal2;
 689         if (mpi_uninit_check(pm8001_ha) != 0) {
 690                 PM8001_FAIL_DBG(pm8001_ha,
 691                         pm8001_printk("MPI state is not ready\n"));
 692                 return -1;
 693         }
 694         /* read the scratch pad 2 register bit 2 */
 695         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 696                 & SCRATCH_PAD2_FWRDY_RST;
 697         if (regVal == SCRATCH_PAD2_FWRDY_RST) {
 698                 PM8001_INIT_DBG(pm8001_ha,
 699                         pm8001_printk("Firmware is ready for reset .\n"));
 700         } else {
 701                 unsigned long flags;
 702                 /* Trigger NMI twice via RB6 */
 703                 spin_lock_irqsave(&pm8001_ha->lock, flags);
 704                 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
 705                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 706                         PM8001_FAIL_DBG(pm8001_ha,
 707                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 708                                         RB6_ACCESS_REG));
 709                         return -1;
 710                 }
 711                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
 712                         RB6_MAGIC_NUMBER_RST);
 713                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
 714                 /* wait for 100 ms */
 715                 mdelay(100);
 716                 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
 717                         SCRATCH_PAD2_FWRDY_RST;
 718                 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
 719                         regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 720                         regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 721                         PM8001_FAIL_DBG(pm8001_ha,
 722                                 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
 723                                 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
 724                                 regVal1, regVal2));
 725                         PM8001_FAIL_DBG(pm8001_ha,
 726                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
 727                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
 728                         PM8001_FAIL_DBG(pm8001_ha,
 729                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
 730                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
 731                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 732                         return -1;
 733                 }
 734                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 735         }
 736         return 0;
 737 }
 738
 739 /**
 740  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 741  * the FW register status to the originated status.
 742  * @pm8001_ha: our hba card information
 743  * @signature: signature in host scratch pad0 register.
 744  */
 745 static int
 746 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
 747 {
 748         u32     regVal, toggleVal;
 749         u32     max_wait_count;
 750         u32     regVal1, regVal2, regVal3;
 751         unsigned long flags;
 752
 753         /* step1: Check FW is ready for soft reset */
 754         if (soft_reset_ready_check(pm8001_ha) != 0) {
 755                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
 756                 return -1;
 757         }
 758
 759         /* step 2: clear NMI status register on AAP1 and IOP, write the same
 760         value to clear */
 761         /* map 0x60000 to BAR4(0x20), BAR2(win) */
 762         spin_lock_irqsave(&pm8001_ha->lock, flags);
 763         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
 764                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 765                 PM8001_FAIL_DBG(pm8001_ha,
 766                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 767                         MBIC_AAP1_ADDR_BASE));
 768                 return -1;
 769         }
 770         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
 771         PM8001_INIT_DBG(pm8001_ha,
 772                 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
 773         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
 774         /* map 0x70000 to BAR4(0x20), BAR2(win) */
 775         if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
 776                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 777                 PM8001_FAIL_DBG(pm8001_ha,
 778                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 779                         MBIC_IOP_ADDR_BASE));
 780                 return -1;
 781         }
 782         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
 783         PM8001_INIT_DBG(pm8001_ha,
 784                 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
 785         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
 786
 787         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
 788         PM8001_INIT_DBG(pm8001_ha,
 789                 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
 790         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
 791
 792         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
 793         PM8001_INIT_DBG(pm8001_ha,
 794                 pm8001_printk("PCIE - Event Interrupt  = 0x%x\n", regVal));
 795         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
 796
 797         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
 798         PM8001_INIT_DBG(pm8001_ha,
 799                 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
 800         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
 801
 802         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
 803         PM8001_INIT_DBG(pm8001_ha,
 804                 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
 805         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
 806
 807         /* read the scratch pad 1 register bit 2 */
 808         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 809                 & SCRATCH_PAD1_RST;
 810         toggleVal = regVal ^ SCRATCH_PAD1_RST;
 811
 812         /* set signature in host scratch pad0 register to tell SPC that the
 813         host performs the soft reset */
 814         pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
 815
 816         /* read required registers for confirmming */
 817         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 818         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 819                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 820                 PM8001_FAIL_DBG(pm8001_ha,
 821                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 822                         GSM_ADDR_BASE));
 823                 return -1;
 824         }
 825         PM8001_INIT_DBG(pm8001_ha,
 826                 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
 827                 " Reset = 0x%x\n",
 828                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 829
 830         /* step 3: host read GSM Configuration and Reset register */
 831         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 832         /* Put those bits to low */
 833         /* GSM XCBI offset = 0x70 0000
 834         0x00 Bit 13 COM_SLV_SW_RSTB 1
 835         0x00 Bit 12 QSSP_SW_RSTB 1
 836         0x00 Bit 11 RAAE_SW_RSTB 1
 837         0x00 Bit 9 RB_1_SW_RSTB 1
 838         0x00 Bit 8 SM_SW_RSTB 1
 839         */
 840         regVal &= ~(0x00003b00);
 841         /* host write GSM Configuration and Reset register */
 842         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 843         PM8001_INIT_DBG(pm8001_ha,
 844                 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
 845                 "Configuration and Reset is set to = 0x%x\n",
 846                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 847
 848         /* step 4: */
 849         /* disable GSM - Read Address Parity Check */
 850         regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 851         PM8001_INIT_DBG(pm8001_ha,
 852                 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
 853                 "Enable = 0x%x\n", regVal1));
 854         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
 855         PM8001_INIT_DBG(pm8001_ha,
 856                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
 857                 "is set to = 0x%x\n",
 858                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
 859
 860         /* disable GSM - Write Address Parity Check */
 861         regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 862         PM8001_INIT_DBG(pm8001_ha,
 863                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
 864                 " Enable = 0x%x\n", regVal2));
 865         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
 866         PM8001_INIT_DBG(pm8001_ha,
 867                 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
 868                 "Enable is set to = 0x%x\n",
 869                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
 870
 871         /* disable GSM - Write Data Parity Check */
 872         regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 873         PM8001_INIT_DBG(pm8001_ha,
 874                 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
 875                 " Enable = 0x%x\n", regVal3));
 876         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
 877         PM8001_INIT_DBG(pm8001_ha,
 878                 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
 879                 "is set to = 0x%x\n",
 880         pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
 881
 882         /* step 5: delay 10 usec */
 883         udelay(10);
 884         /* step 5-b: set GPIO-0 output control to tristate anyway */
 885         if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
 886                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 887                 PM8001_INIT_DBG(pm8001_ha,
 888                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 889                                 GPIO_ADDR_BASE));
 890                 return -1;
 891         }
 892         regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
 893                 PM8001_INIT_DBG(pm8001_ha,
 894                                 pm8001_printk("GPIO Output Control Register:"
 895                                 " = 0x%x\n", regVal));
 896         /* set GPIO-0 output control to tri-state */
 897         regVal &= 0xFFFFFFFC;
 898         pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
 899
 900         /* Step 6: Reset the IOP and AAP1 */
 901         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 902         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 903                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 904                 PM8001_FAIL_DBG(pm8001_ha,
 905                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 906                         SPC_TOP_LEVEL_ADDR_BASE));
 907                 return -1;
 908         }
 909         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 910         PM8001_INIT_DBG(pm8001_ha,
 911                 pm8001_printk("Top Register before resetting IOP/AAP1"
 912                 ":= 0x%x\n", regVal));
 913         regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 914         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 915
 916         /* step 7: Reset the BDMA/OSSP */
 917         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 918         PM8001_INIT_DBG(pm8001_ha,
 919                 pm8001_printk("Top Register before resetting BDMA/OSSP"
 920                 ": = 0x%x\n", regVal));
 921         regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 922         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 923
 924         /* step 8: delay 10 usec */
 925         udelay(10);
 926
 927         /* step 9: bring the BDMA and OSSP out of reset */
 928         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 929         PM8001_INIT_DBG(pm8001_ha,
 930                 pm8001_printk("Top Register before bringing up BDMA/OSSP"
 931                 ":= 0x%x\n", regVal));
 932         regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 933         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 934
 935         /* step 10: delay 10 usec */
 936         udelay(10);
 937
 938         /* step 11: reads and sets the GSM Configuration and Reset Register */
 939         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 940         if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 941                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 942                 PM8001_FAIL_DBG(pm8001_ha,
 943                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 944                         GSM_ADDR_BASE));
 945                 return -1;
 946         }
 947         PM8001_INIT_DBG(pm8001_ha,
 948                 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
 949                 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 950         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 951         /* Put those bits to high */
 952         /* GSM XCBI offset = 0x70 0000
 953         0x00 Bit 13 COM_SLV_SW_RSTB 1
 954         0x00 Bit 12 QSSP_SW_RSTB 1
 955         0x00 Bit 11 RAAE_SW_RSTB 1
 956         0x00 Bit 9   RB_1_SW_RSTB 1
 957         0x00 Bit 8   SM_SW_RSTB 1
 958         */
 959         regVal |= (GSM_CONFIG_RESET_VALUE);
 960         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 961         PM8001_INIT_DBG(pm8001_ha,
 962                 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
 963                 " Configuration and Reset is set to = 0x%x\n",
 964                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 965
 966         /* step 12: Restore GSM - Read Address Parity Check */
 967         regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 968         /* just for debugging */
 969         PM8001_INIT_DBG(pm8001_ha,
 970                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
 971                 " = 0x%x\n", regVal));
 972         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
 973         PM8001_INIT_DBG(pm8001_ha,
 974                 pm8001_printk("GSM 0x700038 - Read Address Parity"
 975                 " Check Enable is set to = 0x%x\n",
 976                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
 977         /* Restore GSM - Write Address Parity Check */
 978         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 979         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
 980         PM8001_INIT_DBG(pm8001_ha,
 981                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
 982                 " Enable is set to = 0x%x\n",
 983                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
 984         /* Restore GSM - Write Data Parity Check */
 985         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 986         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
 987         PM8001_INIT_DBG(pm8001_ha,
 988                 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
 989                 "is set to = 0x%x\n",
 990                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
 991
 992         /* step 13: bring the IOP and AAP1 out of reset */
 993         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 994         if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 995                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 996                 PM8001_FAIL_DBG(pm8001_ha,
 997                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 998                         SPC_TOP_LEVEL_ADDR_BASE));
 999                 return -1;
1000         }
1001         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1002         regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1003         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1004
1005         /* step 14: delay 10 usec - Normal Mode */
1006         udelay(10);
1007         /* check Soft Reset Normal mode or Soft Reset HDA mode */
1008         if (signature == SPC_SOFT_RESET_SIGNATURE) {
1009                 /* step 15 (Normal Mode): wait until scratch pad1 register
1010                 bit 2 toggled */
1011                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1012                 do {
1013                         udelay(1);
1014                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1015                                 SCRATCH_PAD1_RST;
1016                 } while ((regVal != toggleVal) && (--max_wait_count));
1017
1018                 if (!max_wait_count) {
1019                         regVal = pm8001_cr32(pm8001_ha, 0,
1020                                 MSGU_SCRATCH_PAD_1);
1021                         PM8001_FAIL_DBG(pm8001_ha,
1022                                 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1023                                 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1024                                 toggleVal, regVal));
1025                         PM8001_FAIL_DBG(pm8001_ha,
1026                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1027                                 pm8001_cr32(pm8001_ha, 0,
1028                                 MSGU_SCRATCH_PAD_0)));
1029                         PM8001_FAIL_DBG(pm8001_ha,
1030                                 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1031                                 pm8001_cr32(pm8001_ha, 0,
1032                                 MSGU_SCRATCH_PAD_2)));
1033                         PM8001_FAIL_DBG(pm8001_ha,
1034                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1035                                 pm8001_cr32(pm8001_ha, 0,
1036                                 MSGU_SCRATCH_PAD_3)));
1037                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1038                         return -1;
1039                 }
1040
1041                 /* step 16 (Normal) - Clear ODMR and ODCR */
1042                 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1043                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1044
1045                 /* step 17 (Normal Mode): wait for the FW and IOP to get
1046                 ready - 1 sec timeout */
1047                 /* Wait for the SPC Configuration Table to be ready */
1048                 if (check_fw_ready(pm8001_ha) == -1) {
1049                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1050                         /* return error if MPI Configuration Table not ready */
1051                         PM8001_INIT_DBG(pm8001_ha,
1052                                 pm8001_printk("FW not ready SCRATCH_PAD1"
1053                                 " = 0x%x\n", regVal));
1054                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1055                         /* return error if MPI Configuration Table not ready */
1056                         PM8001_INIT_DBG(pm8001_ha,
1057                                 pm8001_printk("FW not ready SCRATCH_PAD2"
1058                                 " = 0x%x\n", regVal));
1059                         PM8001_INIT_DBG(pm8001_ha,
1060                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1061                                 pm8001_cr32(pm8001_ha, 0,
1062                                 MSGU_SCRATCH_PAD_0)));
1063                         PM8001_INIT_DBG(pm8001_ha,
1064                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1065                                 pm8001_cr32(pm8001_ha, 0,
1066                                 MSGU_SCRATCH_PAD_3)));
1067                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1068                         return -1;
1069                 }
1070         }
1071         pm8001_bar4_shift(pm8001_ha, 0);
1072         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1073
1074         PM8001_INIT_DBG(pm8001_ha,
1075                 pm8001_printk("SPC soft reset Complete\n"));
1076         return 0;
1077 }
1078
1079 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1080 {
1081         u32 i;
1082         u32 regVal;
1083         PM8001_INIT_DBG(pm8001_ha,
1084                 pm8001_printk("chip reset start\n"));
1085
1086         /* do SPC chip reset. */
1087         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1088         regVal &= ~(SPC_REG_RESET_DEVICE);
1089         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1090
1091         /* delay 10 usec */
1092         udelay(10);
1093
1094         /* bring chip reset out of reset */
1095         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1096         regVal |= SPC_REG_RESET_DEVICE;
1097         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1098
1099         /* delay 10 usec */
1100         udelay(10);
1101
1102         /* wait for 20 msec until the firmware gets reloaded */
1103         i = 20;
1104         do {
1105                 mdelay(1);
1106         } while ((--i) != 0);
1107
1108         PM8001_INIT_DBG(pm8001_ha,
1109                 pm8001_printk("chip reset finished\n"));
1110 }
1111
1112 /**
1113  * pm8001_chip_iounmap - which maped when initialized.
1114  * @pm8001_ha: our hba card information
1115  */
1116 static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1117 {
1118         s8 bar, logical = 0;
1119         for (bar = 0; bar < 6; bar++) {
1120                 /*
1121                 ** logical BARs for SPC:
1122                 ** bar 0 and 1 - logical BAR0
1123                 ** bar 2 and 3 - logical BAR1
1124                 ** bar4 - logical BAR2
1125                 ** bar5 - logical BAR3
1126                 ** Skip the appropriate assignments:
1127                 */
1128                 if ((bar == 1) || (bar == 3))
1129                         continue;
1130                 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1131                         iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1132                         logical++;
1133                 }
1134         }
1135 }
1136
1137 /**
1138  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1139  * @pm8001_ha: our hba card information
1140  */
1141 static void
1142 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1143 {
1144         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1145         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1146 }
1147
1148  /**
1149   * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1150   * @pm8001_ha: our hba card information
1151   */
1152 static void
1153 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1154 {
1155         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1156 }
1157
1158 /**
1159  * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1160  * @pm8001_ha: our hba card information
1161  */
1162 static void
1163 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1164         u32 int_vec_idx)
1165 {
1166         u32 msi_index;
1167         u32 value;
1168         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1169         msi_index += MSIX_TABLE_BASE;
1170         pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1171         value = (1 << int_vec_idx);
1172         pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1173
1174 }
1175
1176 /**
1177  * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1178  * @pm8001_ha: our hba card information
1179  */
1180 static void
1181 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1182         u32 int_vec_idx)
1183 {
1184         u32 msi_index;
1185         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1186         msi_index += MSIX_TABLE_BASE;
1187         pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1188 }
1189
1190 /**
1191  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1192  * @pm8001_ha: our hba card information
1193  */
1194 static void
1195 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1196 {
1197 #ifdef PM8001_USE_MSIX
1198         pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1199         return;
1200 #endif
1201         pm8001_chip_intx_interrupt_enable(pm8001_ha);
1202
1203 }
1204
1205 /**
1206  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1207  * @pm8001_ha: our hba card information
1208  */
1209 static void
1210 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1211 {
1212 #ifdef PM8001_USE_MSIX
1213         pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1214         return;
1215 #endif
1216         pm8001_chip_intx_interrupt_disable(pm8001_ha);
1217
1218 }
1219
1220 /**
1221  * mpi_msg_free_get- get the free message buffer for transfer inbound queue.
1222  * @circularQ: the inbound queue  we want to transfer to HBA.
1223  * @messageSize: the message size of this transfer, normally it is 64 bytes
1224  * @messagePtr: the pointer to message.
1225  */
1226 static int mpi_msg_free_get(struct inbound_queue_table *circularQ,
1227                             u16 messageSize, void **messagePtr)
1228 {
1229         u32 offset, consumer_index;
1230         struct mpi_msg_hdr *msgHeader;
1231         u8 bcCount = 1; /* only support single buffer */
1232
1233         /* Checks is the requested message size can be allocated in this queue*/
1234         if (messageSize > 64) {
1235                 *messagePtr = NULL;
1236                 return -1;
1237         }
1238
1239         /* Stores the new consumer index */
1240         consumer_index = pm8001_read_32(circularQ->ci_virt);
1241         circularQ->consumer_index = cpu_to_le32(consumer_index);
1242         if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1243                 le32_to_cpu(circularQ->consumer_index)) {
1244                 *messagePtr = NULL;
1245                 return -1;
1246         }
1247         /* get memory IOMB buffer address */
1248         offset = circularQ->producer_idx * 64;
1249         /* increment to next bcCount element */
1250         circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1251                                 % PM8001_MPI_QUEUE;
1252         /* Adds that distance to the base of the region virtual address plus
1253         the message header size*/
1254         msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1255         *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1256         return 0;
1257 }
1258
1259 /**
1260  * mpi_build_cmd- build the message queue for transfer, update the PI to FW
1261  * to tell the fw to get this message from IOMB.
1262  * @pm8001_ha: our hba card information
1263  * @circularQ: the inbound queue we want to transfer to HBA.
1264  * @opCode: the operation code represents commands which LLDD and fw recognized.
1265  * @payload: the command payload of each operation command.
1266  */
1267 static int mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1268                          struct inbound_queue_table *circularQ,
1269                          u32 opCode, void *payload)
1270 {
1271         u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1272         u32 responseQueue = 0;
1273         void *pMessage;
1274
1275         if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) {
1276                 PM8001_IO_DBG(pm8001_ha,
1277                         pm8001_printk("No free mpi buffer\n"));
1278                 return -1;
1279         }
1280         BUG_ON(!payload);
1281         /*Copy to the payload*/
1282         memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr)));
1283
1284         /*Build the header*/
1285         Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1286                 | ((responseQueue & 0x3F) << 16)
1287                 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1288
1289         pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1290         /*Update the PI to the firmware*/
1291         pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1292                 circularQ->pi_offset, circularQ->producer_idx);
1293         PM8001_IO_DBG(pm8001_ha,
1294                 pm8001_printk("after PI= %d CI= %d\n", circularQ->producer_idx,
1295                 circularQ->consumer_index));
1296         return 0;
1297 }
1298
1299 static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1300                             struct outbound_queue_table *circularQ, u8 bc)
1301 {
1302         u32 producer_index;
1303         struct mpi_msg_hdr *msgHeader;
1304         struct mpi_msg_hdr *pOutBoundMsgHeader;
1305
1306         msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1307         pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1308                                 circularQ->consumer_idx * 64);
1309         if (pOutBoundMsgHeader != msgHeader) {
1310                 PM8001_FAIL_DBG(pm8001_ha,
1311                         pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1312                         circularQ->consumer_idx, msgHeader));
1313
1314                 /* Update the producer index from SPC */
1315                 producer_index = pm8001_read_32(circularQ->pi_virt);
1316                 circularQ->producer_index = cpu_to_le32(producer_index);
1317                 PM8001_FAIL_DBG(pm8001_ha,
1318                         pm8001_printk("consumer_idx = %d producer_index = %d"
1319                         "msgHeader = %p\n", circularQ->consumer_idx,
1320                         circularQ->producer_index, msgHeader));
1321                 return 0;
1322         }
1323         /* free the circular queue buffer elements associated with the message*/
1324         circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1325                                 % PM8001_MPI_QUEUE;
1326         /* update the CI of outbound queue */
1327         pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1328                 circularQ->consumer_idx);
1329         /* Update the producer index from SPC*/
1330         producer_index = pm8001_read_32(circularQ->pi_virt);
1331         circularQ->producer_index = cpu_to_le32(producer_index);
1332         PM8001_IO_DBG(pm8001_ha,
1333                 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1334                 circularQ->producer_index));
1335         return 0;
1336 }
1337
1338 /**
1339  * mpi_msg_consume- get the MPI message from  outbound queue message table.
1340  * @pm8001_ha: our hba card information
1341  * @circularQ: the outbound queue  table.
1342  * @messagePtr1: the message contents of this outbound message.
1343  * @pBC: the message size.
1344  */
1345 static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1346                            struct outbound_queue_table *circularQ,
1347                            void **messagePtr1, u8 *pBC)
1348 {
1349         struct mpi_msg_hdr      *msgHeader;
1350         __le32  msgHeader_tmp;
1351         u32 header_tmp;
1352         do {
1353                 /* If there are not-yet-delivered messages ... */
1354                 if (le32_to_cpu(circularQ->producer_index)
1355                         != circularQ->consumer_idx) {
1356                         /*Get the pointer to the circular queue buffer element*/
1357                         msgHeader = (struct mpi_msg_hdr *)
1358                                 (circularQ->base_virt +
1359                                 circularQ->consumer_idx * 64);
1360                         /* read header */
1361                         header_tmp = pm8001_read_32(msgHeader);
1362                         msgHeader_tmp = cpu_to_le32(header_tmp);
1363                         if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1364                                 if (OPC_OUB_SKIP_ENTRY !=
1365                                         (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1366                                         *messagePtr1 =
1367                                                 ((u8 *)msgHeader) +
1368                                                 sizeof(struct mpi_msg_hdr);
1369                                         *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1370                                                 >> 24) & 0x1f);
1371                                         PM8001_IO_DBG(pm8001_ha,
1372                                                 pm8001_printk(": CI=%d PI=%d "
1373                                                 "msgHeader=%x\n",
1374                                                 circularQ->consumer_idx,
1375                                                 circularQ->producer_index,
1376                                                 msgHeader_tmp));
1377                                         return MPI_IO_STATUS_SUCCESS;
1378                                 } else {
1379                                         circularQ->consumer_idx =
1380                                                 (circularQ->consumer_idx +
1381                                                 ((le32_to_cpu(msgHeader_tmp)
1382                                                  >> 24) & 0x1f))
1383                                                         % PM8001_MPI_QUEUE;
1384                                         msgHeader_tmp = 0;
1385                                         pm8001_write_32(msgHeader, 0, 0);
1386                                         /* update the CI of outbound queue */
1387                                         pm8001_cw32(pm8001_ha,
1388                                                 circularQ->ci_pci_bar,
1389                                                 circularQ->ci_offset,
1390                                                 circularQ->consumer_idx);
1391                                 }
1392                         } else {
1393                                 circularQ->consumer_idx =
1394                                         (circularQ->consumer_idx +
1395                                         ((le32_to_cpu(msgHeader_tmp) >> 24) &
1396                                         0x1f)) % PM8001_MPI_QUEUE;
1397                                 msgHeader_tmp = 0;
1398                                 pm8001_write_32(msgHeader, 0, 0);
1399                                 /* update the CI of outbound queue */
1400                                 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1401                                         circularQ->ci_offset,
1402                                         circularQ->consumer_idx);
1403                                 return MPI_IO_STATUS_FAIL;
1404                         }
1405                 } else {
1406                         u32 producer_index;
1407                         void *pi_virt = circularQ->pi_virt;
1408                         /* Update the producer index from SPC */
1409                         producer_index = pm8001_read_32(pi_virt);
1410                         circularQ->producer_index = cpu_to_le32(producer_index);
1411                 }
1412         } while (le32_to_cpu(circularQ->producer_index) !=
1413                 circularQ->consumer_idx);
1414         /* while we don't have any more not-yet-delivered message */
1415         /* report empty */
1416         return MPI_IO_STATUS_BUSY;
1417 }
1418
1419 static void pm8001_work_fn(struct work_struct *work)
1420 {
1421         struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1422         struct pm8001_device *pm8001_dev;
1423         struct domain_device *dev;
1424
1425         /*
1426          * So far, all users of this stash an associated structure here.
1427          * If we get here, and this pointer is null, then the action
1428          * was cancelled. This nullification happens when the device
1429          * goes away.
1430          */
1431         pm8001_dev = pw->data; /* Most stash device structure */
1432         if ((pm8001_dev == NULL)
1433          || ((pw->handler != IO_XFER_ERROR_BREAK)
1434           && (pm8001_dev->dev_type == NO_DEVICE))) {
1435                 kfree(pw);
1436                 return;
1437         }
1438
1439         switch (pw->handler) {
1440         case IO_XFER_ERROR_BREAK:
1441         {       /* This one stashes the sas_task instead */
1442                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1443                 u32 tag;
1444                 struct pm8001_ccb_info *ccb;
1445                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1446                 unsigned long flags, flags1;
1447                 struct task_status_struct *ts;
1448                 int i;
1449
1450                 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1451                         break; /* Task still on lu */
1452                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1453
1454                 spin_lock_irqsave(&t->task_state_lock, flags1);
1455                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1456                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1457                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1458                         break; /* Task got completed by another */
1459                 }
1460                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1461
1462                 /* Search for a possible ccb that matches the task */
1463                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1464                         ccb = &pm8001_ha->ccb_info[i];
1465                         tag = ccb->ccb_tag;
1466                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1467                                 break;
1468                 }
1469                 if (!ccb) {
1470                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1471                         break; /* Task got freed by another */
1472                 }
1473                 ts = &t->task_status;
1474                 ts->resp = SAS_TASK_COMPLETE;
1475                 /* Force the midlayer to retry */
1476                 ts->stat = SAS_QUEUE_FULL;
1477                 pm8001_dev = ccb->device;
1478                 if (pm8001_dev)
1479                         pm8001_dev->running_req--;
1480                 spin_lock_irqsave(&t->task_state_lock, flags1);
1481                 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1482                 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1483                 t->task_state_flags |= SAS_TASK_STATE_DONE;
1484                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1485                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1486                         PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p"
1487                                 " done with event 0x%x resp 0x%x stat 0x%x but"
1488                                 " aborted by upper layer!\n",
1489                                 t, pw->handler, ts->resp, ts->stat));
1490                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1491                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1492                 } else {
1493                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1494                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1495                         mb();/* in order to force CPU ordering */
1496                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1497                         t->task_done(t);
1498                 }
1499         }       break;
1500         case IO_XFER_OPEN_RETRY_TIMEOUT:
1501         {       /* This one stashes the sas_task instead */
1502                 struct sas_task *t = (struct sas_task *)pm8001_dev;
1503                 u32 tag;
1504                 struct pm8001_ccb_info *ccb;
1505                 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1506                 unsigned long flags, flags1;
1507                 int i, ret = 0;
1508
1509                 PM8001_IO_DBG(pm8001_ha,
1510                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1511
1512                 ret = pm8001_query_task(t);
1513
1514                 PM8001_IO_DBG(pm8001_ha,
1515                         switch (ret) {
1516                         case TMF_RESP_FUNC_SUCC:
1517                                 pm8001_printk("...Task on lu\n");
1518                                 break;
1519
1520                         case TMF_RESP_FUNC_COMPLETE:
1521                                 pm8001_printk("...Task NOT on lu\n");
1522                                 break;
1523
1524                         default:
1525                                 pm8001_printk("...query task failed!!!\n");
1526                                 break;
1527                         });
1528
1529                 spin_lock_irqsave(&pm8001_ha->lock, flags);
1530
1531                 spin_lock_irqsave(&t->task_state_lock, flags1);
1532
1533                 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1534                         spin_unlock_irqrestore(&t->task_state_lock, flags1);
1535                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1536                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1537                                 (void)pm8001_abort_task(t);
1538                         break; /* Task got completed by another */
1539                 }
1540
1541                 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1542
1543                 /* Search for a possible ccb that matches the task */
1544                 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1545                         ccb = &pm8001_ha->ccb_info[i];
1546                         tag = ccb->ccb_tag;
1547                         if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1548                                 break;
1549                 }
1550                 if (!ccb) {
1551                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1552                         if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1553                                 (void)pm8001_abort_task(t);
1554                         break; /* Task got freed by another */
1555                 }
1556
1557                 pm8001_dev = ccb->device;
1558                 dev = pm8001_dev->sas_device;
1559
1560                 switch (ret) {
1561                 case TMF_RESP_FUNC_SUCC: /* task on lu */
1562                         ccb->open_retry = 1; /* Snub completion */
1563                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1564                         ret = pm8001_abort_task(t);
1565                         ccb->open_retry = 0;
1566                         switch (ret) {
1567                         case TMF_RESP_FUNC_SUCC:
1568                         case TMF_RESP_FUNC_COMPLETE:
1569                                 break;
1570                         default: /* device misbehavior */
1571                                 ret = TMF_RESP_FUNC_FAILED;
1572                                 PM8001_IO_DBG(pm8001_ha,
1573                                         pm8001_printk("...Reset phy\n"));
1574                                 pm8001_I_T_nexus_reset(dev);
1575                                 break;
1576                         }
1577                         break;
1578
1579                 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1580                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1581                         /* Do we need to abort the task locally? */
1582                         break;
1583
1584                 default: /* device misbehavior */
1585                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1586                         ret = TMF_RESP_FUNC_FAILED;
1587                         PM8001_IO_DBG(pm8001_ha,
1588                                 pm8001_printk("...Reset phy\n"));
1589                         pm8001_I_T_nexus_reset(dev);
1590                 }
1591
1592                 if (ret == TMF_RESP_FUNC_FAILED)
1593                         t = NULL;
1594                 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1595                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n"));
1596         }       break;
1597         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1598                 dev = pm8001_dev->sas_device;
1599                 pm8001_I_T_nexus_reset(dev);
1600                 break;
1601         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1602                 dev = pm8001_dev->sas_device;
1603                 pm8001_I_T_nexus_reset(dev);
1604                 break;
1605         case IO_DS_IN_ERROR:
1606                 dev = pm8001_dev->sas_device;
1607                 pm8001_I_T_nexus_reset(dev);
1608                 break;
1609         case IO_DS_NON_OPERATIONAL:
1610                 dev = pm8001_dev->sas_device;
1611                 pm8001_I_T_nexus_reset(dev);
1612                 break;
1613         }
1614         kfree(pw);
1615 }
1616
1617 static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1618                                int handler)
1619 {
1620         struct pm8001_work *pw;
1621         int ret = 0;
1622
1623         pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1624         if (pw) {
1625                 pw->pm8001_ha = pm8001_ha;
1626                 pw->data = data;
1627                 pw->handler = handler;
1628                 INIT_WORK(&pw->work, pm8001_work_fn);
1629                 queue_work(pm8001_wq, &pw->work);
1630         } else
1631                 ret = -ENOMEM;
1632
1633         return ret;
1634 }
1635
1636 /**
1637  * mpi_ssp_completion- process the event that FW response to the SSP request.
1638  * @pm8001_ha: our hba card information
1639  * @piomb: the message contents of this outbound message.
1640  *
1641  * When FW has completed a ssp request for example a IO request, after it has
1642  * filled the SG data with the data, it will trigger this event represent
1643  * that he has finished the job,please check the coresponding buffer.
1644  * So we will tell the caller who maybe waiting the result to tell upper layer
1645  * that the task has been finished.
1646  */
1647 static void
1648 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1649 {
1650         struct sas_task *t;
1651         struct pm8001_ccb_info *ccb;
1652         unsigned long flags;
1653         u32 status;
1654         u32 param;
1655         u32 tag;
1656         struct ssp_completion_resp *psspPayload;
1657         struct task_status_struct *ts;
1658         struct ssp_response_iu *iu;
1659         struct pm8001_device *pm8001_dev;
1660         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1661         status = le32_to_cpu(psspPayload->status);
1662         tag = le32_to_cpu(psspPayload->tag);
1663         ccb = &pm8001_ha->ccb_info[tag];
1664         if ((status == IO_ABORTED) && ccb->open_retry) {
1665                 /* Being completed by another */
1666                 ccb->open_retry = 0;
1667                 return;
1668         }
1669         pm8001_dev = ccb->device;
1670         param = le32_to_cpu(psspPayload->param);
1671
1672         t = ccb->task;
1673
1674         if (status && status != IO_UNDERFLOW)
1675                 PM8001_FAIL_DBG(pm8001_ha,
1676                         pm8001_printk("sas IO status 0x%x\n", status));
1677         if (unlikely(!t || !t->lldd_task || !t->dev))
1678                 return;
1679         ts = &t->task_status;
1680         switch (status) {
1681         case IO_SUCCESS:
1682                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1683                         ",param = %d\n", param));
1684                 if (param == 0) {
1685                         ts->resp = SAS_TASK_COMPLETE;
1686                         ts->stat = SAM_STAT_GOOD;
1687                 } else {
1688                         ts->resp = SAS_TASK_COMPLETE;
1689                         ts->stat = SAS_PROTO_RESPONSE;
1690                         ts->residual = param;
1691                         iu = &psspPayload->ssp_resp_iu;
1692                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1693                 }
1694                 if (pm8001_dev)
1695                         pm8001_dev->running_req--;
1696                 break;
1697         case IO_ABORTED:
1698                 PM8001_IO_DBG(pm8001_ha,
1699                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
1700                 ts->resp = SAS_TASK_COMPLETE;
1701                 ts->stat = SAS_ABORTED_TASK;
1702                 break;
1703         case IO_UNDERFLOW:
1704                 /* SSP Completion with error */
1705                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1706                         ",param = %d\n", param));
1707                 ts->resp = SAS_TASK_COMPLETE;
1708                 ts->stat = SAS_DATA_UNDERRUN;
1709                 ts->residual = param;
1710                 if (pm8001_dev)
1711                         pm8001_dev->running_req--;
1712                 break;
1713         case IO_NO_DEVICE:
1714                 PM8001_IO_DBG(pm8001_ha,
1715                         pm8001_printk("IO_NO_DEVICE\n"));
1716                 ts->resp = SAS_TASK_UNDELIVERED;
1717                 ts->stat = SAS_PHY_DOWN;
1718                 break;
1719         case IO_XFER_ERROR_BREAK:
1720                 PM8001_IO_DBG(pm8001_ha,
1721                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1722                 ts->resp = SAS_TASK_COMPLETE;
1723                 ts->stat = SAS_OPEN_REJECT;
1724                 /* Force the midlayer to retry */
1725                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1726                 break;
1727         case IO_XFER_ERROR_PHY_NOT_READY:
1728                 PM8001_IO_DBG(pm8001_ha,
1729                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1730                 ts->resp = SAS_TASK_COMPLETE;
1731                 ts->stat = SAS_OPEN_REJECT;
1732                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1733                 break;
1734         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1735                 PM8001_IO_DBG(pm8001_ha,
1736                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1737                 ts->resp = SAS_TASK_COMPLETE;
1738                 ts->stat = SAS_OPEN_REJECT;
1739                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1740                 break;
1741         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1742                 PM8001_IO_DBG(pm8001_ha,
1743                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1744                 ts->resp = SAS_TASK_COMPLETE;
1745                 ts->stat = SAS_OPEN_REJECT;
1746                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1747                 break;
1748         case IO_OPEN_CNX_ERROR_BREAK:
1749                 PM8001_IO_DBG(pm8001_ha,
1750                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1751                 ts->resp = SAS_TASK_COMPLETE;
1752                 ts->stat = SAS_OPEN_REJECT;
1753                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1754                 break;
1755         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1756                 PM8001_IO_DBG(pm8001_ha,
1757                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1758                 ts->resp = SAS_TASK_COMPLETE;
1759                 ts->stat = SAS_OPEN_REJECT;
1760                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1761                 if (!t->uldd_task)
1762                         pm8001_handle_event(pm8001_ha,
1763                                 pm8001_dev,
1764                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1765                 break;
1766         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1767                 PM8001_IO_DBG(pm8001_ha,
1768                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1769                 ts->resp = SAS_TASK_COMPLETE;
1770                 ts->stat = SAS_OPEN_REJECT;
1771                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1772                 break;
1773         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1774                 PM8001_IO_DBG(pm8001_ha,
1775                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1776                         "NOT_SUPPORTED\n"));
1777                 ts->resp = SAS_TASK_COMPLETE;
1778                 ts->stat = SAS_OPEN_REJECT;
1779                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1780                 break;
1781         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1782                 PM8001_IO_DBG(pm8001_ha,
1783                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1784                 ts->resp = SAS_TASK_UNDELIVERED;
1785                 ts->stat = SAS_OPEN_REJECT;
1786                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1787                 break;
1788         case IO_XFER_ERROR_NAK_RECEIVED:
1789                 PM8001_IO_DBG(pm8001_ha,
1790                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1791                 ts->resp = SAS_TASK_COMPLETE;
1792                 ts->stat = SAS_OPEN_REJECT;
1793                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1794                 break;
1795         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1796                 PM8001_IO_DBG(pm8001_ha,
1797                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1798                 ts->resp = SAS_TASK_COMPLETE;
1799                 ts->stat = SAS_NAK_R_ERR;
1800                 break;
1801         case IO_XFER_ERROR_DMA:
1802                 PM8001_IO_DBG(pm8001_ha,
1803                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1804                 ts->resp = SAS_TASK_COMPLETE;
1805                 ts->stat = SAS_OPEN_REJECT;
1806                 break;
1807         case IO_XFER_OPEN_RETRY_TIMEOUT:
1808                 PM8001_IO_DBG(pm8001_ha,
1809                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1810                 ts->resp = SAS_TASK_COMPLETE;
1811                 ts->stat = SAS_OPEN_REJECT;
1812                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1813                 break;
1814         case IO_XFER_ERROR_OFFSET_MISMATCH:
1815                 PM8001_IO_DBG(pm8001_ha,
1816                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1817                 ts->resp = SAS_TASK_COMPLETE;
1818                 ts->stat = SAS_OPEN_REJECT;
1819                 break;
1820         case IO_PORT_IN_RESET:
1821                 PM8001_IO_DBG(pm8001_ha,
1822                         pm8001_printk("IO_PORT_IN_RESET\n"));
1823                 ts->resp = SAS_TASK_COMPLETE;
1824                 ts->stat = SAS_OPEN_REJECT;
1825                 break;
1826         case IO_DS_NON_OPERATIONAL:
1827                 PM8001_IO_DBG(pm8001_ha,
1828                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1829                 ts->resp = SAS_TASK_COMPLETE;
1830                 ts->stat = SAS_OPEN_REJECT;
1831                 if (!t->uldd_task)
1832                         pm8001_handle_event(pm8001_ha,
1833                                 pm8001_dev,
1834                                 IO_DS_NON_OPERATIONAL);
1835                 break;
1836         case IO_DS_IN_RECOVERY:
1837                 PM8001_IO_DBG(pm8001_ha,
1838                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
1839                 ts->resp = SAS_TASK_COMPLETE;
1840                 ts->stat = SAS_OPEN_REJECT;
1841                 break;
1842         case IO_TM_TAG_NOT_FOUND:
1843                 PM8001_IO_DBG(pm8001_ha,
1844                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1845                 ts->resp = SAS_TASK_COMPLETE;
1846                 ts->stat = SAS_OPEN_REJECT;
1847                 break;
1848         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1849                 PM8001_IO_DBG(pm8001_ha,
1850                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1851                 ts->resp = SAS_TASK_COMPLETE;
1852                 ts->stat = SAS_OPEN_REJECT;
1853                 break;
1854         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1855                 PM8001_IO_DBG(pm8001_ha,
1856                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1857                 ts->resp = SAS_TASK_COMPLETE;
1858                 ts->stat = SAS_OPEN_REJECT;
1859                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1860                 break;
1861         default:
1862                 PM8001_IO_DBG(pm8001_ha,
1863                         pm8001_printk("Unknown status 0x%x\n", status));
1864                 /* not allowed case. Therefore, return failed status */
1865                 ts->resp = SAS_TASK_COMPLETE;
1866                 ts->stat = SAS_OPEN_REJECT;
1867                 break;
1868         }
1869         PM8001_IO_DBG(pm8001_ha,
1870                 pm8001_printk("scsi_status = %x \n ",
1871                 psspPayload->ssp_resp_iu.status));
1872         spin_lock_irqsave(&t->task_state_lock, flags);
1873         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1874         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1875         t->task_state_flags |= SAS_TASK_STATE_DONE;
1876         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1877                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1878                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1879                         " io_status 0x%x resp 0x%x "
1880                         "stat 0x%x but aborted by upper layer!\n",
1881                         t, status, ts->resp, ts->stat));
1882                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1883         } else {
1884                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1885                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1886                 mb();/* in order to force CPU ordering */
1887                 t->task_done(t);
1888         }
1889 }
1890
1891 /*See the comments for mpi_ssp_completion */
1892 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1893 {
1894         struct sas_task *t;
1895         unsigned long flags;
1896         struct task_status_struct *ts;
1897         struct pm8001_ccb_info *ccb;
1898         struct pm8001_device *pm8001_dev;
1899         struct ssp_event_resp *psspPayload =
1900                 (struct ssp_event_resp *)(piomb + 4);
1901         u32 event = le32_to_cpu(psspPayload->event);
1902         u32 tag = le32_to_cpu(psspPayload->tag);
1903         u32 port_id = le32_to_cpu(psspPayload->port_id);
1904         u32 dev_id = le32_to_cpu(psspPayload->device_id);
1905
1906         ccb = &pm8001_ha->ccb_info[tag];
1907         t = ccb->task;
1908         pm8001_dev = ccb->device;
1909         if (event)
1910                 PM8001_FAIL_DBG(pm8001_ha,
1911                         pm8001_printk("sas IO status 0x%x\n", event));
1912         if (unlikely(!t || !t->lldd_task || !t->dev))
1913                 return;
1914         ts = &t->task_status;
1915         PM8001_IO_DBG(pm8001_ha,
1916                 pm8001_printk("port_id = %x,device_id = %x\n",
1917                 port_id, dev_id));
1918         switch (event) {
1919         case IO_OVERFLOW:
1920                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1921                 ts->resp = SAS_TASK_COMPLETE;
1922                 ts->stat = SAS_DATA_OVERRUN;
1923                 ts->residual = 0;
1924                 if (pm8001_dev)
1925                         pm8001_dev->running_req--;
1926                 break;
1927         case IO_XFER_ERROR_BREAK:
1928                 PM8001_IO_DBG(pm8001_ha,
1929                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1930                 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1931                 return;
1932         case IO_XFER_ERROR_PHY_NOT_READY:
1933                 PM8001_IO_DBG(pm8001_ha,
1934                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1935                 ts->resp = SAS_TASK_COMPLETE;
1936                 ts->stat = SAS_OPEN_REJECT;
1937                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1938                 break;
1939         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1940                 PM8001_IO_DBG(pm8001_ha,
1941                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1942                         "_SUPPORTED\n"));
1943                 ts->resp = SAS_TASK_COMPLETE;
1944                 ts->stat = SAS_OPEN_REJECT;
1945                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1946                 break;
1947         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1948                 PM8001_IO_DBG(pm8001_ha,
1949                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1950                 ts->resp = SAS_TASK_COMPLETE;
1951                 ts->stat = SAS_OPEN_REJECT;
1952                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1953                 break;
1954         case IO_OPEN_CNX_ERROR_BREAK:
1955                 PM8001_IO_DBG(pm8001_ha,
1956                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1957                 ts->resp = SAS_TASK_COMPLETE;
1958                 ts->stat = SAS_OPEN_REJECT;
1959                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1960                 break;
1961         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1962                 PM8001_IO_DBG(pm8001_ha,
1963                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1964                 ts->resp = SAS_TASK_COMPLETE;
1965                 ts->stat = SAS_OPEN_REJECT;
1966                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1967                 if (!t->uldd_task)
1968                         pm8001_handle_event(pm8001_ha,
1969                                 pm8001_dev,
1970                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1971                 break;
1972         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1973                 PM8001_IO_DBG(pm8001_ha,
1974                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1975                 ts->resp = SAS_TASK_COMPLETE;
1976                 ts->stat = SAS_OPEN_REJECT;
1977                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1978                 break;
1979         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1980                 PM8001_IO_DBG(pm8001_ha,
1981                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1982                         "NOT_SUPPORTED\n"));
1983                 ts->resp = SAS_TASK_COMPLETE;
1984                 ts->stat = SAS_OPEN_REJECT;
1985                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1986                 break;
1987         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1988                 PM8001_IO_DBG(pm8001_ha,
1989                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1990                 ts->resp = SAS_TASK_COMPLETE;
1991                 ts->stat = SAS_OPEN_REJECT;
1992                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1993                 break;
1994         case IO_XFER_ERROR_NAK_RECEIVED:
1995                 PM8001_IO_DBG(pm8001_ha,
1996                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1997                 ts->resp = SAS_TASK_COMPLETE;
1998                 ts->stat = SAS_OPEN_REJECT;
1999                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2000                 break;
2001         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2002                 PM8001_IO_DBG(pm8001_ha,
2003                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2004                 ts->resp = SAS_TASK_COMPLETE;
2005                 ts->stat = SAS_NAK_R_ERR;
2006                 break;
2007         case IO_XFER_OPEN_RETRY_TIMEOUT:
2008                 PM8001_IO_DBG(pm8001_ha,
2009                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2010                 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2011                 return;
2012         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2013                 PM8001_IO_DBG(pm8001_ha,
2014                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2015                 ts->resp = SAS_TASK_COMPLETE;
2016                 ts->stat = SAS_DATA_OVERRUN;
2017                 break;
2018         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2019                 PM8001_IO_DBG(pm8001_ha,
2020                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2021                 ts->resp = SAS_TASK_COMPLETE;
2022                 ts->stat = SAS_DATA_OVERRUN;
2023                 break;
2024         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2025                 PM8001_IO_DBG(pm8001_ha,
2026                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2027                 ts->resp = SAS_TASK_COMPLETE;
2028                 ts->stat = SAS_DATA_OVERRUN;
2029                 break;
2030         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2031                 PM8001_IO_DBG(pm8001_ha,
2032                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2033                 ts->resp = SAS_TASK_COMPLETE;
2034                 ts->stat = SAS_DATA_OVERRUN;
2035                 break;
2036         case IO_XFER_ERROR_OFFSET_MISMATCH:
2037                 PM8001_IO_DBG(pm8001_ha,
2038                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2039                 ts->resp = SAS_TASK_COMPLETE;
2040                 ts->stat = SAS_DATA_OVERRUN;
2041                 break;
2042         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2043                 PM8001_IO_DBG(pm8001_ha,
2044                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2045                 ts->resp = SAS_TASK_COMPLETE;
2046                 ts->stat = SAS_DATA_OVERRUN;
2047                 break;
2048         case IO_XFER_CMD_FRAME_ISSUED:
2049                 PM8001_IO_DBG(pm8001_ha,
2050                         pm8001_printk("  IO_XFER_CMD_FRAME_ISSUED\n"));
2051                 return;
2052         default:
2053                 PM8001_IO_DBG(pm8001_ha,
2054                         pm8001_printk("Unknown status 0x%x\n", event));
2055                 /* not allowed case. Therefore, return failed status */
2056                 ts->resp = SAS_TASK_COMPLETE;
2057                 ts->stat = SAS_DATA_OVERRUN;
2058                 break;
2059         }
2060         spin_lock_irqsave(&t->task_state_lock, flags);
2061         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2062         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2063         t->task_state_flags |= SAS_TASK_STATE_DONE;
2064         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2065                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2066                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2067                         " event 0x%x resp 0x%x "
2068                         "stat 0x%x but aborted by upper layer!\n",
2069                         t, event, ts->resp, ts->stat));
2070                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2071         } else {
2072                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2073                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2074                 mb();/* in order to force CPU ordering */
2075                 t->task_done(t);
2076         }
2077 }
2078
2079 /*See the comments for mpi_ssp_completion */
2080 static void
2081 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2082 {
2083         struct sas_task *t;
2084         struct pm8001_ccb_info *ccb;
2085         u32 param;
2086         u32 status;
2087         u32 tag;
2088         struct sata_completion_resp *psataPayload;
2089         struct task_status_struct *ts;
2090         struct ata_task_resp *resp ;
2091         u32 *sata_resp;
2092         struct pm8001_device *pm8001_dev;
2093         unsigned long flags;
2094
2095         psataPayload = (struct sata_completion_resp *)(piomb + 4);
2096         status = le32_to_cpu(psataPayload->status);
2097         tag = le32_to_cpu(psataPayload->tag);
2098
2099         ccb = &pm8001_ha->ccb_info[tag];
2100         param = le32_to_cpu(psataPayload->param);
2101         t = ccb->task;
2102         ts = &t->task_status;
2103         pm8001_dev = ccb->device;
2104         if (status)
2105                 PM8001_FAIL_DBG(pm8001_ha,
2106                         pm8001_printk("sata IO status 0x%x\n", status));
2107         if (unlikely(!t || !t->lldd_task || !t->dev))
2108                 return;
2109
2110         switch (status) {
2111         case IO_SUCCESS:
2112                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2113                 if (param == 0) {
2114                         ts->resp = SAS_TASK_COMPLETE;
2115                         ts->stat = SAM_STAT_GOOD;
2116                 } else {
2117                         u8 len;
2118                         ts->resp = SAS_TASK_COMPLETE;
2119                         ts->stat = SAS_PROTO_RESPONSE;
2120                         ts->residual = param;
2121                         PM8001_IO_DBG(pm8001_ha,
2122                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2123                                 param));
2124                         sata_resp = &psataPayload->sata_resp[0];
2125                         resp = (struct ata_task_resp *)ts->buf;
2126                         if (t->ata_task.dma_xfer == 0 &&
2127                         t->data_dir == PCI_DMA_FROMDEVICE) {
2128                                 len = sizeof(struct pio_setup_fis);
2129                                 PM8001_IO_DBG(pm8001_ha,
2130                                 pm8001_printk("PIO read len = %d\n", len));
2131                         } else if (t->ata_task.use_ncq) {
2132                                 len = sizeof(struct set_dev_bits_fis);
2133                                 PM8001_IO_DBG(pm8001_ha,
2134                                         pm8001_printk("FPDMA len = %d\n", len));
2135                         } else {
2136                                 len = sizeof(struct dev_to_host_fis);
2137                                 PM8001_IO_DBG(pm8001_ha,
2138                                 pm8001_printk("other len = %d\n", len));
2139                         }
2140                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2141                                 resp->frame_len = len;
2142                                 memcpy(&resp->ending_fis[0], sata_resp, len);
2143                                 ts->buf_valid_size = sizeof(*resp);
2144                         } else
2145                                 PM8001_IO_DBG(pm8001_ha,
2146                                         pm8001_printk("response to large\n"));
2147                 }
2148                 if (pm8001_dev)
2149                         pm8001_dev->running_req--;
2150                 break;
2151         case IO_ABORTED:
2152                 PM8001_IO_DBG(pm8001_ha,
2153                         pm8001_printk("IO_ABORTED IOMB Tag\n"));
2154                 ts->resp = SAS_TASK_COMPLETE;
2155                 ts->stat = SAS_ABORTED_TASK;
2156                 if (pm8001_dev)
2157                         pm8001_dev->running_req--;
2158                 break;
2159                 /* following cases are to do cases */
2160         case IO_UNDERFLOW:
2161                 /* SATA Completion with error */
2162                 PM8001_IO_DBG(pm8001_ha,
2163                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2164                 ts->resp = SAS_TASK_COMPLETE;
2165                 ts->stat = SAS_DATA_UNDERRUN;
2166                 ts->residual =  param;
2167                 if (pm8001_dev)
2168                         pm8001_dev->running_req--;
2169                 break;
2170         case IO_NO_DEVICE:
2171                 PM8001_IO_DBG(pm8001_ha,
2172                         pm8001_printk("IO_NO_DEVICE\n"));
2173                 ts->resp = SAS_TASK_UNDELIVERED;
2174                 ts->stat = SAS_PHY_DOWN;
2175                 break;
2176         case IO_XFER_ERROR_BREAK:
2177                 PM8001_IO_DBG(pm8001_ha,
2178                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2179                 ts->resp = SAS_TASK_COMPLETE;
2180                 ts->stat = SAS_INTERRUPTED;
2181                 break;
2182         case IO_XFER_ERROR_PHY_NOT_READY:
2183                 PM8001_IO_DBG(pm8001_ha,
2184                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2185                 ts->resp = SAS_TASK_COMPLETE;
2186                 ts->stat = SAS_OPEN_REJECT;
2187                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2188                 break;
2189         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2190                 PM8001_IO_DBG(pm8001_ha,
2191                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2192                         "_SUPPORTED\n"));
2193                 ts->resp = SAS_TASK_COMPLETE;
2194                 ts->stat = SAS_OPEN_REJECT;
2195                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2196                 break;
2197         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2198                 PM8001_IO_DBG(pm8001_ha,
2199                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2200                 ts->resp = SAS_TASK_COMPLETE;
2201                 ts->stat = SAS_OPEN_REJECT;
2202                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2203                 break;
2204         case IO_OPEN_CNX_ERROR_BREAK:
2205                 PM8001_IO_DBG(pm8001_ha,
2206                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2207                 ts->resp = SAS_TASK_COMPLETE;
2208                 ts->stat = SAS_OPEN_REJECT;
2209                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2210                 break;
2211         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2212                 PM8001_IO_DBG(pm8001_ha,
2213                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2214                 ts->resp = SAS_TASK_COMPLETE;
2215                 ts->stat = SAS_DEV_NO_RESPONSE;
2216                 if (!t->uldd_task) {
2217                         pm8001_handle_event(pm8001_ha,
2218                                 pm8001_dev,
2219                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2220                         ts->resp = SAS_TASK_UNDELIVERED;
2221                         ts->stat = SAS_QUEUE_FULL;
2222                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2223                         mb();/*in order to force CPU ordering*/
2224                         spin_unlock_irq(&pm8001_ha->lock);
2225                         t->task_done(t);
2226                         spin_lock_irq(&pm8001_ha->lock);
2227                         return;
2228                 }
2229                 break;
2230         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2231                 PM8001_IO_DBG(pm8001_ha,
2232                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2233                 ts->resp = SAS_TASK_UNDELIVERED;
2234                 ts->stat = SAS_OPEN_REJECT;
2235                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2236                 if (!t->uldd_task) {
2237                         pm8001_handle_event(pm8001_ha,
2238                                 pm8001_dev,
2239                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2240                         ts->resp = SAS_TASK_UNDELIVERED;
2241                         ts->stat = SAS_QUEUE_FULL;
2242                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2243                         mb();/*ditto*/
2244                         spin_unlock_irq(&pm8001_ha->lock);
2245                         t->task_done(t);
2246                         spin_lock_irq(&pm8001_ha->lock);
2247                         return;
2248                 }
2249                 break;
2250         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2251                 PM8001_IO_DBG(pm8001_ha,
2252                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2253                         "NOT_SUPPORTED\n"));
2254                 ts->resp = SAS_TASK_COMPLETE;
2255                 ts->stat = SAS_OPEN_REJECT;
2256                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2257                 break;
2258         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2259                 PM8001_IO_DBG(pm8001_ha,
2260                         pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2261                         "_BUSY\n"));
2262                 ts->resp = SAS_TASK_COMPLETE;
2263                 ts->stat = SAS_DEV_NO_RESPONSE;
2264                 if (!t->uldd_task) {
2265                         pm8001_handle_event(pm8001_ha,
2266                                 pm8001_dev,
2267                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2268                         ts->resp = SAS_TASK_UNDELIVERED;
2269                         ts->stat = SAS_QUEUE_FULL;
2270                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2271                         mb();/* ditto*/
2272                         spin_unlock_irq(&pm8001_ha->lock);
2273                         t->task_done(t);
2274                         spin_lock_irq(&pm8001_ha->lock);
2275                         return;
2276                 }
2277                 break;
2278         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2279                 PM8001_IO_DBG(pm8001_ha,
2280                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2281                 ts->resp = SAS_TASK_COMPLETE;
2282                 ts->stat = SAS_OPEN_REJECT;
2283                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2284                 break;
2285         case IO_XFER_ERROR_NAK_RECEIVED:
2286                 PM8001_IO_DBG(pm8001_ha,
2287                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2288                 ts->resp = SAS_TASK_COMPLETE;
2289                 ts->stat = SAS_NAK_R_ERR;
2290                 break;
2291         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2292                 PM8001_IO_DBG(pm8001_ha,
2293                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2294                 ts->resp = SAS_TASK_COMPLETE;
2295                 ts->stat = SAS_NAK_R_ERR;
2296                 break;
2297         case IO_XFER_ERROR_DMA:
2298                 PM8001_IO_DBG(pm8001_ha,
2299                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2300                 ts->resp = SAS_TASK_COMPLETE;
2301                 ts->stat = SAS_ABORTED_TASK;
2302                 break;
2303         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2304                 PM8001_IO_DBG(pm8001_ha,
2305                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2306                 ts->resp = SAS_TASK_UNDELIVERED;
2307                 ts->stat = SAS_DEV_NO_RESPONSE;
2308                 break;
2309         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2310                 PM8001_IO_DBG(pm8001_ha,
2311                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2312                 ts->resp = SAS_TASK_COMPLETE;
2313                 ts->stat = SAS_DATA_UNDERRUN;
2314                 break;
2315         case IO_XFER_OPEN_RETRY_TIMEOUT:
2316                 PM8001_IO_DBG(pm8001_ha,
2317                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2318                 ts->resp = SAS_TASK_COMPLETE;
2319                 ts->stat = SAS_OPEN_TO;
2320                 break;
2321         case IO_PORT_IN_RESET:
2322                 PM8001_IO_DBG(pm8001_ha,
2323                         pm8001_printk("IO_PORT_IN_RESET\n"));
2324                 ts->resp = SAS_TASK_COMPLETE;
2325                 ts->stat = SAS_DEV_NO_RESPONSE;
2326                 break;
2327         case IO_DS_NON_OPERATIONAL:
2328                 PM8001_IO_DBG(pm8001_ha,
2329                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2330                 ts->resp = SAS_TASK_COMPLETE;
2331                 ts->stat = SAS_DEV_NO_RESPONSE;
2332                 if (!t->uldd_task) {
2333                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2334                                     IO_DS_NON_OPERATIONAL);
2335                         ts->resp = SAS_TASK_UNDELIVERED;
2336                         ts->stat = SAS_QUEUE_FULL;
2337                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2338                         mb();/*ditto*/
2339                         spin_unlock_irq(&pm8001_ha->lock);
2340                         t->task_done(t);
2341                         spin_lock_irq(&pm8001_ha->lock);
2342                         return;
2343                 }
2344                 break;
2345         case IO_DS_IN_RECOVERY:
2346                 PM8001_IO_DBG(pm8001_ha,
2347                         pm8001_printk("  IO_DS_IN_RECOVERY\n"));
2348                 ts->resp = SAS_TASK_COMPLETE;
2349                 ts->stat = SAS_DEV_NO_RESPONSE;
2350                 break;
2351         case IO_DS_IN_ERROR:
2352                 PM8001_IO_DBG(pm8001_ha,
2353                         pm8001_printk("IO_DS_IN_ERROR\n"));
2354                 ts->resp = SAS_TASK_COMPLETE;
2355                 ts->stat = SAS_DEV_NO_RESPONSE;
2356                 if (!t->uldd_task) {
2357                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2358                                     IO_DS_IN_ERROR);
2359                         ts->resp = SAS_TASK_UNDELIVERED;
2360                         ts->stat = SAS_QUEUE_FULL;
2361                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2362                         mb();/*ditto*/
2363                         spin_unlock_irq(&pm8001_ha->lock);
2364                         t->task_done(t);
2365                         spin_lock_irq(&pm8001_ha->lock);
2366                         return;
2367                 }
2368                 break;
2369         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2370                 PM8001_IO_DBG(pm8001_ha,
2371                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2372                 ts->resp = SAS_TASK_COMPLETE;
2373                 ts->stat = SAS_OPEN_REJECT;
2374                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2375         default:
2376                 PM8001_IO_DBG(pm8001_ha,
2377                         pm8001_printk("Unknown status 0x%x\n", status));
2378                 /* not allowed case. Therefore, return failed status */
2379                 ts->resp = SAS_TASK_COMPLETE;
2380                 ts->stat = SAS_DEV_NO_RESPONSE;
2381                 break;
2382         }
2383         spin_lock_irqsave(&t->task_state_lock, flags);
2384         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2385         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2386         t->task_state_flags |= SAS_TASK_STATE_DONE;
2387         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2388                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2389                 PM8001_FAIL_DBG(pm8001_ha,
2390                         pm8001_printk("task 0x%p done with io_status 0x%x"
2391                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2392                         t, status, ts->resp, ts->stat));
2393                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2394         } else if (t->uldd_task) {
2395                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2396                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2397                 mb();/* ditto */
2398                 spin_unlock_irq(&pm8001_ha->lock);
2399                 t->task_done(t);
2400                 spin_lock_irq(&pm8001_ha->lock);
2401         } else if (!t->uldd_task) {
2402                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2403                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2404                 mb();/*ditto*/
2405                 spin_unlock_irq(&pm8001_ha->lock);
2406                 t->task_done(t);
2407                 spin_lock_irq(&pm8001_ha->lock);
2408         }
2409 }
2410
2411 /*See the comments for mpi_ssp_completion */
2412 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2413 {
2414         struct sas_task *t;
2415         struct task_status_struct *ts;
2416         struct pm8001_ccb_info *ccb;
2417         struct pm8001_device *pm8001_dev;
2418         struct sata_event_resp *psataPayload =
2419                 (struct sata_event_resp *)(piomb + 4);
2420         u32 event = le32_to_cpu(psataPayload->event);
2421         u32 tag = le32_to_cpu(psataPayload->tag);
2422         u32 port_id = le32_to_cpu(psataPayload->port_id);
2423         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2424         unsigned long flags;
2425
2426         ccb = &pm8001_ha->ccb_info[tag];
2427         t = ccb->task;
2428         pm8001_dev = ccb->device;
2429         if (event)
2430                 PM8001_FAIL_DBG(pm8001_ha,
2431                         pm8001_printk("sata IO status 0x%x\n", event));
2432         if (unlikely(!t || !t->lldd_task || !t->dev))
2433                 return;
2434         ts = &t->task_status;
2435         PM8001_IO_DBG(pm8001_ha,
2436                 pm8001_printk("port_id = %x,device_id = %x\n",
2437                 port_id, dev_id));
2438         switch (event) {
2439         case IO_OVERFLOW:
2440                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2441                 ts->resp = SAS_TASK_COMPLETE;
2442                 ts->stat = SAS_DATA_OVERRUN;
2443                 ts->residual = 0;
2444                 if (pm8001_dev)
2445                         pm8001_dev->running_req--;
2446                 break;
2447         case IO_XFER_ERROR_BREAK:
2448                 PM8001_IO_DBG(pm8001_ha,
2449                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2450                 ts->resp = SAS_TASK_COMPLETE;
2451                 ts->stat = SAS_INTERRUPTED;
2452                 break;
2453         case IO_XFER_ERROR_PHY_NOT_READY:
2454                 PM8001_IO_DBG(pm8001_ha,
2455                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2456                 ts->resp = SAS_TASK_COMPLETE;
2457                 ts->stat = SAS_OPEN_REJECT;
2458                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2459                 break;
2460         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2461                 PM8001_IO_DBG(pm8001_ha,
2462                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2463                         "_SUPPORTED\n"));
2464                 ts->resp = SAS_TASK_COMPLETE;
2465                 ts->stat = SAS_OPEN_REJECT;
2466                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2467                 break;
2468         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2469                 PM8001_IO_DBG(pm8001_ha,
2470                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2471                 ts->resp = SAS_TASK_COMPLETE;
2472                 ts->stat = SAS_OPEN_REJECT;
2473                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2474                 break;
2475         case IO_OPEN_CNX_ERROR_BREAK:
2476                 PM8001_IO_DBG(pm8001_ha,
2477                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2478                 ts->resp = SAS_TASK_COMPLETE;
2479                 ts->stat = SAS_OPEN_REJECT;
2480                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2481                 break;
2482         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2483                 PM8001_IO_DBG(pm8001_ha,
2484                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2485                 ts->resp = SAS_TASK_UNDELIVERED;
2486                 ts->stat = SAS_DEV_NO_RESPONSE;
2487                 if (!t->uldd_task) {
2488                         pm8001_handle_event(pm8001_ha,
2489                                 pm8001_dev,
2490                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2491                         ts->resp = SAS_TASK_COMPLETE;
2492                         ts->stat = SAS_QUEUE_FULL;
2493                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2494                         mb();/*ditto*/
2495                         spin_unlock_irq(&pm8001_ha->lock);
2496                         t->task_done(t);
2497                         spin_lock_irq(&pm8001_ha->lock);
2498                         return;
2499                 }
2500                 break;
2501         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2502                 PM8001_IO_DBG(pm8001_ha,
2503                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2504                 ts->resp = SAS_TASK_UNDELIVERED;
2505                 ts->stat = SAS_OPEN_REJECT;
2506                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2507                 break;
2508         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2509                 PM8001_IO_DBG(pm8001_ha,
2510                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2511                         "NOT_SUPPORTED\n"));
2512                 ts->resp = SAS_TASK_COMPLETE;
2513                 ts->stat = SAS_OPEN_REJECT;
2514                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2515                 break;
2516         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2517                 PM8001_IO_DBG(pm8001_ha,
2518                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2519                 ts->resp = SAS_TASK_COMPLETE;
2520                 ts->stat = SAS_OPEN_REJECT;
2521                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2522                 break;
2523         case IO_XFER_ERROR_NAK_RECEIVED:
2524                 PM8001_IO_DBG(pm8001_ha,
2525                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2526                 ts->resp = SAS_TASK_COMPLETE;
2527                 ts->stat = SAS_NAK_R_ERR;
2528                 break;
2529         case IO_XFER_ERROR_PEER_ABORTED:
2530                 PM8001_IO_DBG(pm8001_ha,
2531                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2532                 ts->resp = SAS_TASK_COMPLETE;
2533                 ts->stat = SAS_NAK_R_ERR;
2534                 break;
2535         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2536                 PM8001_IO_DBG(pm8001_ha,
2537                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2538                 ts->resp = SAS_TASK_COMPLETE;
2539                 ts->stat = SAS_DATA_UNDERRUN;
2540                 break;
2541         case IO_XFER_OPEN_RETRY_TIMEOUT:
2542                 PM8001_IO_DBG(pm8001_ha,
2543                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2544                 ts->resp = SAS_TASK_COMPLETE;
2545                 ts->stat = SAS_OPEN_TO;
2546                 break;
2547         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2548                 PM8001_IO_DBG(pm8001_ha,
2549                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2550                 ts->resp = SAS_TASK_COMPLETE;
2551                 ts->stat = SAS_OPEN_TO;
2552                 break;
2553         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2554                 PM8001_IO_DBG(pm8001_ha,
2555                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2556                 ts->resp = SAS_TASK_COMPLETE;
2557                 ts->stat = SAS_OPEN_TO;
2558                 break;
2559         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2560                 PM8001_IO_DBG(pm8001_ha,
2561                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2562                 ts->resp = SAS_TASK_COMPLETE;
2563                 ts->stat = SAS_OPEN_TO;
2564                 break;
2565         case IO_XFER_ERROR_OFFSET_MISMATCH:
2566                 PM8001_IO_DBG(pm8001_ha,
2567                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2568                 ts->resp = SAS_TASK_COMPLETE;
2569                 ts->stat = SAS_OPEN_TO;
2570                 break;
2571         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2572                 PM8001_IO_DBG(pm8001_ha,
2573                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2574                 ts->resp = SAS_TASK_COMPLETE;
2575                 ts->stat = SAS_OPEN_TO;
2576                 break;
2577         case IO_XFER_CMD_FRAME_ISSUED:
2578                 PM8001_IO_DBG(pm8001_ha,
2579                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2580                 break;
2581         case IO_XFER_PIO_SETUP_ERROR:
2582                 PM8001_IO_DBG(pm8001_ha,
2583                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2584                 ts->resp = SAS_TASK_COMPLETE;
2585                 ts->stat = SAS_OPEN_TO;
2586                 break;
2587         default:
2588                 PM8001_IO_DBG(pm8001_ha,
2589                         pm8001_printk("Unknown status 0x%x\n", event));
2590                 /* not allowed case. Therefore, return failed status */
2591                 ts->resp = SAS_TASK_COMPLETE;
2592                 ts->stat = SAS_OPEN_TO;
2593                 break;
2594         }
2595         spin_lock_irqsave(&t->task_state_lock, flags);
2596         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2597         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2598         t->task_state_flags |= SAS_TASK_STATE_DONE;
2599         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2600                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2601                 PM8001_FAIL_DBG(pm8001_ha,
2602                         pm8001_printk("task 0x%p done with io_status 0x%x"
2603                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2604                         t, event, ts->resp, ts->stat));
2605                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2606         } else if (t->uldd_task) {
2607                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2608                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2609                 mb();/* ditto */
2610                 spin_unlock_irq(&pm8001_ha->lock);
2611                 t->task_done(t);
2612                 spin_lock_irq(&pm8001_ha->lock);
2613         } else if (!t->uldd_task) {
2614                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2615                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2616                 mb();/*ditto*/
2617                 spin_unlock_irq(&pm8001_ha->lock);
2618                 t->task_done(t);
2619                 spin_lock_irq(&pm8001_ha->lock);
2620         }
2621 }
2622
2623 /*See the comments for mpi_ssp_completion */
2624 static void
2625 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2626 {
2627         u32 param;
2628         struct sas_task *t;
2629         struct pm8001_ccb_info *ccb;
2630         unsigned long flags;
2631         u32 status;
2632         u32 tag;
2633         struct smp_completion_resp *psmpPayload;
2634         struct task_status_struct *ts;
2635         struct pm8001_device *pm8001_dev;
2636
2637         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2638         status = le32_to_cpu(psmpPayload->status);
2639         tag = le32_to_cpu(psmpPayload->tag);
2640
2641         ccb = &pm8001_ha->ccb_info[tag];
2642         param = le32_to_cpu(psmpPayload->param);
2643         t = ccb->task;
2644         ts = &t->task_status;
2645         pm8001_dev = ccb->device;
2646         if (status)
2647                 PM8001_FAIL_DBG(pm8001_ha,
2648                         pm8001_printk("smp IO status 0x%x\n", status));
2649         if (unlikely(!t || !t->lldd_task || !t->dev))
2650                 return;
2651
2652         switch (status) {
2653         case IO_SUCCESS:
2654                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2655                 ts->resp = SAS_TASK_COMPLETE;
2656                 ts->stat = SAM_STAT_GOOD;
2657         if (pm8001_dev)
2658                         pm8001_dev->running_req--;
2659                 break;
2660         case IO_ABORTED:
2661                 PM8001_IO_DBG(pm8001_ha,
2662                         pm8001_printk("IO_ABORTED IOMB\n"));
2663                 ts->resp = SAS_TASK_COMPLETE;
2664                 ts->stat = SAS_ABORTED_TASK;
2665                 if (pm8001_dev)
2666                         pm8001_dev->running_req--;
2667                 break;
2668         case IO_OVERFLOW:
2669                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2670                 ts->resp = SAS_TASK_COMPLETE;
2671                 ts->stat = SAS_DATA_OVERRUN;
2672                 ts->residual = 0;
2673                 if (pm8001_dev)
2674                         pm8001_dev->running_req--;
2675                 break;
2676         case IO_NO_DEVICE:
2677                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2678                 ts->resp = SAS_TASK_COMPLETE;
2679                 ts->stat = SAS_PHY_DOWN;
2680                 break;
2681         case IO_ERROR_HW_TIMEOUT:
2682                 PM8001_IO_DBG(pm8001_ha,
2683                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2684                 ts->resp = SAS_TASK_COMPLETE;
2685                 ts->stat = SAM_STAT_BUSY;
2686                 break;
2687         case IO_XFER_ERROR_BREAK:
2688                 PM8001_IO_DBG(pm8001_ha,
2689                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2690                 ts->resp = SAS_TASK_COMPLETE;
2691                 ts->stat = SAM_STAT_BUSY;
2692                 break;
2693         case IO_XFER_ERROR_PHY_NOT_READY:
2694                 PM8001_IO_DBG(pm8001_ha,
2695                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2696                 ts->resp = SAS_TASK_COMPLETE;
2697                 ts->stat = SAM_STAT_BUSY;
2698                 break;
2699         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2700                 PM8001_IO_DBG(pm8001_ha,
2701                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2702                 ts->resp = SAS_TASK_COMPLETE;
2703                 ts->stat = SAS_OPEN_REJECT;
2704                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2705                 break;
2706         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2707                 PM8001_IO_DBG(pm8001_ha,
2708                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2709                 ts->resp = SAS_TASK_COMPLETE;
2710                 ts->stat = SAS_OPEN_REJECT;
2711                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2712                 break;
2713         case IO_OPEN_CNX_ERROR_BREAK:
2714                 PM8001_IO_DBG(pm8001_ha,
2715                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2716                 ts->resp = SAS_TASK_COMPLETE;
2717                 ts->stat = SAS_OPEN_REJECT;
2718                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2719                 break;
2720         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2721                 PM8001_IO_DBG(pm8001_ha,
2722                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2723                 ts->resp = SAS_TASK_COMPLETE;
2724                 ts->stat = SAS_OPEN_REJECT;
2725                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2726                 pm8001_handle_event(pm8001_ha,
2727                                 pm8001_dev,
2728                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2729                 break;
2730         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2731                 PM8001_IO_DBG(pm8001_ha,
2732                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2733                 ts->resp = SAS_TASK_COMPLETE;
2734                 ts->stat = SAS_OPEN_REJECT;
2735                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2736                 break;
2737         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2738                 PM8001_IO_DBG(pm8001_ha,
2739                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2740                         "NOT_SUPPORTED\n"));
2741                 ts->resp = SAS_TASK_COMPLETE;
2742                 ts->stat = SAS_OPEN_REJECT;
2743                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2744                 break;
2745         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2746                 PM8001_IO_DBG(pm8001_ha,
2747                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2748                 ts->resp = SAS_TASK_COMPLETE;
2749                 ts->stat = SAS_OPEN_REJECT;
2750                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2751                 break;
2752         case IO_XFER_ERROR_RX_FRAME:
2753                 PM8001_IO_DBG(pm8001_ha,
2754                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2755                 ts->resp = SAS_TASK_COMPLETE;
2756                 ts->stat = SAS_DEV_NO_RESPONSE;
2757                 break;
2758         case IO_XFER_OPEN_RETRY_TIMEOUT:
2759                 PM8001_IO_DBG(pm8001_ha,
2760                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2761                 ts->resp = SAS_TASK_COMPLETE;
2762                 ts->stat = SAS_OPEN_REJECT;
2763                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2764                 break;
2765         case IO_ERROR_INTERNAL_SMP_RESOURCE:
2766                 PM8001_IO_DBG(pm8001_ha,
2767                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2768                 ts->resp = SAS_TASK_COMPLETE;
2769                 ts->stat = SAS_QUEUE_FULL;
2770                 break;
2771         case IO_PORT_IN_RESET:
2772                 PM8001_IO_DBG(pm8001_ha,
2773                         pm8001_printk("IO_PORT_IN_RESET\n"));
2774                 ts->resp = SAS_TASK_COMPLETE;
2775                 ts->stat = SAS_OPEN_REJECT;
2776                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2777                 break;
2778         case IO_DS_NON_OPERATIONAL:
2779                 PM8001_IO_DBG(pm8001_ha,
2780                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2781                 ts->resp = SAS_TASK_COMPLETE;
2782                 ts->stat = SAS_DEV_NO_RESPONSE;
2783                 break;
2784         case IO_DS_IN_RECOVERY:
2785                 PM8001_IO_DBG(pm8001_ha,
2786                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2787                 ts->resp = SAS_TASK_COMPLETE;
2788                 ts->stat = SAS_OPEN_REJECT;
2789                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2790                 break;
2791         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2792                 PM8001_IO_DBG(pm8001_ha,
2793                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2794                 ts->resp = SAS_TASK_COMPLETE;
2795                 ts->stat = SAS_OPEN_REJECT;
2796                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2797                 break;
2798         default:
2799                 PM8001_IO_DBG(pm8001_ha,
2800                         pm8001_printk("Unknown status 0x%x\n", status));
2801                 ts->resp = SAS_TASK_COMPLETE;
2802                 ts->stat = SAS_DEV_NO_RESPONSE;
2803                 /* not allowed case. Therefore, return failed status */
2804                 break;
2805         }
2806         spin_lock_irqsave(&t->task_state_lock, flags);
2807         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2808         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2809         t->task_state_flags |= SAS_TASK_STATE_DONE;
2810         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2811                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2812                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2813                         " io_status 0x%x resp 0x%x "
2814                         "stat 0x%x but aborted by upper layer!\n",
2815                         t, status, ts->resp, ts->stat));
2816                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2817         } else {
2818                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2819                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2820                 mb();/* in order to force CPU ordering */
2821                 t->task_done(t);
2822         }
2823 }
2824
2825 static void
2826 mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2827 {
2828         struct set_dev_state_resp *pPayload =
2829                 (struct set_dev_state_resp *)(piomb + 4);
2830         u32 tag = le32_to_cpu(pPayload->tag);
2831         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2832         struct pm8001_device *pm8001_dev = ccb->device;
2833         u32 status = le32_to_cpu(pPayload->status);
2834         u32 device_id = le32_to_cpu(pPayload->device_id);
2835         u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
2836         u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
2837         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
2838                 "from 0x%x to 0x%x status = 0x%x!\n",
2839                 device_id, pds, nds, status));
2840         complete(pm8001_dev->setds_completion);
2841         ccb->task = NULL;
2842         ccb->ccb_tag = 0xFFFFFFFF;
2843         pm8001_ccb_free(pm8001_ha, tag);
2844 }
2845
2846 static void
2847 mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2848 {
2849         struct get_nvm_data_resp *pPayload =
2850                 (struct get_nvm_data_resp *)(piomb + 4);
2851         u32 tag = le32_to_cpu(pPayload->tag);
2852         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2853         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2854         complete(pm8001_ha->nvmd_completion);
2855         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
2856         if ((dlen_status & NVMD_STAT) != 0) {
2857                 PM8001_FAIL_DBG(pm8001_ha,
2858                         pm8001_printk("Set nvm data error!\n"));
2859                 return;
2860         }
2861         ccb->task = NULL;
2862         ccb->ccb_tag = 0xFFFFFFFF;
2863         pm8001_ccb_free(pm8001_ha, tag);
2864 }
2865
2866 static void
2867 mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2868 {
2869         struct fw_control_ex    *fw_control_context;
2870         struct get_nvm_data_resp *pPayload =
2871                 (struct get_nvm_data_resp *)(piomb + 4);
2872         u32 tag = le32_to_cpu(pPayload->tag);
2873         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2874         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2875         u32 ir_tds_bn_dps_das_nvm =
2876                 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
2877         void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
2878         fw_control_context = ccb->fw_control_context;
2879
2880         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
2881         if ((dlen_status & NVMD_STAT) != 0) {
2882                 PM8001_FAIL_DBG(pm8001_ha,
2883                         pm8001_printk("Get nvm data error!\n"));
2884                 complete(pm8001_ha->nvmd_completion);
2885                 return;
2886         }
2887
2888         if (ir_tds_bn_dps_das_nvm & IPMode) {
2889                 /* indirect mode - IR bit set */
2890                 PM8001_MSG_DBG(pm8001_ha,
2891                         pm8001_printk("Get NVMD success, IR=1\n"));
2892                 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
2893                         if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
2894                                 memcpy(pm8001_ha->sas_addr,
2895                                       ((u8 *)virt_addr + 4),
2896                                        SAS_ADDR_SIZE);
2897                                 PM8001_MSG_DBG(pm8001_ha,
2898                                         pm8001_printk("Get SAS address"
2899                                         " from VPD successfully!\n"));
2900                         }
2901                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
2902                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
2903                         ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
2904                                 ;
2905                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
2906                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
2907                         ;
2908                 } else {
2909                         /* Should not be happened*/
2910                         PM8001_MSG_DBG(pm8001_ha,
2911                                 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
2912                                 ir_tds_bn_dps_das_nvm));
2913                 }
2914         } else /* direct mode */{
2915                 PM8001_MSG_DBG(pm8001_ha,
2916                         pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
2917                         (dlen_status & NVMD_LEN) >> 24));
2918         }
2919         memcpy(fw_control_context->usrAddr,
2920                 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
2921                 fw_control_context->len);
2922         complete(pm8001_ha->nvmd_completion);
2923         ccb->task = NULL;
2924         ccb->ccb_tag = 0xFFFFFFFF;
2925         pm8001_ccb_free(pm8001_ha, tag);
2926 }
2927
2928 static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
2929 {
2930         struct local_phy_ctl_resp *pPayload =
2931                 (struct local_phy_ctl_resp *)(piomb + 4);
2932         u32 status = le32_to_cpu(pPayload->status);
2933         u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
2934         u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
2935         if (status != 0) {
2936                 PM8001_MSG_DBG(pm8001_ha,
2937                         pm8001_printk("%x phy execute %x phy op failed!\n",
2938                         phy_id, phy_op));
2939         } else
2940                 PM8001_MSG_DBG(pm8001_ha,
2941                         pm8001_printk("%x phy execute %x phy op success!\n",
2942                         phy_id, phy_op));
2943         return 0;
2944 }
2945
2946 /**
2947  * pm8001_bytes_dmaed - one of the interface function communication with libsas
2948  * @pm8001_ha: our hba card information
2949  * @i: which phy that received the event.
2950  *
2951  * when HBA driver received the identify done event or initiate FIS received
2952  * event(for SATA), it will invoke this function to notify the sas layer that
2953  * the sas toplogy has formed, please discover the the whole sas domain,
2954  * while receive a broadcast(change) primitive just tell the sas
2955  * layer to discover the changed domain rather than the whole domain.
2956  */
2957 static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
2958 {
2959         struct pm8001_phy *phy = &pm8001_ha->phy[i];
2960         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2961         struct sas_ha_struct *sas_ha;
2962         if (!phy->phy_attached)
2963                 return;
2964
2965         sas_ha = pm8001_ha->sas;
2966         if (sas_phy->phy) {
2967                 struct sas_phy *sphy = sas_phy->phy;
2968                 sphy->negotiated_linkrate = sas_phy->linkrate;
2969                 sphy->minimum_linkrate = phy->minimum_linkrate;
2970                 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2971                 sphy->maximum_linkrate = phy->maximum_linkrate;
2972                 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
2973         }
2974
2975         if (phy->phy_type & PORT_TYPE_SAS) {
2976                 struct sas_identify_frame *id;
2977                 id = (struct sas_identify_frame *)phy->frame_rcvd;
2978                 id->dev_type = phy->identify.device_type;
2979                 id->initiator_bits = SAS_PROTOCOL_ALL;
2980                 id->target_bits = phy->identify.target_port_protocols;
2981         } else if (phy->phy_type & PORT_TYPE_SATA) {
2982                 /*Nothing*/
2983         }
2984         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
2985
2986         sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
2987         pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
2988 }
2989
2990 /* Get the link rate speed  */
2991 static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
2992 {
2993         struct sas_phy *sas_phy = phy->sas_phy.phy;
2994
2995         switch (link_rate) {
2996         case PHY_SPEED_60:
2997                 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
2998                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
2999                 break;
3000         case PHY_SPEED_30:
3001                 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3002                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3003                 break;
3004         case PHY_SPEED_15:
3005                 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3006                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3007                 break;
3008         }
3009         sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3010         sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3011         sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3012         sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3013         sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3014 }
3015
3016 /**
3017  * asd_get_attached_sas_addr -- extract/generate attached SAS address
3018  * @phy: pointer to asd_phy
3019  * @sas_addr: pointer to buffer where the SAS address is to be written
3020  *
3021  * This function extracts the SAS address from an IDENTIFY frame
3022  * received.  If OOB is SATA, then a SAS address is generated from the
3023  * HA tables.
3024  *
3025  * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3026  * buffer.
3027  */
3028 static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3029         u8 *sas_addr)
3030 {
3031         if (phy->sas_phy.frame_rcvd[0] == 0x34
3032                 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3033                 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3034                 /* FIS device-to-host */
3035                 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3036                 addr += phy->sas_phy.id;
3037                 *(__be64 *)sas_addr = cpu_to_be64(addr);
3038         } else {
3039                 struct sas_identify_frame *idframe =
3040                         (void *) phy->sas_phy.frame_rcvd;
3041                 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3042         }
3043 }
3044
3045 /**
3046  * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3047  * @pm8001_ha: our hba card information
3048  * @Qnum: the outbound queue message number.
3049  * @SEA: source of event to ack
3050  * @port_id: port id.
3051  * @phyId: phy id.
3052  * @param0: parameter 0.
3053  * @param1: parameter 1.
3054  */
3055 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3056         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3057 {
3058         struct hw_event_ack_req  payload;
3059         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3060
3061         struct inbound_queue_table *circularQ;
3062
3063         memset((u8 *)&payload, 0, sizeof(payload));
3064         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3065         payload.tag = cpu_to_le32(1);
3066         payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3067                 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3068         payload.param0 = cpu_to_le32(param0);
3069         payload.param1 = cpu_to_le32(param1);
3070         mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
3071 }
3072
3073 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3074         u32 phyId, u32 phy_op);
3075
3076 /**
3077  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3078  * @pm8001_ha: our hba card information
3079  * @piomb: IO message buffer
3080  */
3081 static void
3082 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3083 {
3084         struct hw_event_resp *pPayload =
3085                 (struct hw_event_resp *)(piomb + 4);
3086         u32 lr_evt_status_phyid_portid =
3087                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3088         u8 link_rate =
3089                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3090         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3091         u8 phy_id =
3092                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3093         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3094         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3095         struct pm8001_port *port = &pm8001_ha->port[port_id];
3096         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3097         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3098         unsigned long flags;
3099         u8 deviceType = pPayload->sas_identify.dev_type;
3100         port->port_state =  portstate;
3101         PM8001_MSG_DBG(pm8001_ha,
3102                 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3103                 port_id, phy_id));
3104
3105         switch (deviceType) {
3106         case SAS_PHY_UNUSED:
3107                 PM8001_MSG_DBG(pm8001_ha,
3108                         pm8001_printk("device type no device.\n"));
3109                 break;
3110         case SAS_END_DEVICE:
3111                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3112                 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3113                         PHY_NOTIFY_ENABLE_SPINUP);
3114                 port->port_attached = 1;
3115                 get_lrate_mode(phy, link_rate);
3116                 break;
3117         case SAS_EDGE_EXPANDER_DEVICE:
3118                 PM8001_MSG_DBG(pm8001_ha,
3119                         pm8001_printk("expander device.\n"));
3120                 port->port_attached = 1;
3121                 get_lrate_mode(phy, link_rate);
3122                 break;
3123         case SAS_FANOUT_EXPANDER_DEVICE:
3124                 PM8001_MSG_DBG(pm8001_ha,
3125                         pm8001_printk("fanout expander device.\n"));
3126                 port->port_attached = 1;
3127                 get_lrate_mode(phy, link_rate);
3128                 break;
3129         default:
3130                 PM8001_MSG_DBG(pm8001_ha,
3131                         pm8001_printk("unknown device type(%x)\n", deviceType));
3132                 break;
3133         }
3134         phy->phy_type |= PORT_TYPE_SAS;
3135         phy->identify.device_type = deviceType;
3136         phy->phy_attached = 1;
3137         if (phy->identify.device_type == SAS_END_DEVICE)
3138                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3139         else if (phy->identify.device_type != SAS_PHY_UNUSED)
3140                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3141         phy->sas_phy.oob_mode = SAS_OOB_MODE;
3142         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3143         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3144         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3145                 sizeof(struct sas_identify_frame)-4);
3146         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3147         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3148         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3149         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3150                 mdelay(200);/*delay a moment to wait disk to spinup*/
3151         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3152 }
3153
3154 /**
3155  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3156  * @pm8001_ha: our hba card information
3157  * @piomb: IO message buffer
3158  */
3159 static void
3160 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3161 {
3162         struct hw_event_resp *pPayload =
3163                 (struct hw_event_resp *)(piomb + 4);
3164         u32 lr_evt_status_phyid_portid =
3165                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3166         u8 link_rate =
3167                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3168         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3169         u8 phy_id =
3170                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3171         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3172         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3173         struct pm8001_port *port = &pm8001_ha->port[port_id];
3174         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3175         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3176         unsigned long flags;
3177         PM8001_MSG_DBG(pm8001_ha,
3178                 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3179                 " phy id = %d\n", port_id, phy_id));
3180         port->port_state =  portstate;
3181         port->port_attached = 1;
3182         get_lrate_mode(phy, link_rate);
3183         phy->phy_type |= PORT_TYPE_SATA;
3184         phy->phy_attached = 1;
3185         phy->sas_phy.oob_mode = SATA_OOB_MODE;
3186         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3187         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3188         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3189                 sizeof(struct dev_to_host_fis));
3190         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3191         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3192         phy->identify.device_type = SATA_DEV;
3193         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3194         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3195         pm8001_bytes_dmaed(pm8001_ha, phy_id);
3196 }
3197
3198 /**
3199  * hw_event_phy_down -we should notify the libsas the phy is down.
3200  * @pm8001_ha: our hba card information
3201  * @piomb: IO message buffer
3202  */
3203 static void
3204 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3205 {
3206         struct hw_event_resp *pPayload =
3207                 (struct hw_event_resp *)(piomb + 4);
3208         u32 lr_evt_status_phyid_portid =
3209                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3210         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3211         u8 phy_id =
3212                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3213         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3214         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3215         struct pm8001_port *port = &pm8001_ha->port[port_id];
3216         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3217         port->port_state =  portstate;
3218         phy->phy_type = 0;
3219         phy->identify.device_type = 0;
3220         phy->phy_attached = 0;
3221         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3222         switch (portstate) {
3223         case PORT_VALID:
3224                 break;
3225         case PORT_INVALID:
3226                 PM8001_MSG_DBG(pm8001_ha,
3227                         pm8001_printk(" PortInvalid portID %d\n", port_id));
3228                 PM8001_MSG_DBG(pm8001_ha,
3229                         pm8001_printk(" Last phy Down and port invalid\n"));
3230                 port->port_attached = 0;
3231                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3232                         port_id, phy_id, 0, 0);
3233                 break;
3234         case PORT_IN_RESET:
3235                 PM8001_MSG_DBG(pm8001_ha,
3236                         pm8001_printk(" Port In Reset portID %d\n", port_id));
3237                 break;
3238         case PORT_NOT_ESTABLISHED:
3239                 PM8001_MSG_DBG(pm8001_ha,
3240                         pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3241                 port->port_attached = 0;
3242                 break;
3243         case PORT_LOSTCOMM:
3244                 PM8001_MSG_DBG(pm8001_ha,
3245                         pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3246                 PM8001_MSG_DBG(pm8001_ha,
3247                         pm8001_printk(" Last phy Down and port invalid\n"));
3248                 port->port_attached = 0;
3249                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3250                         port_id, phy_id, 0, 0);
3251                 break;
3252         default:
3253                 port->port_attached = 0;
3254                 PM8001_MSG_DBG(pm8001_ha,
3255                         pm8001_printk(" phy Down and(default) = %x\n",
3256                         portstate));
3257                 break;
3258
3259         }
3260 }
3261
3262 /**
3263  * mpi_reg_resp -process register device ID response.
3264  * @pm8001_ha: our hba card information
3265  * @piomb: IO message buffer
3266  *
3267  * when sas layer find a device it will notify LLDD, then the driver register
3268  * the domain device to FW, this event is the return device ID which the FW
3269  * has assigned, from now,inter-communication with FW is no longer using the
3270  * SAS address, use device ID which FW assigned.
3271  */
3272 static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3273 {
3274         u32 status;
3275         u32 device_id;
3276         u32 htag;
3277         struct pm8001_ccb_info *ccb;
3278         struct pm8001_device *pm8001_dev;
3279         struct dev_reg_resp *registerRespPayload =
3280                 (struct dev_reg_resp *)(piomb + 4);
3281
3282         htag = le32_to_cpu(registerRespPayload->tag);
3283         ccb = &pm8001_ha->ccb_info[htag];
3284         pm8001_dev = ccb->device;
3285         status = le32_to_cpu(registerRespPayload->status);
3286         device_id = le32_to_cpu(registerRespPayload->device_id);
3287         PM8001_MSG_DBG(pm8001_ha,
3288                 pm8001_printk(" register device is status = %d\n", status));
3289         switch (status) {
3290         case DEVREG_SUCCESS:
3291                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3292                 pm8001_dev->device_id = device_id;
3293                 break;
3294         case DEVREG_FAILURE_OUT_OF_RESOURCE:
3295                 PM8001_MSG_DBG(pm8001_ha,
3296                         pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3297                 break;
3298         case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3299                 PM8001_MSG_DBG(pm8001_ha,
3300                    pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3301                 break;
3302         case DEVREG_FAILURE_INVALID_PHY_ID:
3303                 PM8001_MSG_DBG(pm8001_ha,
3304                         pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3305                 break;
3306         case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3307                 PM8001_MSG_DBG(pm8001_ha,
3308                    pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3309                 break;
3310         case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3311                 PM8001_MSG_DBG(pm8001_ha,
3312                         pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3313                 break;
3314         case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3315                 PM8001_MSG_DBG(pm8001_ha,
3316                         pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3317                 break;
3318         case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3319                 PM8001_MSG_DBG(pm8001_ha,
3320                        pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3321                 break;
3322         default:
3323                 PM8001_MSG_DBG(pm8001_ha,
3324                  pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3325                 break;
3326         }
3327         complete(pm8001_dev->dcompletion);
3328         ccb->task = NULL;
3329         ccb->ccb_tag = 0xFFFFFFFF;
3330         pm8001_ccb_free(pm8001_ha, htag);
3331         return 0;
3332 }
3333
3334 static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3335 {
3336         u32 status;
3337         u32 device_id;
3338         struct dev_reg_resp *registerRespPayload =
3339                 (struct dev_reg_resp *)(piomb + 4);
3340
3341         status = le32_to_cpu(registerRespPayload->status);
3342         device_id = le32_to_cpu(registerRespPayload->device_id);
3343         if (status != 0)
3344                 PM8001_MSG_DBG(pm8001_ha,
3345                         pm8001_printk(" deregister device failed ,status = %x"
3346                         ", device_id = %x\n", status, device_id));
3347         return 0;
3348 }
3349
3350 static int
3351 mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3352 {
3353         u32 status;
3354         struct fw_control_ex    fw_control_context;
3355         struct fw_flash_Update_resp *ppayload =
3356                 (struct fw_flash_Update_resp *)(piomb + 4);
3357         u32 tag = le32_to_cpu(ppayload->tag);
3358         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3359         status = le32_to_cpu(ppayload->status);
3360         memcpy(&fw_control_context,
3361                 ccb->fw_control_context,
3362                 sizeof(fw_control_context));
3363         switch (status) {
3364         case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3365                 PM8001_MSG_DBG(pm8001_ha,
3366                 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3367                 break;
3368         case FLASH_UPDATE_IN_PROGRESS:
3369                 PM8001_MSG_DBG(pm8001_ha,
3370                         pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3371                 break;
3372         case FLASH_UPDATE_HDR_ERR:
3373                 PM8001_MSG_DBG(pm8001_ha,
3374                         pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3375                 break;
3376         case FLASH_UPDATE_OFFSET_ERR:
3377                 PM8001_MSG_DBG(pm8001_ha,
3378                         pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3379                 break;
3380         case FLASH_UPDATE_CRC_ERR:
3381                 PM8001_MSG_DBG(pm8001_ha,
3382                         pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3383                 break;
3384         case FLASH_UPDATE_LENGTH_ERR:
3385                 PM8001_MSG_DBG(pm8001_ha,
3386                         pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3387                 break;
3388         case FLASH_UPDATE_HW_ERR:
3389                 PM8001_MSG_DBG(pm8001_ha,
3390                         pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3391                 break;
3392         case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3393                 PM8001_MSG_DBG(pm8001_ha,
3394                         pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3395                 break;
3396         case FLASH_UPDATE_DISABLED:
3397                 PM8001_MSG_DBG(pm8001_ha,
3398                         pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3399                 break;
3400         default:
3401                 PM8001_MSG_DBG(pm8001_ha,
3402                         pm8001_printk("No matched status = %d\n", status));
3403                 break;
3404         }
3405         ccb->fw_control_context->fw_control->retcode = status;
3406         pci_free_consistent(pm8001_ha->pdev,
3407                         fw_control_context.len,
3408                         fw_control_context.virtAddr,
3409                         fw_control_context.phys_addr);
3410         complete(pm8001_ha->nvmd_completion);
3411         ccb->task = NULL;
3412         ccb->ccb_tag = 0xFFFFFFFF;
3413         pm8001_ccb_free(pm8001_ha, tag);
3414         return 0;
3415 }
3416
3417 static int
3418 mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3419 {
3420         u32 status;
3421         int i;
3422         struct general_event_resp *pPayload =
3423                 (struct general_event_resp *)(piomb + 4);
3424         status = le32_to_cpu(pPayload->status);
3425         PM8001_MSG_DBG(pm8001_ha,
3426                 pm8001_printk(" status = 0x%x\n", status));
3427         for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3428                 PM8001_MSG_DBG(pm8001_ha,
3429                         pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
3430                         pPayload->inb_IOMB_payload[i]));
3431         return 0;
3432 }
3433
3434 static int
3435 mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3436 {
3437         struct sas_task *t;
3438         struct pm8001_ccb_info *ccb;
3439         unsigned long flags;
3440         u32 status ;
3441         u32 tag, scp;
3442         struct task_status_struct *ts;
3443
3444         struct task_abort_resp *pPayload =
3445                 (struct task_abort_resp *)(piomb + 4);
3446
3447         status = le32_to_cpu(pPayload->status);
3448         tag = le32_to_cpu(pPayload->tag);
3449         scp = le32_to_cpu(pPayload->scp);
3450         ccb = &pm8001_ha->ccb_info[tag];
3451         t = ccb->task;
3452         PM8001_IO_DBG(pm8001_ha,
3453                 pm8001_printk(" status = 0x%x\n", status));
3454         if (t == NULL)
3455                 return -1;
3456         ts = &t->task_status;
3457         if (status != 0)
3458                 PM8001_FAIL_DBG(pm8001_ha,
3459                         pm8001_printk("task abort failed status 0x%x ,"
3460                         "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3461         switch (status) {
3462         case IO_SUCCESS:
3463                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3464                 ts->resp = SAS_TASK_COMPLETE;
3465                 ts->stat = SAM_STAT_GOOD;
3466                 break;
3467         case IO_NOT_VALID:
3468                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3469                 ts->resp = TMF_RESP_FUNC_FAILED;
3470                 break;
3471         }
3472         spin_lock_irqsave(&t->task_state_lock, flags);
3473         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3474         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3475         t->task_state_flags |= SAS_TASK_STATE_DONE;
3476         spin_unlock_irqrestore(&t->task_state_lock, flags);
3477         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3478         mb();
3479         t->task_done(t);
3480         return 0;
3481 }
3482
3483 /**
3484  * mpi_hw_event -The hw event has come.
3485  * @pm8001_ha: our hba card information
3486  * @piomb: IO message buffer
3487  */
3488 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3489 {
3490         unsigned long flags;
3491         struct hw_event_resp *pPayload =
3492                 (struct hw_event_resp *)(piomb + 4);
3493         u32 lr_evt_status_phyid_portid =
3494                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3495         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3496         u8 phy_id =
3497                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3498         u16 eventType =
3499                 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3500         u8 status =
3501                 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3502         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3503         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3504         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3505         PM8001_MSG_DBG(pm8001_ha,
3506                 pm8001_printk("outbound queue HW event & event type : "));
3507         switch (eventType) {
3508         case HW_EVENT_PHY_START_STATUS:
3509                 PM8001_MSG_DBG(pm8001_ha,
3510                 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3511                         " status = %x\n", status));
3512                 if (status == 0) {
3513                         phy->phy_state = 1;
3514                         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3515                                 complete(phy->enable_completion);
3516                 }
3517                 break;
3518         case HW_EVENT_SAS_PHY_UP:
3519                 PM8001_MSG_DBG(pm8001_ha,
3520                         pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3521                 hw_event_sas_phy_up(pm8001_ha, piomb);
3522                 break;
3523         case HW_EVENT_SATA_PHY_UP:
3524                 PM8001_MSG_DBG(pm8001_ha,
3525                         pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3526                 hw_event_sata_phy_up(pm8001_ha, piomb);
3527                 break;
3528         case HW_EVENT_PHY_STOP_STATUS:
3529                 PM8001_MSG_DBG(pm8001_ha,
3530                         pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3531                         "status = %x\n", status));
3532                 if (status == 0)
3533                         phy->phy_state = 0;
3534                 break;
3535         case HW_EVENT_SATA_SPINUP_HOLD:
3536                 PM8001_MSG_DBG(pm8001_ha,
3537                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3538                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3539                 break;
3540         case HW_EVENT_PHY_DOWN:
3541                 PM8001_MSG_DBG(pm8001_ha,
3542                         pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3543                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3544                 phy->phy_attached = 0;
3545                 phy->phy_state = 0;
3546                 hw_event_phy_down(pm8001_ha, piomb);
3547                 break;
3548         case HW_EVENT_PORT_INVALID:
3549                 PM8001_MSG_DBG(pm8001_ha,
3550                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3551                 sas_phy_disconnected(sas_phy);
3552                 phy->phy_attached = 0;
3553                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3554                 break;
3555         /* the broadcast change primitive received, tell the LIBSAS this event
3556         to revalidate the sas domain*/
3557         case HW_EVENT_BROADCAST_CHANGE:
3558                 PM8001_MSG_DBG(pm8001_ha,
3559                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3560                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3561                         port_id, phy_id, 1, 0);
3562                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3563                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3564                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3565                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3566                 break;
3567         case HW_EVENT_PHY_ERROR:
3568                 PM8001_MSG_DBG(pm8001_ha,
3569                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3570                 sas_phy_disconnected(&phy->sas_phy);
3571                 phy->phy_attached = 0;
3572                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3573                 break;
3574         case HW_EVENT_BROADCAST_EXP:
3575                 PM8001_MSG_DBG(pm8001_ha,
3576                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3577                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3578                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3579                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3580                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3581                 break;
3582         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3583                 PM8001_MSG_DBG(pm8001_ha,
3584                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3585                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3586                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3587                 sas_phy_disconnected(sas_phy);
3588                 phy->phy_attached = 0;
3589                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3590                 break;
3591         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3592                 PM8001_MSG_DBG(pm8001_ha,
3593                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3594                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3595                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3596                         port_id, phy_id, 0, 0);
3597                 sas_phy_disconnected(sas_phy);
3598                 phy->phy_attached = 0;
3599                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3600                 break;
3601         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3602                 PM8001_MSG_DBG(pm8001_ha,
3603                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3604                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3605                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3606                         port_id, phy_id, 0, 0);
3607                 sas_phy_disconnected(sas_phy);
3608                 phy->phy_attached = 0;
3609                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3610                 break;
3611         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3612                 PM8001_MSG_DBG(pm8001_ha,
3613                       pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3614                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3615                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3616                         port_id, phy_id, 0, 0);
3617                 sas_phy_disconnected(sas_phy);
3618                 phy->phy_attached = 0;
3619                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3620                 break;
3621         case HW_EVENT_MALFUNCTION:
3622                 PM8001_MSG_DBG(pm8001_ha,
3623                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3624                 break;
3625         case HW_EVENT_BROADCAST_SES:
3626                 PM8001_MSG_DBG(pm8001_ha,
3627                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3628                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3629                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3630                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3631                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3632                 break;
3633         case HW_EVENT_INBOUND_CRC_ERROR:
3634                 PM8001_MSG_DBG(pm8001_ha,
3635                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3636                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3637                         HW_EVENT_INBOUND_CRC_ERROR,
3638                         port_id, phy_id, 0, 0);
3639                 break;
3640         case HW_EVENT_HARD_RESET_RECEIVED:
3641                 PM8001_MSG_DBG(pm8001_ha,
3642                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3643                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3644                 break;
3645         case HW_EVENT_ID_FRAME_TIMEOUT:
3646                 PM8001_MSG_DBG(pm8001_ha,
3647                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3648                 sas_phy_disconnected(sas_phy);
3649                 phy->phy_attached = 0;
3650                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3651                 break;
3652         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3653                 PM8001_MSG_DBG(pm8001_ha,
3654                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3655                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3656                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3657                         port_id, phy_id, 0, 0);
3658                 sas_phy_disconnected(sas_phy);
3659                 phy->phy_attached = 0;
3660                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3661                 break;
3662         case HW_EVENT_PORT_RESET_TIMER_TMO:
3663                 PM8001_MSG_DBG(pm8001_ha,
3664                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3665                 sas_phy_disconnected(sas_phy);
3666                 phy->phy_attached = 0;
3667                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3668                 break;
3669         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3670                 PM8001_MSG_DBG(pm8001_ha,
3671                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3672                 sas_phy_disconnected(sas_phy);
3673                 phy->phy_attached = 0;
3674                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3675                 break;
3676         case HW_EVENT_PORT_RECOVER:
3677                 PM8001_MSG_DBG(pm8001_ha,
3678                         pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3679                 break;
3680         case HW_EVENT_PORT_RESET_COMPLETE:
3681                 PM8001_MSG_DBG(pm8001_ha,
3682                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3683                 break;
3684         case EVENT_BROADCAST_ASYNCH_EVENT:
3685                 PM8001_MSG_DBG(pm8001_ha,
3686                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3687                 break;
3688         default:
3689                 PM8001_MSG_DBG(pm8001_ha,
3690                         pm8001_printk("Unknown event type = %x\n", eventType));
3691                 break;
3692         }
3693         return 0;
3694 }
3695
3696 /**
3697  * process_one_iomb - process one outbound Queue memory block
3698  * @pm8001_ha: our hba card information
3699  * @piomb: IO message buffer
3700  */
3701 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3702 {
3703         __le32 pHeader = *(__le32 *)piomb;
3704         u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3705
3706         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
3707
3708         switch (opc) {
3709         case OPC_OUB_ECHO:
3710                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3711                 break;
3712         case OPC_OUB_HW_EVENT:
3713                 PM8001_MSG_DBG(pm8001_ha,
3714                         pm8001_printk("OPC_OUB_HW_EVENT\n"));
3715                 mpi_hw_event(pm8001_ha, piomb);
3716                 break;
3717         case OPC_OUB_SSP_COMP:
3718                 PM8001_MSG_DBG(pm8001_ha,
3719                         pm8001_printk("OPC_OUB_SSP_COMP\n"));
3720                 mpi_ssp_completion(pm8001_ha, piomb);
3721                 break;
3722         case OPC_OUB_SMP_COMP:
3723                 PM8001_MSG_DBG(pm8001_ha,
3724                         pm8001_printk("OPC_OUB_SMP_COMP\n"));
3725                 mpi_smp_completion(pm8001_ha, piomb);
3726                 break;
3727         case OPC_OUB_LOCAL_PHY_CNTRL:
3728                 PM8001_MSG_DBG(pm8001_ha,
3729                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3730                 mpi_local_phy_ctl(pm8001_ha, piomb);
3731                 break;
3732         case OPC_OUB_DEV_REGIST:
3733                 PM8001_MSG_DBG(pm8001_ha,
3734                         pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3735                 mpi_reg_resp(pm8001_ha, piomb);
3736                 break;
3737         case OPC_OUB_DEREG_DEV:
3738                 PM8001_MSG_DBG(pm8001_ha,
3739                         pm8001_printk("unregister the device\n"));
3740                 mpi_dereg_resp(pm8001_ha, piomb);
3741                 break;
3742         case OPC_OUB_GET_DEV_HANDLE:
3743                 PM8001_MSG_DBG(pm8001_ha,
3744                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3745                 break;
3746         case OPC_OUB_SATA_COMP:
3747                 PM8001_MSG_DBG(pm8001_ha,
3748                         pm8001_printk("OPC_OUB_SATA_COMP\n"));
3749                 mpi_sata_completion(pm8001_ha, piomb);
3750                 break;
3751         case OPC_OUB_SATA_EVENT:
3752                 PM8001_MSG_DBG(pm8001_ha,
3753                         pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3754                 mpi_sata_event(pm8001_ha, piomb);
3755                 break;
3756         case OPC_OUB_SSP_EVENT:
3757                 PM8001_MSG_DBG(pm8001_ha,
3758                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3759                 mpi_ssp_event(pm8001_ha, piomb);
3760                 break;
3761         case OPC_OUB_DEV_HANDLE_ARRIV:
3762                 PM8001_MSG_DBG(pm8001_ha,
3763                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3764                 /*This is for target*/
3765                 break;
3766         case OPC_OUB_SSP_RECV_EVENT:
3767                 PM8001_MSG_DBG(pm8001_ha,
3768                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3769                 /*This is for target*/
3770                 break;
3771         case OPC_OUB_DEV_INFO:
3772                 PM8001_MSG_DBG(pm8001_ha,
3773                         pm8001_printk("OPC_OUB_DEV_INFO\n"));
3774                 break;
3775         case OPC_OUB_FW_FLASH_UPDATE:
3776                 PM8001_MSG_DBG(pm8001_ha,
3777                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3778                 mpi_fw_flash_update_resp(pm8001_ha, piomb);
3779                 break;
3780         case OPC_OUB_GPIO_RESPONSE:
3781                 PM8001_MSG_DBG(pm8001_ha,
3782                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3783                 break;
3784         case OPC_OUB_GPIO_EVENT:
3785                 PM8001_MSG_DBG(pm8001_ha,
3786                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3787                 break;
3788         case OPC_OUB_GENERAL_EVENT:
3789                 PM8001_MSG_DBG(pm8001_ha,
3790                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3791                 mpi_general_event(pm8001_ha, piomb);
3792                 break;
3793         case OPC_OUB_SSP_ABORT_RSP:
3794                 PM8001_MSG_DBG(pm8001_ha,
3795                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3796                 mpi_task_abort_resp(pm8001_ha, piomb);
3797                 break;
3798         case OPC_OUB_SATA_ABORT_RSP:
3799                 PM8001_MSG_DBG(pm8001_ha,
3800                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3801                 mpi_task_abort_resp(pm8001_ha, piomb);
3802                 break;
3803         case OPC_OUB_SAS_DIAG_MODE_START_END:
3804                 PM8001_MSG_DBG(pm8001_ha,
3805                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3806                 break;
3807         case OPC_OUB_SAS_DIAG_EXECUTE:
3808                 PM8001_MSG_DBG(pm8001_ha,
3809                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3810                 break;
3811         case OPC_OUB_GET_TIME_STAMP:
3812                 PM8001_MSG_DBG(pm8001_ha,
3813                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3814                 break;
3815         case OPC_OUB_SAS_HW_EVENT_ACK:
3816                 PM8001_MSG_DBG(pm8001_ha,
3817                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3818                 break;
3819         case OPC_OUB_PORT_CONTROL:
3820                 PM8001_MSG_DBG(pm8001_ha,
3821                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3822                 break;
3823         case OPC_OUB_SMP_ABORT_RSP:
3824                 PM8001_MSG_DBG(pm8001_ha,
3825                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3826                 mpi_task_abort_resp(pm8001_ha, piomb);
3827                 break;
3828         case OPC_OUB_GET_NVMD_DATA:
3829                 PM8001_MSG_DBG(pm8001_ha,
3830                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3831                 mpi_get_nvmd_resp(pm8001_ha, piomb);
3832                 break;
3833         case OPC_OUB_SET_NVMD_DATA:
3834                 PM8001_MSG_DBG(pm8001_ha,
3835                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3836                 mpi_set_nvmd_resp(pm8001_ha, piomb);
3837                 break;
3838         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3839                 PM8001_MSG_DBG(pm8001_ha,
3840                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3841                 break;
3842         case OPC_OUB_SET_DEVICE_STATE:
3843                 PM8001_MSG_DBG(pm8001_ha,
3844                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3845                 mpi_set_dev_state_resp(pm8001_ha, piomb);
3846                 break;
3847         case OPC_OUB_GET_DEVICE_STATE:
3848                 PM8001_MSG_DBG(pm8001_ha,
3849                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3850                 break;
3851         case OPC_OUB_SET_DEV_INFO:
3852                 PM8001_MSG_DBG(pm8001_ha,
3853                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3854                 break;
3855         case OPC_OUB_SAS_RE_INITIALIZE:
3856                 PM8001_MSG_DBG(pm8001_ha,
3857                         pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
3858                 break;
3859         default:
3860                 PM8001_MSG_DBG(pm8001_ha,
3861                         pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
3862                         opc));
3863                 break;
3864         }
3865 }
3866
3867 static int process_oq(struct pm8001_hba_info *pm8001_ha)
3868 {
3869         struct outbound_queue_table *circularQ;
3870         void *pMsg1 = NULL;
3871         u8 uninitialized_var(bc);
3872         u32 ret = MPI_IO_STATUS_FAIL;
3873         unsigned long flags;
3874
3875         spin_lock_irqsave(&pm8001_ha->lock, flags);
3876         circularQ = &pm8001_ha->outbnd_q_tbl[0];
3877         do {
3878                 ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3879                 if (MPI_IO_STATUS_SUCCESS == ret) {
3880                         /* process the outbound message */
3881                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3882                         /* free the message from the outbound circular buffer */
3883                         mpi_msg_free_set(pm8001_ha, pMsg1, circularQ, bc);
3884                 }
3885                 if (MPI_IO_STATUS_BUSY == ret) {
3886                         /* Update the producer index from SPC */
3887                         circularQ->producer_index =
3888                                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3889                         if (le32_to_cpu(circularQ->producer_index) ==
3890                                 circularQ->consumer_idx)
3891                                 /* OQ is empty */
3892                                 break;
3893                 }
3894         } while (1);
3895         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3896         return ret;
3897 }
3898
3899 /* PCI_DMA_... to our direction translation. */
3900 static const u8 data_dir_flags[] = {
3901         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3902         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
3903         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
3904         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
3905 };
3906 static void
3907 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
3908 {
3909         int i;
3910         struct scatterlist *sg;
3911         struct pm8001_prd *buf_prd = prd;
3912
3913         for_each_sg(scatter, sg, nr, i) {
3914                 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
3915                 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
3916                 buf_prd->im_len.e = 0;
3917                 buf_prd++;
3918         }
3919 }
3920
3921 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
3922 {
3923         psmp_cmd->tag = hTag;
3924         psmp_cmd->device_id = cpu_to_le32(deviceID);
3925         psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3926 }
3927
3928 /**
3929  * pm8001_chip_smp_req - send a SMP task to FW
3930  * @pm8001_ha: our hba card information.
3931  * @ccb: the ccb information this request used.
3932  */
3933 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3934         struct pm8001_ccb_info *ccb)
3935 {
3936         int elem, rc;
3937         struct sas_task *task = ccb->task;
3938         struct domain_device *dev = task->dev;
3939         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3940         struct scatterlist *sg_req, *sg_resp;
3941         u32 req_len, resp_len;
3942         struct smp_req smp_cmd;
3943         u32 opc;
3944         struct inbound_queue_table *circularQ;
3945
3946         memset(&smp_cmd, 0, sizeof(smp_cmd));
3947         /*
3948          * DMA-map SMP request, response buffers
3949          */
3950         sg_req = &task->smp_task.smp_req;
3951         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3952         if (!elem)
3953                 return -ENOMEM;
3954         req_len = sg_dma_len(sg_req);
3955
3956         sg_resp = &task->smp_task.smp_resp;
3957         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3958         if (!elem) {
3959                 rc = -ENOMEM;
3960                 goto err_out;
3961         }
3962         resp_len = sg_dma_len(sg_resp);
3963         /* must be in dwords */
3964         if ((req_len & 0x3) || (resp_len & 0x3)) {
3965                 rc = -EINVAL;
3966                 goto err_out_2;
3967         }
3968
3969         opc = OPC_INB_SMP_REQUEST;
3970         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3971         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3972         smp_cmd.long_smp_req.long_req_addr =
3973                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3974         smp_cmd.long_smp_req.long_req_size =
3975                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3976         smp_cmd.long_smp_req.long_resp_addr =
3977                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
3978         smp_cmd.long_smp_req.long_resp_size =
3979                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3980         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
3981         mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd);
3982         return 0;
3983
3984 err_out_2:
3985         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3986                         PCI_DMA_FROMDEVICE);
3987 err_out:
3988         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3989                         PCI_DMA_TODEVICE);
3990         return rc;
3991 }
3992
3993 /**
3994  * pm8001_chip_ssp_io_req - send a SSP task to FW
3995  * @pm8001_ha: our hba card information.
3996  * @ccb: the ccb information this request used.
3997  */
3998 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3999         struct pm8001_ccb_info *ccb)
4000 {
4001         struct sas_task *task = ccb->task;
4002         struct domain_device *dev = task->dev;
4003         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4004         struct ssp_ini_io_start_req ssp_cmd;
4005         u32 tag = ccb->ccb_tag;
4006         int ret;
4007         u64 phys_addr;
4008         struct inbound_queue_table *circularQ;
4009         u32 opc = OPC_INB_SSPINIIOSTART;
4010         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4011         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4012         ssp_cmd.dir_m_tlr =
4013                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4014         SAS 1.1 compatible TLR*/
4015         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4016         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4017         ssp_cmd.tag = cpu_to_le32(tag);
4018         if (task->ssp_task.enable_first_burst)
4019                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4020         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4021         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4022         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
4023         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4024
4025         /* fill in PRD (scatter/gather) table, if any */
4026         if (task->num_scatter > 1) {
4027                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4028                 phys_addr = ccb->ccb_dma_handle +
4029                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4030                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4031                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4032                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4033         } else if (task->num_scatter == 1) {
4034                 u64 dma_addr = sg_dma_address(task->scatter);
4035                 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4036                 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4037                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4038                 ssp_cmd.esgl = 0;
4039         } else if (task->num_scatter == 0) {
4040                 ssp_cmd.addr_low = 0;
4041                 ssp_cmd.addr_high = 0;
4042                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4043                 ssp_cmd.esgl = 0;
4044         }
4045         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd);
4046         return ret;
4047 }
4048
4049 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4050         struct pm8001_ccb_info *ccb)
4051 {
4052         struct sas_task *task = ccb->task;
4053         struct domain_device *dev = task->dev;
4054         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4055         u32 tag = ccb->ccb_tag;
4056         int ret;
4057         struct sata_start_req sata_cmd;
4058         u32 hdr_tag, ncg_tag = 0;
4059         u64 phys_addr;
4060         u32 ATAP = 0x0;
4061         u32 dir;
4062         struct inbound_queue_table *circularQ;
4063         u32  opc = OPC_INB_SATA_HOST_OPSTART;
4064         memset(&sata_cmd, 0, sizeof(sata_cmd));
4065         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4066         if (task->data_dir == PCI_DMA_NONE) {
4067                 ATAP = 0x04;  /* no data*/
4068                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4069         } else if (likely(!task->ata_task.device_control_reg_update)) {
4070                 if (task->ata_task.dma_xfer) {
4071                         ATAP = 0x06; /* DMA */
4072                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4073                 } else {
4074                         ATAP = 0x05; /* PIO*/
4075                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4076                 }
4077                 if (task->ata_task.use_ncq &&
4078                         dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
4079                         ATAP = 0x07; /* FPDMA */
4080                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4081                 }
4082         }
4083         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
4084                 ncg_tag = hdr_tag;
4085         dir = data_dir_flags[task->data_dir] << 8;
4086         sata_cmd.tag = cpu_to_le32(tag);
4087         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4088         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4089         sata_cmd.ncqtag_atap_dir_m =
4090                 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4091         sata_cmd.sata_fis = task->ata_task.fis;
4092         if (likely(!task->ata_task.device_control_reg_update))
4093                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4094         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4095         /* fill in PRD (scatter/gather) table, if any */
4096         if (task->num_scatter > 1) {
4097                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4098                 phys_addr = ccb->ccb_dma_handle +
4099                                 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4100                 sata_cmd.addr_low = lower_32_bits(phys_addr);
4101                 sata_cmd.addr_high = upper_32_bits(phys_addr);
4102                 sata_cmd.esgl = cpu_to_le32(1 << 31);
4103         } else if (task->num_scatter == 1) {
4104                 u64 dma_addr = sg_dma_address(task->scatter);
4105                 sata_cmd.addr_low = lower_32_bits(dma_addr);
4106                 sata_cmd.addr_high = upper_32_bits(dma_addr);
4107                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4108                 sata_cmd.esgl = 0;
4109         } else if (task->num_scatter == 0) {
4110                 sata_cmd.addr_low = 0;
4111                 sata_cmd.addr_high = 0;
4112                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4113                 sata_cmd.esgl = 0;
4114         }
4115         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd);
4116         return ret;
4117 }
4118
4119 /**
4120  * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4121  * @pm8001_ha: our hba card information.
4122  * @num: the inbound queue number
4123  * @phy_id: the phy id which we wanted to start up.
4124  */
4125 static int
4126 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4127 {
4128         struct phy_start_req payload;
4129         struct inbound_queue_table *circularQ;
4130         int ret;
4131         u32 tag = 0x01;
4132         u32 opcode = OPC_INB_PHYSTART;
4133         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4134         memset(&payload, 0, sizeof(payload));
4135         payload.tag = cpu_to_le32(tag);
4136         /*
4137          ** [0:7]   PHY Identifier
4138          ** [8:11]  link rate 1.5G, 3G, 6G
4139          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4140          ** [14]    0b disable spin up hold; 1b enable spin up hold
4141          */
4142         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4143                 LINKMODE_AUTO | LINKRATE_15 |
4144                 LINKRATE_30 | LINKRATE_60 | phy_id);
4145         payload.sas_identify.dev_type = SAS_END_DEV;
4146         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4147         memcpy(payload.sas_identify.sas_addr,
4148                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4149         payload.sas_identify.phy_id = phy_id;
4150         ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
4151         return ret;
4152 }
4153
4154 /**
4155  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4156  * @pm8001_ha: our hba card information.
4157  * @num: the inbound queue number
4158  * @phy_id: the phy id which we wanted to start up.
4159  */
4160 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4161         u8 phy_id)
4162 {
4163         struct phy_stop_req payload;
4164         struct inbound_queue_table *circularQ;
4165         int ret;
4166         u32 tag = 0x01;
4167         u32 opcode = OPC_INB_PHYSTOP;
4168         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4169         memset(&payload, 0, sizeof(payload));
4170         payload.tag = cpu_to_le32(tag);
4171         payload.phy_id = cpu_to_le32(phy_id);
4172         ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
4173         return ret;
4174 }
4175
4176 /**
4177  * see comments on mpi_reg_resp.
4178  */
4179 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4180         struct pm8001_device *pm8001_dev, u32 flag)
4181 {
4182         struct reg_dev_req payload;
4183         u32     opc;
4184         u32 stp_sspsmp_sata = 0x4;
4185         struct inbound_queue_table *circularQ;
4186         u32 linkrate, phy_id;
4187         int rc, tag = 0xdeadbeef;
4188         struct pm8001_ccb_info *ccb;
4189         u8 retryFlag = 0x1;
4190         u16 firstBurstSize = 0;
4191         u16 ITNT = 2000;
4192         struct domain_device *dev = pm8001_dev->sas_device;
4193         struct domain_device *parent_dev = dev->parent;
4194         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4195
4196         memset(&payload, 0, sizeof(payload));
4197         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4198         if (rc)
4199                 return rc;
4200         ccb = &pm8001_ha->ccb_info[tag];
4201         ccb->device = pm8001_dev;
4202         ccb->ccb_tag = tag;
4203         payload.tag = cpu_to_le32(tag);
4204         if (flag == 1)
4205                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4206         else {
4207                 if (pm8001_dev->dev_type == SATA_DEV)
4208                         stp_sspsmp_sata = 0x00; /* stp*/
4209                 else if (pm8001_dev->dev_type == SAS_END_DEV ||
4210                         pm8001_dev->dev_type == EDGE_DEV ||
4211                         pm8001_dev->dev_type == FANOUT_DEV)
4212                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4213         }
4214         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4215                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4216         else
4217                 phy_id = pm8001_dev->attached_phy;
4218         opc = OPC_INB_REG_DEV;
4219         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4220                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4221         payload.phyid_portid =
4222                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4223                 ((phy_id & 0x0F) << 4));
4224         payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4225                 ((linkrate & 0x0F) * 0x1000000) |
4226                 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4227         payload.firstburstsize_ITNexustimeout =
4228                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4229         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4230                 SAS_ADDR_SIZE);
4231         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4232         return rc;
4233 }
4234
4235 /**
4236  * see comments on mpi_reg_resp.
4237  */
4238 static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4239         u32 device_id)
4240 {
4241         struct dereg_dev_req payload;
4242         u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4243         int ret;
4244         struct inbound_queue_table *circularQ;
4245
4246         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4247         memset(&payload, 0, sizeof(payload));
4248         payload.tag = cpu_to_le32(1);
4249         payload.device_id = cpu_to_le32(device_id);
4250         PM8001_MSG_DBG(pm8001_ha,
4251                 pm8001_printk("unregister device device_id = %d\n", device_id));
4252         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4253         return ret;
4254 }
4255
4256 /**
4257  * pm8001_chip_phy_ctl_req - support the local phy operation
4258  * @pm8001_ha: our hba card information.
4259  * @num: the inbound queue number
4260  * @phy_id: the phy id which we wanted to operate
4261  * @phy_op:
4262  */
4263 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4264         u32 phyId, u32 phy_op)
4265 {
4266         struct local_phy_ctl_req payload;
4267         struct inbound_queue_table *circularQ;
4268         int ret;
4269         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4270         memset(&payload, 0, sizeof(payload));
4271         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4272         payload.tag = cpu_to_le32(1);
4273         payload.phyop_phyid =
4274                 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4275         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4276         return ret;
4277 }
4278
4279 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4280 {
4281         u32 value;
4282 #ifdef PM8001_USE_MSIX
4283         return 1;
4284 #endif
4285         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4286         if (value)
4287                 return 1;
4288         return 0;
4289
4290 }
4291
4292 /**
4293  * pm8001_chip_isr - PM8001 isr handler.
4294  * @pm8001_ha: our hba card information.
4295  * @irq: irq number.
4296  * @stat: stat.
4297  */
4298 static irqreturn_t
4299 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha)
4300 {
4301         pm8001_chip_interrupt_disable(pm8001_ha);
4302         process_oq(pm8001_ha);
4303         pm8001_chip_interrupt_enable(pm8001_ha);
4304         return IRQ_HANDLED;
4305 }
4306
4307 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4308         u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4309 {
4310         struct task_abort_req task_abort;
4311         struct inbound_queue_table *circularQ;
4312         int ret;
4313         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4314         memset(&task_abort, 0, sizeof(task_abort));
4315         if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4316                 task_abort.abort_all = 0;
4317                 task_abort.device_id = cpu_to_le32(dev_id);
4318                 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4319                 task_abort.tag = cpu_to_le32(cmd_tag);
4320         } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4321                 task_abort.abort_all = cpu_to_le32(1);
4322                 task_abort.device_id = cpu_to_le32(dev_id);
4323                 task_abort.tag = cpu_to_le32(cmd_tag);
4324         }
4325         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort);
4326         return ret;
4327 }
4328
4329 /**
4330  * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4331  * @task: the task we wanted to aborted.
4332  * @flag: the abort flag.
4333  */
4334 static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4335         struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4336 {
4337         u32 opc, device_id;
4338         int rc = TMF_RESP_FUNC_FAILED;
4339         PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag"
4340                 " = %x", cmd_tag, task_tag));
4341         if (pm8001_dev->dev_type == SAS_END_DEV)
4342                 opc = OPC_INB_SSP_ABORT;
4343         else if (pm8001_dev->dev_type == SATA_DEV)
4344                 opc = OPC_INB_SATA_ABORT;
4345         else
4346                 opc = OPC_INB_SMP_ABORT;/* SMP */
4347         device_id = pm8001_dev->device_id;
4348         rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4349                 task_tag, cmd_tag);
4350         if (rc != TMF_RESP_FUNC_COMPLETE)
4351                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4352         return rc;
4353 }
4354
4355 /**
4356  * pm8001_chip_ssp_tm_req - built the task management command.
4357  * @pm8001_ha: our hba card information.
4358  * @ccb: the ccb information.
4359  * @tmf: task management function.
4360  */
4361 static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4362         struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4363 {
4364         struct sas_task *task = ccb->task;
4365         struct domain_device *dev = task->dev;
4366         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4367         u32 opc = OPC_INB_SSPINITMSTART;
4368         struct inbound_queue_table *circularQ;
4369         struct ssp_ini_tm_start_req sspTMCmd;
4370         int ret;
4371
4372         memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4373         sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4374         sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4375         sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4376         memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4377         sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4378         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4379         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd);
4380         return ret;
4381 }
4382
4383 static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4384         void *payload)
4385 {
4386         u32 opc = OPC_INB_GET_NVMD_DATA;
4387         u32 nvmd_type;
4388         int rc;
4389         u32 tag;
4390         struct pm8001_ccb_info *ccb;
4391         struct inbound_queue_table *circularQ;
4392         struct get_nvm_data_req nvmd_req;
4393         struct fw_control_ex *fw_control_context;
4394         struct pm8001_ioctl_payload *ioctl_payload = payload;
4395
4396         nvmd_type = ioctl_payload->minor_function;
4397         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4398         if (!fw_control_context)
4399                 return -ENOMEM;
4400         fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0];
4401         fw_control_context->len = ioctl_payload->length;
4402         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4403         memset(&nvmd_req, 0, sizeof(nvmd_req));
4404         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4405         if (rc) {
4406                 kfree(fw_control_context);
4407                 return rc;
4408         }
4409         ccb = &pm8001_ha->ccb_info[tag];
4410         ccb->ccb_tag = tag;
4411         ccb->fw_control_context = fw_control_context;
4412         nvmd_req.tag = cpu_to_le32(tag);
4413
4414         switch (nvmd_type) {
4415         case TWI_DEVICE: {
4416                 u32 twi_addr, twi_page_size;
4417                 twi_addr = 0xa8;
4418                 twi_page_size = 2;
4419
4420                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4421                         twi_page_size << 8 | TWI_DEVICE);
4422                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4423                 nvmd_req.resp_addr_hi =
4424                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4425                 nvmd_req.resp_addr_lo =
4426                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4427                 break;
4428         }
4429         case C_SEEPROM: {
4430                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4431                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4432                 nvmd_req.resp_addr_hi =
4433                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4434                 nvmd_req.resp_addr_lo =
4435                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4436                 break;
4437         }
4438         case VPD_FLASH: {
4439                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4440                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4441                 nvmd_req.resp_addr_hi =
4442                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4443                 nvmd_req.resp_addr_lo =
4444                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4445                 break;
4446         }
4447         case EXPAN_ROM: {
4448                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4449                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4450                 nvmd_req.resp_addr_hi =
4451                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4452                 nvmd_req.resp_addr_lo =
4453                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4454                 break;
4455         }
4456         default:
4457                 break;
4458         }
4459         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4460         return rc;
4461 }
4462
4463 static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4464         void *payload)
4465 {
4466         u32 opc = OPC_INB_SET_NVMD_DATA;
4467         u32 nvmd_type;
4468         int rc;
4469         u32 tag;
4470         struct pm8001_ccb_info *ccb;
4471         struct inbound_queue_table *circularQ;
4472         struct set_nvm_data_req nvmd_req;
4473         struct fw_control_ex *fw_control_context;
4474         struct pm8001_ioctl_payload *ioctl_payload = payload;
4475
4476         nvmd_type = ioctl_payload->minor_function;
4477         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4478         if (!fw_control_context)
4479                 return -ENOMEM;
4480         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4481         memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4482                 ioctl_payload->func_specific,
4483                 ioctl_payload->length);
4484         memset(&nvmd_req, 0, sizeof(nvmd_req));
4485         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4486         if (rc) {
4487                 kfree(fw_control_context);
4488                 return rc;
4489         }
4490         ccb = &pm8001_ha->ccb_info[tag];
4491         ccb->fw_control_context = fw_control_context;
4492         ccb->ccb_tag = tag;
4493         nvmd_req.tag = cpu_to_le32(tag);
4494         switch (nvmd_type) {
4495         case TWI_DEVICE: {
4496                 u32 twi_addr, twi_page_size;
4497                 twi_addr = 0xa8;
4498                 twi_page_size = 2;
4499                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4500                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4501                         twi_page_size << 8 | TWI_DEVICE);
4502                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4503                 nvmd_req.resp_addr_hi =
4504                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4505                 nvmd_req.resp_addr_lo =
4506                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4507                 break;
4508         }
4509         case C_SEEPROM:
4510                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4511                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4512                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4513                 nvmd_req.resp_addr_hi =
4514                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4515                 nvmd_req.resp_addr_lo =
4516                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4517                 break;
4518         case VPD_FLASH:
4519                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4520                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4521                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4522                 nvmd_req.resp_addr_hi =
4523                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4524                 nvmd_req.resp_addr_lo =
4525                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4526                 break;
4527         case EXPAN_ROM:
4528                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4529                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4530                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4531                 nvmd_req.resp_addr_hi =
4532                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4533                 nvmd_req.resp_addr_lo =
4534                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4535                 break;
4536         default:
4537                 break;
4538         }
4539         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4540         return rc;
4541 }
4542
4543 /**
4544  * pm8001_chip_fw_flash_update_build - support the firmware update operation
4545  * @pm8001_ha: our hba card information.
4546  * @fw_flash_updata_info: firmware flash update param
4547  */
4548 static int
4549 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4550         void *fw_flash_updata_info, u32 tag)
4551 {
4552         struct fw_flash_Update_req payload;
4553         struct fw_flash_updata_info *info;
4554         struct inbound_queue_table *circularQ;
4555         int ret;
4556         u32 opc = OPC_INB_FW_FLASH_UPDATE;
4557
4558         memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4559         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4560         info = fw_flash_updata_info;
4561         payload.tag = cpu_to_le32(tag);
4562         payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4563         payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4564         payload.total_image_len = cpu_to_le32(info->total_image_len);
4565         payload.len = info->sgl.im_len.len ;
4566         payload.sgl_addr_lo =
4567                 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4568         payload.sgl_addr_hi =
4569                 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4570         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4571         return ret;
4572 }
4573
4574 static int
4575 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4576         void *payload)
4577 {
4578         struct fw_flash_updata_info flash_update_info;
4579         struct fw_control_info *fw_control;
4580         struct fw_control_ex *fw_control_context;
4581         int rc;
4582         u32 tag;
4583         struct pm8001_ccb_info *ccb;
4584         void *buffer = NULL;
4585         dma_addr_t phys_addr;
4586         u32 phys_addr_hi;
4587         u32 phys_addr_lo;
4588         struct pm8001_ioctl_payload *ioctl_payload = payload;
4589
4590         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4591         if (!fw_control_context)
4592                 return -ENOMEM;
4593         fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0];
4594         if (fw_control->len != 0) {
4595                 if (pm8001_mem_alloc(pm8001_ha->pdev,
4596                         (void **)&buffer,
4597                         &phys_addr,
4598                         &phys_addr_hi,
4599                         &phys_addr_lo,
4600                         fw_control->len, 0) != 0) {
4601                                 PM8001_FAIL_DBG(pm8001_ha,
4602                                         pm8001_printk("Mem alloc failure\n"));
4603                                 kfree(fw_control_context);
4604                                 return -ENOMEM;
4605                 }
4606         }
4607         memcpy(buffer, fw_control->buffer, fw_control->len);
4608         flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4609         flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4610         flash_update_info.sgl.im_len.e = 0;
4611         flash_update_info.cur_image_offset = fw_control->offset;
4612         flash_update_info.cur_image_len = fw_control->len;
4613         flash_update_info.total_image_len = fw_control->size;
4614         fw_control_context->fw_control = fw_control;
4615         fw_control_context->virtAddr = buffer;
4616         fw_control_context->len = fw_control->len;
4617         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4618         if (rc) {
4619                 kfree(fw_control_context);
4620                 return rc;
4621         }
4622         ccb = &pm8001_ha->ccb_info[tag];
4623         ccb->fw_control_context = fw_control_context;
4624         ccb->ccb_tag = tag;
4625         rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4626                 tag);
4627         return rc;
4628 }
4629
4630 static int
4631 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4632         struct pm8001_device *pm8001_dev, u32 state)
4633 {
4634         struct set_dev_state_req payload;
4635         struct inbound_queue_table *circularQ;
4636         struct pm8001_ccb_info *ccb;
4637         int rc;
4638         u32 tag;
4639         u32 opc = OPC_INB_SET_DEVICE_STATE;
4640         memset(&payload, 0, sizeof(payload));
4641         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4642         if (rc)
4643                 return -1;
4644         ccb = &pm8001_ha->ccb_info[tag];
4645         ccb->ccb_tag = tag;
4646         ccb->device = pm8001_dev;
4647         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4648         payload.tag = cpu_to_le32(tag);
4649         payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4650         payload.nds = cpu_to_le32(state);
4651         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4652         return rc;
4653
4654 }
4655
4656 static int
4657 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4658 {
4659         struct sas_re_initialization_req payload;
4660         struct inbound_queue_table *circularQ;
4661         struct pm8001_ccb_info *ccb;
4662         int rc;
4663         u32 tag;
4664         u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4665         memset(&payload, 0, sizeof(payload));
4666         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4667         if (rc)
4668                 return -1;
4669         ccb = &pm8001_ha->ccb_info[tag];
4670         ccb->ccb_tag = tag;
4671         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4672         payload.tag = cpu_to_le32(tag);
4673         payload.SSAHOLT = cpu_to_le32(0xd << 25);
4674         payload.sata_hol_tmo = cpu_to_le32(80);
4675         payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4676         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4677         return rc;
4678
4679 }
4680
4681 const struct pm8001_dispatch pm8001_8001_dispatch = {
4682         .name                   = "pmc8001",
4683         .chip_init              = pm8001_chip_init,
4684         .chip_soft_rst          = pm8001_chip_soft_rst,
4685         .chip_rst               = pm8001_hw_chip_rst,
4686         .chip_iounmap           = pm8001_chip_iounmap,
4687         .isr                    = pm8001_chip_isr,
4688         .is_our_interupt        = pm8001_chip_is_our_interupt,
4689         .isr_process_oq         = process_oq,
4690         .interrupt_enable       = pm8001_chip_interrupt_enable,
4691         .interrupt_disable      = pm8001_chip_interrupt_disable,
4692         .make_prd               = pm8001_chip_make_sg,
4693         .smp_req                = pm8001_chip_smp_req,
4694         .ssp_io_req             = pm8001_chip_ssp_io_req,
4695         .sata_req               = pm8001_chip_sata_req,
4696         .phy_start_req          = pm8001_chip_phy_start_req,
4697         .phy_stop_req           = pm8001_chip_phy_stop_req,
4698         .reg_dev_req            = pm8001_chip_reg_dev_req,
4699         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
4700         .phy_ctl_req            = pm8001_chip_phy_ctl_req,
4701         .task_abort             = pm8001_chip_abort_task,
4702         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
4703         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
4704         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
4705         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
4706         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
4707         .sas_re_init_req        = pm8001_chip_sas_re_initialization,
4708 };
4709