2 * Marvell 88SE64xx/88SE94xx pci init
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
8 * This file is licensed under GPLv2.
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
29 static int lldd_max_execute_num = 1;
30 module_param_named(collector, lldd_max_execute_num, int, S_IRUGO);
31 MODULE_PARM_DESC(collector, "\n"
32 "\tIf greater than one, tells the SAS Layer to run in Task Collector\n"
33 "\tMode. If 1 or 0, tells the SAS Layer to run in Direct Mode.\n"
34 "\tThe mvsas SAS LLDD supports both modes.\n"
35 "\tDefault: 1 (Direct Mode).\n");
37 static struct scsi_transport_template *mvs_stt;
38 struct kmem_cache *mvs_task_list_cache;
39 static const struct mvs_chip_info mvs_chips[] = {
40 [chip_6320] = { 1, 2, 0x400, 17, 16, 9, &mvs_64xx_dispatch, },
41 [chip_6440] = { 1, 4, 0x400, 17, 16, 9, &mvs_64xx_dispatch, },
42 [chip_6485] = { 1, 8, 0x800, 33, 32, 10, &mvs_64xx_dispatch, },
43 [chip_9180] = { 2, 4, 0x800, 17, 64, 9, &mvs_94xx_dispatch, },
44 [chip_9480] = { 2, 4, 0x800, 17, 64, 9, &mvs_94xx_dispatch, },
45 [chip_9445] = { 1, 4, 0x800, 17, 64, 11, &mvs_94xx_dispatch, },
46 [chip_9485] = { 2, 4, 0x800, 17, 64, 11, &mvs_94xx_dispatch, },
47 [chip_1300] = { 1, 4, 0x400, 17, 16, 9, &mvs_64xx_dispatch, },
48 [chip_1320] = { 2, 4, 0x800, 17, 64, 9, &mvs_94xx_dispatch, },
54 static struct scsi_host_template mvs_sht = {
55 .module = THIS_MODULE,
57 .queuecommand = sas_queuecommand,
58 .target_alloc = sas_target_alloc,
59 .slave_configure = mvs_slave_configure,
60 .slave_destroy = sas_slave_destroy,
61 .scan_finished = mvs_scan_finished,
62 .scan_start = mvs_scan_start,
63 .change_queue_depth = sas_change_queue_depth,
64 .change_queue_type = sas_change_queue_type,
65 .bios_param = sas_bios_param,
69 .sg_tablesize = SG_MX,
70 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
71 .use_clustering = ENABLE_CLUSTERING,
72 .eh_device_reset_handler = sas_eh_device_reset_handler,
73 .eh_bus_reset_handler = sas_eh_bus_reset_handler,
74 .slave_alloc = mvs_slave_alloc,
75 .target_destroy = sas_target_destroy,
79 static struct sas_domain_function_template mvs_transport_ops = {
80 .lldd_dev_found = mvs_dev_found,
81 .lldd_dev_gone = mvs_dev_gone,
82 .lldd_execute_task = mvs_queue_command,
83 .lldd_control_phy = mvs_phy_control,
85 .lldd_abort_task = mvs_abort_task,
86 .lldd_abort_task_set = mvs_abort_task_set,
87 .lldd_clear_aca = mvs_clear_aca,
88 .lldd_clear_task_set = mvs_clear_task_set,
89 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset,
90 .lldd_lu_reset = mvs_lu_reset,
91 .lldd_query_task = mvs_query_task,
92 .lldd_port_formed = mvs_port_formed,
93 .lldd_port_deformed = mvs_port_deformed,
97 static void __devinit mvs_phy_init(struct mvs_info *mvi, int phy_id)
99 struct mvs_phy *phy = &mvi->phy[phy_id];
100 struct asd_sas_phy *sas_phy = &phy->sas_phy;
103 init_timer(&phy->timer);
104 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
105 sas_phy->class = SAS;
106 sas_phy->iproto = SAS_PROTOCOL_ALL;
108 sas_phy->type = PHY_TYPE_PHYSICAL;
109 sas_phy->role = PHY_ROLE_INITIATOR;
110 sas_phy->oob_mode = OOB_NOT_CONNECTED;
111 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
113 sas_phy->id = phy_id;
114 sas_phy->sas_addr = &mvi->sas_addr[0];
115 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
116 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
117 sas_phy->lldd_phy = phy;
120 static void mvs_free(struct mvs_info *mvi)
128 if (mvi->flags & MVF_FLAG_SOC)
129 slot_nr = MVS_SOC_SLOTS;
134 pci_pool_destroy(mvi->dma_pool);
137 dma_free_coherent(mvi->dev,
138 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
139 mvi->tx, mvi->tx_dma);
141 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
142 mvi->rx_fis, mvi->rx_fis_dma);
144 dma_free_coherent(mvi->dev,
145 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
146 mvi->rx, mvi->rx_dma);
148 dma_free_coherent(mvi->dev,
149 sizeof(*mvi->slot) * slot_nr,
150 mvi->slot, mvi->slot_dma);
151 #ifndef DISABLE_HOTPLUG_DMA_FIX
152 if (mvi->bulk_buffer)
153 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
154 mvi->bulk_buffer, mvi->bulk_buffer_dma);
157 MVS_CHIP_DISP->chip_iounmap(mvi);
159 scsi_host_put(mvi->shost);
160 list_for_each_entry(mwq, &mvi->wq_list, entry)
161 cancel_delayed_work(&mwq->work_q);
165 #ifdef MVS_USE_TASKLET
166 struct tasklet_struct mv_tasklet;
167 static void mvs_tasklet(unsigned long opaque)
173 struct mvs_info *mvi;
174 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
176 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
177 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
182 for (i = 0; i < core_nr; i++) {
183 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
184 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->irq);
186 MVS_CHIP_DISP->isr(mvi, mvi->irq, stat);
192 static irqreturn_t mvs_interrupt(int irq, void *opaque)
196 struct mvs_info *mvi;
197 struct sas_ha_struct *sha = opaque;
199 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
200 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
205 stat = MVS_CHIP_DISP->isr_status(mvi, irq);
209 #ifdef MVS_USE_TASKLET
210 tasklet_schedule(&mv_tasklet);
212 for (i = 0; i < core_nr; i++) {
213 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
214 MVS_CHIP_DISP->isr(mvi, irq, stat);
220 static int __devinit mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
225 if (mvi->flags & MVF_FLAG_SOC)
226 slot_nr = MVS_SOC_SLOTS;
230 spin_lock_init(&mvi->lock);
231 for (i = 0; i < mvi->chip->n_phy; i++) {
232 mvs_phy_init(mvi, i);
233 mvi->port[i].wide_port_phymap = 0;
234 mvi->port[i].port_attached = 0;
235 INIT_LIST_HEAD(&mvi->port[i].list);
237 for (i = 0; i < MVS_MAX_DEVICES; i++) {
238 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
239 mvi->devices[i].dev_type = NO_DEVICE;
240 mvi->devices[i].device_id = i;
241 mvi->devices[i].dev_status = MVS_DEV_NORMAL;
242 init_timer(&mvi->devices[i].timer);
246 * alloc and init our DMA areas
248 mvi->tx = dma_alloc_coherent(mvi->dev,
249 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
250 &mvi->tx_dma, GFP_KERNEL);
253 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
254 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
255 &mvi->rx_fis_dma, GFP_KERNEL);
258 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
260 mvi->rx = dma_alloc_coherent(mvi->dev,
261 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
262 &mvi->rx_dma, GFP_KERNEL);
265 memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
266 mvi->rx[0] = cpu_to_le32(0xfff);
267 mvi->rx_cons = 0xfff;
269 mvi->slot = dma_alloc_coherent(mvi->dev,
270 sizeof(*mvi->slot) * slot_nr,
271 &mvi->slot_dma, GFP_KERNEL);
274 memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr);
276 #ifndef DISABLE_HOTPLUG_DMA_FIX
277 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
279 &mvi->bulk_buffer_dma, GFP_KERNEL);
280 if (!mvi->bulk_buffer)
283 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);
284 mvi->dma_pool = pci_pool_create(pool_name, mvi->pdev, MVS_SLOT_BUF_SZ, 16, 0);
285 if (!mvi->dma_pool) {
286 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);
289 mvi->tags_num = slot_nr;
291 /* Initialize tags */
299 int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
301 unsigned long res_start, res_len, res_flag, res_flag_ex = 0;
302 struct pci_dev *pdev = mvi->pdev;
305 * ioremap main and peripheral registers
307 res_start = pci_resource_start(pdev, bar_ex);
308 res_len = pci_resource_len(pdev, bar_ex);
309 if (!res_start || !res_len)
312 res_flag_ex = pci_resource_flags(pdev, bar_ex);
313 if (res_flag_ex & IORESOURCE_MEM) {
314 if (res_flag_ex & IORESOURCE_CACHEABLE)
315 mvi->regs_ex = ioremap(res_start, res_len);
317 mvi->regs_ex = ioremap_nocache(res_start,
320 mvi->regs_ex = (void *)res_start;
325 res_start = pci_resource_start(pdev, bar);
326 res_len = pci_resource_len(pdev, bar);
327 if (!res_start || !res_len)
330 res_flag = pci_resource_flags(pdev, bar);
331 if (res_flag & IORESOURCE_CACHEABLE)
332 mvi->regs = ioremap(res_start, res_len);
334 mvi->regs = ioremap_nocache(res_start, res_len);
337 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
338 iounmap(mvi->regs_ex);
348 void mvs_iounmap(void __iomem *regs)
353 static struct mvs_info *__devinit mvs_pci_alloc(struct pci_dev *pdev,
354 const struct pci_device_id *ent,
355 struct Scsi_Host *shost, unsigned int id)
357 struct mvs_info *mvi;
358 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
360 mvi = kzalloc(sizeof(*mvi) + MVS_SLOTS * sizeof(struct mvs_slot_info),
366 mvi->dev = &pdev->dev;
367 mvi->chip_id = ent->driver_data;
368 mvi->chip = &mvs_chips[mvi->chip_id];
369 INIT_LIST_HEAD(&mvi->wq_list);
370 mvi->irq = pdev->irq;
372 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
373 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
378 #ifdef MVS_USE_TASKLET
379 tasklet_init(&mv_tasklet, mvs_tasklet, (unsigned long)sha);
382 if (MVS_CHIP_DISP->chip_ioremap(mvi))
384 if (!mvs_alloc(mvi, shost))
391 /* move to PCI layer or libata core? */
392 static int pci_go_64(struct pci_dev *pdev)
396 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
397 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
399 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
401 dev_printk(KERN_ERR, &pdev->dev,
402 "64-bit DMA enable failed\n");
407 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
409 dev_printk(KERN_ERR, &pdev->dev,
410 "32-bit DMA enable failed\n");
413 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
415 dev_printk(KERN_ERR, &pdev->dev,
416 "32-bit consistent DMA enable failed\n");
424 static int __devinit mvs_prep_sas_ha_init(struct Scsi_Host *shost,
425 const struct mvs_chip_info *chip_info)
427 int phy_nr, port_nr; unsigned short core_nr;
428 struct asd_sas_phy **arr_phy;
429 struct asd_sas_port **arr_port;
430 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
432 core_nr = chip_info->n_host;
433 phy_nr = core_nr * chip_info->n_phy;
436 memset(sha, 0x00, sizeof(struct sas_ha_struct));
437 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
438 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
439 if (!arr_phy || !arr_port)
442 sha->sas_phy = arr_phy;
443 sha->sas_port = arr_port;
444 sha->core.shost = shost;
446 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
450 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
452 shost->transportt = mvs_stt;
455 shost->max_channel = 1;
456 shost->max_cmd_len = 16;
466 static void __devinit mvs_post_sas_ha_init(struct Scsi_Host *shost,
467 const struct mvs_chip_info *chip_info)
469 int can_queue, i = 0, j = 0;
470 struct mvs_info *mvi = NULL;
471 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
472 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
474 for (j = 0; j < nr_core; j++) {
475 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
476 for (i = 0; i < chip_info->n_phy; i++) {
477 sha->sas_phy[j * chip_info->n_phy + i] =
478 &mvi->phy[i].sas_phy;
479 sha->sas_port[j * chip_info->n_phy + i] =
480 &mvi->port[i].sas_port;
484 sha->sas_ha_name = DRV_NAME;
486 sha->lldd_module = THIS_MODULE;
487 sha->sas_addr = &mvi->sas_addr[0];
489 sha->num_phys = nr_core * chip_info->n_phy;
491 sha->lldd_max_execute_num = lldd_max_execute_num;
493 if (mvi->flags & MVF_FLAG_SOC)
494 can_queue = MVS_SOC_CAN_QUEUE;
496 can_queue = MVS_CAN_QUEUE;
498 sha->lldd_queue_size = can_queue;
499 shost->can_queue = can_queue;
500 mvi->shost->cmd_per_lun = MVS_SLOTS/sha->num_phys;
501 sha->core.shost = mvi->shost;
504 static void mvs_init_sas_add(struct mvs_info *mvi)
507 for (i = 0; i < mvi->chip->n_phy; i++) {
508 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
509 mvi->phy[i].dev_sas_addr =
510 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
513 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
516 static int __devinit mvs_pci_init(struct pci_dev *pdev,
517 const struct pci_device_id *ent)
519 unsigned int rc, nhost = 0;
520 struct mvs_info *mvi;
521 irq_handler_t irq_handler = mvs_interrupt;
522 struct Scsi_Host *shost = NULL;
523 const struct mvs_chip_info *chip;
525 dev_printk(KERN_INFO, &pdev->dev,
526 "mvsas: driver version %s\n", DRV_VERSION);
527 rc = pci_enable_device(pdev);
531 pci_set_master(pdev);
533 rc = pci_request_regions(pdev, DRV_NAME);
535 goto err_out_disable;
537 rc = pci_go_64(pdev);
539 goto err_out_regions;
541 shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
544 goto err_out_regions;
547 chip = &mvs_chips[ent->driver_data];
548 SHOST_TO_SAS_HA(shost) =
549 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
550 if (!SHOST_TO_SAS_HA(shost)) {
553 goto err_out_regions;
556 rc = mvs_prep_sas_ha_init(shost, chip);
560 goto err_out_regions;
563 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
566 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
569 goto err_out_regions;
572 mvs_init_sas_add(mvi);
574 mvi->instance = nhost;
575 rc = MVS_CHIP_DISP->chip_init(mvi);
578 goto err_out_regions;
581 } while (nhost < chip->n_host);
582 #ifdef MVS_USE_TASKLET
583 tasklet_init(&mv_tasklet, mvs_tasklet,
584 (unsigned long)SHOST_TO_SAS_HA(shost));
587 mvs_post_sas_ha_init(shost, chip);
589 rc = scsi_add_host(shost, &pdev->dev);
593 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
596 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
597 DRV_NAME, SHOST_TO_SAS_HA(shost));
601 MVS_CHIP_DISP->interrupt_enable(mvi);
603 scsi_scan_host(mvi->shost);
608 sas_unregister_ha(SHOST_TO_SAS_HA(shost));
610 scsi_remove_host(mvi->shost);
612 pci_release_regions(pdev);
614 pci_disable_device(pdev);
619 static void __devexit mvs_pci_remove(struct pci_dev *pdev)
621 unsigned short core_nr, i = 0;
622 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
623 struct mvs_info *mvi = NULL;
625 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
626 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
628 #ifdef MVS_USE_TASKLET
629 tasklet_kill(&mv_tasklet);
632 pci_set_drvdata(pdev, NULL);
633 sas_unregister_ha(sha);
634 sas_remove_host(mvi->shost);
635 scsi_remove_host(mvi->shost);
637 MVS_CHIP_DISP->interrupt_disable(mvi);
638 free_irq(mvi->irq, sha);
639 for (i = 0; i < core_nr; i++) {
640 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
644 kfree(sha->sas_port);
646 pci_release_regions(pdev);
647 pci_disable_device(pdev);
651 static struct pci_device_id __devinitdata mvs_pci_table[] = {
652 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
653 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
655 .vendor = PCI_VENDOR_ID_MARVELL,
657 .subvendor = PCI_ANY_ID,
661 .driver_data = chip_6485,
663 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
664 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
665 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
666 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
667 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },
668 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },
669 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },
670 { PCI_VDEVICE(TTI, 0x2710), chip_9480 },
671 { PCI_VDEVICE(TTI, 0x2720), chip_9480 },
672 { PCI_VDEVICE(TTI, 0x2721), chip_9480 },
673 { PCI_VDEVICE(TTI, 0x2722), chip_9480 },
674 { PCI_VDEVICE(TTI, 0x2740), chip_9480 },
675 { PCI_VDEVICE(TTI, 0x2744), chip_9480 },
676 { PCI_VDEVICE(TTI, 0x2760), chip_9480 },
680 .subvendor = PCI_ANY_ID,
684 .driver_data = chip_9445,
689 .subvendor = PCI_ANY_ID,
693 .driver_data = chip_9485,
696 { } /* terminate list */
699 static struct pci_driver mvs_pci_driver = {
701 .id_table = mvs_pci_table,
702 .probe = mvs_pci_init,
703 .remove = __devexit_p(mvs_pci_remove),
707 struct task_struct *mvs_th;
708 static int __init mvs_init(void)
711 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
715 mvs_task_list_cache = kmem_cache_create("mvs_task_list", sizeof(struct mvs_task_list),
716 0, SLAB_HWCACHE_ALIGN, NULL);
717 if (!mvs_task_list_cache) {
719 mv_printk("%s: mvs_task_list_cache alloc failed! \n", __func__);
723 rc = pci_register_driver(&mvs_pci_driver);
731 sas_release_transport(mvs_stt);
735 static void __exit mvs_exit(void)
737 pci_unregister_driver(&mvs_pci_driver);
738 sas_release_transport(mvs_stt);
739 kmem_cache_destroy(mvs_task_list_cache);
742 module_init(mvs_init);
743 module_exit(mvs_exit);
745 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
746 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
747 MODULE_VERSION(DRV_VERSION);
748 MODULE_LICENSE("GPL");
750 MODULE_DEVICE_TABLE(pci, mvs_pci_table);