2 * Marvell 88SE64xx/88SE94xx register IO interface
4 * Copyright 2007 Red Hat, Inc.
5 * Copyright 2008 Marvell. <kewei@marvell.com>
6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
8 * This file is licensed under GPLv2.
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; version 2 of the
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
30 #define mr32(reg) readl(regs + reg)
31 #define mw32(reg, val) writel((val), regs + reg)
32 #define mw32_f(reg, val) do { \
37 #define iow32(reg, val) outl(val, (unsigned long)(regs + reg))
38 #define ior32(reg) inl((unsigned long)(regs + reg))
39 #define iow16(reg, val) outw((unsigned long)(val, regs + reg))
40 #define ior16(reg) inw((unsigned long)(regs + reg))
41 #define iow8(reg, val) outb((unsigned long)(val, regs + reg))
42 #define ior8(reg) inb((unsigned long)(regs + reg))
44 static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr)
46 void __iomem *regs = mvi->regs;
47 mw32(MVS_CMD_ADDR, addr);
48 return mr32(MVS_CMD_DATA);
51 static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val)
53 void __iomem *regs = mvi->regs;
54 mw32(MVS_CMD_ADDR, addr);
55 mw32(MVS_CMD_DATA, val);
58 static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
60 void __iomem *regs = mvi->regs;
61 return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) :
62 mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4);
65 static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
67 void __iomem *regs = mvi->regs;
69 mw32(MVS_P0_SER_CTLSTAT + port * 4, val);
71 mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val);
74 static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off,
77 void __iomem *regs = mvi->regs + off;
78 void __iomem *regs2 = mvi->regs + off2;
79 return (port < 4) ? readl(regs + port * 8) :
80 readl(regs2 + (port - 4) * 8);
83 static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
86 void __iomem *regs = mvi->regs + off;
87 void __iomem *regs2 = mvi->regs + off2;
89 writel(val, regs + port * 8);
91 writel(val, regs2 + (port - 4) * 8);
94 static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
96 return mvs_read_port(mvi, MVS_P0_CFG_DATA,
97 MVS_P4_CFG_DATA, port);
100 static inline void mvs_write_port_cfg_data(struct mvs_info *mvi,
103 mvs_write_port(mvi, MVS_P0_CFG_DATA,
104 MVS_P4_CFG_DATA, port, val);
107 static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi,
110 mvs_write_port(mvi, MVS_P0_CFG_ADDR,
111 MVS_P4_CFG_ADDR, port, addr);
115 static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
117 return mvs_read_port(mvi, MVS_P0_VSR_DATA,
118 MVS_P4_VSR_DATA, port);
121 static inline void mvs_write_port_vsr_data(struct mvs_info *mvi,
124 mvs_write_port(mvi, MVS_P0_VSR_DATA,
125 MVS_P4_VSR_DATA, port, val);
128 static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi,
131 mvs_write_port(mvi, MVS_P0_VSR_ADDR,
132 MVS_P4_VSR_ADDR, port, addr);
136 static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
138 return mvs_read_port(mvi, MVS_P0_INT_STAT,
139 MVS_P4_INT_STAT, port);
142 static inline void mvs_write_port_irq_stat(struct mvs_info *mvi,
145 mvs_write_port(mvi, MVS_P0_INT_STAT,
146 MVS_P4_INT_STAT, port, val);
149 static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
151 return mvs_read_port(mvi, MVS_P0_INT_MASK,
152 MVS_P4_INT_MASK, port);
156 static inline void mvs_write_port_irq_mask(struct mvs_info *mvi,
159 mvs_write_port(mvi, MVS_P0_INT_MASK,
160 MVS_P4_INT_MASK, port, val);
163 static inline void __devinit mvs_phy_hacks(struct mvs_info *mvi)
167 /* workaround for SATA R-ERR, to ignore phy glitch */
168 tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
171 mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
173 /* enable retry 127 times */
174 mvs_cw32(mvi, CMD_SAS_CTL1, 0x7f7f);
176 /* extend open frame timeout to max */
177 tmp = mvs_cr32(mvi, CMD_SAS_CTL0);
180 mvs_cw32(mvi, CMD_SAS_CTL0, tmp);
182 /* workaround for WDTIMEOUT , set to 550 ms */
183 mvs_cw32(mvi, CMD_WD_TIMER, 0x7a0000);
185 /* not to halt for different port op during wideport link change */
186 mvs_cw32(mvi, CMD_APP_ERR_CONFIG, 0xffefbf7d);
188 /* workaround for Seagate disk not-found OOB sequence, recv
189 * COMINIT before sending out COMWAKE */
190 tmp = mvs_cr32(mvi, CMD_PHY_MODE_21);
193 mvs_cw32(mvi, CMD_PHY_MODE_21, tmp);
195 tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
197 tmp |= (2U << 29); /* 8 ms retry */
198 mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
201 static inline void mvs_int_sata(struct mvs_info *mvi)
204 void __iomem *regs = mvi->regs;
205 tmp = mr32(MVS_INT_STAT_SRS_0);
207 mw32(MVS_INT_STAT_SRS_0, tmp);
208 MVS_CHIP_DISP->clear_active_cmds(mvi);
211 static inline void mvs_int_full(struct mvs_info *mvi)
213 void __iomem *regs = mvi->regs;
217 stat = mr32(MVS_INT_STAT);
218 mvs_int_rx(mvi, false);
220 for (i = 0; i < mvi->chip->n_phy; i++) {
221 tmp = (stat >> i) & (CINT_PORT | CINT_PORT_STOPPED);
223 mvs_int_port(mvi, i, tmp);
229 mw32(MVS_INT_STAT, stat);
232 static inline void mvs_start_delivery(struct mvs_info *mvi, u32 tx)
234 void __iomem *regs = mvi->regs;
235 mw32(MVS_TX_PROD_IDX, tx);
238 static inline u32 mvs_rx_update(struct mvs_info *mvi)
240 void __iomem *regs = mvi->regs;
241 return mr32(MVS_RX_CONS_IDX);
244 static inline u32 mvs_get_prd_size(void)
246 return sizeof(struct mvs_prd);
249 static inline u32 mvs_get_prd_count(void)
254 static inline void mvs_show_pcie_usage(struct mvs_info *mvi)
256 u16 link_stat, link_spd;
257 const char *spd[] = {
262 if (mvi->flags & MVF_FLAG_SOC || mvi->id > 0)
265 pci_read_config_word(mvi->pdev, PCR_LINK_STAT, &link_stat);
266 link_spd = (link_stat & PLS_LINK_SPD) >> PLS_LINK_SPD_OFFS;
269 dev_printk(KERN_INFO, mvi->dev,
270 "mvsas: PCI-E x%u, Bandwidth Usage: %s Gbps\n",
271 (link_stat & PLS_NEG_LINK_WD) >> PLS_NEG_LINK_WD_OFFS,
275 static inline u32 mvs_hw_max_link_rate(void)
277 return MAX_LINK_RATE;
280 #endif /* _MV_CHIPS_H_ */