drivers/scsi/lpfc/lpfc_hw4.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2009 Emulex.  All rights reserved.                *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *******************************************************************/
  20
  21 /* Macros to deal with bit fields. Each bit field must have 3 #defines
  22  * associated with it (_SHIFT, _MASK, and _WORD).
  23  * EG. For a bit field that is in the 7th bit of the "field4" field of a
  24  * structure and is 2 bits in size the following #defines must exist:
  25  *      struct temp {
  26  *              uint32_t        field1;
  27  *              uint32_t        field2;
  28  *              uint32_t        field3;
  29  *              uint32_t        field4;
  30  *      #define example_bit_field_SHIFT         7
  31  *      #define example_bit_field_MASK          0x03
  32  *      #define example_bit_field_WORD          field4
  33  *              uint32_t        field5;
  34  *      };
  35  * Then the macros below may be used to get or set the value of that field.
  36  * EG. To get the value of the bit field from the above example:
  37  *      struct temp t1;
  38  *      value = bf_get(example_bit_field, &t1);
  39  * And then to set that bit field:
  40  *      bf_set(example_bit_field, &t1, 2);
  41  * Or clear that bit field:
  42  *      bf_set(example_bit_field, &t1, 0);
  43  */
  44 #define bf_get(name, ptr) \
  45         (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
  46 #define bf_set(name, ptr, value) \
  47         ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
  48                  ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
  49
  50 struct dma_address {
  51         uint32_t addr_lo;
  52         uint32_t addr_hi;
  53 };
  54
  55 struct lpfc_sli_intf {
  56         uint32_t word0;
  57 #define lpfc_sli_intf_valid_SHIFT               29
  58 #define lpfc_sli_intf_valid_MASK                0x00000007
  59 #define lpfc_sli_intf_valid_WORD                word0
  60 #define LPFC_SLI_INTF_VALID             6
  61 #define lpfc_sli_intf_featurelevel2_SHIFT       24
  62 #define lpfc_sli_intf_featurelevel2_MASK        0x0000001F
  63 #define lpfc_sli_intf_featurelevel2_WORD        word0
  64 #define lpfc_sli_intf_featurelevel1_SHIFT       16
  65 #define lpfc_sli_intf_featurelevel1_MASK        0x000000FF
  66 #define lpfc_sli_intf_featurelevel1_WORD        word0
  67 #define LPFC_SLI_INTF_FEATURELEVEL1_1   1
  68 #define LPFC_SLI_INTF_FEATURELEVEL1_2   2
  69 #define lpfc_sli_intf_sli_family_SHIFT          8
  70 #define lpfc_sli_intf_sli_family_MASK           0x000000FF
  71 #define lpfc_sli_intf_sli_family_WORD           word0
  72 #define LPFC_SLI_INTF_FAMILY_BE2        0
  73 #define LPFC_SLI_INTF_FAMILY_BE3        1
  74 #define lpfc_sli_intf_slirev_SHIFT              4
  75 #define lpfc_sli_intf_slirev_MASK               0x0000000F
  76 #define lpfc_sli_intf_slirev_WORD               word0
  77 #define LPFC_SLI_INTF_REV_SLI3          3
  78 #define LPFC_SLI_INTF_REV_SLI4          4
  79 #define lpfc_sli_intf_if_type_SHIFT             0
  80 #define lpfc_sli_intf_if_type_MASK              0x00000007
  81 #define lpfc_sli_intf_if_type_WORD              word0
  82 #define LPFC_SLI_INTF_IF_TYPE_0         0
  83 #define LPFC_SLI_INTF_IF_TYPE_1         1
  84 };
  85
  86 #define LPFC_SLI4_MBX_EMBED     true
  87 #define LPFC_SLI4_MBX_NEMBED    false
  88
  89 #define LPFC_SLI4_MB_WORD_COUNT         64
  90 #define LPFC_MAX_MQ_PAGE                8
  91 #define LPFC_MAX_WQ_PAGE                8
  92 #define LPFC_MAX_CQ_PAGE                4
  93 #define LPFC_MAX_EQ_PAGE                8
  94
  95 #define LPFC_VIR_FUNC_MAX       32 /* Maximum number of virtual functions */
  96 #define LPFC_PCI_FUNC_MAX        5 /* Maximum number of PCI functions */
  97 #define LPFC_VFR_PAGE_SIZE      0x1000 /* 4KB BAR2 per-VF register page size */
  98
  99 /* Define SLI4 Alignment requirements. */
 100 #define LPFC_ALIGN_16_BYTE      16
 101 #define LPFC_ALIGN_64_BYTE      64
 102
 103 /* Define SLI4 specific definitions. */
 104 #define LPFC_MQ_CQE_BYTE_OFFSET 256
 105 #define LPFC_MBX_CMD_HDR_LENGTH 16
 106 #define LPFC_MBX_ERROR_RANGE    0x4000
 107 #define LPFC_BMBX_BIT1_ADDR_HI  0x2
 108 #define LPFC_BMBX_BIT1_ADDR_LO  0
 109 #define LPFC_RPI_HDR_COUNT      64
 110 #define LPFC_HDR_TEMPLATE_SIZE  4096
 111 #define LPFC_RPI_ALLOC_ERROR    0xFFFF
 112 #define LPFC_FCF_RECORD_WD_CNT  132
 113 #define LPFC_ENTIRE_FCF_DATABASE 0
 114 #define LPFC_DFLT_FCF_INDEX      0
 115
 116 /* Virtual function numbers */
 117 #define LPFC_VF0                0
 118 #define LPFC_VF1                1
 119 #define LPFC_VF2                2
 120 #define LPFC_VF3                3
 121 #define LPFC_VF4                4
 122 #define LPFC_VF5                5
 123 #define LPFC_VF6                6
 124 #define LPFC_VF7                7
 125 #define LPFC_VF8                8
 126 #define LPFC_VF9                9
 127 #define LPFC_VF10               10
 128 #define LPFC_VF11               11
 129 #define LPFC_VF12               12
 130 #define LPFC_VF13               13
 131 #define LPFC_VF14               14
 132 #define LPFC_VF15               15
 133 #define LPFC_VF16               16
 134 #define LPFC_VF17               17
 135 #define LPFC_VF18               18
 136 #define LPFC_VF19               19
 137 #define LPFC_VF20               20
 138 #define LPFC_VF21               21
 139 #define LPFC_VF22               22
 140 #define LPFC_VF23               23
 141 #define LPFC_VF24               24
 142 #define LPFC_VF25               25
 143 #define LPFC_VF26               26
 144 #define LPFC_VF27               27
 145 #define LPFC_VF28               28
 146 #define LPFC_VF29               29
 147 #define LPFC_VF30               30
 148 #define LPFC_VF31               31
 149
 150 /* PCI function numbers */
 151 #define LPFC_PCI_FUNC0          0
 152 #define LPFC_PCI_FUNC1          1
 153 #define LPFC_PCI_FUNC2          2
 154 #define LPFC_PCI_FUNC3          3
 155 #define LPFC_PCI_FUNC4          4
 156
 157 /* Active interrupt test count */
 158 #define LPFC_ACT_INTR_CNT       4
 159
 160 /* Delay Multiplier constant */
 161 #define LPFC_DMULT_CONST       651042
 162 #define LPFC_MIM_IMAX          636
 163 #define LPFC_FP_DEF_IMAX       10000
 164 #define LPFC_SP_DEF_IMAX       10000
 165
 166 /* PORT_CAPABILITIES constants. */
 167 #define LPFC_MAX_SUPPORTED_PAGES        8
 168
 169 struct ulp_bde64 {
 170         union ULP_BDE_TUS {
 171                 uint32_t w;
 172                 struct {
 173 #ifdef __BIG_ENDIAN_BITFIELD
 174                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 175                                                    VALUE !! */
 176                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 177 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 178                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 179                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 180                                                    VALUE !! */
 181 #endif
 182 #define BUFF_TYPE_BDE_64    0x00        /* BDE (Host_resident) */
 183 #define BUFF_TYPE_BDE_IMMED 0x01        /* Immediate Data BDE */
 184 #define BUFF_TYPE_BDE_64P   0x02        /* BDE (Port-resident) */
 185 #define BUFF_TYPE_BDE_64I   0x08        /* Input BDE (Host-resident) */
 186 #define BUFF_TYPE_BDE_64IP  0x0A        /* Input BDE (Port-resident) */
 187 #define BUFF_TYPE_BLP_64    0x40        /* BLP (Host-resident) */
 188 #define BUFF_TYPE_BLP_64P   0x42        /* BLP (Port-resident) */
 189                 } f;
 190         } tus;
 191         uint32_t addrLow;
 192         uint32_t addrHigh;
 193 };
 194
 195 struct lpfc_sli4_flags {
 196         uint32_t word0;
 197 #define lpfc_fip_flag_SHIFT 0
 198 #define lpfc_fip_flag_MASK 0x00000001
 199 #define lpfc_fip_flag_WORD word0
 200 };
 201
 202 struct sli4_bls_acc {
 203         uint32_t word0_rsvd;      /* Word0 must be reserved */
 204         uint32_t word1;
 205 #define lpfc_abts_orig_SHIFT      0
 206 #define lpfc_abts_orig_MASK       0x00000001
 207 #define lpfc_abts_orig_WORD       word1
 208 #define LPFC_ABTS_UNSOL_RSP       1
 209 #define LPFC_ABTS_UNSOL_INT       0
 210         uint32_t word2;
 211 #define lpfc_abts_rxid_SHIFT      0
 212 #define lpfc_abts_rxid_MASK       0x0000FFFF
 213 #define lpfc_abts_rxid_WORD       word2
 214 #define lpfc_abts_oxid_SHIFT      16
 215 #define lpfc_abts_oxid_MASK       0x0000FFFF
 216 #define lpfc_abts_oxid_WORD       word2
 217         uint32_t word3;
 218         uint32_t word4;
 219         uint32_t word5_rsvd;    /* Word5 must be reserved */
 220 };
 221
 222 /* event queue entry structure */
 223 struct lpfc_eqe {
 224         uint32_t word0;
 225 #define lpfc_eqe_resource_id_SHIFT      16
 226 #define lpfc_eqe_resource_id_MASK       0x000000FF
 227 #define lpfc_eqe_resource_id_WORD       word0
 228 #define lpfc_eqe_minor_code_SHIFT       4
 229 #define lpfc_eqe_minor_code_MASK        0x00000FFF
 230 #define lpfc_eqe_minor_code_WORD        word0
 231 #define lpfc_eqe_major_code_SHIFT       1
 232 #define lpfc_eqe_major_code_MASK        0x00000007
 233 #define lpfc_eqe_major_code_WORD        word0
 234 #define lpfc_eqe_valid_SHIFT            0
 235 #define lpfc_eqe_valid_MASK             0x00000001
 236 #define lpfc_eqe_valid_WORD             word0
 237 };
 238
 239 /* completion queue entry structure (common fields for all cqe types) */
 240 struct lpfc_cqe {
 241         uint32_t reserved0;
 242         uint32_t reserved1;
 243         uint32_t reserved2;
 244         uint32_t word3;
 245 #define lpfc_cqe_valid_SHIFT            31
 246 #define lpfc_cqe_valid_MASK             0x00000001
 247 #define lpfc_cqe_valid_WORD             word3
 248 #define lpfc_cqe_code_SHIFT             16
 249 #define lpfc_cqe_code_MASK              0x000000FF
 250 #define lpfc_cqe_code_WORD              word3
 251 };
 252
 253 /* Completion Queue Entry Status Codes */
 254 #define CQE_STATUS_SUCCESS              0x0
 255 #define CQE_STATUS_FCP_RSP_FAILURE      0x1
 256 #define CQE_STATUS_REMOTE_STOP          0x2
 257 #define CQE_STATUS_LOCAL_REJECT         0x3
 258 #define CQE_STATUS_NPORT_RJT            0x4
 259 #define CQE_STATUS_FABRIC_RJT           0x5
 260 #define CQE_STATUS_NPORT_BSY            0x6
 261 #define CQE_STATUS_FABRIC_BSY           0x7
 262 #define CQE_STATUS_INTERMED_RSP         0x8
 263 #define CQE_STATUS_LS_RJT               0x9
 264 #define CQE_STATUS_CMD_REJECT           0xb
 265 #define CQE_STATUS_FCP_TGT_LENCHECK     0xc
 266 #define CQE_STATUS_NEED_BUFF_ENTRY      0xf
 267
 268 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
 269 #define CQE_HW_STATUS_NO_ERR            0x0
 270 #define CQE_HW_STATUS_UNDERRUN          0x1
 271 #define CQE_HW_STATUS_OVERRUN           0x2
 272
 273 /* Completion Queue Entry Codes */
 274 #define CQE_CODE_COMPL_WQE              0x1
 275 #define CQE_CODE_RELEASE_WQE            0x2
 276 #define CQE_CODE_RECEIVE                0x4
 277 #define CQE_CODE_XRI_ABORTED            0x5
 278
 279 /* completion queue entry for wqe completions */
 280 struct lpfc_wcqe_complete {
 281         uint32_t word0;
 282 #define lpfc_wcqe_c_request_tag_SHIFT   16
 283 #define lpfc_wcqe_c_request_tag_MASK    0x0000FFFF
 284 #define lpfc_wcqe_c_request_tag_WORD    word0
 285 #define lpfc_wcqe_c_status_SHIFT        8
 286 #define lpfc_wcqe_c_status_MASK         0x000000FF
 287 #define lpfc_wcqe_c_status_WORD         word0
 288 #define lpfc_wcqe_c_hw_status_SHIFT     0
 289 #define lpfc_wcqe_c_hw_status_MASK      0x000000FF
 290 #define lpfc_wcqe_c_hw_status_WORD      word0
 291         uint32_t total_data_placed;
 292         uint32_t parameter;
 293         uint32_t word3;
 294 #define lpfc_wcqe_c_valid_SHIFT         lpfc_cqe_valid_SHIFT
 295 #define lpfc_wcqe_c_valid_MASK          lpfc_cqe_valid_MASK
 296 #define lpfc_wcqe_c_valid_WORD          lpfc_cqe_valid_WORD
 297 #define lpfc_wcqe_c_xb_SHIFT            28
 298 #define lpfc_wcqe_c_xb_MASK             0x00000001
 299 #define lpfc_wcqe_c_xb_WORD             word3
 300 #define lpfc_wcqe_c_pv_SHIFT            27
 301 #define lpfc_wcqe_c_pv_MASK             0x00000001
 302 #define lpfc_wcqe_c_pv_WORD             word3
 303 #define lpfc_wcqe_c_priority_SHIFT      24
 304 #define lpfc_wcqe_c_priority_MASK               0x00000007
 305 #define lpfc_wcqe_c_priority_WORD               word3
 306 #define lpfc_wcqe_c_code_SHIFT          lpfc_cqe_code_SHIFT
 307 #define lpfc_wcqe_c_code_MASK           lpfc_cqe_code_MASK
 308 #define lpfc_wcqe_c_code_WORD           lpfc_cqe_code_WORD
 309 };
 310
 311 /* completion queue entry for wqe release */
 312 struct lpfc_wcqe_release {
 313         uint32_t reserved0;
 314         uint32_t reserved1;
 315         uint32_t word2;
 316 #define lpfc_wcqe_r_wq_id_SHIFT         16
 317 #define lpfc_wcqe_r_wq_id_MASK          0x0000FFFF
 318 #define lpfc_wcqe_r_wq_id_WORD          word2
 319 #define lpfc_wcqe_r_wqe_index_SHIFT     0
 320 #define lpfc_wcqe_r_wqe_index_MASK      0x0000FFFF
 321 #define lpfc_wcqe_r_wqe_index_WORD      word2
 322         uint32_t word3;
 323 #define lpfc_wcqe_r_valid_SHIFT         lpfc_cqe_valid_SHIFT
 324 #define lpfc_wcqe_r_valid_MASK          lpfc_cqe_valid_MASK
 325 #define lpfc_wcqe_r_valid_WORD          lpfc_cqe_valid_WORD
 326 #define lpfc_wcqe_r_code_SHIFT          lpfc_cqe_code_SHIFT
 327 #define lpfc_wcqe_r_code_MASK           lpfc_cqe_code_MASK
 328 #define lpfc_wcqe_r_code_WORD           lpfc_cqe_code_WORD
 329 };
 330
 331 struct sli4_wcqe_xri_aborted {
 332         uint32_t word0;
 333 #define lpfc_wcqe_xa_status_SHIFT               8
 334 #define lpfc_wcqe_xa_status_MASK                0x000000FF
 335 #define lpfc_wcqe_xa_status_WORD                word0
 336         uint32_t parameter;
 337         uint32_t word2;
 338 #define lpfc_wcqe_xa_remote_xid_SHIFT   16
 339 #define lpfc_wcqe_xa_remote_xid_MASK    0x0000FFFF
 340 #define lpfc_wcqe_xa_remote_xid_WORD    word2
 341 #define lpfc_wcqe_xa_xri_SHIFT          0
 342 #define lpfc_wcqe_xa_xri_MASK           0x0000FFFF
 343 #define lpfc_wcqe_xa_xri_WORD           word2
 344         uint32_t word3;
 345 #define lpfc_wcqe_xa_valid_SHIFT        lpfc_cqe_valid_SHIFT
 346 #define lpfc_wcqe_xa_valid_MASK         lpfc_cqe_valid_MASK
 347 #define lpfc_wcqe_xa_valid_WORD         lpfc_cqe_valid_WORD
 348 #define lpfc_wcqe_xa_ia_SHIFT           30
 349 #define lpfc_wcqe_xa_ia_MASK            0x00000001
 350 #define lpfc_wcqe_xa_ia_WORD            word3
 351 #define CQE_XRI_ABORTED_IA_REMOTE       0
 352 #define CQE_XRI_ABORTED_IA_LOCAL        1
 353 #define lpfc_wcqe_xa_br_SHIFT           29
 354 #define lpfc_wcqe_xa_br_MASK            0x00000001
 355 #define lpfc_wcqe_xa_br_WORD            word3
 356 #define CQE_XRI_ABORTED_BR_BA_ACC       0
 357 #define CQE_XRI_ABORTED_BR_BA_RJT       1
 358 #define lpfc_wcqe_xa_eo_SHIFT           28
 359 #define lpfc_wcqe_xa_eo_MASK            0x00000001
 360 #define lpfc_wcqe_xa_eo_WORD            word3
 361 #define CQE_XRI_ABORTED_EO_REMOTE       0
 362 #define CQE_XRI_ABORTED_EO_LOCAL        1
 363 #define lpfc_wcqe_xa_code_SHIFT         lpfc_cqe_code_SHIFT
 364 #define lpfc_wcqe_xa_code_MASK          lpfc_cqe_code_MASK
 365 #define lpfc_wcqe_xa_code_WORD          lpfc_cqe_code_WORD
 366 };
 367
 368 /* completion queue entry structure for rqe completion */
 369 struct lpfc_rcqe {
 370         uint32_t word0;
 371 #define lpfc_rcqe_bindex_SHIFT          16
 372 #define lpfc_rcqe_bindex_MASK           0x0000FFF
 373 #define lpfc_rcqe_bindex_WORD           word0
 374 #define lpfc_rcqe_status_SHIFT          8
 375 #define lpfc_rcqe_status_MASK           0x000000FF
 376 #define lpfc_rcqe_status_WORD           word0
 377 #define FC_STATUS_RQ_SUCCESS            0x10 /* Async receive successful */
 378 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED   0x11 /* payload truncated */
 379 #define FC_STATUS_INSUFF_BUF_NEED_BUF   0x12 /* Insufficient buffers */
 380 #define FC_STATUS_INSUFF_BUF_FRM_DISC   0x13 /* Frame Discard */
 381         uint32_t reserved1;
 382         uint32_t word2;
 383 #define lpfc_rcqe_length_SHIFT          16
 384 #define lpfc_rcqe_length_MASK           0x0000FFFF
 385 #define lpfc_rcqe_length_WORD           word2
 386 #define lpfc_rcqe_rq_id_SHIFT           6
 387 #define lpfc_rcqe_rq_id_MASK            0x000003FF
 388 #define lpfc_rcqe_rq_id_WORD            word2
 389 #define lpfc_rcqe_fcf_id_SHIFT          0
 390 #define lpfc_rcqe_fcf_id_MASK           0x0000003F
 391 #define lpfc_rcqe_fcf_id_WORD           word2
 392         uint32_t word3;
 393 #define lpfc_rcqe_valid_SHIFT           lpfc_cqe_valid_SHIFT
 394 #define lpfc_rcqe_valid_MASK            lpfc_cqe_valid_MASK
 395 #define lpfc_rcqe_valid_WORD            lpfc_cqe_valid_WORD
 396 #define lpfc_rcqe_port_SHIFT            30
 397 #define lpfc_rcqe_port_MASK             0x00000001
 398 #define lpfc_rcqe_port_WORD             word3
 399 #define lpfc_rcqe_hdr_length_SHIFT      24
 400 #define lpfc_rcqe_hdr_length_MASK       0x0000001F
 401 #define lpfc_rcqe_hdr_length_WORD       word3
 402 #define lpfc_rcqe_code_SHIFT            lpfc_cqe_code_SHIFT
 403 #define lpfc_rcqe_code_MASK             lpfc_cqe_code_MASK
 404 #define lpfc_rcqe_code_WORD             lpfc_cqe_code_WORD
 405 #define lpfc_rcqe_eof_SHIFT             8
 406 #define lpfc_rcqe_eof_MASK              0x000000FF
 407 #define lpfc_rcqe_eof_WORD              word3
 408 #define FCOE_EOFn       0x41
 409 #define FCOE_EOFt       0x42
 410 #define FCOE_EOFni      0x49
 411 #define FCOE_EOFa       0x50
 412 #define lpfc_rcqe_sof_SHIFT             0
 413 #define lpfc_rcqe_sof_MASK              0x000000FF
 414 #define lpfc_rcqe_sof_WORD              word3
 415 #define FCOE_SOFi2      0x2d
 416 #define FCOE_SOFi3      0x2e
 417 #define FCOE_SOFn2      0x35
 418 #define FCOE_SOFn3      0x36
 419 };
 420
 421 struct lpfc_wqe_generic{
 422         struct ulp_bde64 bde;
 423         uint32_t word3;
 424         uint32_t word4;
 425         uint32_t word5;
 426         uint32_t word6;
 427 #define lpfc_wqe_gen_context_SHIFT      16
 428 #define lpfc_wqe_gen_context_MASK       0x0000FFFF
 429 #define lpfc_wqe_gen_context_WORD       word6
 430 #define lpfc_wqe_gen_xri_SHIFT          0
 431 #define lpfc_wqe_gen_xri_MASK           0x0000FFFF
 432 #define lpfc_wqe_gen_xri_WORD           word6
 433         uint32_t word7;
 434 #define lpfc_wqe_gen_lnk_SHIFT          23
 435 #define lpfc_wqe_gen_lnk_MASK           0x00000001
 436 #define lpfc_wqe_gen_lnk_WORD           word7
 437 #define lpfc_wqe_gen_erp_SHIFT          22
 438 #define lpfc_wqe_gen_erp_MASK           0x00000001
 439 #define lpfc_wqe_gen_erp_WORD           word7
 440 #define lpfc_wqe_gen_pu_SHIFT           20
 441 #define lpfc_wqe_gen_pu_MASK            0x00000003
 442 #define lpfc_wqe_gen_pu_WORD            word7
 443 #define lpfc_wqe_gen_class_SHIFT        16
 444 #define lpfc_wqe_gen_class_MASK         0x00000007
 445 #define lpfc_wqe_gen_class_WORD         word7
 446 #define lpfc_wqe_gen_command_SHIFT      8
 447 #define lpfc_wqe_gen_command_MASK       0x000000FF
 448 #define lpfc_wqe_gen_command_WORD       word7
 449 #define lpfc_wqe_gen_status_SHIFT       4
 450 #define lpfc_wqe_gen_status_MASK        0x0000000F
 451 #define lpfc_wqe_gen_status_WORD        word7
 452 #define lpfc_wqe_gen_ct_SHIFT           2
 453 #define lpfc_wqe_gen_ct_MASK            0x00000003
 454 #define lpfc_wqe_gen_ct_WORD            word7
 455         uint32_t abort_tag;
 456         uint32_t word9;
 457 #define lpfc_wqe_gen_request_tag_SHIFT  0
 458 #define lpfc_wqe_gen_request_tag_MASK   0x0000FFFF
 459 #define lpfc_wqe_gen_request_tag_WORD   word9
 460         uint32_t word10;
 461 #define lpfc_wqe_gen_ccp_SHIFT          24
 462 #define lpfc_wqe_gen_ccp_MASK           0x000000FF
 463 #define lpfc_wqe_gen_ccp_WORD           word10
 464 #define lpfc_wqe_gen_ccpe_SHIFT         23
 465 #define lpfc_wqe_gen_ccpe_MASK          0x00000001
 466 #define lpfc_wqe_gen_ccpe_WORD          word10
 467 #define lpfc_wqe_gen_pv_SHIFT           19
 468 #define lpfc_wqe_gen_pv_MASK            0x00000001
 469 #define lpfc_wqe_gen_pv_WORD            word10
 470 #define lpfc_wqe_gen_pri_SHIFT          16
 471 #define lpfc_wqe_gen_pri_MASK           0x00000007
 472 #define lpfc_wqe_gen_pri_WORD           word10
 473         uint32_t word11;
 474 #define lpfc_wqe_gen_cq_id_SHIFT        16
 475 #define lpfc_wqe_gen_cq_id_MASK         0x0000FFFF
 476 #define lpfc_wqe_gen_cq_id_WORD         word11
 477 #define LPFC_WQE_CQ_ID_DEFAULT  0xffff
 478 #define lpfc_wqe_gen_wqec_SHIFT         7
 479 #define lpfc_wqe_gen_wqec_MASK          0x00000001
 480 #define lpfc_wqe_gen_wqec_WORD          word11
 481 #define ELS_ID_FLOGI 3
 482 #define ELS_ID_FDISC 2
 483 #define ELS_ID_LOGO  1
 484 #define ELS_ID_DEFAULT 0
 485 #define lpfc_wqe_gen_els_id_SHIFT       4
 486 #define lpfc_wqe_gen_els_id_MASK        0x00000003
 487 #define lpfc_wqe_gen_els_id_WORD        word11
 488 #define lpfc_wqe_gen_cmd_type_SHIFT     0
 489 #define lpfc_wqe_gen_cmd_type_MASK      0x0000000F
 490 #define lpfc_wqe_gen_cmd_type_WORD      word11
 491         uint32_t payload[4];
 492 };
 493
 494 struct lpfc_rqe {
 495         uint32_t address_hi;
 496         uint32_t address_lo;
 497 };
 498
 499 /* buffer descriptors */
 500 struct lpfc_bde4 {
 501         uint32_t addr_hi;
 502         uint32_t addr_lo;
 503         uint32_t word2;
 504 #define lpfc_bde4_last_SHIFT            31
 505 #define lpfc_bde4_last_MASK             0x00000001
 506 #define lpfc_bde4_last_WORD             word2
 507 #define lpfc_bde4_sge_offset_SHIFT      0
 508 #define lpfc_bde4_sge_offset_MASK       0x000003FF
 509 #define lpfc_bde4_sge_offset_WORD       word2
 510         uint32_t word3;
 511 #define lpfc_bde4_length_SHIFT          0
 512 #define lpfc_bde4_length_MASK           0x000000FF
 513 #define lpfc_bde4_length_WORD           word3
 514 };
 515
 516 struct lpfc_register {
 517         uint32_t word0;
 518 };
 519
 520 #define LPFC_UERR_STATUS_HI             0x00A4
 521 #define LPFC_UERR_STATUS_LO             0x00A0
 522 #define LPFC_UE_MASK_HI                 0x00AC
 523 #define LPFC_UE_MASK_LO                 0x00A8
 524 #define LPFC_SLI_INTF                   0x0058
 525
 526 /* BAR0 Registers */
 527 #define LPFC_HST_STATE                  0x00AC
 528 #define lpfc_hst_state_perr_SHIFT       31
 529 #define lpfc_hst_state_perr_MASK        0x1
 530 #define lpfc_hst_state_perr_WORD        word0
 531 #define lpfc_hst_state_sfi_SHIFT        30
 532 #define lpfc_hst_state_sfi_MASK         0x1
 533 #define lpfc_hst_state_sfi_WORD         word0
 534 #define lpfc_hst_state_nip_SHIFT        29
 535 #define lpfc_hst_state_nip_MASK         0x1
 536 #define lpfc_hst_state_nip_WORD         word0
 537 #define lpfc_hst_state_ipc_SHIFT        28
 538 #define lpfc_hst_state_ipc_MASK         0x1
 539 #define lpfc_hst_state_ipc_WORD         word0
 540 #define lpfc_hst_state_xrom_SHIFT       27
 541 #define lpfc_hst_state_xrom_MASK        0x1
 542 #define lpfc_hst_state_xrom_WORD        word0
 543 #define lpfc_hst_state_dl_SHIFT         26
 544 #define lpfc_hst_state_dl_MASK          0x1
 545 #define lpfc_hst_state_dl_WORD          word0
 546 #define lpfc_hst_state_port_status_SHIFT        0
 547 #define lpfc_hst_state_port_status_MASK         0xFFFF
 548 #define lpfc_hst_state_port_status_WORD         word0
 549
 550 #define LPFC_POST_STAGE_POWER_ON_RESET                  0x0000
 551 #define LPFC_POST_STAGE_AWAITING_HOST_RDY               0x0001
 552 #define LPFC_POST_STAGE_HOST_RDY                        0x0002
 553 #define LPFC_POST_STAGE_BE_RESET                        0x0003
 554 #define LPFC_POST_STAGE_SEEPROM_CS_START                0x0100
 555 #define LPFC_POST_STAGE_SEEPROM_CS_DONE                 0x0101
 556 #define LPFC_POST_STAGE_DDR_CONFIG_START                0x0200
 557 #define LPFC_POST_STAGE_DDR_CONFIG_DONE                 0x0201
 558 #define LPFC_POST_STAGE_DDR_CALIBRATE_START             0x0300
 559 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE              0x0301
 560 #define LPFC_POST_STAGE_DDR_TEST_START                  0x0400
 561 #define LPFC_POST_STAGE_DDR_TEST_DONE                   0x0401
 562 #define LPFC_POST_STAGE_REDBOOT_INIT_START              0x0600
 563 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE               0x0601
 564 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START             0x0700
 565 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE              0x0701
 566 #define LPFC_POST_STAGE_ARMFW_START                     0x0800
 567 #define LPFC_POST_STAGE_DHCP_QUERY_START                0x0900
 568 #define LPFC_POST_STAGE_DHCP_QUERY_DONE                 0x0901
 569 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START     0x0A00
 570 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE      0x0A01
 571 #define LPFC_POST_STAGE_RC_OPTION_SET                   0x0B00
 572 #define LPFC_POST_STAGE_SWITCH_LINK                     0x0B01
 573 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE               0x0B02
 574 #define LPFC_POST_STAGE_PERFROM_TFTP                    0x0B03
 575 #define LPFC_POST_STAGE_PARSE_XML                       0x0B04
 576 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE                  0x0B05
 577 #define LPFC_POST_STAGE_FLASH_IMAGE                     0x0B06
 578 #define LPFC_POST_STAGE_RC_DONE                         0x0B07
 579 #define LPFC_POST_STAGE_REBOOT_SYSTEM                   0x0B08
 580 #define LPFC_POST_STAGE_MAC_ADDRESS                     0x0C00
 581 #define LPFC_POST_STAGE_ARMFW_READY                     0xC000
 582 #define LPFC_POST_STAGE_ARMFW_UE                        0xF000
 583
 584 /* BAR1 Registers */
 585 #define LPFC_IMR_MASK_ALL       0xFFFFFFFF
 586 #define LPFC_ISCR_CLEAR_ALL     0xFFFFFFFF
 587
 588 #define LPFC_HST_ISR0           0x0C18
 589 #define LPFC_HST_ISR1           0x0C1C
 590 #define LPFC_HST_ISR2           0x0C20
 591 #define LPFC_HST_ISR3           0x0C24
 592 #define LPFC_HST_ISR4           0x0C28
 593
 594 #define LPFC_HST_IMR0           0x0C48
 595 #define LPFC_HST_IMR1           0x0C4C
 596 #define LPFC_HST_IMR2           0x0C50
 597 #define LPFC_HST_IMR3           0x0C54
 598 #define LPFC_HST_IMR4           0x0C58
 599
 600 #define LPFC_HST_ISCR0          0x0C78
 601 #define LPFC_HST_ISCR1          0x0C7C
 602 #define LPFC_HST_ISCR2          0x0C80
 603 #define LPFC_HST_ISCR3          0x0C84
 604 #define LPFC_HST_ISCR4          0x0C88
 605
 606 #define LPFC_SLI4_INTR0                 BIT0
 607 #define LPFC_SLI4_INTR1                 BIT1
 608 #define LPFC_SLI4_INTR2                 BIT2
 609 #define LPFC_SLI4_INTR3                 BIT3
 610 #define LPFC_SLI4_INTR4                 BIT4
 611 #define LPFC_SLI4_INTR5                 BIT5
 612 #define LPFC_SLI4_INTR6                 BIT6
 613 #define LPFC_SLI4_INTR7                 BIT7
 614 #define LPFC_SLI4_INTR8                 BIT8
 615 #define LPFC_SLI4_INTR9                 BIT9
 616 #define LPFC_SLI4_INTR10                BIT10
 617 #define LPFC_SLI4_INTR11                BIT11
 618 #define LPFC_SLI4_INTR12                BIT12
 619 #define LPFC_SLI4_INTR13                BIT13
 620 #define LPFC_SLI4_INTR14                BIT14
 621 #define LPFC_SLI4_INTR15                BIT15
 622 #define LPFC_SLI4_INTR16                BIT16
 623 #define LPFC_SLI4_INTR17                BIT17
 624 #define LPFC_SLI4_INTR18                BIT18
 625 #define LPFC_SLI4_INTR19                BIT19
 626 #define LPFC_SLI4_INTR20                BIT20
 627 #define LPFC_SLI4_INTR21                BIT21
 628 #define LPFC_SLI4_INTR22                BIT22
 629 #define LPFC_SLI4_INTR23                BIT23
 630 #define LPFC_SLI4_INTR24                BIT24
 631 #define LPFC_SLI4_INTR25                BIT25
 632 #define LPFC_SLI4_INTR26                BIT26
 633 #define LPFC_SLI4_INTR27                BIT27
 634 #define LPFC_SLI4_INTR28                BIT28
 635 #define LPFC_SLI4_INTR29                BIT29
 636 #define LPFC_SLI4_INTR30                BIT30
 637 #define LPFC_SLI4_INTR31                BIT31
 638
 639 /* BAR2 Registers */
 640 #define LPFC_RQ_DOORBELL                0x00A0
 641 #define lpfc_rq_doorbell_num_posted_SHIFT       16
 642 #define lpfc_rq_doorbell_num_posted_MASK        0x3FFF
 643 #define lpfc_rq_doorbell_num_posted_WORD        word0
 644 #define LPFC_RQ_POST_BATCH              8       /* RQEs to post at one time */
 645 #define lpfc_rq_doorbell_id_SHIFT               0
 646 #define lpfc_rq_doorbell_id_MASK                0x03FF
 647 #define lpfc_rq_doorbell_id_WORD                word0
 648
 649 #define LPFC_WQ_DOORBELL                0x0040
 650 #define lpfc_wq_doorbell_num_posted_SHIFT       24
 651 #define lpfc_wq_doorbell_num_posted_MASK        0x00FF
 652 #define lpfc_wq_doorbell_num_posted_WORD        word0
 653 #define lpfc_wq_doorbell_index_SHIFT            16
 654 #define lpfc_wq_doorbell_index_MASK             0x00FF
 655 #define lpfc_wq_doorbell_index_WORD             word0
 656 #define lpfc_wq_doorbell_id_SHIFT               0
 657 #define lpfc_wq_doorbell_id_MASK                0xFFFF
 658 #define lpfc_wq_doorbell_id_WORD                word0
 659
 660 #define LPFC_EQCQ_DOORBELL              0x0120
 661 #define lpfc_eqcq_doorbell_arm_SHIFT            29
 662 #define lpfc_eqcq_doorbell_arm_MASK             0x0001
 663 #define lpfc_eqcq_doorbell_arm_WORD             word0
 664 #define lpfc_eqcq_doorbell_num_released_SHIFT   16
 665 #define lpfc_eqcq_doorbell_num_released_MASK    0x1FFF
 666 #define lpfc_eqcq_doorbell_num_released_WORD    word0
 667 #define lpfc_eqcq_doorbell_qt_SHIFT             10
 668 #define lpfc_eqcq_doorbell_qt_MASK              0x0001
 669 #define lpfc_eqcq_doorbell_qt_WORD              word0
 670 #define LPFC_QUEUE_TYPE_COMPLETION      0
 671 #define LPFC_QUEUE_TYPE_EVENT           1
 672 #define lpfc_eqcq_doorbell_eqci_SHIFT           9
 673 #define lpfc_eqcq_doorbell_eqci_MASK            0x0001
 674 #define lpfc_eqcq_doorbell_eqci_WORD            word0
 675 #define lpfc_eqcq_doorbell_cqid_SHIFT           0
 676 #define lpfc_eqcq_doorbell_cqid_MASK            0x03FF
 677 #define lpfc_eqcq_doorbell_cqid_WORD            word0
 678 #define lpfc_eqcq_doorbell_eqid_SHIFT           0
 679 #define lpfc_eqcq_doorbell_eqid_MASK            0x01FF
 680 #define lpfc_eqcq_doorbell_eqid_WORD            word0
 681
 682 #define LPFC_BMBX                       0x0160
 683 #define lpfc_bmbx_addr_SHIFT            2
 684 #define lpfc_bmbx_addr_MASK             0x3FFFFFFF
 685 #define lpfc_bmbx_addr_WORD             word0
 686 #define lpfc_bmbx_hi_SHIFT              1
 687 #define lpfc_bmbx_hi_MASK               0x0001
 688 #define lpfc_bmbx_hi_WORD               word0
 689 #define lpfc_bmbx_rdy_SHIFT             0
 690 #define lpfc_bmbx_rdy_MASK              0x0001
 691 #define lpfc_bmbx_rdy_WORD              word0
 692
 693 #define LPFC_MQ_DOORBELL                        0x0140
 694 #define lpfc_mq_doorbell_num_posted_SHIFT       16
 695 #define lpfc_mq_doorbell_num_posted_MASK        0x3FFF
 696 #define lpfc_mq_doorbell_num_posted_WORD        word0
 697 #define lpfc_mq_doorbell_id_SHIFT               0
 698 #define lpfc_mq_doorbell_id_MASK                0x03FF
 699 #define lpfc_mq_doorbell_id_WORD                word0
 700
 701 struct lpfc_sli4_cfg_mhdr {
 702         uint32_t word1;
 703 #define lpfc_mbox_hdr_emb_SHIFT         0
 704 #define lpfc_mbox_hdr_emb_MASK          0x00000001
 705 #define lpfc_mbox_hdr_emb_WORD          word1
 706 #define lpfc_mbox_hdr_sge_cnt_SHIFT     3
 707 #define lpfc_mbox_hdr_sge_cnt_MASK      0x0000001F
 708 #define lpfc_mbox_hdr_sge_cnt_WORD      word1
 709         uint32_t payload_length;
 710         uint32_t tag_lo;
 711         uint32_t tag_hi;
 712         uint32_t reserved5;
 713 };
 714
 715 union lpfc_sli4_cfg_shdr {
 716         struct {
 717                 uint32_t word6;
 718 #define lpfc_mbox_hdr_opcode_SHIFT              0
 719 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
 720 #define lpfc_mbox_hdr_opcode_WORD               word6
 721 #define lpfc_mbox_hdr_subsystem_SHIFT           8
 722 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
 723 #define lpfc_mbox_hdr_subsystem_WORD            word6
 724 #define lpfc_mbox_hdr_port_number_SHIFT         16
 725 #define lpfc_mbox_hdr_port_number_MASK          0x000000FF
 726 #define lpfc_mbox_hdr_port_number_WORD          word6
 727 #define lpfc_mbox_hdr_domain_SHIFT              24
 728 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
 729 #define lpfc_mbox_hdr_domain_WORD               word6
 730                 uint32_t timeout;
 731                 uint32_t request_length;
 732                 uint32_t reserved9;
 733         } request;
 734         struct {
 735                 uint32_t word6;
 736 #define lpfc_mbox_hdr_opcode_SHIFT              0
 737 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
 738 #define lpfc_mbox_hdr_opcode_WORD               word6
 739 #define lpfc_mbox_hdr_subsystem_SHIFT           8
 740 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
 741 #define lpfc_mbox_hdr_subsystem_WORD            word6
 742 #define lpfc_mbox_hdr_domain_SHIFT              24
 743 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
 744 #define lpfc_mbox_hdr_domain_WORD               word6
 745                 uint32_t word7;
 746 #define lpfc_mbox_hdr_status_SHIFT              0
 747 #define lpfc_mbox_hdr_status_MASK               0x000000FF
 748 #define lpfc_mbox_hdr_status_WORD               word7
 749 #define lpfc_mbox_hdr_add_status_SHIFT          8
 750 #define lpfc_mbox_hdr_add_status_MASK           0x000000FF
 751 #define lpfc_mbox_hdr_add_status_WORD           word7
 752                 uint32_t response_length;
 753                 uint32_t actual_response_length;
 754         } response;
 755 };
 756
 757 /* Mailbox structures */
 758 struct mbox_header {
 759         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
 760         union  lpfc_sli4_cfg_shdr cfg_shdr;
 761 };
 762
 763 /* Subsystem Definitions */
 764 #define LPFC_MBOX_SUBSYSTEM_COMMON      0x1
 765 #define LPFC_MBOX_SUBSYSTEM_FCOE        0xC
 766
 767 /* Device Specific Definitions */
 768
 769 /* The HOST ENDIAN defines are in Big Endian format. */
 770 #define HOST_ENDIAN_LOW_WORD0   0xFF3412FF
 771 #define HOST_ENDIAN_HIGH_WORD1  0xFF7856FF
 772
 773 /* Common Opcodes */
 774 #define LPFC_MBOX_OPCODE_CQ_CREATE              0x0C
 775 #define LPFC_MBOX_OPCODE_EQ_CREATE              0x0D
 776 #define LPFC_MBOX_OPCODE_MQ_CREATE              0x15
 777 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES    0x20
 778 #define LPFC_MBOX_OPCODE_NOP                    0x21
 779 #define LPFC_MBOX_OPCODE_MQ_DESTROY             0x35
 780 #define LPFC_MBOX_OPCODE_CQ_DESTROY             0x36
 781 #define LPFC_MBOX_OPCODE_EQ_DESTROY             0x37
 782 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG           0x3A
 783 #define LPFC_MBOX_OPCODE_FUNCTION_RESET         0x3D
 784
 785 /* FCoE Opcodes */
 786 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE                 0x01
 787 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY                0x02
 788 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES            0x03
 789 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES          0x04
 790 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE                 0x05
 791 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY                0x06
 792 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE            0x08
 793 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF                   0x09
 794 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF                0x0A
 795 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE         0x0B
 796 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF            0x10
 797
 798 /* Mailbox command structures */
 799 struct eq_context {
 800         uint32_t word0;
 801 #define lpfc_eq_context_size_SHIFT      31
 802 #define lpfc_eq_context_size_MASK       0x00000001
 803 #define lpfc_eq_context_size_WORD       word0
 804 #define LPFC_EQE_SIZE_4                 0x0
 805 #define LPFC_EQE_SIZE_16                0x1
 806 #define lpfc_eq_context_valid_SHIFT     29
 807 #define lpfc_eq_context_valid_MASK      0x00000001
 808 #define lpfc_eq_context_valid_WORD      word0
 809         uint32_t word1;
 810 #define lpfc_eq_context_count_SHIFT     26
 811 #define lpfc_eq_context_count_MASK      0x00000003
 812 #define lpfc_eq_context_count_WORD      word1
 813 #define LPFC_EQ_CNT_256         0x0
 814 #define LPFC_EQ_CNT_512         0x1
 815 #define LPFC_EQ_CNT_1024        0x2
 816 #define LPFC_EQ_CNT_2048        0x3
 817 #define LPFC_EQ_CNT_4096        0x4
 818         uint32_t word2;
 819 #define lpfc_eq_context_delay_multi_SHIFT       13
 820 #define lpfc_eq_context_delay_multi_MASK        0x000003FF
 821 #define lpfc_eq_context_delay_multi_WORD        word2
 822         uint32_t reserved3;
 823 };
 824
 825 struct sgl_page_pairs {
 826         uint32_t sgl_pg0_addr_lo;
 827         uint32_t sgl_pg0_addr_hi;
 828         uint32_t sgl_pg1_addr_lo;
 829         uint32_t sgl_pg1_addr_hi;
 830 };
 831
 832 struct lpfc_mbx_post_sgl_pages {
 833         struct mbox_header header;
 834         uint32_t word0;
 835 #define lpfc_post_sgl_pages_xri_SHIFT   0
 836 #define lpfc_post_sgl_pages_xri_MASK    0x0000FFFF
 837 #define lpfc_post_sgl_pages_xri_WORD    word0
 838 #define lpfc_post_sgl_pages_xricnt_SHIFT        16
 839 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
 840 #define lpfc_post_sgl_pages_xricnt_WORD word0
 841         struct sgl_page_pairs  sgl_pg_pairs[1];
 842 };
 843
 844 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
 845 struct lpfc_mbx_post_uembed_sgl_page1 {
 846         union  lpfc_sli4_cfg_shdr cfg_shdr;
 847         uint32_t word0;
 848         struct sgl_page_pairs sgl_pg_pairs;
 849 };
 850
 851 struct lpfc_mbx_sge {
 852         uint32_t pa_lo;
 853         uint32_t pa_hi;
 854         uint32_t length;
 855 };
 856
 857 struct lpfc_mbx_nembed_cmd {
 858         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
 859 #define LPFC_SLI4_MBX_SGE_MAX_PAGES     19
 860         struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
 861 };
 862
 863 struct lpfc_mbx_nembed_sge_virt {
 864         void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
 865 };
 866
 867 struct lpfc_mbx_eq_create {
 868         struct mbox_header header;
 869         union {
 870                 struct {
 871                         uint32_t word0;
 872 #define lpfc_mbx_eq_create_num_pages_SHIFT      0
 873 #define lpfc_mbx_eq_create_num_pages_MASK       0x0000FFFF
 874 #define lpfc_mbx_eq_create_num_pages_WORD       word0
 875                         struct eq_context context;
 876                         struct dma_address page[LPFC_MAX_EQ_PAGE];
 877                 } request;
 878                 struct {
 879                         uint32_t word0;
 880 #define lpfc_mbx_eq_create_q_id_SHIFT   0
 881 #define lpfc_mbx_eq_create_q_id_MASK    0x0000FFFF
 882 #define lpfc_mbx_eq_create_q_id_WORD    word0
 883                 } response;
 884         } u;
 885 };
 886
 887 struct lpfc_mbx_eq_destroy {
 888         struct mbox_header header;
 889         union {
 890                 struct {
 891                         uint32_t word0;
 892 #define lpfc_mbx_eq_destroy_q_id_SHIFT  0
 893 #define lpfc_mbx_eq_destroy_q_id_MASK   0x0000FFFF
 894 #define lpfc_mbx_eq_destroy_q_id_WORD   word0
 895                 } request;
 896                 struct {
 897                         uint32_t word0;
 898                 } response;
 899         } u;
 900 };
 901
 902 struct lpfc_mbx_nop {
 903         struct mbox_header header;
 904         uint32_t context[2];
 905 };
 906
 907 struct cq_context {
 908         uint32_t word0;
 909 #define lpfc_cq_context_event_SHIFT     31
 910 #define lpfc_cq_context_event_MASK      0x00000001
 911 #define lpfc_cq_context_event_WORD      word0
 912 #define lpfc_cq_context_valid_SHIFT     29
 913 #define lpfc_cq_context_valid_MASK      0x00000001
 914 #define lpfc_cq_context_valid_WORD      word0
 915 #define lpfc_cq_context_count_SHIFT     27
 916 #define lpfc_cq_context_count_MASK      0x00000003
 917 #define lpfc_cq_context_count_WORD      word0
 918 #define LPFC_CQ_CNT_256         0x0
 919 #define LPFC_CQ_CNT_512         0x1
 920 #define LPFC_CQ_CNT_1024        0x2
 921         uint32_t word1;
 922 #define lpfc_cq_eq_id_SHIFT             22
 923 #define lpfc_cq_eq_id_MASK              0x000000FF
 924 #define lpfc_cq_eq_id_WORD              word1
 925         uint32_t reserved0;
 926         uint32_t reserved1;
 927 };
 928
 929 struct lpfc_mbx_cq_create {
 930         struct mbox_header header;
 931         union {
 932                 struct {
 933                         uint32_t word0;
 934 #define lpfc_mbx_cq_create_num_pages_SHIFT      0
 935 #define lpfc_mbx_cq_create_num_pages_MASK       0x0000FFFF
 936 #define lpfc_mbx_cq_create_num_pages_WORD       word0
 937                         struct cq_context context;
 938                         struct dma_address page[LPFC_MAX_CQ_PAGE];
 939                 } request;
 940                 struct {
 941                         uint32_t word0;
 942 #define lpfc_mbx_cq_create_q_id_SHIFT   0
 943 #define lpfc_mbx_cq_create_q_id_MASK    0x0000FFFF
 944 #define lpfc_mbx_cq_create_q_id_WORD    word0
 945                 } response;
 946         } u;
 947 };
 948
 949 struct lpfc_mbx_cq_destroy {
 950         struct mbox_header header;
 951         union {
 952                 struct {
 953                         uint32_t word0;
 954 #define lpfc_mbx_cq_destroy_q_id_SHIFT  0
 955 #define lpfc_mbx_cq_destroy_q_id_MASK   0x0000FFFF
 956 #define lpfc_mbx_cq_destroy_q_id_WORD   word0
 957                 } request;
 958                 struct {
 959                         uint32_t word0;
 960                 } response;
 961         } u;
 962 };
 963
 964 struct wq_context {
 965         uint32_t reserved0;
 966         uint32_t reserved1;
 967         uint32_t reserved2;
 968         uint32_t reserved3;
 969 };
 970
 971 struct lpfc_mbx_wq_create {
 972         struct mbox_header header;
 973         union {
 974                 struct {
 975                         uint32_t word0;
 976 #define lpfc_mbx_wq_create_num_pages_SHIFT      0
 977 #define lpfc_mbx_wq_create_num_pages_MASK       0x0000FFFF
 978 #define lpfc_mbx_wq_create_num_pages_WORD       word0
 979 #define lpfc_mbx_wq_create_cq_id_SHIFT          16
 980 #define lpfc_mbx_wq_create_cq_id_MASK           0x0000FFFF
 981 #define lpfc_mbx_wq_create_cq_id_WORD           word0
 982                         struct dma_address page[LPFC_MAX_WQ_PAGE];
 983                 } request;
 984                 struct {
 985                         uint32_t word0;
 986 #define lpfc_mbx_wq_create_q_id_SHIFT   0
 987 #define lpfc_mbx_wq_create_q_id_MASK    0x0000FFFF
 988 #define lpfc_mbx_wq_create_q_id_WORD    word0
 989                 } response;
 990         } u;
 991 };
 992
 993 struct lpfc_mbx_wq_destroy {
 994         struct mbox_header header;
 995         union {
 996                 struct {
 997                         uint32_t word0;
 998 #define lpfc_mbx_wq_destroy_q_id_SHIFT  0
 999 #define lpfc_mbx_wq_destroy_q_id_MASK   0x0000FFFF
1000 #define lpfc_mbx_wq_destroy_q_id_WORD   word0
1001                 } request;
1002                 struct {
1003                         uint32_t word0;
1004                 } response;
1005         } u;
1006 };
1007
1008 #define LPFC_HDR_BUF_SIZE 128
1009 #define LPFC_DATA_BUF_SIZE 2048
1010 struct rq_context {
1011         uint32_t word0;
1012 #define lpfc_rq_context_rq_size_SHIFT   16
1013 #define lpfc_rq_context_rq_size_MASK    0x0000000F
1014 #define lpfc_rq_context_rq_size_WORD    word0
1015 #define LPFC_RQ_RING_SIZE_512           9       /* 512 entries */
1016 #define LPFC_RQ_RING_SIZE_1024          10      /* 1024 entries */
1017 #define LPFC_RQ_RING_SIZE_2048          11      /* 2048 entries */
1018 #define LPFC_RQ_RING_SIZE_4096          12      /* 4096 entries */
1019         uint32_t reserved1;
1020         uint32_t word2;
1021 #define lpfc_rq_context_cq_id_SHIFT     16
1022 #define lpfc_rq_context_cq_id_MASK      0x000003FF
1023 #define lpfc_rq_context_cq_id_WORD      word2
1024 #define lpfc_rq_context_buf_size_SHIFT  0
1025 #define lpfc_rq_context_buf_size_MASK   0x0000FFFF
1026 #define lpfc_rq_context_buf_size_WORD   word2
1027         uint32_t reserved3;
1028 };
1029
1030 struct lpfc_mbx_rq_create {
1031         struct mbox_header header;
1032         union {
1033                 struct {
1034                         uint32_t word0;
1035 #define lpfc_mbx_rq_create_num_pages_SHIFT      0
1036 #define lpfc_mbx_rq_create_num_pages_MASK       0x0000FFFF
1037 #define lpfc_mbx_rq_create_num_pages_WORD       word0
1038                         struct rq_context context;
1039                         struct dma_address page[LPFC_MAX_WQ_PAGE];
1040                 } request;
1041                 struct {
1042                         uint32_t word0;
1043 #define lpfc_mbx_rq_create_q_id_SHIFT   0
1044 #define lpfc_mbx_rq_create_q_id_MASK    0x0000FFFF
1045 #define lpfc_mbx_rq_create_q_id_WORD    word0
1046                 } response;
1047         } u;
1048 };
1049
1050 struct lpfc_mbx_rq_destroy {
1051         struct mbox_header header;
1052         union {
1053                 struct {
1054                         uint32_t word0;
1055 #define lpfc_mbx_rq_destroy_q_id_SHIFT  0
1056 #define lpfc_mbx_rq_destroy_q_id_MASK   0x0000FFFF
1057 #define lpfc_mbx_rq_destroy_q_id_WORD   word0
1058                 } request;
1059                 struct {
1060                         uint32_t word0;
1061                 } response;
1062         } u;
1063 };
1064
1065 struct mq_context {
1066         uint32_t word0;
1067 #define lpfc_mq_context_cq_id_SHIFT     22
1068 #define lpfc_mq_context_cq_id_MASK      0x000003FF
1069 #define lpfc_mq_context_cq_id_WORD      word0
1070 #define lpfc_mq_context_count_SHIFT     16
1071 #define lpfc_mq_context_count_MASK      0x0000000F
1072 #define lpfc_mq_context_count_WORD      word0
1073 #define LPFC_MQ_CNT_16          0x5
1074 #define LPFC_MQ_CNT_32          0x6
1075 #define LPFC_MQ_CNT_64          0x7
1076 #define LPFC_MQ_CNT_128         0x8
1077         uint32_t word1;
1078 #define lpfc_mq_context_valid_SHIFT     31
1079 #define lpfc_mq_context_valid_MASK      0x00000001
1080 #define lpfc_mq_context_valid_WORD      word1
1081         uint32_t reserved2;
1082         uint32_t reserved3;
1083 };
1084
1085 struct lpfc_mbx_mq_create {
1086         struct mbox_header header;
1087         union {
1088                 struct {
1089                         uint32_t word0;
1090 #define lpfc_mbx_mq_create_num_pages_SHIFT      0
1091 #define lpfc_mbx_mq_create_num_pages_MASK       0x0000FFFF
1092 #define lpfc_mbx_mq_create_num_pages_WORD       word0
1093                         struct mq_context context;
1094                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1095                 } request;
1096                 struct {
1097                         uint32_t word0;
1098 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1099 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1100 #define lpfc_mbx_mq_create_q_id_WORD    word0
1101                 } response;
1102         } u;
1103 };
1104
1105 struct lpfc_mbx_mq_destroy {
1106         struct mbox_header header;
1107         union {
1108                 struct {
1109                         uint32_t word0;
1110 #define lpfc_mbx_mq_destroy_q_id_SHIFT  0
1111 #define lpfc_mbx_mq_destroy_q_id_MASK   0x0000FFFF
1112 #define lpfc_mbx_mq_destroy_q_id_WORD   word0
1113                 } request;
1114                 struct {
1115                         uint32_t word0;
1116                 } response;
1117         } u;
1118 };
1119
1120 struct lpfc_mbx_post_hdr_tmpl {
1121         struct mbox_header header;
1122         uint32_t word10;
1123 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT  0
1124 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK   0x0000FFFF
1125 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD   word10
1126 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT   16
1127 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK    0x0000FFFF
1128 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD    word10
1129         uint32_t rpi_paddr_lo;
1130         uint32_t rpi_paddr_hi;
1131 };
1132
1133 struct sli4_sge {       /* SLI-4 */
1134         uint32_t addr_hi;
1135         uint32_t addr_lo;
1136
1137         uint32_t word2;
1138 #define lpfc_sli4_sge_offset_SHIFT      0 /* Offset of buffer - Not used*/
1139 #define lpfc_sli4_sge_offset_MASK       0x00FFFFFF
1140 #define lpfc_sli4_sge_offset_WORD       word2
1141 #define lpfc_sli4_sge_last_SHIFT        31 /* Last SEG in the SGL sets
1142                                                 this  flag !! */
1143 #define lpfc_sli4_sge_last_MASK         0x00000001
1144 #define lpfc_sli4_sge_last_WORD         word2
1145         uint32_t sge_len;
1146 };
1147
1148 struct fcf_record {
1149         uint32_t max_rcv_size;
1150         uint32_t fka_adv_period;
1151         uint32_t fip_priority;
1152         uint32_t word3;
1153 #define lpfc_fcf_record_mac_0_SHIFT             0
1154 #define lpfc_fcf_record_mac_0_MASK              0x000000FF
1155 #define lpfc_fcf_record_mac_0_WORD              word3
1156 #define lpfc_fcf_record_mac_1_SHIFT             8
1157 #define lpfc_fcf_record_mac_1_MASK              0x000000FF
1158 #define lpfc_fcf_record_mac_1_WORD              word3
1159 #define lpfc_fcf_record_mac_2_SHIFT             16
1160 #define lpfc_fcf_record_mac_2_MASK              0x000000FF
1161 #define lpfc_fcf_record_mac_2_WORD              word3
1162 #define lpfc_fcf_record_mac_3_SHIFT             24
1163 #define lpfc_fcf_record_mac_3_MASK              0x000000FF
1164 #define lpfc_fcf_record_mac_3_WORD              word3
1165         uint32_t word4;
1166 #define lpfc_fcf_record_mac_4_SHIFT             0
1167 #define lpfc_fcf_record_mac_4_MASK              0x000000FF
1168 #define lpfc_fcf_record_mac_4_WORD              word4
1169 #define lpfc_fcf_record_mac_5_SHIFT             8
1170 #define lpfc_fcf_record_mac_5_MASK              0x000000FF
1171 #define lpfc_fcf_record_mac_5_WORD              word4
1172 #define lpfc_fcf_record_fcf_avail_SHIFT         16
1173 #define lpfc_fcf_record_fcf_avail_MASK          0x000000FF
1174 #define lpfc_fcf_record_fcf_avail_WORD          word4
1175 #define lpfc_fcf_record_mac_addr_prov_SHIFT     24
1176 #define lpfc_fcf_record_mac_addr_prov_MASK      0x000000FF
1177 #define lpfc_fcf_record_mac_addr_prov_WORD      word4
1178 #define LPFC_FCF_FPMA           1       /* Fabric Provided MAC Address */
1179 #define LPFC_FCF_SPMA           2       /* Server Provided MAC Address */
1180         uint32_t word5;
1181 #define lpfc_fcf_record_fab_name_0_SHIFT        0
1182 #define lpfc_fcf_record_fab_name_0_MASK         0x000000FF
1183 #define lpfc_fcf_record_fab_name_0_WORD         word5
1184 #define lpfc_fcf_record_fab_name_1_SHIFT        8
1185 #define lpfc_fcf_record_fab_name_1_MASK         0x000000FF
1186 #define lpfc_fcf_record_fab_name_1_WORD         word5
1187 #define lpfc_fcf_record_fab_name_2_SHIFT        16
1188 #define lpfc_fcf_record_fab_name_2_MASK         0x000000FF
1189 #define lpfc_fcf_record_fab_name_2_WORD         word5
1190 #define lpfc_fcf_record_fab_name_3_SHIFT        24
1191 #define lpfc_fcf_record_fab_name_3_MASK         0x000000FF
1192 #define lpfc_fcf_record_fab_name_3_WORD         word5
1193         uint32_t word6;
1194 #define lpfc_fcf_record_fab_name_4_SHIFT        0
1195 #define lpfc_fcf_record_fab_name_4_MASK         0x000000FF
1196 #define lpfc_fcf_record_fab_name_4_WORD         word6
1197 #define lpfc_fcf_record_fab_name_5_SHIFT        8
1198 #define lpfc_fcf_record_fab_name_5_MASK         0x000000FF
1199 #define lpfc_fcf_record_fab_name_5_WORD         word6
1200 #define lpfc_fcf_record_fab_name_6_SHIFT        16
1201 #define lpfc_fcf_record_fab_name_6_MASK         0x000000FF
1202 #define lpfc_fcf_record_fab_name_6_WORD         word6
1203 #define lpfc_fcf_record_fab_name_7_SHIFT        24
1204 #define lpfc_fcf_record_fab_name_7_MASK         0x000000FF
1205 #define lpfc_fcf_record_fab_name_7_WORD         word6
1206         uint32_t word7;
1207 #define lpfc_fcf_record_fc_map_0_SHIFT          0
1208 #define lpfc_fcf_record_fc_map_0_MASK           0x000000FF
1209 #define lpfc_fcf_record_fc_map_0_WORD           word7
1210 #define lpfc_fcf_record_fc_map_1_SHIFT          8
1211 #define lpfc_fcf_record_fc_map_1_MASK           0x000000FF
1212 #define lpfc_fcf_record_fc_map_1_WORD           word7
1213 #define lpfc_fcf_record_fc_map_2_SHIFT          16
1214 #define lpfc_fcf_record_fc_map_2_MASK           0x000000FF
1215 #define lpfc_fcf_record_fc_map_2_WORD           word7
1216 #define lpfc_fcf_record_fcf_valid_SHIFT         24
1217 #define lpfc_fcf_record_fcf_valid_MASK          0x000000FF
1218 #define lpfc_fcf_record_fcf_valid_WORD          word7
1219         uint32_t word8;
1220 #define lpfc_fcf_record_fcf_index_SHIFT         0
1221 #define lpfc_fcf_record_fcf_index_MASK          0x0000FFFF
1222 #define lpfc_fcf_record_fcf_index_WORD          word8
1223 #define lpfc_fcf_record_fcf_state_SHIFT         16
1224 #define lpfc_fcf_record_fcf_state_MASK          0x0000FFFF
1225 #define lpfc_fcf_record_fcf_state_WORD          word8
1226         uint8_t vlan_bitmap[512];
1227         uint32_t word137;
1228 #define lpfc_fcf_record_switch_name_0_SHIFT     0
1229 #define lpfc_fcf_record_switch_name_0_MASK      0x000000FF
1230 #define lpfc_fcf_record_switch_name_0_WORD      word137
1231 #define lpfc_fcf_record_switch_name_1_SHIFT     8
1232 #define lpfc_fcf_record_switch_name_1_MASK      0x000000FF
1233 #define lpfc_fcf_record_switch_name_1_WORD      word137
1234 #define lpfc_fcf_record_switch_name_2_SHIFT     16
1235 #define lpfc_fcf_record_switch_name_2_MASK      0x000000FF
1236 #define lpfc_fcf_record_switch_name_2_WORD      word137
1237 #define lpfc_fcf_record_switch_name_3_SHIFT     24
1238 #define lpfc_fcf_record_switch_name_3_MASK      0x000000FF
1239 #define lpfc_fcf_record_switch_name_3_WORD      word137
1240         uint32_t word138;
1241 #define lpfc_fcf_record_switch_name_4_SHIFT     0
1242 #define lpfc_fcf_record_switch_name_4_MASK      0x000000FF
1243 #define lpfc_fcf_record_switch_name_4_WORD      word138
1244 #define lpfc_fcf_record_switch_name_5_SHIFT     8
1245 #define lpfc_fcf_record_switch_name_5_MASK      0x000000FF
1246 #define lpfc_fcf_record_switch_name_5_WORD      word138
1247 #define lpfc_fcf_record_switch_name_6_SHIFT     16
1248 #define lpfc_fcf_record_switch_name_6_MASK      0x000000FF
1249 #define lpfc_fcf_record_switch_name_6_WORD      word138
1250 #define lpfc_fcf_record_switch_name_7_SHIFT     24
1251 #define lpfc_fcf_record_switch_name_7_MASK      0x000000FF
1252 #define lpfc_fcf_record_switch_name_7_WORD      word138
1253 };
1254
1255 struct lpfc_mbx_read_fcf_tbl {
1256         union lpfc_sli4_cfg_shdr cfg_shdr;
1257         union {
1258                 struct {
1259                         uint32_t word10;
1260 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT        0
1261 #define lpfc_mbx_read_fcf_tbl_indx_MASK         0x0000FFFF
1262 #define lpfc_mbx_read_fcf_tbl_indx_WORD         word10
1263                 } request;
1264                 struct {
1265                         uint32_t eventag;
1266                 } response;
1267         } u;
1268         uint32_t word11;
1269 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT   0
1270 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK    0x0000FFFF
1271 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD    word11
1272 };
1273
1274 struct lpfc_mbx_add_fcf_tbl_entry {
1275         union lpfc_sli4_cfg_shdr cfg_shdr;
1276         uint32_t word10;
1277 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT        0
1278 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK         0x0000FFFF
1279 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD         word10
1280         struct lpfc_mbx_sge fcf_sge;
1281 };
1282
1283 struct lpfc_mbx_del_fcf_tbl_entry {
1284         struct mbox_header header;
1285         uint32_t word10;
1286 #define lpfc_mbx_del_fcf_tbl_count_SHIFT        0
1287 #define lpfc_mbx_del_fcf_tbl_count_MASK         0x0000FFFF
1288 #define lpfc_mbx_del_fcf_tbl_count_WORD         word10
1289 #define lpfc_mbx_del_fcf_tbl_index_SHIFT        16
1290 #define lpfc_mbx_del_fcf_tbl_index_MASK         0x0000FFFF
1291 #define lpfc_mbx_del_fcf_tbl_index_WORD         word10
1292 };
1293
1294 struct lpfc_mbx_redisc_fcf_tbl {
1295         struct mbox_header header;
1296         uint32_t word10;
1297 #define lpfc_mbx_redisc_fcf_count_SHIFT         0
1298 #define lpfc_mbx_redisc_fcf_count_MASK          0x0000FFFF
1299 #define lpfc_mbx_redisc_fcf_count_WORD          word10
1300         uint32_t resvd;
1301         uint32_t word12;
1302 #define lpfc_mbx_redisc_fcf_index_SHIFT         0
1303 #define lpfc_mbx_redisc_fcf_index_MASK          0x0000FFFF
1304 #define lpfc_mbx_redisc_fcf_index_WORD          word12
1305 };
1306
1307 struct lpfc_mbx_query_fw_cfg {
1308         struct mbox_header header;
1309         uint32_t config_number;
1310         uint32_t asic_rev;
1311         uint32_t phys_port;
1312         uint32_t function_mode;
1313 /* firmware Function Mode */
1314 #define lpfc_function_mode_toe_SHIFT            0
1315 #define lpfc_function_mode_toe_MASK             0x00000001
1316 #define lpfc_function_mode_toe_WORD             function_mode
1317 #define lpfc_function_mode_nic_SHIFT            1
1318 #define lpfc_function_mode_nic_MASK             0x00000001
1319 #define lpfc_function_mode_nic_WORD             function_mode
1320 #define lpfc_function_mode_rdma_SHIFT           2
1321 #define lpfc_function_mode_rdma_MASK            0x00000001
1322 #define lpfc_function_mode_rdma_WORD            function_mode
1323 #define lpfc_function_mode_vm_SHIFT             3
1324 #define lpfc_function_mode_vm_MASK              0x00000001
1325 #define lpfc_function_mode_vm_WORD              function_mode
1326 #define lpfc_function_mode_iscsi_i_SHIFT        4
1327 #define lpfc_function_mode_iscsi_i_MASK         0x00000001
1328 #define lpfc_function_mode_iscsi_i_WORD         function_mode
1329 #define lpfc_function_mode_iscsi_t_SHIFT        5
1330 #define lpfc_function_mode_iscsi_t_MASK         0x00000001
1331 #define lpfc_function_mode_iscsi_t_WORD         function_mode
1332 #define lpfc_function_mode_fcoe_i_SHIFT         6
1333 #define lpfc_function_mode_fcoe_i_MASK          0x00000001
1334 #define lpfc_function_mode_fcoe_i_WORD          function_mode
1335 #define lpfc_function_mode_fcoe_t_SHIFT         7
1336 #define lpfc_function_mode_fcoe_t_MASK          0x00000001
1337 #define lpfc_function_mode_fcoe_t_WORD          function_mode
1338 #define lpfc_function_mode_dal_SHIFT            8
1339 #define lpfc_function_mode_dal_MASK             0x00000001
1340 #define lpfc_function_mode_dal_WORD             function_mode
1341 #define lpfc_function_mode_lro_SHIFT            9
1342 #define lpfc_function_mode_lro_MASK             0x00000001
1343 #define lpfc_function_mode_lro_WORD             function_mode9
1344 #define lpfc_function_mode_flex10_SHIFT         10
1345 #define lpfc_function_mode_flex10_MASK          0x00000001
1346 #define lpfc_function_mode_flex10_WORD          function_mode
1347 #define lpfc_function_mode_ncsi_SHIFT           11
1348 #define lpfc_function_mode_ncsi_MASK            0x00000001
1349 #define lpfc_function_mode_ncsi_WORD            function_mode
1350 };
1351
1352 /* Status field for embedded SLI_CONFIG mailbox command */
1353 #define STATUS_SUCCESS                                  0x0
1354 #define STATUS_FAILED                                   0x1
1355 #define STATUS_ILLEGAL_REQUEST                          0x2
1356 #define STATUS_ILLEGAL_FIELD                            0x3
1357 #define STATUS_INSUFFICIENT_BUFFER                      0x4
1358 #define STATUS_UNAUTHORIZED_REQUEST                     0x5
1359 #define STATUS_FLASHROM_SAVE_FAILED                     0x17
1360 #define STATUS_FLASHROM_RESTORE_FAILED                  0x18
1361 #define STATUS_ICCBINDEX_ALLOC_FAILED                   0x1a
1362 #define STATUS_IOCTLHANDLE_ALLOC_FAILED                 0x1b
1363 #define STATUS_INVALID_PHY_ADDR_FROM_OSM                0x1c
1364 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM            0x1d
1365 #define STATUS_ASSERT_FAILED                            0x1e
1366 #define STATUS_INVALID_SESSION                          0x1f
1367 #define STATUS_INVALID_CONNECTION                       0x20
1368 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT               0x21
1369 #define STATUS_BTL_NO_FREE_SLOT_PATH                    0x24
1370 #define STATUS_BTL_NO_FREE_SLOT_TGTID                   0x25
1371 #define STATUS_OSM_DEVSLOT_NOT_FOUND                    0x26
1372 #define STATUS_FLASHROM_READ_FAILED                     0x27
1373 #define STATUS_POLL_IOCTL_TIMEOUT                       0x28
1374 #define STATUS_ERROR_ACITMAIN                           0x2a
1375 #define STATUS_REBOOT_REQUIRED                          0x2c
1376 #define STATUS_FCF_IN_USE                               0x3a
1377 #define STATUS_FCF_TABLE_EMPTY                          0x43
1378
1379 struct lpfc_mbx_sli4_config {
1380         struct mbox_header header;
1381 };
1382
1383 struct lpfc_mbx_init_vfi {
1384         uint32_t word1;
1385 #define lpfc_init_vfi_vr_SHIFT          31
1386 #define lpfc_init_vfi_vr_MASK           0x00000001
1387 #define lpfc_init_vfi_vr_WORD           word1
1388 #define lpfc_init_vfi_vt_SHIFT          30
1389 #define lpfc_init_vfi_vt_MASK           0x00000001
1390 #define lpfc_init_vfi_vt_WORD           word1
1391 #define lpfc_init_vfi_vf_SHIFT          29
1392 #define lpfc_init_vfi_vf_MASK           0x00000001
1393 #define lpfc_init_vfi_vf_WORD           word1
1394 #define lpfc_init_vfi_vfi_SHIFT         0
1395 #define lpfc_init_vfi_vfi_MASK          0x0000FFFF
1396 #define lpfc_init_vfi_vfi_WORD          word1
1397         uint32_t word2;
1398 #define lpfc_init_vfi_fcfi_SHIFT        0
1399 #define lpfc_init_vfi_fcfi_MASK         0x0000FFFF
1400 #define lpfc_init_vfi_fcfi_WORD         word2
1401         uint32_t word3;
1402 #define lpfc_init_vfi_pri_SHIFT         13
1403 #define lpfc_init_vfi_pri_MASK          0x00000007
1404 #define lpfc_init_vfi_pri_WORD          word3
1405 #define lpfc_init_vfi_vf_id_SHIFT       1
1406 #define lpfc_init_vfi_vf_id_MASK        0x00000FFF
1407 #define lpfc_init_vfi_vf_id_WORD        word3
1408         uint32_t word4;
1409 #define lpfc_init_vfi_hop_count_SHIFT   24
1410 #define lpfc_init_vfi_hop_count_MASK    0x000000FF
1411 #define lpfc_init_vfi_hop_count_WORD    word4
1412 };
1413
1414 struct lpfc_mbx_reg_vfi {
1415         uint32_t word1;
1416 #define lpfc_reg_vfi_vp_SHIFT           28
1417 #define lpfc_reg_vfi_vp_MASK            0x00000001
1418 #define lpfc_reg_vfi_vp_WORD            word1
1419 #define lpfc_reg_vfi_vfi_SHIFT          0
1420 #define lpfc_reg_vfi_vfi_MASK           0x0000FFFF
1421 #define lpfc_reg_vfi_vfi_WORD           word1
1422         uint32_t word2;
1423 #define lpfc_reg_vfi_vpi_SHIFT          16
1424 #define lpfc_reg_vfi_vpi_MASK           0x0000FFFF
1425 #define lpfc_reg_vfi_vpi_WORD           word2
1426 #define lpfc_reg_vfi_fcfi_SHIFT         0
1427 #define lpfc_reg_vfi_fcfi_MASK          0x0000FFFF
1428 #define lpfc_reg_vfi_fcfi_WORD          word2
1429         uint32_t wwn[2];
1430         struct ulp_bde64 bde;
1431         uint32_t word8_rsvd;
1432         uint32_t word9_rsvd;
1433         uint32_t word10;
1434 #define lpfc_reg_vfi_nport_id_SHIFT             0
1435 #define lpfc_reg_vfi_nport_id_MASK              0x00FFFFFF
1436 #define lpfc_reg_vfi_nport_id_WORD              word10
1437 };
1438
1439 struct lpfc_mbx_init_vpi {
1440         uint32_t word1;
1441 #define lpfc_init_vpi_vfi_SHIFT         16
1442 #define lpfc_init_vpi_vfi_MASK          0x0000FFFF
1443 #define lpfc_init_vpi_vfi_WORD          word1
1444 #define lpfc_init_vpi_vpi_SHIFT         0
1445 #define lpfc_init_vpi_vpi_MASK          0x0000FFFF
1446 #define lpfc_init_vpi_vpi_WORD          word1
1447 };
1448
1449 struct lpfc_mbx_read_vpi {
1450         uint32_t word1_rsvd;
1451         uint32_t word2;
1452 #define lpfc_mbx_read_vpi_vnportid_SHIFT        0
1453 #define lpfc_mbx_read_vpi_vnportid_MASK         0x00FFFFFF
1454 #define lpfc_mbx_read_vpi_vnportid_WORD         word2
1455         uint32_t word3_rsvd;
1456         uint32_t word4;
1457 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT        0
1458 #define lpfc_mbx_read_vpi_acq_alpa_MASK         0x000000FF
1459 #define lpfc_mbx_read_vpi_acq_alpa_WORD         word4
1460 #define lpfc_mbx_read_vpi_pb_SHIFT              15
1461 #define lpfc_mbx_read_vpi_pb_MASK               0x00000001
1462 #define lpfc_mbx_read_vpi_pb_WORD               word4
1463 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT       16
1464 #define lpfc_mbx_read_vpi_spec_alpa_MASK        0x000000FF
1465 #define lpfc_mbx_read_vpi_spec_alpa_WORD        word4
1466 #define lpfc_mbx_read_vpi_ns_SHIFT              30
1467 #define lpfc_mbx_read_vpi_ns_MASK               0x00000001
1468 #define lpfc_mbx_read_vpi_ns_WORD               word4
1469 #define lpfc_mbx_read_vpi_hl_SHIFT              31
1470 #define lpfc_mbx_read_vpi_hl_MASK               0x00000001
1471 #define lpfc_mbx_read_vpi_hl_WORD               word4
1472         uint32_t word5_rsvd;
1473         uint32_t word6;
1474 #define lpfc_mbx_read_vpi_vpi_SHIFT             0
1475 #define lpfc_mbx_read_vpi_vpi_MASK              0x0000FFFF
1476 #define lpfc_mbx_read_vpi_vpi_WORD              word6
1477         uint32_t word7;
1478 #define lpfc_mbx_read_vpi_mac_0_SHIFT           0
1479 #define lpfc_mbx_read_vpi_mac_0_MASK            0x000000FF
1480 #define lpfc_mbx_read_vpi_mac_0_WORD            word7
1481 #define lpfc_mbx_read_vpi_mac_1_SHIFT           8
1482 #define lpfc_mbx_read_vpi_mac_1_MASK            0x000000FF
1483 #define lpfc_mbx_read_vpi_mac_1_WORD            word7
1484 #define lpfc_mbx_read_vpi_mac_2_SHIFT           16
1485 #define lpfc_mbx_read_vpi_mac_2_MASK            0x000000FF
1486 #define lpfc_mbx_read_vpi_mac_2_WORD            word7
1487 #define lpfc_mbx_read_vpi_mac_3_SHIFT           24
1488 #define lpfc_mbx_read_vpi_mac_3_MASK            0x000000FF
1489 #define lpfc_mbx_read_vpi_mac_3_WORD            word7
1490         uint32_t word8;
1491 #define lpfc_mbx_read_vpi_mac_4_SHIFT           0
1492 #define lpfc_mbx_read_vpi_mac_4_MASK            0x000000FF
1493 #define lpfc_mbx_read_vpi_mac_4_WORD            word8
1494 #define lpfc_mbx_read_vpi_mac_5_SHIFT           8
1495 #define lpfc_mbx_read_vpi_mac_5_MASK            0x000000FF
1496 #define lpfc_mbx_read_vpi_mac_5_WORD            word8
1497 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT        16
1498 #define lpfc_mbx_read_vpi_vlan_tag_MASK         0x00000FFF
1499 #define lpfc_mbx_read_vpi_vlan_tag_WORD         word8
1500 #define lpfc_mbx_read_vpi_vv_SHIFT              28
1501 #define lpfc_mbx_read_vpi_vv_MASK               0x0000001
1502 #define lpfc_mbx_read_vpi_vv_WORD               word8
1503 };
1504
1505 struct lpfc_mbx_unreg_vfi {
1506         uint32_t word1_rsvd;
1507         uint32_t word2;
1508 #define lpfc_unreg_vfi_vfi_SHIFT        0
1509 #define lpfc_unreg_vfi_vfi_MASK         0x0000FFFF
1510 #define lpfc_unreg_vfi_vfi_WORD         word2
1511 };
1512
1513 struct lpfc_mbx_resume_rpi {
1514         uint32_t word1;
1515 #define lpfc_resume_rpi_index_SHIFT     0
1516 #define lpfc_resume_rpi_index_MASK      0x0000FFFF
1517 #define lpfc_resume_rpi_index_WORD      word1
1518 #define lpfc_resume_rpi_ii_SHIFT        30
1519 #define lpfc_resume_rpi_ii_MASK         0x00000003
1520 #define lpfc_resume_rpi_ii_WORD         word1
1521 #define RESUME_INDEX_RPI                0
1522 #define RESUME_INDEX_VPI                1
1523 #define RESUME_INDEX_VFI                2
1524 #define RESUME_INDEX_FCFI               3
1525         uint32_t event_tag;
1526 };
1527
1528 #define REG_FCF_INVALID_QID     0xFFFF
1529 struct lpfc_mbx_reg_fcfi {
1530         uint32_t word1;
1531 #define lpfc_reg_fcfi_info_index_SHIFT  0
1532 #define lpfc_reg_fcfi_info_index_MASK   0x0000FFFF
1533 #define lpfc_reg_fcfi_info_index_WORD   word1
1534 #define lpfc_reg_fcfi_fcfi_SHIFT        16
1535 #define lpfc_reg_fcfi_fcfi_MASK         0x0000FFFF
1536 #define lpfc_reg_fcfi_fcfi_WORD         word1
1537         uint32_t word2;
1538 #define lpfc_reg_fcfi_rq_id1_SHIFT      0
1539 #define lpfc_reg_fcfi_rq_id1_MASK       0x0000FFFF
1540 #define lpfc_reg_fcfi_rq_id1_WORD       word2
1541 #define lpfc_reg_fcfi_rq_id0_SHIFT      16
1542 #define lpfc_reg_fcfi_rq_id0_MASK       0x0000FFFF
1543 #define lpfc_reg_fcfi_rq_id0_WORD       word2
1544         uint32_t word3;
1545 #define lpfc_reg_fcfi_rq_id3_SHIFT      0
1546 #define lpfc_reg_fcfi_rq_id3_MASK       0x0000FFFF
1547 #define lpfc_reg_fcfi_rq_id3_WORD       word3
1548 #define lpfc_reg_fcfi_rq_id2_SHIFT      16
1549 #define lpfc_reg_fcfi_rq_id2_MASK       0x0000FFFF
1550 #define lpfc_reg_fcfi_rq_id2_WORD       word3
1551         uint32_t word4;
1552 #define lpfc_reg_fcfi_type_match0_SHIFT 24
1553 #define lpfc_reg_fcfi_type_match0_MASK  0x000000FF
1554 #define lpfc_reg_fcfi_type_match0_WORD  word4
1555 #define lpfc_reg_fcfi_type_mask0_SHIFT  16
1556 #define lpfc_reg_fcfi_type_mask0_MASK   0x000000FF
1557 #define lpfc_reg_fcfi_type_mask0_WORD   word4
1558 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
1559 #define lpfc_reg_fcfi_rctl_match0_MASK  0x000000FF
1560 #define lpfc_reg_fcfi_rctl_match0_WORD  word4
1561 #define lpfc_reg_fcfi_rctl_mask0_SHIFT  0
1562 #define lpfc_reg_fcfi_rctl_mask0_MASK   0x000000FF
1563 #define lpfc_reg_fcfi_rctl_mask0_WORD   word4
1564         uint32_t word5;
1565 #define lpfc_reg_fcfi_type_match1_SHIFT 24
1566 #define lpfc_reg_fcfi_type_match1_MASK  0x000000FF
1567 #define lpfc_reg_fcfi_type_match1_WORD  word5
1568 #define lpfc_reg_fcfi_type_mask1_SHIFT  16
1569 #define lpfc_reg_fcfi_type_mask1_MASK   0x000000FF
1570 #define lpfc_reg_fcfi_type_mask1_WORD   word5
1571 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
1572 #define lpfc_reg_fcfi_rctl_match1_MASK  0x000000FF
1573 #define lpfc_reg_fcfi_rctl_match1_WORD  word5
1574 #define lpfc_reg_fcfi_rctl_mask1_SHIFT  0
1575 #define lpfc_reg_fcfi_rctl_mask1_MASK   0x000000FF
1576 #define lpfc_reg_fcfi_rctl_mask1_WORD   word5
1577         uint32_t word6;
1578 #define lpfc_reg_fcfi_type_match2_SHIFT 24
1579 #define lpfc_reg_fcfi_type_match2_MASK  0x000000FF
1580 #define lpfc_reg_fcfi_type_match2_WORD  word6
1581 #define lpfc_reg_fcfi_type_mask2_SHIFT  16
1582 #define lpfc_reg_fcfi_type_mask2_MASK   0x000000FF
1583 #define lpfc_reg_fcfi_type_mask2_WORD   word6
1584 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
1585 #define lpfc_reg_fcfi_rctl_match2_MASK  0x000000FF
1586 #define lpfc_reg_fcfi_rctl_match2_WORD  word6
1587 #define lpfc_reg_fcfi_rctl_mask2_SHIFT  0
1588 #define lpfc_reg_fcfi_rctl_mask2_MASK   0x000000FF
1589 #define lpfc_reg_fcfi_rctl_mask2_WORD   word6
1590         uint32_t word7;
1591 #define lpfc_reg_fcfi_type_match3_SHIFT 24
1592 #define lpfc_reg_fcfi_type_match3_MASK  0x000000FF
1593 #define lpfc_reg_fcfi_type_match3_WORD  word7
1594 #define lpfc_reg_fcfi_type_mask3_SHIFT  16
1595 #define lpfc_reg_fcfi_type_mask3_MASK   0x000000FF
1596 #define lpfc_reg_fcfi_type_mask3_WORD   word7
1597 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
1598 #define lpfc_reg_fcfi_rctl_match3_MASK  0x000000FF
1599 #define lpfc_reg_fcfi_rctl_match3_WORD  word7
1600 #define lpfc_reg_fcfi_rctl_mask3_SHIFT  0
1601 #define lpfc_reg_fcfi_rctl_mask3_MASK   0x000000FF
1602 #define lpfc_reg_fcfi_rctl_mask3_WORD   word7
1603         uint32_t word8;
1604 #define lpfc_reg_fcfi_mam_SHIFT         13
1605 #define lpfc_reg_fcfi_mam_MASK          0x00000003
1606 #define lpfc_reg_fcfi_mam_WORD          word8
1607 #define LPFC_MAM_BOTH           0       /* Both SPMA and FPMA */
1608 #define LPFC_MAM_SPMA           1       /* Server Provided MAC Address */
1609 #define LPFC_MAM_FPMA           2       /* Fabric Provided MAC Address */
1610 #define lpfc_reg_fcfi_vv_SHIFT          12
1611 #define lpfc_reg_fcfi_vv_MASK           0x00000001
1612 #define lpfc_reg_fcfi_vv_WORD           word8
1613 #define lpfc_reg_fcfi_vlan_tag_SHIFT    0
1614 #define lpfc_reg_fcfi_vlan_tag_MASK     0x00000FFF
1615 #define lpfc_reg_fcfi_vlan_tag_WORD     word8
1616 };
1617
1618 struct lpfc_mbx_unreg_fcfi {
1619         uint32_t word1_rsv;
1620         uint32_t word2;
1621 #define lpfc_unreg_fcfi_SHIFT           0
1622 #define lpfc_unreg_fcfi_MASK            0x0000FFFF
1623 #define lpfc_unreg_fcfi_WORD            word2
1624 };
1625
1626 struct lpfc_mbx_read_rev {
1627         uint32_t word1;
1628 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT           16
1629 #define lpfc_mbx_rd_rev_sli_lvl_MASK            0x0000000F
1630 #define lpfc_mbx_rd_rev_sli_lvl_WORD            word1
1631 #define lpfc_mbx_rd_rev_fcoe_SHIFT              20
1632 #define lpfc_mbx_rd_rev_fcoe_MASK               0x00000001
1633 #define lpfc_mbx_rd_rev_fcoe_WORD               word1
1634 #define lpfc_mbx_rd_rev_cee_ver_SHIFT           21
1635 #define lpfc_mbx_rd_rev_cee_ver_MASK            0x00000003
1636 #define lpfc_mbx_rd_rev_cee_ver_WORD            word1
1637 #define LPFC_PREDCBX_CEE_MODE   0
1638 #define LPFC_DCBX_CEE_MODE      1
1639 #define lpfc_mbx_rd_rev_vpd_SHIFT               29
1640 #define lpfc_mbx_rd_rev_vpd_MASK                0x00000001
1641 #define lpfc_mbx_rd_rev_vpd_WORD                word1
1642         uint32_t first_hw_rev;
1643         uint32_t second_hw_rev;
1644         uint32_t word4_rsvd;
1645         uint32_t third_hw_rev;
1646         uint32_t word6;
1647 #define lpfc_mbx_rd_rev_fcph_low_SHIFT          0
1648 #define lpfc_mbx_rd_rev_fcph_low_MASK           0x000000FF
1649 #define lpfc_mbx_rd_rev_fcph_low_WORD           word6
1650 #define lpfc_mbx_rd_rev_fcph_high_SHIFT         8
1651 #define lpfc_mbx_rd_rev_fcph_high_MASK          0x000000FF
1652 #define lpfc_mbx_rd_rev_fcph_high_WORD          word6
1653 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT       16
1654 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK        0x000000FF
1655 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD        word6
1656 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT      24
1657 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK       0x000000FF
1658 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD       word6
1659         uint32_t word7_rsvd;
1660         uint32_t fw_id_rev;
1661         uint8_t  fw_name[16];
1662         uint32_t ulp_fw_id_rev;
1663         uint8_t  ulp_fw_name[16];
1664         uint32_t word18_47_rsvd[30];
1665         uint32_t word48;
1666 #define lpfc_mbx_rd_rev_avail_len_SHIFT         0
1667 #define lpfc_mbx_rd_rev_avail_len_MASK          0x00FFFFFF
1668 #define lpfc_mbx_rd_rev_avail_len_WORD          word48
1669         uint32_t vpd_paddr_low;
1670         uint32_t vpd_paddr_high;
1671         uint32_t avail_vpd_len;
1672         uint32_t rsvd_52_63[12];
1673 };
1674
1675 struct lpfc_mbx_read_config {
1676         uint32_t word1;
1677 #define lpfc_mbx_rd_conf_max_bbc_SHIFT          0
1678 #define lpfc_mbx_rd_conf_max_bbc_MASK           0x000000FF
1679 #define lpfc_mbx_rd_conf_max_bbc_WORD           word1
1680 #define lpfc_mbx_rd_conf_init_bbc_SHIFT         8
1681 #define lpfc_mbx_rd_conf_init_bbc_MASK          0x000000FF
1682 #define lpfc_mbx_rd_conf_init_bbc_WORD          word1
1683         uint32_t word2;
1684 #define lpfc_mbx_rd_conf_nport_did_SHIFT        0
1685 #define lpfc_mbx_rd_conf_nport_did_MASK         0x00FFFFFF
1686 #define lpfc_mbx_rd_conf_nport_did_WORD         word2
1687 #define lpfc_mbx_rd_conf_topology_SHIFT         24
1688 #define lpfc_mbx_rd_conf_topology_MASK          0x000000FF
1689 #define lpfc_mbx_rd_conf_topology_WORD          word2
1690         uint32_t word3;
1691 #define lpfc_mbx_rd_conf_ao_SHIFT               0
1692 #define lpfc_mbx_rd_conf_ao_MASK                0x00000001
1693 #define lpfc_mbx_rd_conf_ao_WORD                word3
1694 #define lpfc_mbx_rd_conf_bb_scn_SHIFT           8
1695 #define lpfc_mbx_rd_conf_bb_scn_MASK            0x0000000F
1696 #define lpfc_mbx_rd_conf_bb_scn_WORD            word3
1697 #define lpfc_mbx_rd_conf_cbb_scn_SHIFT          12
1698 #define lpfc_mbx_rd_conf_cbb_scn_MASK           0x0000000F
1699 #define lpfc_mbx_rd_conf_cbb_scn_WORD           word3
1700 #define lpfc_mbx_rd_conf_mc_SHIFT               29
1701 #define lpfc_mbx_rd_conf_mc_MASK                0x00000001
1702 #define lpfc_mbx_rd_conf_mc_WORD                word3
1703         uint32_t word4;
1704 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT          0
1705 #define lpfc_mbx_rd_conf_e_d_tov_MASK           0x0000FFFF
1706 #define lpfc_mbx_rd_conf_e_d_tov_WORD           word4
1707         uint32_t word5;
1708 #define lpfc_mbx_rd_conf_lp_tov_SHIFT           0
1709 #define lpfc_mbx_rd_conf_lp_tov_MASK            0x0000FFFF
1710 #define lpfc_mbx_rd_conf_lp_tov_WORD            word5
1711         uint32_t word6;
1712 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT          0
1713 #define lpfc_mbx_rd_conf_r_a_tov_MASK           0x0000FFFF
1714 #define lpfc_mbx_rd_conf_r_a_tov_WORD           word6
1715         uint32_t word7;
1716 #define lpfc_mbx_rd_conf_r_t_tov_SHIFT          0
1717 #define lpfc_mbx_rd_conf_r_t_tov_MASK           0x000000FF
1718 #define lpfc_mbx_rd_conf_r_t_tov_WORD           word7
1719         uint32_t word8;
1720 #define lpfc_mbx_rd_conf_al_tov_SHIFT           0
1721 #define lpfc_mbx_rd_conf_al_tov_MASK            0x0000000F
1722 #define lpfc_mbx_rd_conf_al_tov_WORD            word8
1723         uint32_t word9;
1724 #define lpfc_mbx_rd_conf_lmt_SHIFT              0
1725 #define lpfc_mbx_rd_conf_lmt_MASK               0x0000FFFF
1726 #define lpfc_mbx_rd_conf_lmt_WORD               word9
1727         uint32_t word10;
1728 #define lpfc_mbx_rd_conf_max_alpa_SHIFT         0
1729 #define lpfc_mbx_rd_conf_max_alpa_MASK          0x000000FF
1730 #define lpfc_mbx_rd_conf_max_alpa_WORD          word10
1731         uint32_t word11_rsvd;
1732         uint32_t word12;
1733 #define lpfc_mbx_rd_conf_xri_base_SHIFT         0
1734 #define lpfc_mbx_rd_conf_xri_base_MASK          0x0000FFFF
1735 #define lpfc_mbx_rd_conf_xri_base_WORD          word12
1736 #define lpfc_mbx_rd_conf_xri_count_SHIFT        16
1737 #define lpfc_mbx_rd_conf_xri_count_MASK         0x0000FFFF
1738 #define lpfc_mbx_rd_conf_xri_count_WORD         word12
1739         uint32_t word13;
1740 #define lpfc_mbx_rd_conf_rpi_base_SHIFT         0
1741 #define lpfc_mbx_rd_conf_rpi_base_MASK          0x0000FFFF
1742 #define lpfc_mbx_rd_conf_rpi_base_WORD          word13
1743 #define lpfc_mbx_rd_conf_rpi_count_SHIFT        16
1744 #define lpfc_mbx_rd_conf_rpi_count_MASK         0x0000FFFF
1745 #define lpfc_mbx_rd_conf_rpi_count_WORD         word13
1746         uint32_t word14;
1747 #define lpfc_mbx_rd_conf_vpi_base_SHIFT         0
1748 #define lpfc_mbx_rd_conf_vpi_base_MASK          0x0000FFFF
1749 #define lpfc_mbx_rd_conf_vpi_base_WORD          word14
1750 #define lpfc_mbx_rd_conf_vpi_count_SHIFT        16
1751 #define lpfc_mbx_rd_conf_vpi_count_MASK         0x0000FFFF
1752 #define lpfc_mbx_rd_conf_vpi_count_WORD         word14
1753         uint32_t word15;
1754 #define lpfc_mbx_rd_conf_vfi_base_SHIFT         0
1755 #define lpfc_mbx_rd_conf_vfi_base_MASK          0x0000FFFF
1756 #define lpfc_mbx_rd_conf_vfi_base_WORD          word15
1757 #define lpfc_mbx_rd_conf_vfi_count_SHIFT        16
1758 #define lpfc_mbx_rd_conf_vfi_count_MASK         0x0000FFFF
1759 #define lpfc_mbx_rd_conf_vfi_count_WORD         word15
1760         uint32_t word16;
1761 #define lpfc_mbx_rd_conf_fcfi_base_SHIFT        0
1762 #define lpfc_mbx_rd_conf_fcfi_base_MASK         0x0000FFFF
1763 #define lpfc_mbx_rd_conf_fcfi_base_WORD         word16
1764 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT       16
1765 #define lpfc_mbx_rd_conf_fcfi_count_MASK        0x0000FFFF
1766 #define lpfc_mbx_rd_conf_fcfi_count_WORD        word16
1767         uint32_t word17;
1768 #define lpfc_mbx_rd_conf_rq_count_SHIFT         0
1769 #define lpfc_mbx_rd_conf_rq_count_MASK          0x0000FFFF
1770 #define lpfc_mbx_rd_conf_rq_count_WORD          word17
1771 #define lpfc_mbx_rd_conf_eq_count_SHIFT         16
1772 #define lpfc_mbx_rd_conf_eq_count_MASK          0x0000FFFF
1773 #define lpfc_mbx_rd_conf_eq_count_WORD          word17
1774         uint32_t word18;
1775 #define lpfc_mbx_rd_conf_wq_count_SHIFT         0
1776 #define lpfc_mbx_rd_conf_wq_count_MASK          0x0000FFFF
1777 #define lpfc_mbx_rd_conf_wq_count_WORD          word18
1778 #define lpfc_mbx_rd_conf_cq_count_SHIFT         16
1779 #define lpfc_mbx_rd_conf_cq_count_MASK          0x0000FFFF
1780 #define lpfc_mbx_rd_conf_cq_count_WORD          word18
1781 };
1782
1783 struct lpfc_mbx_request_features {
1784         uint32_t word1;
1785 #define lpfc_mbx_rq_ftr_qry_SHIFT               0
1786 #define lpfc_mbx_rq_ftr_qry_MASK                0x00000001
1787 #define lpfc_mbx_rq_ftr_qry_WORD                word1
1788         uint32_t word2;
1789 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT           0
1790 #define lpfc_mbx_rq_ftr_rq_iaab_MASK            0x00000001
1791 #define lpfc_mbx_rq_ftr_rq_iaab_WORD            word2
1792 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT           1
1793 #define lpfc_mbx_rq_ftr_rq_npiv_MASK            0x00000001
1794 #define lpfc_mbx_rq_ftr_rq_npiv_WORD            word2
1795 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT            2
1796 #define lpfc_mbx_rq_ftr_rq_dif_MASK             0x00000001
1797 #define lpfc_mbx_rq_ftr_rq_dif_WORD             word2
1798 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT             3
1799 #define lpfc_mbx_rq_ftr_rq_vf_MASK              0x00000001
1800 #define lpfc_mbx_rq_ftr_rq_vf_WORD              word2
1801 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT           4
1802 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK            0x00000001
1803 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD            word2
1804 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT           5
1805 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK            0x00000001
1806 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD            word2
1807 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT           6
1808 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK            0x00000001
1809 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD            word2
1810 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT           7
1811 #define lpfc_mbx_rq_ftr_rq_ifip_MASK            0x00000001
1812 #define lpfc_mbx_rq_ftr_rq_ifip_WORD            word2
1813         uint32_t word3;
1814 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT          0
1815 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK           0x00000001
1816 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD           word3
1817 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT          1
1818 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK           0x00000001
1819 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD           word3
1820 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT           2
1821 #define lpfc_mbx_rq_ftr_rsp_dif_MASK            0x00000001
1822 #define lpfc_mbx_rq_ftr_rsp_dif_WORD            word3
1823 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT            3
1824 #define lpfc_mbx_rq_ftr_rsp_vf__MASK            0x00000001
1825 #define lpfc_mbx_rq_ftr_rsp_vf_WORD             word3
1826 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT          4
1827 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK           0x00000001
1828 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD           word3
1829 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT          5
1830 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK           0x00000001
1831 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD           word3
1832 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT          6
1833 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK           0x00000001
1834 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD           word3
1835 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT          7
1836 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK           0x00000001
1837 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD           word3
1838 };
1839
1840 struct lpfc_mbx_supp_pages {
1841         uint32_t word1;
1842 #define qs_SHIFT                                0
1843 #define qs_MASK                                 0x00000001
1844 #define qs_WORD                                 word1
1845 #define wr_SHIFT                                1
1846 #define wr_MASK                                 0x00000001
1847 #define wr_WORD                                 word1
1848 #define pf_SHIFT                                8
1849 #define pf_MASK                                 0x000000ff
1850 #define pf_WORD                                 word1
1851 #define cpn_SHIFT                               16
1852 #define cpn_MASK                                0x000000ff
1853 #define cpn_WORD                                word1
1854         uint32_t word2;
1855 #define list_offset_SHIFT                       0
1856 #define list_offset_MASK                        0x000000ff
1857 #define list_offset_WORD                        word2
1858 #define next_offset_SHIFT                       8
1859 #define next_offset_MASK                        0x000000ff
1860 #define next_offset_WORD                        word2
1861 #define elem_cnt_SHIFT                          16
1862 #define elem_cnt_MASK                           0x000000ff
1863 #define elem_cnt_WORD                           word2
1864         uint32_t word3;
1865 #define pn_0_SHIFT                              24
1866 #define pn_0_MASK                               0x000000ff
1867 #define pn_0_WORD                               word3
1868 #define pn_1_SHIFT                              16
1869 #define pn_1_MASK                               0x000000ff
1870 #define pn_1_WORD                               word3
1871 #define pn_2_SHIFT                              8
1872 #define pn_2_MASK                               0x000000ff
1873 #define pn_2_WORD                               word3
1874 #define pn_3_SHIFT                              0
1875 #define pn_3_MASK                               0x000000ff
1876 #define pn_3_WORD                               word3
1877         uint32_t word4;
1878 #define pn_4_SHIFT                              24
1879 #define pn_4_MASK                               0x000000ff
1880 #define pn_4_WORD                               word4
1881 #define pn_5_SHIFT                              16
1882 #define pn_5_MASK                               0x000000ff
1883 #define pn_5_WORD                               word4
1884 #define pn_6_SHIFT                              8
1885 #define pn_6_MASK                               0x000000ff
1886 #define pn_6_WORD                               word4
1887 #define pn_7_SHIFT                              0
1888 #define pn_7_MASK                               0x000000ff
1889 #define pn_7_WORD                               word4
1890         uint32_t rsvd[27];
1891 #define LPFC_SUPP_PAGES                 0
1892 #define LPFC_BLOCK_GUARD_PROFILES       1
1893 #define LPFC_SLI4_PARAMETERS            2
1894 };
1895
1896 struct lpfc_mbx_sli4_params {
1897         uint32_t word1;
1898 #define qs_SHIFT                                0
1899 #define qs_MASK                                 0x00000001
1900 #define qs_WORD                                 word1
1901 #define wr_SHIFT                                1
1902 #define wr_MASK                                 0x00000001
1903 #define wr_WORD                                 word1
1904 #define pf_SHIFT                                8
1905 #define pf_MASK                                 0x000000ff
1906 #define pf_WORD                                 word1
1907 #define cpn_SHIFT                               16
1908 #define cpn_MASK                                0x000000ff
1909 #define cpn_WORD                                word1
1910         uint32_t word2;
1911 #define if_type_SHIFT                           0
1912 #define if_type_MASK                            0x00000007
1913 #define if_type_WORD                            word2
1914 #define sli_rev_SHIFT                           4
1915 #define sli_rev_MASK                            0x0000000f
1916 #define sli_rev_WORD                            word2
1917 #define sli_family_SHIFT                        8
1918 #define sli_family_MASK                         0x000000ff
1919 #define sli_family_WORD                         word2
1920 #define featurelevel_1_SHIFT                    16
1921 #define featurelevel_1_MASK                     0x000000ff
1922 #define featurelevel_1_WORD                     word2
1923 #define featurelevel_2_SHIFT                    24
1924 #define featurelevel_2_MASK                     0x0000001f
1925 #define featurelevel_2_WORD                     word2
1926         uint32_t word3;
1927 #define fcoe_SHIFT                              0
1928 #define fcoe_MASK                               0x00000001
1929 #define fcoe_WORD                               word3
1930 #define fc_SHIFT                                1
1931 #define fc_MASK                                 0x00000001
1932 #define fc_WORD                                 word3
1933 #define nic_SHIFT                               2
1934 #define nic_MASK                                0x00000001
1935 #define nic_WORD                                word3
1936 #define iscsi_SHIFT                             3
1937 #define iscsi_MASK                              0x00000001
1938 #define iscsi_WORD                              word3
1939 #define rdma_SHIFT                              4
1940 #define rdma_MASK                               0x00000001
1941 #define rdma_WORD                               word3
1942         uint32_t sge_supp_len;
1943         uint32_t word5;
1944 #define if_page_sz_SHIFT                        0
1945 #define if_page_sz_MASK                         0x0000ffff
1946 #define if_page_sz_WORD                         word5
1947 #define loopbk_scope_SHIFT                      24
1948 #define loopbk_scope_MASK                       0x0000000f
1949 #define loopbk_scope_WORD                       word5
1950 #define rq_db_window_SHIFT                      28
1951 #define rq_db_window_MASK                       0x0000000f
1952 #define rq_db_window_WORD                       word5
1953         uint32_t word6;
1954 #define eq_pages_SHIFT                          0
1955 #define eq_pages_MASK                           0x0000000f
1956 #define eq_pages_WORD                           word6
1957 #define eqe_size_SHIFT                          8
1958 #define eqe_size_MASK                           0x000000ff
1959 #define eqe_size_WORD                           word6
1960         uint32_t word7;
1961 #define cq_pages_SHIFT                          0
1962 #define cq_pages_MASK                           0x0000000f
1963 #define cq_pages_WORD                           word7
1964 #define cqe_size_SHIFT                          8
1965 #define cqe_size_MASK                           0x000000ff
1966 #define cqe_size_WORD                           word7
1967         uint32_t word8;
1968 #define mq_pages_SHIFT                          0
1969 #define mq_pages_MASK                           0x0000000f
1970 #define mq_pages_WORD                           word8
1971 #define mqe_size_SHIFT                          8
1972 #define mqe_size_MASK                           0x000000ff
1973 #define mqe_size_WORD                           word8
1974 #define mq_elem_cnt_SHIFT                       16
1975 #define mq_elem_cnt_MASK                        0x000000ff
1976 #define mq_elem_cnt_WORD                        word8
1977         uint32_t word9;
1978 #define wq_pages_SHIFT                          0
1979 #define wq_pages_MASK                           0x0000ffff
1980 #define wq_pages_WORD                           word9
1981 #define wqe_size_SHIFT                          8
1982 #define wqe_size_MASK                           0x000000ff
1983 #define wqe_size_WORD                           word9
1984         uint32_t word10;
1985 #define rq_pages_SHIFT                          0
1986 #define rq_pages_MASK                           0x0000ffff
1987 #define rq_pages_WORD                           word10
1988 #define rqe_size_SHIFT                          8
1989 #define rqe_size_MASK                           0x000000ff
1990 #define rqe_size_WORD                           word10
1991         uint32_t word11;
1992 #define hdr_pages_SHIFT                         0
1993 #define hdr_pages_MASK                          0x0000000f
1994 #define hdr_pages_WORD                          word11
1995 #define hdr_size_SHIFT                          8
1996 #define hdr_size_MASK                           0x0000000f
1997 #define hdr_size_WORD                           word11
1998 #define hdr_pp_align_SHIFT                      16
1999 #define hdr_pp_align_MASK                       0x0000ffff
2000 #define hdr_pp_align_WORD                       word11
2001         uint32_t word12;
2002 #define sgl_pages_SHIFT                         0
2003 #define sgl_pages_MASK                          0x0000000f
2004 #define sgl_pages_WORD                          word12
2005 #define sgl_pp_align_SHIFT                      16
2006 #define sgl_pp_align_MASK                       0x0000ffff
2007 #define sgl_pp_align_WORD                       word12
2008         uint32_t rsvd_13_63[51];
2009 };
2010
2011 /* Mailbox Completion Queue Error Messages */
2012 #define MB_CQE_STATUS_SUCCESS                   0x0
2013 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES   0x1
2014 #define MB_CQE_STATUS_INVALID_PARAMETER         0x2
2015 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES    0x3
2016 #define MB_CEQ_STATUS_QUEUE_FLUSHING            0x4
2017 #define MB_CQE_STATUS_DMA_FAILED                0x5
2018
2019 /* mailbox queue entry structure */
2020 struct lpfc_mqe {
2021         uint32_t word0;
2022 #define lpfc_mqe_status_SHIFT           16
2023 #define lpfc_mqe_status_MASK            0x0000FFFF
2024 #define lpfc_mqe_status_WORD            word0
2025 #define lpfc_mqe_command_SHIFT          8
2026 #define lpfc_mqe_command_MASK           0x000000FF
2027 #define lpfc_mqe_command_WORD           word0
2028         union {
2029                 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
2030                 /* sli4 mailbox commands */
2031                 struct lpfc_mbx_sli4_config sli4_config;
2032                 struct lpfc_mbx_init_vfi init_vfi;
2033                 struct lpfc_mbx_reg_vfi reg_vfi;
2034                 struct lpfc_mbx_reg_vfi unreg_vfi;
2035                 struct lpfc_mbx_init_vpi init_vpi;
2036                 struct lpfc_mbx_resume_rpi resume_rpi;
2037                 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
2038                 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
2039                 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
2040                 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
2041                 struct lpfc_mbx_reg_fcfi reg_fcfi;
2042                 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
2043                 struct lpfc_mbx_mq_create mq_create;
2044                 struct lpfc_mbx_eq_create eq_create;
2045                 struct lpfc_mbx_cq_create cq_create;
2046                 struct lpfc_mbx_wq_create wq_create;
2047                 struct lpfc_mbx_rq_create rq_create;
2048                 struct lpfc_mbx_mq_destroy mq_destroy;
2049                 struct lpfc_mbx_eq_destroy eq_destroy;
2050                 struct lpfc_mbx_cq_destroy cq_destroy;
2051                 struct lpfc_mbx_wq_destroy wq_destroy;
2052                 struct lpfc_mbx_rq_destroy rq_destroy;
2053                 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
2054                 struct lpfc_mbx_nembed_cmd nembed_cmd;
2055                 struct lpfc_mbx_read_rev read_rev;
2056                 struct lpfc_mbx_read_vpi read_vpi;
2057                 struct lpfc_mbx_read_config rd_config;
2058                 struct lpfc_mbx_request_features req_ftrs;
2059                 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
2060                 struct lpfc_mbx_query_fw_cfg query_fw_cfg;
2061                 struct lpfc_mbx_supp_pages supp_pages;
2062                 struct lpfc_mbx_sli4_params sli4_params;
2063                 struct lpfc_mbx_nop nop;
2064         } un;
2065 };
2066
2067 struct lpfc_mcqe {
2068         uint32_t word0;
2069 #define lpfc_mcqe_status_SHIFT          0
2070 #define lpfc_mcqe_status_MASK           0x0000FFFF
2071 #define lpfc_mcqe_status_WORD           word0
2072 #define lpfc_mcqe_ext_status_SHIFT      16
2073 #define lpfc_mcqe_ext_status_MASK       0x0000FFFF
2074 #define lpfc_mcqe_ext_status_WORD       word0
2075         uint32_t mcqe_tag0;
2076         uint32_t mcqe_tag1;
2077         uint32_t trailer;
2078 #define lpfc_trailer_valid_SHIFT        31
2079 #define lpfc_trailer_valid_MASK         0x00000001
2080 #define lpfc_trailer_valid_WORD         trailer
2081 #define lpfc_trailer_async_SHIFT        30
2082 #define lpfc_trailer_async_MASK         0x00000001
2083 #define lpfc_trailer_async_WORD         trailer
2084 #define lpfc_trailer_hpi_SHIFT          29
2085 #define lpfc_trailer_hpi_MASK           0x00000001
2086 #define lpfc_trailer_hpi_WORD           trailer
2087 #define lpfc_trailer_completed_SHIFT    28
2088 #define lpfc_trailer_completed_MASK     0x00000001
2089 #define lpfc_trailer_completed_WORD     trailer
2090 #define lpfc_trailer_consumed_SHIFT     27
2091 #define lpfc_trailer_consumed_MASK      0x00000001
2092 #define lpfc_trailer_consumed_WORD      trailer
2093 #define lpfc_trailer_type_SHIFT         16
2094 #define lpfc_trailer_type_MASK          0x000000FF
2095 #define lpfc_trailer_type_WORD          trailer
2096 #define lpfc_trailer_code_SHIFT         8
2097 #define lpfc_trailer_code_MASK          0x000000FF
2098 #define lpfc_trailer_code_WORD          trailer
2099 #define LPFC_TRAILER_CODE_LINK  0x1
2100 #define LPFC_TRAILER_CODE_FCOE  0x2
2101 #define LPFC_TRAILER_CODE_DCBX  0x3
2102 };
2103
2104 struct lpfc_acqe_link {
2105         uint32_t word0;
2106 #define lpfc_acqe_link_speed_SHIFT              24
2107 #define lpfc_acqe_link_speed_MASK               0x000000FF
2108 #define lpfc_acqe_link_speed_WORD               word0
2109 #define LPFC_ASYNC_LINK_SPEED_ZERO              0x0
2110 #define LPFC_ASYNC_LINK_SPEED_10MBPS            0x1
2111 #define LPFC_ASYNC_LINK_SPEED_100MBPS           0x2
2112 #define LPFC_ASYNC_LINK_SPEED_1GBPS             0x3
2113 #define LPFC_ASYNC_LINK_SPEED_10GBPS            0x4
2114 #define lpfc_acqe_link_duplex_SHIFT             16
2115 #define lpfc_acqe_link_duplex_MASK              0x000000FF
2116 #define lpfc_acqe_link_duplex_WORD              word0
2117 #define LPFC_ASYNC_LINK_DUPLEX_NONE             0x0
2118 #define LPFC_ASYNC_LINK_DUPLEX_HALF             0x1
2119 #define LPFC_ASYNC_LINK_DUPLEX_FULL             0x2
2120 #define lpfc_acqe_link_status_SHIFT             8
2121 #define lpfc_acqe_link_status_MASK              0x000000FF
2122 #define lpfc_acqe_link_status_WORD              word0
2123 #define LPFC_ASYNC_LINK_STATUS_DOWN             0x0
2124 #define LPFC_ASYNC_LINK_STATUS_UP               0x1
2125 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN     0x2
2126 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP       0x3
2127 #define lpfc_acqe_link_physical_SHIFT           0
2128 #define lpfc_acqe_link_physical_MASK            0x000000FF
2129 #define lpfc_acqe_link_physical_WORD            word0
2130 #define LPFC_ASYNC_LINK_PORT_A                  0x0
2131 #define LPFC_ASYNC_LINK_PORT_B                  0x1
2132         uint32_t word1;
2133 #define lpfc_acqe_link_fault_SHIFT      0
2134 #define lpfc_acqe_link_fault_MASK       0x000000FF
2135 #define lpfc_acqe_link_fault_WORD       word1
2136 #define LPFC_ASYNC_LINK_FAULT_NONE      0x0
2137 #define LPFC_ASYNC_LINK_FAULT_LOCAL     0x1
2138 #define LPFC_ASYNC_LINK_FAULT_REMOTE    0x2
2139 #define lpfc_acqe_qos_link_speed_SHIFT  16
2140 #define lpfc_acqe_qos_link_speed_MASK   0x0000FFFF
2141 #define lpfc_acqe_qos_link_speed_WORD   word1
2142         uint32_t event_tag;
2143         uint32_t trailer;
2144 };
2145
2146 struct lpfc_acqe_fcoe {
2147         uint32_t index;
2148         uint32_t word1;
2149 #define lpfc_acqe_fcoe_fcf_count_SHIFT          0
2150 #define lpfc_acqe_fcoe_fcf_count_MASK           0x0000FFFF
2151 #define lpfc_acqe_fcoe_fcf_count_WORD           word1
2152 #define lpfc_acqe_fcoe_event_type_SHIFT         16
2153 #define lpfc_acqe_fcoe_event_type_MASK          0x0000FFFF
2154 #define lpfc_acqe_fcoe_event_type_WORD          word1
2155 #define LPFC_FCOE_EVENT_TYPE_NEW_FCF            0x1
2156 #define LPFC_FCOE_EVENT_TYPE_FCF_TABLE_FULL     0x2
2157 #define LPFC_FCOE_EVENT_TYPE_FCF_DEAD           0x3
2158 #define LPFC_FCOE_EVENT_TYPE_CVL                0x4
2159 #define LPFC_FCOE_EVENT_TYPE_FCF_PARAM_MOD      0x5
2160         uint32_t event_tag;
2161         uint32_t trailer;
2162 };
2163
2164 struct lpfc_acqe_dcbx {
2165         uint32_t tlv_ttl;
2166         uint32_t reserved;
2167         uint32_t event_tag;
2168         uint32_t trailer;
2169 };
2170
2171 /*
2172  * Define the bootstrap mailbox (bmbx) region used to communicate
2173  * mailbox command between the host and port. The mailbox consists
2174  * of a payload area of 256 bytes and a completion queue of length
2175  * 16 bytes.
2176  */
2177 struct lpfc_bmbx_create {
2178         struct lpfc_mqe mqe;
2179         struct lpfc_mcqe mcqe;
2180 };
2181
2182 #define SGL_ALIGN_SZ 64
2183 #define SGL_PAGE_SIZE 4096
2184 /* align SGL addr on a size boundary - adjust address up */
2185 #define NO_XRI  ((uint16_t)-1)
2186
2187 struct wqe_common {
2188         uint32_t word6;
2189 #define wqe_xri_tag_SHIFT     0
2190 #define wqe_xri_tag_MASK      0x0000FFFF
2191 #define wqe_xri_tag_WORD      word6
2192 #define wqe_ctxt_tag_SHIFT    16
2193 #define wqe_ctxt_tag_MASK     0x0000FFFF
2194 #define wqe_ctxt_tag_WORD     word6
2195         uint32_t word7;
2196 #define wqe_ct_SHIFT          2
2197 #define wqe_ct_MASK           0x00000003
2198 #define wqe_ct_WORD           word7
2199 #define wqe_status_SHIFT      4
2200 #define wqe_status_MASK       0x0000000f
2201 #define wqe_status_WORD       word7
2202 #define wqe_cmnd_SHIFT        8
2203 #define wqe_cmnd_MASK         0x000000ff
2204 #define wqe_cmnd_WORD         word7
2205 #define wqe_class_SHIFT       16
2206 #define wqe_class_MASK        0x00000007
2207 #define wqe_class_WORD        word7
2208 #define wqe_pu_SHIFT          20
2209 #define wqe_pu_MASK           0x00000003
2210 #define wqe_pu_WORD           word7
2211 #define wqe_erp_SHIFT         22
2212 #define wqe_erp_MASK          0x00000001
2213 #define wqe_erp_WORD          word7
2214 #define wqe_lnk_SHIFT         23
2215 #define wqe_lnk_MASK          0x00000001
2216 #define wqe_lnk_WORD          word7
2217 #define wqe_tmo_SHIFT         24
2218 #define wqe_tmo_MASK          0x000000ff
2219 #define wqe_tmo_WORD          word7
2220         uint32_t abort_tag; /* word 8 in WQE */
2221         uint32_t word9;
2222 #define wqe_reqtag_SHIFT      0
2223 #define wqe_reqtag_MASK       0x0000FFFF
2224 #define wqe_reqtag_WORD       word9
2225 #define wqe_rcvoxid_SHIFT     16
2226 #define wqe_rcvoxid_MASK       0x0000FFFF
2227 #define wqe_rcvoxid_WORD       word9
2228         uint32_t word10;
2229 #define wqe_pri_SHIFT         16
2230 #define wqe_pri_MASK          0x00000007
2231 #define wqe_pri_WORD          word10
2232 #define wqe_pv_SHIFT          19
2233 #define wqe_pv_MASK           0x00000001
2234 #define wqe_pv_WORD           word10
2235 #define wqe_xc_SHIFT          21
2236 #define wqe_xc_MASK           0x00000001
2237 #define wqe_xc_WORD           word10
2238 #define wqe_ccpe_SHIFT        23
2239 #define wqe_ccpe_MASK         0x00000001
2240 #define wqe_ccpe_WORD         word10
2241 #define wqe_ccp_SHIFT         24
2242 #define wqe_ccp_MASK         0x000000ff
2243 #define wqe_ccp_WORD         word10
2244         uint32_t word11;
2245 #define wqe_cmd_type_SHIFT  0
2246 #define wqe_cmd_type_MASK   0x0000000f
2247 #define wqe_cmd_type_WORD   word11
2248 #define wqe_wqec_SHIFT      7
2249 #define wqe_wqec_MASK       0x00000001
2250 #define wqe_wqec_WORD       word11
2251 #define wqe_cqid_SHIFT      16
2252 #define wqe_cqid_MASK       0x0000ffff
2253 #define wqe_cqid_WORD       word11
2254 };
2255
2256 struct wqe_did {
2257         uint32_t word5;
2258 #define wqe_els_did_SHIFT         0
2259 #define wqe_els_did_MASK          0x00FFFFFF
2260 #define wqe_els_did_WORD          word5
2261 #define wqe_xmit_bls_pt_SHIFT         28
2262 #define wqe_xmit_bls_pt_MASK          0x00000003
2263 #define wqe_xmit_bls_pt_WORD          word5
2264 #define wqe_xmit_bls_ar_SHIFT         30
2265 #define wqe_xmit_bls_ar_MASK          0x00000001
2266 #define wqe_xmit_bls_ar_WORD          word5
2267 #define wqe_xmit_bls_xo_SHIFT         31
2268 #define wqe_xmit_bls_xo_MASK          0x00000001
2269 #define wqe_xmit_bls_xo_WORD          word5
2270 };
2271
2272 struct els_request64_wqe {
2273         struct ulp_bde64 bde;
2274         uint32_t payload_len;
2275         uint32_t word4;
2276 #define els_req64_sid_SHIFT         0
2277 #define els_req64_sid_MASK          0x00FFFFFF
2278 #define els_req64_sid_WORD          word4
2279 #define els_req64_sp_SHIFT          24
2280 #define els_req64_sp_MASK           0x00000001
2281 #define els_req64_sp_WORD           word4
2282 #define els_req64_vf_SHIFT          25
2283 #define els_req64_vf_MASK           0x00000001
2284 #define els_req64_vf_WORD           word4
2285         struct wqe_did  wqe_dest;
2286         struct wqe_common wqe_com; /* words 6-11 */
2287         uint32_t word12;
2288 #define els_req64_vfid_SHIFT        1
2289 #define els_req64_vfid_MASK         0x00000FFF
2290 #define els_req64_vfid_WORD         word12
2291 #define els_req64_pri_SHIFT         13
2292 #define els_req64_pri_MASK          0x00000007
2293 #define els_req64_pri_WORD          word12
2294         uint32_t word13;
2295 #define els_req64_hopcnt_SHIFT      24
2296 #define els_req64_hopcnt_MASK       0x000000ff
2297 #define els_req64_hopcnt_WORD       word13
2298         uint32_t reserved[2];
2299 };
2300
2301 struct xmit_els_rsp64_wqe {
2302         struct ulp_bde64 bde;
2303         uint32_t rsvd3;
2304         uint32_t rsvd4;
2305         struct wqe_did  wqe_dest;
2306         struct wqe_common wqe_com; /* words 6-11 */
2307         uint32_t rsvd_12_15[4];
2308 };
2309
2310 struct xmit_bls_rsp64_wqe {
2311         uint32_t payload0;
2312 /* Payload0 for BA_ACC */
2313 #define xmit_bls_rsp64_acc_seq_id_SHIFT        16
2314 #define xmit_bls_rsp64_acc_seq_id_MASK         0x000000ff
2315 #define xmit_bls_rsp64_acc_seq_id_WORD         payload0
2316 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT   24
2317 #define xmit_bls_rsp64_acc_seq_id_vald_MASK    0x000000ff
2318 #define xmit_bls_rsp64_acc_seq_id_vald_WORD    payload0
2319 /* Payload0 for BA_RJT */
2320 #define xmit_bls_rsp64_rjt_vspec_SHIFT   0
2321 #define xmit_bls_rsp64_rjt_vspec_MASK    0x000000ff
2322 #define xmit_bls_rsp64_rjt_vspec_WORD    payload0
2323 #define xmit_bls_rsp64_rjt_expc_SHIFT    8
2324 #define xmit_bls_rsp64_rjt_expc_MASK     0x000000ff
2325 #define xmit_bls_rsp64_rjt_expc_WORD     payload0
2326 #define xmit_bls_rsp64_rjt_rsnc_SHIFT    16
2327 #define xmit_bls_rsp64_rjt_rsnc_MASK     0x000000ff
2328 #define xmit_bls_rsp64_rjt_rsnc_WORD     payload0
2329         uint32_t word1;
2330 #define xmit_bls_rsp64_rxid_SHIFT  0
2331 #define xmit_bls_rsp64_rxid_MASK   0x0000ffff
2332 #define xmit_bls_rsp64_rxid_WORD   word1
2333 #define xmit_bls_rsp64_oxid_SHIFT  16
2334 #define xmit_bls_rsp64_oxid_MASK   0x0000ffff
2335 #define xmit_bls_rsp64_oxid_WORD   word1
2336         uint32_t word2;
2337 #define xmit_bls_rsp64_seqcnthi_SHIFT  0
2338 #define xmit_bls_rsp64_seqcnthi_MASK   0x0000ffff
2339 #define xmit_bls_rsp64_seqcnthi_WORD   word2
2340 #define xmit_bls_rsp64_seqcntlo_SHIFT  16
2341 #define xmit_bls_rsp64_seqcntlo_MASK   0x0000ffff
2342 #define xmit_bls_rsp64_seqcntlo_WORD   word2
2343         uint32_t rsrvd3;
2344         uint32_t rsrvd4;
2345         struct wqe_did  wqe_dest;
2346         struct wqe_common wqe_com; /* words 6-11 */
2347         uint32_t rsvd_12_15[4];
2348 };
2349
2350 struct wqe_rctl_dfctl {
2351         uint32_t word5;
2352 #define wqe_si_SHIFT 2
2353 #define wqe_si_MASK  0x000000001
2354 #define wqe_si_WORD  word5
2355 #define wqe_la_SHIFT 3
2356 #define wqe_la_MASK  0x000000001
2357 #define wqe_la_WORD  word5
2358 #define wqe_ls_SHIFT 7
2359 #define wqe_ls_MASK  0x000000001
2360 #define wqe_ls_WORD  word5
2361 #define wqe_dfctl_SHIFT 8
2362 #define wqe_dfctl_MASK  0x0000000ff
2363 #define wqe_dfctl_WORD  word5
2364 #define wqe_type_SHIFT 16
2365 #define wqe_type_MASK  0x0000000ff
2366 #define wqe_type_WORD  word5
2367 #define wqe_rctl_SHIFT 24
2368 #define wqe_rctl_MASK  0x0000000ff
2369 #define wqe_rctl_WORD  word5
2370 };
2371
2372 struct xmit_seq64_wqe {
2373         struct ulp_bde64 bde;
2374         uint32_t paylaod_offset;
2375         uint32_t relative_offset;
2376         struct wqe_rctl_dfctl wge_ctl;
2377         struct wqe_common wqe_com; /* words 6-11 */
2378         /* Note: word10 different REVISIT */
2379         uint32_t xmit_len;
2380         uint32_t rsvd_12_15[3];
2381 };
2382 struct xmit_bcast64_wqe {
2383         struct ulp_bde64 bde;
2384         uint32_t paylaod_len;
2385         uint32_t rsvd4;
2386         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
2387         struct wqe_common wqe_com;     /* words 6-11 */
2388         uint32_t rsvd_12_15[4];
2389 };
2390
2391 struct gen_req64_wqe {
2392         struct ulp_bde64 bde;
2393         uint32_t command_len;
2394         uint32_t payload_len;
2395         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
2396         struct wqe_common wqe_com;     /* words 6-11 */
2397         uint32_t rsvd_12_15[4];
2398 };
2399
2400 struct create_xri_wqe {
2401         uint32_t rsrvd[5];           /* words 0-4 */
2402         struct wqe_did  wqe_dest;  /* word 5 */
2403         struct wqe_common wqe_com; /* words 6-11 */
2404         uint32_t rsvd_12_15[4];         /* word 12-15 */
2405 };
2406
2407 #define T_REQUEST_TAG 3
2408 #define T_XRI_TAG 1
2409
2410 struct abort_cmd_wqe {
2411         uint32_t rsrvd[3];
2412         uint32_t word3;
2413 #define abort_cmd_ia_SHIFT  0
2414 #define abort_cmd_ia_MASK  0x000000001
2415 #define abort_cmd_ia_WORD  word3
2416 #define abort_cmd_criteria_SHIFT  8
2417 #define abort_cmd_criteria_MASK  0x0000000ff
2418 #define abort_cmd_criteria_WORD  word3
2419         uint32_t rsrvd4;
2420         uint32_t rsrvd5;
2421         struct wqe_common wqe_com;     /* words 6-11 */
2422         uint32_t rsvd_12_15[4];         /* word 12-15 */
2423 };
2424
2425 struct fcp_iwrite64_wqe {
2426         struct ulp_bde64 bde;
2427         uint32_t payload_len;
2428         uint32_t total_xfer_len;
2429         uint32_t initial_xfer_len;
2430         struct wqe_common wqe_com;     /* words 6-11 */
2431         uint32_t rsvd_12_15[4];         /* word 12-15 */
2432 };
2433
2434 struct fcp_iread64_wqe {
2435         struct ulp_bde64 bde;
2436         uint32_t payload_len;          /* word 3 */
2437         uint32_t total_xfer_len;       /* word 4 */
2438         uint32_t rsrvd5;               /* word 5 */
2439         struct wqe_common wqe_com;     /* words 6-11 */
2440         uint32_t rsvd_12_15[4];         /* word 12-15 */
2441 };
2442
2443 struct fcp_icmnd64_wqe {
2444         struct ulp_bde64 bde;    /* words 0-2 */
2445         uint32_t rsrvd[3];             /* words 3-5 */
2446         struct wqe_common wqe_com;     /* words 6-11 */
2447         uint32_t rsvd_12_15[4];         /* word 12-15 */
2448 };
2449
2450
2451 union lpfc_wqe {
2452         uint32_t words[16];
2453         struct lpfc_wqe_generic generic;
2454         struct fcp_icmnd64_wqe fcp_icmd;
2455         struct fcp_iread64_wqe fcp_iread;
2456         struct fcp_iwrite64_wqe fcp_iwrite;
2457         struct abort_cmd_wqe abort_cmd;
2458         struct create_xri_wqe create_xri;
2459         struct xmit_bcast64_wqe xmit_bcast64;
2460         struct xmit_seq64_wqe xmit_sequence;
2461         struct xmit_bls_rsp64_wqe xmit_bls_rsp;
2462         struct xmit_els_rsp64_wqe xmit_els_rsp;
2463         struct els_request64_wqe els_req;
2464         struct gen_req64_wqe gen_req;
2465 };
2466
2467 #define FCP_COMMAND 0x0
2468 #define FCP_COMMAND_DATA_OUT 0x1
2469 #define ELS_COMMAND_NON_FIP 0xC
2470 #define ELS_COMMAND_FIP 0xD
2471 #define OTHER_COMMAND 0x8
2472