drivers/scsi/lpfc/lpfc_hw4.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2009 Emulex.  All rights reserved.                *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *******************************************************************/
  20
  21 /* Macros to deal with bit fields. Each bit field must have 3 #defines
  22  * associated with it (_SHIFT, _MASK, and _WORD).
  23  * EG. For a bit field that is in the 7th bit of the "field4" field of a
  24  * structure and is 2 bits in size the following #defines must exist:
  25  *      struct temp {
  26  *              uint32_t        field1;
  27  *              uint32_t        field2;
  28  *              uint32_t        field3;
  29  *              uint32_t        field4;
  30  *      #define example_bit_field_SHIFT         7
  31  *      #define example_bit_field_MASK          0x03
  32  *      #define example_bit_field_WORD          field4
  33  *              uint32_t        field5;
  34  *      };
  35  * Then the macros below may be used to get or set the value of that field.
  36  * EG. To get the value of the bit field from the above example:
  37  *      struct temp t1;
  38  *      value = bf_get(example_bit_field, &t1);
  39  * And then to set that bit field:
  40  *      bf_set(example_bit_field, &t1, 2);
  41  * Or clear that bit field:
  42  *      bf_set(example_bit_field, &t1, 0);
  43  */
  44 #define bf_get_le32(name, ptr) \
  45         ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
  46 #define bf_get(name, ptr) \
  47         (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
  48 #define bf_set_le32(name, ptr, value) \
  49         ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
  50         name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
  51         ~(name##_MASK << name##_SHIFT)))))
  52 #define bf_set(name, ptr, value) \
  53         ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
  54                  ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
  55
  56 struct dma_address {
  57         uint32_t addr_lo;
  58         uint32_t addr_hi;
  59 };
  60
  61 struct lpfc_sli_intf {
  62         uint32_t word0;
  63 #define lpfc_sli_intf_valid_SHIFT               29
  64 #define lpfc_sli_intf_valid_MASK                0x00000007
  65 #define lpfc_sli_intf_valid_WORD                word0
  66 #define LPFC_SLI_INTF_VALID             6
  67 #define lpfc_sli_intf_sli_hint2_SHIFT           24
  68 #define lpfc_sli_intf_sli_hint2_MASK            0x0000001F
  69 #define lpfc_sli_intf_sli_hint2_WORD            word0
  70 #define LPFC_SLI_INTF_SLI_HINT2_NONE    0
  71 #define lpfc_sli_intf_sli_hint1_SHIFT           16
  72 #define lpfc_sli_intf_sli_hint1_MASK            0x000000FF
  73 #define lpfc_sli_intf_sli_hint1_WORD            word0
  74 #define LPFC_SLI_INTF_SLI_HINT1_NONE    0
  75 #define LPFC_SLI_INTF_SLI_HINT1_1       1
  76 #define LPFC_SLI_INTF_SLI_HINT1_2       2
  77 #define lpfc_sli_intf_if_type_SHIFT             12
  78 #define lpfc_sli_intf_if_type_MASK              0x0000000F
  79 #define lpfc_sli_intf_if_type_WORD              word0
  80 #define LPFC_SLI_INTF_IF_TYPE_0         0
  81 #define LPFC_SLI_INTF_IF_TYPE_1         1
  82 #define LPFC_SLI_INTF_IF_TYPE_2         2
  83 #define lpfc_sli_intf_sli_family_SHIFT          8
  84 #define lpfc_sli_intf_sli_family_MASK           0x0000000F
  85 #define lpfc_sli_intf_sli_family_WORD           word0
  86 #define LPFC_SLI_INTF_FAMILY_BE2        0x0
  87 #define LPFC_SLI_INTF_FAMILY_BE3        0x1
  88 #define LPFC_SLI_INTF_FAMILY_LNCR_A0    0xa
  89 #define LPFC_SLI_INTF_FAMILY_LNCR_B0    0xb
  90 #define lpfc_sli_intf_slirev_SHIFT              4
  91 #define lpfc_sli_intf_slirev_MASK               0x0000000F
  92 #define lpfc_sli_intf_slirev_WORD               word0
  93 #define LPFC_SLI_INTF_REV_SLI3          3
  94 #define LPFC_SLI_INTF_REV_SLI4          4
  95 #define lpfc_sli_intf_func_type_SHIFT           0
  96 #define lpfc_sli_intf_func_type_MASK            0x00000001
  97 #define lpfc_sli_intf_func_type_WORD            word0
  98 #define LPFC_SLI_INTF_IF_TYPE_PHYS      0
  99 #define LPFC_SLI_INTF_IF_TYPE_VIRT      1
 100 };
 101
 102 #define LPFC_SLI4_MBX_EMBED     true
 103 #define LPFC_SLI4_MBX_NEMBED    false
 104
 105 #define LPFC_SLI4_MB_WORD_COUNT         64
 106 #define LPFC_MAX_MQ_PAGE                8
 107 #define LPFC_MAX_WQ_PAGE                8
 108 #define LPFC_MAX_CQ_PAGE                4
 109 #define LPFC_MAX_EQ_PAGE                8
 110
 111 #define LPFC_VIR_FUNC_MAX       32 /* Maximum number of virtual functions */
 112 #define LPFC_PCI_FUNC_MAX        5 /* Maximum number of PCI functions */
 113 #define LPFC_VFR_PAGE_SIZE      0x1000 /* 4KB BAR2 per-VF register page size */
 114
 115 /* Define SLI4 Alignment requirements. */
 116 #define LPFC_ALIGN_16_BYTE      16
 117 #define LPFC_ALIGN_64_BYTE      64
 118
 119 /* Define SLI4 specific definitions. */
 120 #define LPFC_MQ_CQE_BYTE_OFFSET 256
 121 #define LPFC_MBX_CMD_HDR_LENGTH 16
 122 #define LPFC_MBX_ERROR_RANGE    0x4000
 123 #define LPFC_BMBX_BIT1_ADDR_HI  0x2
 124 #define LPFC_BMBX_BIT1_ADDR_LO  0
 125 #define LPFC_RPI_HDR_COUNT      64
 126 #define LPFC_HDR_TEMPLATE_SIZE  4096
 127 #define LPFC_RPI_ALLOC_ERROR    0xFFFF
 128 #define LPFC_FCF_RECORD_WD_CNT  132
 129 #define LPFC_ENTIRE_FCF_DATABASE 0
 130 #define LPFC_DFLT_FCF_INDEX      0
 131
 132 /* Virtual function numbers */
 133 #define LPFC_VF0                0
 134 #define LPFC_VF1                1
 135 #define LPFC_VF2                2
 136 #define LPFC_VF3                3
 137 #define LPFC_VF4                4
 138 #define LPFC_VF5                5
 139 #define LPFC_VF6                6
 140 #define LPFC_VF7                7
 141 #define LPFC_VF8                8
 142 #define LPFC_VF9                9
 143 #define LPFC_VF10               10
 144 #define LPFC_VF11               11
 145 #define LPFC_VF12               12
 146 #define LPFC_VF13               13
 147 #define LPFC_VF14               14
 148 #define LPFC_VF15               15
 149 #define LPFC_VF16               16
 150 #define LPFC_VF17               17
 151 #define LPFC_VF18               18
 152 #define LPFC_VF19               19
 153 #define LPFC_VF20               20
 154 #define LPFC_VF21               21
 155 #define LPFC_VF22               22
 156 #define LPFC_VF23               23
 157 #define LPFC_VF24               24
 158 #define LPFC_VF25               25
 159 #define LPFC_VF26               26
 160 #define LPFC_VF27               27
 161 #define LPFC_VF28               28
 162 #define LPFC_VF29               29
 163 #define LPFC_VF30               30
 164 #define LPFC_VF31               31
 165
 166 /* PCI function numbers */
 167 #define LPFC_PCI_FUNC0          0
 168 #define LPFC_PCI_FUNC1          1
 169 #define LPFC_PCI_FUNC2          2
 170 #define LPFC_PCI_FUNC3          3
 171 #define LPFC_PCI_FUNC4          4
 172
 173 /* SLI4 interface type-2 control register offsets */
 174 #define LPFC_CTL_PORT_SEM_OFFSET        0x400
 175 #define LPFC_CTL_PORT_STA_OFFSET        0x404
 176 #define LPFC_CTL_PORT_CTL_OFFSET        0x408
 177 #define LPFC_CTL_PORT_ER1_OFFSET        0x40C
 178 #define LPFC_CTL_PORT_ER2_OFFSET        0x410
 179 #define LPFC_CTL_PDEV_CTL_OFFSET        0x414
 180
 181 /* Some SLI4 interface type-2 PDEV_CTL register bits */
 182 #define LPFC_CTL_PDEV_CTL_DRST          0x00000001
 183 #define LPFC_CTL_PDEV_CTL_FRST          0x00000002
 184 #define LPFC_CTL_PDEV_CTL_DD            0x00000004
 185 #define LPFC_CTL_PDEV_CTL_LC            0x00000008
 186 #define LPFC_CTL_PDEV_CTL_FRL_ALL       0x00
 187 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE   0x10
 188 #define LPFC_CTL_PDEV_CTL_FRL_NIC       0x20
 189
 190 #define LPFC_FW_DUMP_REQUEST    (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
 191
 192 /* Active interrupt test count */
 193 #define LPFC_ACT_INTR_CNT       4
 194
 195 /* Delay Multiplier constant */
 196 #define LPFC_DMULT_CONST       651042
 197 #define LPFC_MIM_IMAX          636
 198 #define LPFC_FP_DEF_IMAX       10000
 199 #define LPFC_SP_DEF_IMAX       10000
 200
 201 /* PORT_CAPABILITIES constants. */
 202 #define LPFC_MAX_SUPPORTED_PAGES        8
 203
 204 struct ulp_bde64 {
 205         union ULP_BDE_TUS {
 206                 uint32_t w;
 207                 struct {
 208 #ifdef __BIG_ENDIAN_BITFIELD
 209                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 210                                                    VALUE !! */
 211                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 212 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 213                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 214                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 215                                                    VALUE !! */
 216 #endif
 217 #define BUFF_TYPE_BDE_64    0x00        /* BDE (Host_resident) */
 218 #define BUFF_TYPE_BDE_IMMED 0x01        /* Immediate Data BDE */
 219 #define BUFF_TYPE_BDE_64P   0x02        /* BDE (Port-resident) */
 220 #define BUFF_TYPE_BDE_64I   0x08        /* Input BDE (Host-resident) */
 221 #define BUFF_TYPE_BDE_64IP  0x0A        /* Input BDE (Port-resident) */
 222 #define BUFF_TYPE_BLP_64    0x40        /* BLP (Host-resident) */
 223 #define BUFF_TYPE_BLP_64P   0x42        /* BLP (Port-resident) */
 224                 } f;
 225         } tus;
 226         uint32_t addrLow;
 227         uint32_t addrHigh;
 228 };
 229
 230 struct lpfc_sli4_flags {
 231         uint32_t word0;
 232 #define lpfc_idx_rsrc_rdy_SHIFT         0
 233 #define lpfc_idx_rsrc_rdy_MASK          0x00000001
 234 #define lpfc_idx_rsrc_rdy_WORD          word0
 235 #define LPFC_IDX_RSRC_RDY               1
 236 #define lpfc_xri_rsrc_rdy_SHIFT         1
 237 #define lpfc_xri_rsrc_rdy_MASK          0x00000001
 238 #define lpfc_xri_rsrc_rdy_WORD          word0
 239 #define LPFC_XRI_RSRC_RDY               1
 240 #define lpfc_rpi_rsrc_rdy_SHIFT         2
 241 #define lpfc_rpi_rsrc_rdy_MASK          0x00000001
 242 #define lpfc_rpi_rsrc_rdy_WORD          word0
 243 #define LPFC_RPI_RSRC_RDY               1
 244 #define lpfc_vpi_rsrc_rdy_SHIFT         3
 245 #define lpfc_vpi_rsrc_rdy_MASK          0x00000001
 246 #define lpfc_vpi_rsrc_rdy_WORD          word0
 247 #define LPFC_VPI_RSRC_RDY               1
 248 #define lpfc_vfi_rsrc_rdy_SHIFT         4
 249 #define lpfc_vfi_rsrc_rdy_MASK          0x00000001
 250 #define lpfc_vfi_rsrc_rdy_WORD          word0
 251 #define LPFC_VFI_RSRC_RDY               1
 252 };
 253
 254 struct sli4_bls_rsp {
 255         uint32_t word0_rsvd;      /* Word0 must be reserved */
 256         uint32_t word1;
 257 #define lpfc_abts_orig_SHIFT      0
 258 #define lpfc_abts_orig_MASK       0x00000001
 259 #define lpfc_abts_orig_WORD       word1
 260 #define LPFC_ABTS_UNSOL_RSP       1
 261 #define LPFC_ABTS_UNSOL_INT       0
 262         uint32_t word2;
 263 #define lpfc_abts_rxid_SHIFT      0
 264 #define lpfc_abts_rxid_MASK       0x0000FFFF
 265 #define lpfc_abts_rxid_WORD       word2
 266 #define lpfc_abts_oxid_SHIFT      16
 267 #define lpfc_abts_oxid_MASK       0x0000FFFF
 268 #define lpfc_abts_oxid_WORD       word2
 269         uint32_t word3;
 270 #define lpfc_vndr_code_SHIFT    0
 271 #define lpfc_vndr_code_MASK     0x000000FF
 272 #define lpfc_vndr_code_WORD     word3
 273 #define lpfc_rsn_expln_SHIFT    8
 274 #define lpfc_rsn_expln_MASK     0x000000FF
 275 #define lpfc_rsn_expln_WORD     word3
 276 #define lpfc_rsn_code_SHIFT     16
 277 #define lpfc_rsn_code_MASK      0x000000FF
 278 #define lpfc_rsn_code_WORD      word3
 279
 280         uint32_t word4;
 281         uint32_t word5_rsvd;    /* Word5 must be reserved */
 282 };
 283
 284 /* event queue entry structure */
 285 struct lpfc_eqe {
 286         uint32_t word0;
 287 #define lpfc_eqe_resource_id_SHIFT      16
 288 #define lpfc_eqe_resource_id_MASK       0x000000FF
 289 #define lpfc_eqe_resource_id_WORD       word0
 290 #define lpfc_eqe_minor_code_SHIFT       4
 291 #define lpfc_eqe_minor_code_MASK        0x00000FFF
 292 #define lpfc_eqe_minor_code_WORD        word0
 293 #define lpfc_eqe_major_code_SHIFT       1
 294 #define lpfc_eqe_major_code_MASK        0x00000007
 295 #define lpfc_eqe_major_code_WORD        word0
 296 #define lpfc_eqe_valid_SHIFT            0
 297 #define lpfc_eqe_valid_MASK             0x00000001
 298 #define lpfc_eqe_valid_WORD             word0
 299 };
 300
 301 /* completion queue entry structure (common fields for all cqe types) */
 302 struct lpfc_cqe {
 303         uint32_t reserved0;
 304         uint32_t reserved1;
 305         uint32_t reserved2;
 306         uint32_t word3;
 307 #define lpfc_cqe_valid_SHIFT            31
 308 #define lpfc_cqe_valid_MASK             0x00000001
 309 #define lpfc_cqe_valid_WORD             word3
 310 #define lpfc_cqe_code_SHIFT             16
 311 #define lpfc_cqe_code_MASK              0x000000FF
 312 #define lpfc_cqe_code_WORD              word3
 313 };
 314
 315 /* Completion Queue Entry Status Codes */
 316 #define CQE_STATUS_SUCCESS              0x0
 317 #define CQE_STATUS_FCP_RSP_FAILURE      0x1
 318 #define CQE_STATUS_REMOTE_STOP          0x2
 319 #define CQE_STATUS_LOCAL_REJECT         0x3
 320 #define CQE_STATUS_NPORT_RJT            0x4
 321 #define CQE_STATUS_FABRIC_RJT           0x5
 322 #define CQE_STATUS_NPORT_BSY            0x6
 323 #define CQE_STATUS_FABRIC_BSY           0x7
 324 #define CQE_STATUS_INTERMED_RSP         0x8
 325 #define CQE_STATUS_LS_RJT               0x9
 326 #define CQE_STATUS_CMD_REJECT           0xb
 327 #define CQE_STATUS_FCP_TGT_LENCHECK     0xc
 328 #define CQE_STATUS_NEED_BUFF_ENTRY      0xf
 329
 330 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
 331 #define CQE_HW_STATUS_NO_ERR            0x0
 332 #define CQE_HW_STATUS_UNDERRUN          0x1
 333 #define CQE_HW_STATUS_OVERRUN           0x2
 334
 335 /* Completion Queue Entry Codes */
 336 #define CQE_CODE_COMPL_WQE              0x1
 337 #define CQE_CODE_RELEASE_WQE            0x2
 338 #define CQE_CODE_RECEIVE                0x4
 339 #define CQE_CODE_XRI_ABORTED            0x5
 340
 341 /* completion queue entry for wqe completions */
 342 struct lpfc_wcqe_complete {
 343         uint32_t word0;
 344 #define lpfc_wcqe_c_request_tag_SHIFT   16
 345 #define lpfc_wcqe_c_request_tag_MASK    0x0000FFFF
 346 #define lpfc_wcqe_c_request_tag_WORD    word0
 347 #define lpfc_wcqe_c_status_SHIFT        8
 348 #define lpfc_wcqe_c_status_MASK         0x000000FF
 349 #define lpfc_wcqe_c_status_WORD         word0
 350 #define lpfc_wcqe_c_hw_status_SHIFT     0
 351 #define lpfc_wcqe_c_hw_status_MASK      0x000000FF
 352 #define lpfc_wcqe_c_hw_status_WORD      word0
 353         uint32_t total_data_placed;
 354         uint32_t parameter;
 355         uint32_t word3;
 356 #define lpfc_wcqe_c_valid_SHIFT         lpfc_cqe_valid_SHIFT
 357 #define lpfc_wcqe_c_valid_MASK          lpfc_cqe_valid_MASK
 358 #define lpfc_wcqe_c_valid_WORD          lpfc_cqe_valid_WORD
 359 #define lpfc_wcqe_c_xb_SHIFT            28
 360 #define lpfc_wcqe_c_xb_MASK             0x00000001
 361 #define lpfc_wcqe_c_xb_WORD             word3
 362 #define lpfc_wcqe_c_pv_SHIFT            27
 363 #define lpfc_wcqe_c_pv_MASK             0x00000001
 364 #define lpfc_wcqe_c_pv_WORD             word3
 365 #define lpfc_wcqe_c_priority_SHIFT      24
 366 #define lpfc_wcqe_c_priority_MASK               0x00000007
 367 #define lpfc_wcqe_c_priority_WORD               word3
 368 #define lpfc_wcqe_c_code_SHIFT          lpfc_cqe_code_SHIFT
 369 #define lpfc_wcqe_c_code_MASK           lpfc_cqe_code_MASK
 370 #define lpfc_wcqe_c_code_WORD           lpfc_cqe_code_WORD
 371 };
 372
 373 /* completion queue entry for wqe release */
 374 struct lpfc_wcqe_release {
 375         uint32_t reserved0;
 376         uint32_t reserved1;
 377         uint32_t word2;
 378 #define lpfc_wcqe_r_wq_id_SHIFT         16
 379 #define lpfc_wcqe_r_wq_id_MASK          0x0000FFFF
 380 #define lpfc_wcqe_r_wq_id_WORD          word2
 381 #define lpfc_wcqe_r_wqe_index_SHIFT     0
 382 #define lpfc_wcqe_r_wqe_index_MASK      0x0000FFFF
 383 #define lpfc_wcqe_r_wqe_index_WORD      word2
 384         uint32_t word3;
 385 #define lpfc_wcqe_r_valid_SHIFT         lpfc_cqe_valid_SHIFT
 386 #define lpfc_wcqe_r_valid_MASK          lpfc_cqe_valid_MASK
 387 #define lpfc_wcqe_r_valid_WORD          lpfc_cqe_valid_WORD
 388 #define lpfc_wcqe_r_code_SHIFT          lpfc_cqe_code_SHIFT
 389 #define lpfc_wcqe_r_code_MASK           lpfc_cqe_code_MASK
 390 #define lpfc_wcqe_r_code_WORD           lpfc_cqe_code_WORD
 391 };
 392
 393 struct sli4_wcqe_xri_aborted {
 394         uint32_t word0;
 395 #define lpfc_wcqe_xa_status_SHIFT               8
 396 #define lpfc_wcqe_xa_status_MASK                0x000000FF
 397 #define lpfc_wcqe_xa_status_WORD                word0
 398         uint32_t parameter;
 399         uint32_t word2;
 400 #define lpfc_wcqe_xa_remote_xid_SHIFT   16
 401 #define lpfc_wcqe_xa_remote_xid_MASK    0x0000FFFF
 402 #define lpfc_wcqe_xa_remote_xid_WORD    word2
 403 #define lpfc_wcqe_xa_xri_SHIFT          0
 404 #define lpfc_wcqe_xa_xri_MASK           0x0000FFFF
 405 #define lpfc_wcqe_xa_xri_WORD           word2
 406         uint32_t word3;
 407 #define lpfc_wcqe_xa_valid_SHIFT        lpfc_cqe_valid_SHIFT
 408 #define lpfc_wcqe_xa_valid_MASK         lpfc_cqe_valid_MASK
 409 #define lpfc_wcqe_xa_valid_WORD         lpfc_cqe_valid_WORD
 410 #define lpfc_wcqe_xa_ia_SHIFT           30
 411 #define lpfc_wcqe_xa_ia_MASK            0x00000001
 412 #define lpfc_wcqe_xa_ia_WORD            word3
 413 #define CQE_XRI_ABORTED_IA_REMOTE       0
 414 #define CQE_XRI_ABORTED_IA_LOCAL        1
 415 #define lpfc_wcqe_xa_br_SHIFT           29
 416 #define lpfc_wcqe_xa_br_MASK            0x00000001
 417 #define lpfc_wcqe_xa_br_WORD            word3
 418 #define CQE_XRI_ABORTED_BR_BA_ACC       0
 419 #define CQE_XRI_ABORTED_BR_BA_RJT       1
 420 #define lpfc_wcqe_xa_eo_SHIFT           28
 421 #define lpfc_wcqe_xa_eo_MASK            0x00000001
 422 #define lpfc_wcqe_xa_eo_WORD            word3
 423 #define CQE_XRI_ABORTED_EO_REMOTE       0
 424 #define CQE_XRI_ABORTED_EO_LOCAL        1
 425 #define lpfc_wcqe_xa_code_SHIFT         lpfc_cqe_code_SHIFT
 426 #define lpfc_wcqe_xa_code_MASK          lpfc_cqe_code_MASK
 427 #define lpfc_wcqe_xa_code_WORD          lpfc_cqe_code_WORD
 428 };
 429
 430 /* completion queue entry structure for rqe completion */
 431 struct lpfc_rcqe {
 432         uint32_t word0;
 433 #define lpfc_rcqe_bindex_SHIFT          16
 434 #define lpfc_rcqe_bindex_MASK           0x0000FFF
 435 #define lpfc_rcqe_bindex_WORD           word0
 436 #define lpfc_rcqe_status_SHIFT          8
 437 #define lpfc_rcqe_status_MASK           0x000000FF
 438 #define lpfc_rcqe_status_WORD           word0
 439 #define FC_STATUS_RQ_SUCCESS            0x10 /* Async receive successful */
 440 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED   0x11 /* payload truncated */
 441 #define FC_STATUS_INSUFF_BUF_NEED_BUF   0x12 /* Insufficient buffers */
 442 #define FC_STATUS_INSUFF_BUF_FRM_DISC   0x13 /* Frame Discard */
 443         uint32_t reserved1;
 444         uint32_t word2;
 445 #define lpfc_rcqe_length_SHIFT          16
 446 #define lpfc_rcqe_length_MASK           0x0000FFFF
 447 #define lpfc_rcqe_length_WORD           word2
 448 #define lpfc_rcqe_rq_id_SHIFT           6
 449 #define lpfc_rcqe_rq_id_MASK            0x000003FF
 450 #define lpfc_rcqe_rq_id_WORD            word2
 451 #define lpfc_rcqe_fcf_id_SHIFT          0
 452 #define lpfc_rcqe_fcf_id_MASK           0x0000003F
 453 #define lpfc_rcqe_fcf_id_WORD           word2
 454         uint32_t word3;
 455 #define lpfc_rcqe_valid_SHIFT           lpfc_cqe_valid_SHIFT
 456 #define lpfc_rcqe_valid_MASK            lpfc_cqe_valid_MASK
 457 #define lpfc_rcqe_valid_WORD            lpfc_cqe_valid_WORD
 458 #define lpfc_rcqe_port_SHIFT            30
 459 #define lpfc_rcqe_port_MASK             0x00000001
 460 #define lpfc_rcqe_port_WORD             word3
 461 #define lpfc_rcqe_hdr_length_SHIFT      24
 462 #define lpfc_rcqe_hdr_length_MASK       0x0000001F
 463 #define lpfc_rcqe_hdr_length_WORD       word3
 464 #define lpfc_rcqe_code_SHIFT            lpfc_cqe_code_SHIFT
 465 #define lpfc_rcqe_code_MASK             lpfc_cqe_code_MASK
 466 #define lpfc_rcqe_code_WORD             lpfc_cqe_code_WORD
 467 #define lpfc_rcqe_eof_SHIFT             8
 468 #define lpfc_rcqe_eof_MASK              0x000000FF
 469 #define lpfc_rcqe_eof_WORD              word3
 470 #define FCOE_EOFn       0x41
 471 #define FCOE_EOFt       0x42
 472 #define FCOE_EOFni      0x49
 473 #define FCOE_EOFa       0x50
 474 #define lpfc_rcqe_sof_SHIFT             0
 475 #define lpfc_rcqe_sof_MASK              0x000000FF
 476 #define lpfc_rcqe_sof_WORD              word3
 477 #define FCOE_SOFi2      0x2d
 478 #define FCOE_SOFi3      0x2e
 479 #define FCOE_SOFn2      0x35
 480 #define FCOE_SOFn3      0x36
 481 };
 482
 483 struct lpfc_rqe {
 484         uint32_t address_hi;
 485         uint32_t address_lo;
 486 };
 487
 488 /* buffer descriptors */
 489 struct lpfc_bde4 {
 490         uint32_t addr_hi;
 491         uint32_t addr_lo;
 492         uint32_t word2;
 493 #define lpfc_bde4_last_SHIFT            31
 494 #define lpfc_bde4_last_MASK             0x00000001
 495 #define lpfc_bde4_last_WORD             word2
 496 #define lpfc_bde4_sge_offset_SHIFT      0
 497 #define lpfc_bde4_sge_offset_MASK       0x000003FF
 498 #define lpfc_bde4_sge_offset_WORD       word2
 499         uint32_t word3;
 500 #define lpfc_bde4_length_SHIFT          0
 501 #define lpfc_bde4_length_MASK           0x000000FF
 502 #define lpfc_bde4_length_WORD           word3
 503 };
 504
 505 struct lpfc_register {
 506         uint32_t word0;
 507 };
 508
 509 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
 510 #define LPFC_UERR_STATUS_HI             0x00A4
 511 #define LPFC_UERR_STATUS_LO             0x00A0
 512 #define LPFC_UE_MASK_HI                 0x00AC
 513 #define LPFC_UE_MASK_LO                 0x00A8
 514
 515 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
 516 #define LPFC_SLI_INTF                   0x0058
 517
 518 #define LPFC_SLIPORT_IF2_SMPHR          0x0400
 519 #define lpfc_port_smphr_perr_SHIFT      31
 520 #define lpfc_port_smphr_perr_MASK       0x1
 521 #define lpfc_port_smphr_perr_WORD       word0
 522 #define lpfc_port_smphr_sfi_SHIFT       30
 523 #define lpfc_port_smphr_sfi_MASK        0x1
 524 #define lpfc_port_smphr_sfi_WORD        word0
 525 #define lpfc_port_smphr_nip_SHIFT       29
 526 #define lpfc_port_smphr_nip_MASK        0x1
 527 #define lpfc_port_smphr_nip_WORD        word0
 528 #define lpfc_port_smphr_ipc_SHIFT       28
 529 #define lpfc_port_smphr_ipc_MASK        0x1
 530 #define lpfc_port_smphr_ipc_WORD        word0
 531 #define lpfc_port_smphr_scr1_SHIFT      27
 532 #define lpfc_port_smphr_scr1_MASK       0x1
 533 #define lpfc_port_smphr_scr1_WORD       word0
 534 #define lpfc_port_smphr_scr2_SHIFT      26
 535 #define lpfc_port_smphr_scr2_MASK       0x1
 536 #define lpfc_port_smphr_scr2_WORD       word0
 537 #define lpfc_port_smphr_host_scratch_SHIFT      16
 538 #define lpfc_port_smphr_host_scratch_MASK       0xFF
 539 #define lpfc_port_smphr_host_scratch_WORD       word0
 540 #define lpfc_port_smphr_port_status_SHIFT       0
 541 #define lpfc_port_smphr_port_status_MASK        0xFFFF
 542 #define lpfc_port_smphr_port_status_WORD        word0
 543
 544 #define LPFC_POST_STAGE_POWER_ON_RESET                  0x0000
 545 #define LPFC_POST_STAGE_AWAITING_HOST_RDY               0x0001
 546 #define LPFC_POST_STAGE_HOST_RDY                        0x0002
 547 #define LPFC_POST_STAGE_BE_RESET                        0x0003
 548 #define LPFC_POST_STAGE_SEEPROM_CS_START                0x0100
 549 #define LPFC_POST_STAGE_SEEPROM_CS_DONE                 0x0101
 550 #define LPFC_POST_STAGE_DDR_CONFIG_START                0x0200
 551 #define LPFC_POST_STAGE_DDR_CONFIG_DONE                 0x0201
 552 #define LPFC_POST_STAGE_DDR_CALIBRATE_START             0x0300
 553 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE              0x0301
 554 #define LPFC_POST_STAGE_DDR_TEST_START                  0x0400
 555 #define LPFC_POST_STAGE_DDR_TEST_DONE                   0x0401
 556 #define LPFC_POST_STAGE_REDBOOT_INIT_START              0x0600
 557 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE               0x0601
 558 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START             0x0700
 559 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE              0x0701
 560 #define LPFC_POST_STAGE_ARMFW_START                     0x0800
 561 #define LPFC_POST_STAGE_DHCP_QUERY_START                0x0900
 562 #define LPFC_POST_STAGE_DHCP_QUERY_DONE                 0x0901
 563 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START     0x0A00
 564 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE      0x0A01
 565 #define LPFC_POST_STAGE_RC_OPTION_SET                   0x0B00
 566 #define LPFC_POST_STAGE_SWITCH_LINK                     0x0B01
 567 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE               0x0B02
 568 #define LPFC_POST_STAGE_PERFROM_TFTP                    0x0B03
 569 #define LPFC_POST_STAGE_PARSE_XML                       0x0B04
 570 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE                  0x0B05
 571 #define LPFC_POST_STAGE_FLASH_IMAGE                     0x0B06
 572 #define LPFC_POST_STAGE_RC_DONE                         0x0B07
 573 #define LPFC_POST_STAGE_REBOOT_SYSTEM                   0x0B08
 574 #define LPFC_POST_STAGE_MAC_ADDRESS                     0x0C00
 575 #define LPFC_POST_STAGE_PORT_READY                      0xC000
 576 #define LPFC_POST_STAGE_PORT_UE                         0xF000
 577
 578 #define LPFC_SLIPORT_STATUS             0x0404
 579 #define lpfc_sliport_status_err_SHIFT   31
 580 #define lpfc_sliport_status_err_MASK    0x1
 581 #define lpfc_sliport_status_err_WORD    word0
 582 #define lpfc_sliport_status_end_SHIFT   30
 583 #define lpfc_sliport_status_end_MASK    0x1
 584 #define lpfc_sliport_status_end_WORD    word0
 585 #define lpfc_sliport_status_oti_SHIFT   29
 586 #define lpfc_sliport_status_oti_MASK    0x1
 587 #define lpfc_sliport_status_oti_WORD    word0
 588 #define lpfc_sliport_status_rn_SHIFT    24
 589 #define lpfc_sliport_status_rn_MASK     0x1
 590 #define lpfc_sliport_status_rn_WORD     word0
 591 #define lpfc_sliport_status_rdy_SHIFT   23
 592 #define lpfc_sliport_status_rdy_MASK    0x1
 593 #define lpfc_sliport_status_rdy_WORD    word0
 594 #define MAX_IF_TYPE_2_RESETS    1000
 595
 596 #define LPFC_SLIPORT_CNTRL              0x0408
 597 #define lpfc_sliport_ctrl_end_SHIFT     30
 598 #define lpfc_sliport_ctrl_end_MASK      0x1
 599 #define lpfc_sliport_ctrl_end_WORD      word0
 600 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
 601 #define LPFC_SLIPORT_BIG_ENDIAN    1
 602 #define lpfc_sliport_ctrl_ip_SHIFT      27
 603 #define lpfc_sliport_ctrl_ip_MASK       0x1
 604 #define lpfc_sliport_ctrl_ip_WORD       word0
 605 #define LPFC_SLIPORT_INIT_PORT  1
 606
 607 #define LPFC_SLIPORT_ERR_1              0x040C
 608 #define LPFC_SLIPORT_ERR_2              0x0410
 609
 610 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
 611  * reside in BAR 2.
 612  */
 613 #define LPFC_SLIPORT_IF0_SMPHR  0x00AC
 614
 615 #define LPFC_IMR_MASK_ALL       0xFFFFFFFF
 616 #define LPFC_ISCR_CLEAR_ALL     0xFFFFFFFF
 617
 618 #define LPFC_HST_ISR0           0x0C18
 619 #define LPFC_HST_ISR1           0x0C1C
 620 #define LPFC_HST_ISR2           0x0C20
 621 #define LPFC_HST_ISR3           0x0C24
 622 #define LPFC_HST_ISR4           0x0C28
 623
 624 #define LPFC_HST_IMR0           0x0C48
 625 #define LPFC_HST_IMR1           0x0C4C
 626 #define LPFC_HST_IMR2           0x0C50
 627 #define LPFC_HST_IMR3           0x0C54
 628 #define LPFC_HST_IMR4           0x0C58
 629
 630 #define LPFC_HST_ISCR0          0x0C78
 631 #define LPFC_HST_ISCR1          0x0C7C
 632 #define LPFC_HST_ISCR2          0x0C80
 633 #define LPFC_HST_ISCR3          0x0C84
 634 #define LPFC_HST_ISCR4          0x0C88
 635
 636 #define LPFC_SLI4_INTR0                 BIT0
 637 #define LPFC_SLI4_INTR1                 BIT1
 638 #define LPFC_SLI4_INTR2                 BIT2
 639 #define LPFC_SLI4_INTR3                 BIT3
 640 #define LPFC_SLI4_INTR4                 BIT4
 641 #define LPFC_SLI4_INTR5                 BIT5
 642 #define LPFC_SLI4_INTR6                 BIT6
 643 #define LPFC_SLI4_INTR7                 BIT7
 644 #define LPFC_SLI4_INTR8                 BIT8
 645 #define LPFC_SLI4_INTR9                 BIT9
 646 #define LPFC_SLI4_INTR10                BIT10
 647 #define LPFC_SLI4_INTR11                BIT11
 648 #define LPFC_SLI4_INTR12                BIT12
 649 #define LPFC_SLI4_INTR13                BIT13
 650 #define LPFC_SLI4_INTR14                BIT14
 651 #define LPFC_SLI4_INTR15                BIT15
 652 #define LPFC_SLI4_INTR16                BIT16
 653 #define LPFC_SLI4_INTR17                BIT17
 654 #define LPFC_SLI4_INTR18                BIT18
 655 #define LPFC_SLI4_INTR19                BIT19
 656 #define LPFC_SLI4_INTR20                BIT20
 657 #define LPFC_SLI4_INTR21                BIT21
 658 #define LPFC_SLI4_INTR22                BIT22
 659 #define LPFC_SLI4_INTR23                BIT23
 660 #define LPFC_SLI4_INTR24                BIT24
 661 #define LPFC_SLI4_INTR25                BIT25
 662 #define LPFC_SLI4_INTR26                BIT26
 663 #define LPFC_SLI4_INTR27                BIT27
 664 #define LPFC_SLI4_INTR28                BIT28
 665 #define LPFC_SLI4_INTR29                BIT29
 666 #define LPFC_SLI4_INTR30                BIT30
 667 #define LPFC_SLI4_INTR31                BIT31
 668
 669 /*
 670  * The Doorbell registers defined here exist in different BAR
 671  * register sets depending on the UCNA Port's reported if_type
 672  * value.  For UCNA ports running SLI4 and if_type 0, they reside in
 673  * BAR4.  For UCNA ports running SLI4 and if_type 2, they reside in
 674  * BAR0.  The offsets are the same so the driver must account for
 675  * any base address difference.
 676  */
 677 #define LPFC_RQ_DOORBELL                0x00A0
 678 #define lpfc_rq_doorbell_num_posted_SHIFT       16
 679 #define lpfc_rq_doorbell_num_posted_MASK        0x3FFF
 680 #define lpfc_rq_doorbell_num_posted_WORD        word0
 681 #define LPFC_RQ_POST_BATCH              8       /* RQEs to post at one time */
 682 #define lpfc_rq_doorbell_id_SHIFT               0
 683 #define lpfc_rq_doorbell_id_MASK                0xFFFF
 684 #define lpfc_rq_doorbell_id_WORD                word0
 685
 686 #define LPFC_WQ_DOORBELL                0x0040
 687 #define lpfc_wq_doorbell_num_posted_SHIFT       24
 688 #define lpfc_wq_doorbell_num_posted_MASK        0x00FF
 689 #define lpfc_wq_doorbell_num_posted_WORD        word0
 690 #define lpfc_wq_doorbell_index_SHIFT            16
 691 #define lpfc_wq_doorbell_index_MASK             0x00FF
 692 #define lpfc_wq_doorbell_index_WORD             word0
 693 #define lpfc_wq_doorbell_id_SHIFT               0
 694 #define lpfc_wq_doorbell_id_MASK                0xFFFF
 695 #define lpfc_wq_doorbell_id_WORD                word0
 696
 697 #define LPFC_EQCQ_DOORBELL              0x0120
 698 #define lpfc_eqcq_doorbell_se_SHIFT             31
 699 #define lpfc_eqcq_doorbell_se_MASK              0x0001
 700 #define lpfc_eqcq_doorbell_se_WORD              word0
 701 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF    0
 702 #define LPFC_EQCQ_SOLICIT_ENABLE_ON     1
 703 #define lpfc_eqcq_doorbell_arm_SHIFT            29
 704 #define lpfc_eqcq_doorbell_arm_MASK             0x0001
 705 #define lpfc_eqcq_doorbell_arm_WORD             word0
 706 #define lpfc_eqcq_doorbell_num_released_SHIFT   16
 707 #define lpfc_eqcq_doorbell_num_released_MASK    0x1FFF
 708 #define lpfc_eqcq_doorbell_num_released_WORD    word0
 709 #define lpfc_eqcq_doorbell_qt_SHIFT             10
 710 #define lpfc_eqcq_doorbell_qt_MASK              0x0001
 711 #define lpfc_eqcq_doorbell_qt_WORD              word0
 712 #define LPFC_QUEUE_TYPE_COMPLETION      0
 713 #define LPFC_QUEUE_TYPE_EVENT           1
 714 #define lpfc_eqcq_doorbell_eqci_SHIFT           9
 715 #define lpfc_eqcq_doorbell_eqci_MASK            0x0001
 716 #define lpfc_eqcq_doorbell_eqci_WORD            word0
 717 #define lpfc_eqcq_doorbell_cqid_SHIFT           0
 718 #define lpfc_eqcq_doorbell_cqid_MASK            0x03FF
 719 #define lpfc_eqcq_doorbell_cqid_WORD            word0
 720 #define lpfc_eqcq_doorbell_eqid_SHIFT           0
 721 #define lpfc_eqcq_doorbell_eqid_MASK            0x01FF
 722 #define lpfc_eqcq_doorbell_eqid_WORD            word0
 723
 724 #define LPFC_BMBX                       0x0160
 725 #define lpfc_bmbx_addr_SHIFT            2
 726 #define lpfc_bmbx_addr_MASK             0x3FFFFFFF
 727 #define lpfc_bmbx_addr_WORD             word0
 728 #define lpfc_bmbx_hi_SHIFT              1
 729 #define lpfc_bmbx_hi_MASK               0x0001
 730 #define lpfc_bmbx_hi_WORD               word0
 731 #define lpfc_bmbx_rdy_SHIFT             0
 732 #define lpfc_bmbx_rdy_MASK              0x0001
 733 #define lpfc_bmbx_rdy_WORD              word0
 734
 735 #define LPFC_MQ_DOORBELL                        0x0140
 736 #define lpfc_mq_doorbell_num_posted_SHIFT       16
 737 #define lpfc_mq_doorbell_num_posted_MASK        0x3FFF
 738 #define lpfc_mq_doorbell_num_posted_WORD        word0
 739 #define lpfc_mq_doorbell_id_SHIFT               0
 740 #define lpfc_mq_doorbell_id_MASK                0xFFFF
 741 #define lpfc_mq_doorbell_id_WORD                word0
 742
 743 struct lpfc_sli4_cfg_mhdr {
 744         uint32_t word1;
 745 #define lpfc_mbox_hdr_emb_SHIFT         0
 746 #define lpfc_mbox_hdr_emb_MASK          0x00000001
 747 #define lpfc_mbox_hdr_emb_WORD          word1
 748 #define lpfc_mbox_hdr_sge_cnt_SHIFT     3
 749 #define lpfc_mbox_hdr_sge_cnt_MASK      0x0000001F
 750 #define lpfc_mbox_hdr_sge_cnt_WORD      word1
 751         uint32_t payload_length;
 752         uint32_t tag_lo;
 753         uint32_t tag_hi;
 754         uint32_t reserved5;
 755 };
 756
 757 union lpfc_sli4_cfg_shdr {
 758         struct {
 759                 uint32_t word6;
 760 #define lpfc_mbox_hdr_opcode_SHIFT      0
 761 #define lpfc_mbox_hdr_opcode_MASK       0x000000FF
 762 #define lpfc_mbox_hdr_opcode_WORD       word6
 763 #define lpfc_mbox_hdr_subsystem_SHIFT   8
 764 #define lpfc_mbox_hdr_subsystem_MASK    0x000000FF
 765 #define lpfc_mbox_hdr_subsystem_WORD    word6
 766 #define lpfc_mbox_hdr_port_number_SHIFT 16
 767 #define lpfc_mbox_hdr_port_number_MASK  0x000000FF
 768 #define lpfc_mbox_hdr_port_number_WORD  word6
 769 #define lpfc_mbox_hdr_domain_SHIFT      24
 770 #define lpfc_mbox_hdr_domain_MASK       0x000000FF
 771 #define lpfc_mbox_hdr_domain_WORD       word6
 772                 uint32_t timeout;
 773                 uint32_t request_length;
 774                 uint32_t word9;
 775 #define lpfc_mbox_hdr_version_SHIFT     0
 776 #define lpfc_mbox_hdr_version_MASK      0x000000FF
 777 #define lpfc_mbox_hdr_version_WORD      word9
 778 #define lpfc_mbox_hdr_pf_num_SHIFT      16
 779 #define lpfc_mbox_hdr_pf_num_MASK       0x000000FF
 780 #define lpfc_mbox_hdr_pf_num_WORD       word9
 781 #define lpfc_mbox_hdr_vh_num_SHIFT      24
 782 #define lpfc_mbox_hdr_vh_num_MASK       0x000000FF
 783 #define lpfc_mbox_hdr_vh_num_WORD       word9
 784 #define LPFC_Q_CREATE_VERSION_2 2
 785 #define LPFC_Q_CREATE_VERSION_1 1
 786 #define LPFC_Q_CREATE_VERSION_0 0
 787         } request;
 788         struct {
 789                 uint32_t word6;
 790 #define lpfc_mbox_hdr_opcode_SHIFT              0
 791 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
 792 #define lpfc_mbox_hdr_opcode_WORD               word6
 793 #define lpfc_mbox_hdr_subsystem_SHIFT           8
 794 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
 795 #define lpfc_mbox_hdr_subsystem_WORD            word6
 796 #define lpfc_mbox_hdr_domain_SHIFT              24
 797 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
 798 #define lpfc_mbox_hdr_domain_WORD               word6
 799                 uint32_t word7;
 800 #define lpfc_mbox_hdr_status_SHIFT              0
 801 #define lpfc_mbox_hdr_status_MASK               0x000000FF
 802 #define lpfc_mbox_hdr_status_WORD               word7
 803 #define lpfc_mbox_hdr_add_status_SHIFT          8
 804 #define lpfc_mbox_hdr_add_status_MASK           0x000000FF
 805 #define lpfc_mbox_hdr_add_status_WORD           word7
 806                 uint32_t response_length;
 807                 uint32_t actual_response_length;
 808         } response;
 809 };
 810
 811 /* Mailbox Header structures.
 812  * struct mbox_header is defined for first generation SLI4_CFG mailbox
 813  * calls deployed for BE-based ports.
 814  *
 815  * struct sli4_mbox_header is defined for second generation SLI4
 816  * ports that don't deploy the SLI4_CFG mechanism.
 817  */
 818 struct mbox_header {
 819         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
 820         union  lpfc_sli4_cfg_shdr cfg_shdr;
 821 };
 822
 823 #define LPFC_EXTENT_LOCAL               0
 824 #define LPFC_TIMEOUT_DEFAULT            0
 825 #define LPFC_EXTENT_VERSION_DEFAULT     0
 826
 827 /* Subsystem Definitions */
 828 #define LPFC_MBOX_SUBSYSTEM_COMMON      0x1
 829 #define LPFC_MBOX_SUBSYSTEM_FCOE        0xC
 830
 831 /* Device Specific Definitions */
 832
 833 /* The HOST ENDIAN defines are in Big Endian format. */
 834 #define HOST_ENDIAN_LOW_WORD0   0xFF3412FF
 835 #define HOST_ENDIAN_HIGH_WORD1  0xFF7856FF
 836
 837 /* Common Opcodes */
 838 #define LPFC_MBOX_OPCODE_CQ_CREATE              0x0C
 839 #define LPFC_MBOX_OPCODE_EQ_CREATE              0x0D
 840 #define LPFC_MBOX_OPCODE_MQ_CREATE              0x15
 841 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES    0x20
 842 #define LPFC_MBOX_OPCODE_NOP                    0x21
 843 #define LPFC_MBOX_OPCODE_MQ_DESTROY             0x35
 844 #define LPFC_MBOX_OPCODE_CQ_DESTROY             0x36
 845 #define LPFC_MBOX_OPCODE_EQ_DESTROY             0x37
 846 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG           0x3A
 847 #define LPFC_MBOX_OPCODE_FUNCTION_RESET         0x3D
 848 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT          0x5A
 849 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO   0x9A
 850 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT  0x9B
 851 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT      0x9C
 852 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT    0x9D
 853 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG    0xA0
 854 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG     0xA4
 855 #define LPFC_MBOX_OPCODE_WRITE_OBJECT           0xAC
 856 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS    0xB5
 857
 858 /* FCoE Opcodes */
 859 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE                 0x01
 860 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY                0x02
 861 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES            0x03
 862 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES          0x04
 863 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE                 0x05
 864 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY                0x06
 865 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE            0x08
 866 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF                   0x09
 867 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF                0x0A
 868 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE         0x0B
 869 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF            0x10
 870 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE           0x22
 871 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK        0x23
 872
 873 /* Mailbox command structures */
 874 struct eq_context {
 875         uint32_t word0;
 876 #define lpfc_eq_context_size_SHIFT      31
 877 #define lpfc_eq_context_size_MASK       0x00000001
 878 #define lpfc_eq_context_size_WORD       word0
 879 #define LPFC_EQE_SIZE_4                 0x0
 880 #define LPFC_EQE_SIZE_16                0x1
 881 #define lpfc_eq_context_valid_SHIFT     29
 882 #define lpfc_eq_context_valid_MASK      0x00000001
 883 #define lpfc_eq_context_valid_WORD      word0
 884         uint32_t word1;
 885 #define lpfc_eq_context_count_SHIFT     26
 886 #define lpfc_eq_context_count_MASK      0x00000003
 887 #define lpfc_eq_context_count_WORD      word1
 888 #define LPFC_EQ_CNT_256         0x0
 889 #define LPFC_EQ_CNT_512         0x1
 890 #define LPFC_EQ_CNT_1024        0x2
 891 #define LPFC_EQ_CNT_2048        0x3
 892 #define LPFC_EQ_CNT_4096        0x4
 893         uint32_t word2;
 894 #define lpfc_eq_context_delay_multi_SHIFT       13
 895 #define lpfc_eq_context_delay_multi_MASK        0x000003FF
 896 #define lpfc_eq_context_delay_multi_WORD        word2
 897         uint32_t reserved3;
 898 };
 899
 900 struct sgl_page_pairs {
 901         uint32_t sgl_pg0_addr_lo;
 902         uint32_t sgl_pg0_addr_hi;
 903         uint32_t sgl_pg1_addr_lo;
 904         uint32_t sgl_pg1_addr_hi;
 905 };
 906
 907 struct lpfc_mbx_post_sgl_pages {
 908         struct mbox_header header;
 909         uint32_t word0;
 910 #define lpfc_post_sgl_pages_xri_SHIFT   0
 911 #define lpfc_post_sgl_pages_xri_MASK    0x0000FFFF
 912 #define lpfc_post_sgl_pages_xri_WORD    word0
 913 #define lpfc_post_sgl_pages_xricnt_SHIFT        16
 914 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
 915 #define lpfc_post_sgl_pages_xricnt_WORD word0
 916         struct sgl_page_pairs  sgl_pg_pairs[1];
 917 };
 918
 919 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
 920 struct lpfc_mbx_post_uembed_sgl_page1 {
 921         union  lpfc_sli4_cfg_shdr cfg_shdr;
 922         uint32_t word0;
 923         struct sgl_page_pairs sgl_pg_pairs;
 924 };
 925
 926 struct lpfc_mbx_sge {
 927         uint32_t pa_lo;
 928         uint32_t pa_hi;
 929         uint32_t length;
 930 };
 931
 932 struct lpfc_mbx_nembed_cmd {
 933         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
 934 #define LPFC_SLI4_MBX_SGE_MAX_PAGES     19
 935         struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
 936 };
 937
 938 struct lpfc_mbx_nembed_sge_virt {
 939         void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
 940 };
 941
 942 struct lpfc_mbx_eq_create {
 943         struct mbox_header header;
 944         union {
 945                 struct {
 946                         uint32_t word0;
 947 #define lpfc_mbx_eq_create_num_pages_SHIFT      0
 948 #define lpfc_mbx_eq_create_num_pages_MASK       0x0000FFFF
 949 #define lpfc_mbx_eq_create_num_pages_WORD       word0
 950                         struct eq_context context;
 951                         struct dma_address page[LPFC_MAX_EQ_PAGE];
 952                 } request;
 953                 struct {
 954                         uint32_t word0;
 955 #define lpfc_mbx_eq_create_q_id_SHIFT   0
 956 #define lpfc_mbx_eq_create_q_id_MASK    0x0000FFFF
 957 #define lpfc_mbx_eq_create_q_id_WORD    word0
 958                 } response;
 959         } u;
 960 };
 961
 962 struct lpfc_mbx_eq_destroy {
 963         struct mbox_header header;
 964         union {
 965                 struct {
 966                         uint32_t word0;
 967 #define lpfc_mbx_eq_destroy_q_id_SHIFT  0
 968 #define lpfc_mbx_eq_destroy_q_id_MASK   0x0000FFFF
 969 #define lpfc_mbx_eq_destroy_q_id_WORD   word0
 970                 } request;
 971                 struct {
 972                         uint32_t word0;
 973                 } response;
 974         } u;
 975 };
 976
 977 struct lpfc_mbx_nop {
 978         struct mbox_header header;
 979         uint32_t context[2];
 980 };
 981
 982 struct cq_context {
 983         uint32_t word0;
 984 #define lpfc_cq_context_event_SHIFT     31
 985 #define lpfc_cq_context_event_MASK      0x00000001
 986 #define lpfc_cq_context_event_WORD      word0
 987 #define lpfc_cq_context_valid_SHIFT     29
 988 #define lpfc_cq_context_valid_MASK      0x00000001
 989 #define lpfc_cq_context_valid_WORD      word0
 990 #define lpfc_cq_context_count_SHIFT     27
 991 #define lpfc_cq_context_count_MASK      0x00000003
 992 #define lpfc_cq_context_count_WORD      word0
 993 #define LPFC_CQ_CNT_256         0x0
 994 #define LPFC_CQ_CNT_512         0x1
 995 #define LPFC_CQ_CNT_1024        0x2
 996         uint32_t word1;
 997 #define lpfc_cq_eq_id_SHIFT             22      /* Version 0 Only */
 998 #define lpfc_cq_eq_id_MASK              0x000000FF
 999 #define lpfc_cq_eq_id_WORD              word1
1000 #define lpfc_cq_eq_id_2_SHIFT           0       /* Version 2 Only */
1001 #define lpfc_cq_eq_id_2_MASK            0x0000FFFF
1002 #define lpfc_cq_eq_id_2_WORD            word1
1003         uint32_t reserved0;
1004         uint32_t reserved1;
1005 };
1006
1007 struct lpfc_mbx_cq_create {
1008         struct mbox_header header;
1009         union {
1010                 struct {
1011                         uint32_t word0;
1012 #define lpfc_mbx_cq_create_page_size_SHIFT      16      /* Version 2 Only */
1013 #define lpfc_mbx_cq_create_page_size_MASK       0x000000FF
1014 #define lpfc_mbx_cq_create_page_size_WORD       word0
1015 #define lpfc_mbx_cq_create_num_pages_SHIFT      0
1016 #define lpfc_mbx_cq_create_num_pages_MASK       0x0000FFFF
1017 #define lpfc_mbx_cq_create_num_pages_WORD       word0
1018                         struct cq_context context;
1019                         struct dma_address page[LPFC_MAX_CQ_PAGE];
1020                 } request;
1021                 struct {
1022                         uint32_t word0;
1023 #define lpfc_mbx_cq_create_q_id_SHIFT   0
1024 #define lpfc_mbx_cq_create_q_id_MASK    0x0000FFFF
1025 #define lpfc_mbx_cq_create_q_id_WORD    word0
1026                 } response;
1027         } u;
1028 };
1029
1030 struct lpfc_mbx_cq_destroy {
1031         struct mbox_header header;
1032         union {
1033                 struct {
1034                         uint32_t word0;
1035 #define lpfc_mbx_cq_destroy_q_id_SHIFT  0
1036 #define lpfc_mbx_cq_destroy_q_id_MASK   0x0000FFFF
1037 #define lpfc_mbx_cq_destroy_q_id_WORD   word0
1038                 } request;
1039                 struct {
1040                         uint32_t word0;
1041                 } response;
1042         } u;
1043 };
1044
1045 struct wq_context {
1046         uint32_t reserved0;
1047         uint32_t reserved1;
1048         uint32_t reserved2;
1049         uint32_t reserved3;
1050 };
1051
1052 struct lpfc_mbx_wq_create {
1053         struct mbox_header header;
1054         union {
1055                 struct {        /* Version 0 Request */
1056                         uint32_t word0;
1057 #define lpfc_mbx_wq_create_num_pages_SHIFT      0
1058 #define lpfc_mbx_wq_create_num_pages_MASK       0x0000FFFF
1059 #define lpfc_mbx_wq_create_num_pages_WORD       word0
1060 #define lpfc_mbx_wq_create_cq_id_SHIFT          16
1061 #define lpfc_mbx_wq_create_cq_id_MASK           0x0000FFFF
1062 #define lpfc_mbx_wq_create_cq_id_WORD           word0
1063                         struct dma_address page[LPFC_MAX_WQ_PAGE];
1064                 } request;
1065                 struct {        /* Version 1 Request */
1066                         uint32_t word0; /* Word 0 is the same as in v0 */
1067                         uint32_t word1;
1068 #define lpfc_mbx_wq_create_page_size_SHIFT      0
1069 #define lpfc_mbx_wq_create_page_size_MASK       0x000000FF
1070 #define lpfc_mbx_wq_create_page_size_WORD       word1
1071 #define lpfc_mbx_wq_create_wqe_size_SHIFT       8
1072 #define lpfc_mbx_wq_create_wqe_size_MASK        0x0000000F
1073 #define lpfc_mbx_wq_create_wqe_size_WORD        word1
1074 #define LPFC_WQ_WQE_SIZE_64     0x5
1075 #define LPFC_WQ_WQE_SIZE_128    0x6
1076 #define lpfc_mbx_wq_create_wqe_count_SHIFT      16
1077 #define lpfc_mbx_wq_create_wqe_count_MASK       0x0000FFFF
1078 #define lpfc_mbx_wq_create_wqe_count_WORD       word1
1079                         uint32_t word2;
1080                         struct dma_address page[LPFC_MAX_WQ_PAGE-1];
1081                 } request_1;
1082                 struct {
1083                         uint32_t word0;
1084 #define lpfc_mbx_wq_create_q_id_SHIFT   0
1085 #define lpfc_mbx_wq_create_q_id_MASK    0x0000FFFF
1086 #define lpfc_mbx_wq_create_q_id_WORD    word0
1087                 } response;
1088         } u;
1089 };
1090
1091 struct lpfc_mbx_wq_destroy {
1092         struct mbox_header header;
1093         union {
1094                 struct {
1095                         uint32_t word0;
1096 #define lpfc_mbx_wq_destroy_q_id_SHIFT  0
1097 #define lpfc_mbx_wq_destroy_q_id_MASK   0x0000FFFF
1098 #define lpfc_mbx_wq_destroy_q_id_WORD   word0
1099                 } request;
1100                 struct {
1101                         uint32_t word0;
1102                 } response;
1103         } u;
1104 };
1105
1106 #define LPFC_HDR_BUF_SIZE 128
1107 #define LPFC_DATA_BUF_SIZE 2048
1108 struct rq_context {
1109         uint32_t word0;
1110 #define lpfc_rq_context_rqe_count_SHIFT 16      /* Version 0 Only */
1111 #define lpfc_rq_context_rqe_count_MASK  0x0000000F
1112 #define lpfc_rq_context_rqe_count_WORD  word0
1113 #define LPFC_RQ_RING_SIZE_512           9       /* 512 entries */
1114 #define LPFC_RQ_RING_SIZE_1024          10      /* 1024 entries */
1115 #define LPFC_RQ_RING_SIZE_2048          11      /* 2048 entries */
1116 #define LPFC_RQ_RING_SIZE_4096          12      /* 4096 entries */
1117 #define lpfc_rq_context_rqe_count_1_SHIFT       16      /* Version 1 Only */
1118 #define lpfc_rq_context_rqe_count_1_MASK        0x0000FFFF
1119 #define lpfc_rq_context_rqe_count_1_WORD        word0
1120 #define lpfc_rq_context_rqe_size_SHIFT  8               /* Version 1 Only */
1121 #define lpfc_rq_context_rqe_size_MASK   0x0000000F
1122 #define lpfc_rq_context_rqe_size_WORD   word0
1123 #define LPFC_RQE_SIZE_8         2
1124 #define LPFC_RQE_SIZE_16        3
1125 #define LPFC_RQE_SIZE_32        4
1126 #define LPFC_RQE_SIZE_64        5
1127 #define LPFC_RQE_SIZE_128       6
1128 #define lpfc_rq_context_page_size_SHIFT 0               /* Version 1 Only */
1129 #define lpfc_rq_context_page_size_MASK  0x000000FF
1130 #define lpfc_rq_context_page_size_WORD  word0
1131         uint32_t reserved1;
1132         uint32_t word2;
1133 #define lpfc_rq_context_cq_id_SHIFT     16
1134 #define lpfc_rq_context_cq_id_MASK      0x000003FF
1135 #define lpfc_rq_context_cq_id_WORD      word2
1136 #define lpfc_rq_context_buf_size_SHIFT  0
1137 #define lpfc_rq_context_buf_size_MASK   0x0000FFFF
1138 #define lpfc_rq_context_buf_size_WORD   word2
1139         uint32_t buffer_size;                           /* Version 1 Only */
1140 };
1141
1142 struct lpfc_mbx_rq_create {
1143         struct mbox_header header;
1144         union {
1145                 struct {
1146                         uint32_t word0;
1147 #define lpfc_mbx_rq_create_num_pages_SHIFT      0
1148 #define lpfc_mbx_rq_create_num_pages_MASK       0x0000FFFF
1149 #define lpfc_mbx_rq_create_num_pages_WORD       word0
1150                         struct rq_context context;
1151                         struct dma_address page[LPFC_MAX_WQ_PAGE];
1152                 } request;
1153                 struct {
1154                         uint32_t word0;
1155 #define lpfc_mbx_rq_create_q_id_SHIFT   0
1156 #define lpfc_mbx_rq_create_q_id_MASK    0x0000FFFF
1157 #define lpfc_mbx_rq_create_q_id_WORD    word0
1158                 } response;
1159         } u;
1160 };
1161
1162 struct lpfc_mbx_rq_destroy {
1163         struct mbox_header header;
1164         union {
1165                 struct {
1166                         uint32_t word0;
1167 #define lpfc_mbx_rq_destroy_q_id_SHIFT  0
1168 #define lpfc_mbx_rq_destroy_q_id_MASK   0x0000FFFF
1169 #define lpfc_mbx_rq_destroy_q_id_WORD   word0
1170                 } request;
1171                 struct {
1172                         uint32_t word0;
1173                 } response;
1174         } u;
1175 };
1176
1177 struct mq_context {
1178         uint32_t word0;
1179 #define lpfc_mq_context_cq_id_SHIFT     22      /* Version 0 Only */
1180 #define lpfc_mq_context_cq_id_MASK      0x000003FF
1181 #define lpfc_mq_context_cq_id_WORD      word0
1182 #define lpfc_mq_context_ring_size_SHIFT 16
1183 #define lpfc_mq_context_ring_size_MASK  0x0000000F
1184 #define lpfc_mq_context_ring_size_WORD  word0
1185 #define LPFC_MQ_RING_SIZE_16            0x5
1186 #define LPFC_MQ_RING_SIZE_32            0x6
1187 #define LPFC_MQ_RING_SIZE_64            0x7
1188 #define LPFC_MQ_RING_SIZE_128           0x8
1189         uint32_t word1;
1190 #define lpfc_mq_context_valid_SHIFT     31
1191 #define lpfc_mq_context_valid_MASK      0x00000001
1192 #define lpfc_mq_context_valid_WORD      word1
1193         uint32_t reserved2;
1194         uint32_t reserved3;
1195 };
1196
1197 struct lpfc_mbx_mq_create {
1198         struct mbox_header header;
1199         union {
1200                 struct {
1201                         uint32_t word0;
1202 #define lpfc_mbx_mq_create_num_pages_SHIFT      0
1203 #define lpfc_mbx_mq_create_num_pages_MASK       0x0000FFFF
1204 #define lpfc_mbx_mq_create_num_pages_WORD       word0
1205                         struct mq_context context;
1206                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1207                 } request;
1208                 struct {
1209                         uint32_t word0;
1210 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1211 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1212 #define lpfc_mbx_mq_create_q_id_WORD    word0
1213                 } response;
1214         } u;
1215 };
1216
1217 struct lpfc_mbx_mq_create_ext {
1218         struct mbox_header header;
1219         union {
1220                 struct {
1221                         uint32_t word0;
1222 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT  0
1223 #define lpfc_mbx_mq_create_ext_num_pages_MASK   0x0000FFFF
1224 #define lpfc_mbx_mq_create_ext_num_pages_WORD   word0
1225 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT      16      /* Version 1 Only */
1226 #define lpfc_mbx_mq_create_ext_cq_id_MASK       0x0000FFFF
1227 #define lpfc_mbx_mq_create_ext_cq_id_WORD       word0
1228                         uint32_t async_evt_bmap;
1229 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT     LPFC_TRAILER_CODE_LINK
1230 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK      0x00000001
1231 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD      async_evt_bmap
1232 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT      LPFC_TRAILER_CODE_FCOE
1233 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK       0x00000001
1234 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD       async_evt_bmap
1235 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT   LPFC_TRAILER_CODE_GRP5
1236 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK    0x00000001
1237 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD    async_evt_bmap
1238 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT       LPFC_TRAILER_CODE_FC
1239 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK        0x00000001
1240 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD        async_evt_bmap
1241 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT      LPFC_TRAILER_CODE_SLI
1242 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK       0x00000001
1243 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD       async_evt_bmap
1244                         struct mq_context context;
1245                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1246                 } request;
1247                 struct {
1248                         uint32_t word0;
1249 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1250 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1251 #define lpfc_mbx_mq_create_q_id_WORD    word0
1252                 } response;
1253         } u;
1254 #define LPFC_ASYNC_EVENT_LINK_STATE     0x2
1255 #define LPFC_ASYNC_EVENT_FCF_STATE      0x4
1256 #define LPFC_ASYNC_EVENT_GROUP5         0x20
1257 };
1258
1259 struct lpfc_mbx_mq_destroy {
1260         struct mbox_header header;
1261         union {
1262                 struct {
1263                         uint32_t word0;
1264 #define lpfc_mbx_mq_destroy_q_id_SHIFT  0
1265 #define lpfc_mbx_mq_destroy_q_id_MASK   0x0000FFFF
1266 #define lpfc_mbx_mq_destroy_q_id_WORD   word0
1267                 } request;
1268                 struct {
1269                         uint32_t word0;
1270                 } response;
1271         } u;
1272 };
1273
1274 /* Start Gen 2 SLI4 Mailbox definitions: */
1275
1276 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1277 #define LPFC_RSC_TYPE_FCOE_VFI  0x20
1278 #define LPFC_RSC_TYPE_FCOE_VPI  0x21
1279 #define LPFC_RSC_TYPE_FCOE_RPI  0x22
1280 #define LPFC_RSC_TYPE_FCOE_XRI  0x23
1281
1282 struct lpfc_mbx_get_rsrc_extent_info {
1283         struct mbox_header header;
1284         union {
1285                 struct {
1286                         uint32_t word4;
1287 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT        0
1288 #define lpfc_mbx_get_rsrc_extent_info_type_MASK         0x0000FFFF
1289 #define lpfc_mbx_get_rsrc_extent_info_type_WORD         word4
1290                 } req;
1291                 struct {
1292                         uint32_t word4;
1293 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT         0
1294 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK          0x0000FFFF
1295 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD          word4
1296 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT        16
1297 #define lpfc_mbx_get_rsrc_extent_info_size_MASK         0x0000FFFF
1298 #define lpfc_mbx_get_rsrc_extent_info_size_WORD         word4
1299                 } rsp;
1300         } u;
1301 };
1302
1303 struct lpfc_id_range {
1304         uint32_t word5;
1305 #define lpfc_mbx_rsrc_id_word4_0_SHIFT  0
1306 #define lpfc_mbx_rsrc_id_word4_0_MASK   0x0000FFFF
1307 #define lpfc_mbx_rsrc_id_word4_0_WORD   word5
1308 #define lpfc_mbx_rsrc_id_word4_1_SHIFT  16
1309 #define lpfc_mbx_rsrc_id_word4_1_MASK   0x0000FFFF
1310 #define lpfc_mbx_rsrc_id_word4_1_WORD   word5
1311 };
1312
1313 struct lpfc_mbx_set_link_diag_state {
1314         struct mbox_header header;
1315         union {
1316                 struct {
1317                         uint32_t word0;
1318 #define lpfc_mbx_set_diag_state_diag_SHIFT      0
1319 #define lpfc_mbx_set_diag_state_diag_MASK       0x00000001
1320 #define lpfc_mbx_set_diag_state_diag_WORD       word0
1321 #define lpfc_mbx_set_diag_state_link_num_SHIFT  16
1322 #define lpfc_mbx_set_diag_state_link_num_MASK   0x0000003F
1323 #define lpfc_mbx_set_diag_state_link_num_WORD   word0
1324 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22
1325 #define lpfc_mbx_set_diag_state_link_type_MASK  0x00000003
1326 #define lpfc_mbx_set_diag_state_link_type_WORD  word0
1327                 } req;
1328                 struct {
1329                         uint32_t word0;
1330                 } rsp;
1331         } u;
1332 };
1333
1334 struct lpfc_mbx_set_link_diag_loopback {
1335         struct mbox_header header;
1336         union {
1337                 struct {
1338                         uint32_t word0;
1339 #define lpfc_mbx_set_diag_lpbk_type_SHIFT       0
1340 #define lpfc_mbx_set_diag_lpbk_type_MASK        0x00000001
1341 #define lpfc_mbx_set_diag_lpbk_type_WORD        word0
1342 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE         0x0
1343 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL        0x1
1344 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL        0x2
1345 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT   16
1346 #define lpfc_mbx_set_diag_lpbk_link_num_MASK    0x0000003F
1347 #define lpfc_mbx_set_diag_lpbk_link_num_WORD    word0
1348 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT  22
1349 #define lpfc_mbx_set_diag_lpbk_link_type_MASK   0x00000003
1350 #define lpfc_mbx_set_diag_lpbk_link_type_WORD   word0
1351                 } req;
1352                 struct {
1353                         uint32_t word0;
1354                 } rsp;
1355         } u;
1356 };
1357
1358 struct lpfc_mbx_run_link_diag_test {
1359         struct mbox_header header;
1360         union {
1361                 struct {
1362                         uint32_t word0;
1363 #define lpfc_mbx_run_diag_test_link_num_SHIFT   16
1364 #define lpfc_mbx_run_diag_test_link_num_MASK    0x0000003F
1365 #define lpfc_mbx_run_diag_test_link_num_WORD    word0
1366 #define lpfc_mbx_run_diag_test_link_type_SHIFT  22
1367 #define lpfc_mbx_run_diag_test_link_type_MASK   0x00000003
1368 #define lpfc_mbx_run_diag_test_link_type_WORD   word0
1369                         uint32_t word1;
1370 #define lpfc_mbx_run_diag_test_test_id_SHIFT    0
1371 #define lpfc_mbx_run_diag_test_test_id_MASK     0x0000FFFF
1372 #define lpfc_mbx_run_diag_test_test_id_WORD     word1
1373 #define lpfc_mbx_run_diag_test_loops_SHIFT      16
1374 #define lpfc_mbx_run_diag_test_loops_MASK       0x0000FFFF
1375 #define lpfc_mbx_run_diag_test_loops_WORD       word1
1376                         uint32_t word2;
1377 #define lpfc_mbx_run_diag_test_test_ver_SHIFT   0
1378 #define lpfc_mbx_run_diag_test_test_ver_MASK    0x0000FFFF
1379 #define lpfc_mbx_run_diag_test_test_ver_WORD    word2
1380 #define lpfc_mbx_run_diag_test_err_act_SHIFT    16
1381 #define lpfc_mbx_run_diag_test_err_act_MASK     0x000000FF
1382 #define lpfc_mbx_run_diag_test_err_act_WORD     word2
1383                 } req;
1384                 struct {
1385                         uint32_t word0;
1386                 } rsp;
1387         } u;
1388 };
1389
1390 /*
1391  * struct lpfc_mbx_alloc_rsrc_extents:
1392  * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
1393  * 6 words of header + 4 words of shared subcommand header +
1394  * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
1395  *
1396  * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
1397  * for extents payload.
1398  *
1399  * 212/2 (bytes per extent) = 106 extents.
1400  * 106/2 (extents per word) = 53 words.
1401  * lpfc_id_range id is statically size to 53.
1402  *
1403  * This mailbox definition is used for ALLOC or GET_ALLOCATED
1404  * extent ranges.  For ALLOC, the type and cnt are required.
1405  * For GET_ALLOCATED, only the type is required.
1406  */
1407 struct lpfc_mbx_alloc_rsrc_extents {
1408         struct mbox_header header;
1409         union {
1410                 struct {
1411                         uint32_t word4;
1412 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT  0
1413 #define lpfc_mbx_alloc_rsrc_extents_type_MASK   0x0000FFFF
1414 #define lpfc_mbx_alloc_rsrc_extents_type_WORD   word4
1415 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT   16
1416 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK    0x0000FFFF
1417 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD    word4
1418                 } req;
1419                 struct {
1420                         uint32_t word4;
1421 #define lpfc_mbx_rsrc_cnt_SHIFT 0
1422 #define lpfc_mbx_rsrc_cnt_MASK  0x0000FFFF
1423 #define lpfc_mbx_rsrc_cnt_WORD  word4
1424                         struct lpfc_id_range id[53];
1425                 } rsp;
1426         } u;
1427 };
1428
1429 /*
1430  * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
1431  * structure shares the same SHIFT/MASK/WORD defines provided in the
1432  * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
1433  * the structures defined above.  This non-embedded structure provides for the
1434  * maximum number of extents supported by the port.
1435  */
1436 struct lpfc_mbx_nembed_rsrc_extent {
1437         union  lpfc_sli4_cfg_shdr cfg_shdr;
1438         uint32_t word4;
1439         struct lpfc_id_range id;
1440 };
1441
1442 struct lpfc_mbx_dealloc_rsrc_extents {
1443         struct mbox_header header;
1444         struct {
1445                 uint32_t word4;
1446 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT        0
1447 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK         0x0000FFFF
1448 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD         word4
1449         } req;
1450
1451 };
1452
1453 /* Start SLI4 FCoE specific mbox structures. */
1454
1455 struct lpfc_mbx_post_hdr_tmpl {
1456         struct mbox_header header;
1457         uint32_t word10;
1458 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT  0
1459 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK   0x0000FFFF
1460 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD   word10
1461 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT   16
1462 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK    0x0000FFFF
1463 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD    word10
1464         uint32_t rpi_paddr_lo;
1465         uint32_t rpi_paddr_hi;
1466 };
1467
1468 struct sli4_sge {       /* SLI-4 */
1469         uint32_t addr_hi;
1470         uint32_t addr_lo;
1471
1472         uint32_t word2;
1473 #define lpfc_sli4_sge_offset_SHIFT      0 /* Offset of buffer - Not used*/
1474 #define lpfc_sli4_sge_offset_MASK       0x1FFFFFFF
1475 #define lpfc_sli4_sge_offset_WORD       word2
1476 #define lpfc_sli4_sge_last_SHIFT        31 /* Last SEG in the SGL sets
1477                                                 this  flag !! */
1478 #define lpfc_sli4_sge_last_MASK         0x00000001
1479 #define lpfc_sli4_sge_last_WORD         word2
1480         uint32_t sge_len;
1481 };
1482
1483 struct fcf_record {
1484         uint32_t max_rcv_size;
1485         uint32_t fka_adv_period;
1486         uint32_t fip_priority;
1487         uint32_t word3;
1488 #define lpfc_fcf_record_mac_0_SHIFT             0
1489 #define lpfc_fcf_record_mac_0_MASK              0x000000FF
1490 #define lpfc_fcf_record_mac_0_WORD              word3
1491 #define lpfc_fcf_record_mac_1_SHIFT             8
1492 #define lpfc_fcf_record_mac_1_MASK              0x000000FF
1493 #define lpfc_fcf_record_mac_1_WORD              word3
1494 #define lpfc_fcf_record_mac_2_SHIFT             16
1495 #define lpfc_fcf_record_mac_2_MASK              0x000000FF
1496 #define lpfc_fcf_record_mac_2_WORD              word3
1497 #define lpfc_fcf_record_mac_3_SHIFT             24
1498 #define lpfc_fcf_record_mac_3_MASK              0x000000FF
1499 #define lpfc_fcf_record_mac_3_WORD              word3
1500         uint32_t word4;
1501 #define lpfc_fcf_record_mac_4_SHIFT             0
1502 #define lpfc_fcf_record_mac_4_MASK              0x000000FF
1503 #define lpfc_fcf_record_mac_4_WORD              word4
1504 #define lpfc_fcf_record_mac_5_SHIFT             8
1505 #define lpfc_fcf_record_mac_5_MASK              0x000000FF
1506 #define lpfc_fcf_record_mac_5_WORD              word4
1507 #define lpfc_fcf_record_fcf_avail_SHIFT         16
1508 #define lpfc_fcf_record_fcf_avail_MASK          0x000000FF
1509 #define lpfc_fcf_record_fcf_avail_WORD          word4
1510 #define lpfc_fcf_record_mac_addr_prov_SHIFT     24
1511 #define lpfc_fcf_record_mac_addr_prov_MASK      0x000000FF
1512 #define lpfc_fcf_record_mac_addr_prov_WORD      word4
1513 #define LPFC_FCF_FPMA           1       /* Fabric Provided MAC Address */
1514 #define LPFC_FCF_SPMA           2       /* Server Provided MAC Address */
1515         uint32_t word5;
1516 #define lpfc_fcf_record_fab_name_0_SHIFT        0
1517 #define lpfc_fcf_record_fab_name_0_MASK         0x000000FF
1518 #define lpfc_fcf_record_fab_name_0_WORD         word5
1519 #define lpfc_fcf_record_fab_name_1_SHIFT        8
1520 #define lpfc_fcf_record_fab_name_1_MASK         0x000000FF
1521 #define lpfc_fcf_record_fab_name_1_WORD         word5
1522 #define lpfc_fcf_record_fab_name_2_SHIFT        16
1523 #define lpfc_fcf_record_fab_name_2_MASK         0x000000FF
1524 #define lpfc_fcf_record_fab_name_2_WORD         word5
1525 #define lpfc_fcf_record_fab_name_3_SHIFT        24
1526 #define lpfc_fcf_record_fab_name_3_MASK         0x000000FF
1527 #define lpfc_fcf_record_fab_name_3_WORD         word5
1528         uint32_t word6;
1529 #define lpfc_fcf_record_fab_name_4_SHIFT        0
1530 #define lpfc_fcf_record_fab_name_4_MASK         0x000000FF
1531 #define lpfc_fcf_record_fab_name_4_WORD         word6
1532 #define lpfc_fcf_record_fab_name_5_SHIFT        8
1533 #define lpfc_fcf_record_fab_name_5_MASK         0x000000FF
1534 #define lpfc_fcf_record_fab_name_5_WORD         word6
1535 #define lpfc_fcf_record_fab_name_6_SHIFT        16
1536 #define lpfc_fcf_record_fab_name_6_MASK         0x000000FF
1537 #define lpfc_fcf_record_fab_name_6_WORD         word6
1538 #define lpfc_fcf_record_fab_name_7_SHIFT        24
1539 #define lpfc_fcf_record_fab_name_7_MASK         0x000000FF
1540 #define lpfc_fcf_record_fab_name_7_WORD         word6
1541         uint32_t word7;
1542 #define lpfc_fcf_record_fc_map_0_SHIFT          0
1543 #define lpfc_fcf_record_fc_map_0_MASK           0x000000FF
1544 #define lpfc_fcf_record_fc_map_0_WORD           word7
1545 #define lpfc_fcf_record_fc_map_1_SHIFT          8
1546 #define lpfc_fcf_record_fc_map_1_MASK           0x000000FF
1547 #define lpfc_fcf_record_fc_map_1_WORD           word7
1548 #define lpfc_fcf_record_fc_map_2_SHIFT          16
1549 #define lpfc_fcf_record_fc_map_2_MASK           0x000000FF
1550 #define lpfc_fcf_record_fc_map_2_WORD           word7
1551 #define lpfc_fcf_record_fcf_valid_SHIFT         24
1552 #define lpfc_fcf_record_fcf_valid_MASK          0x000000FF
1553 #define lpfc_fcf_record_fcf_valid_WORD          word7
1554         uint32_t word8;
1555 #define lpfc_fcf_record_fcf_index_SHIFT         0
1556 #define lpfc_fcf_record_fcf_index_MASK          0x0000FFFF
1557 #define lpfc_fcf_record_fcf_index_WORD          word8
1558 #define lpfc_fcf_record_fcf_state_SHIFT         16
1559 #define lpfc_fcf_record_fcf_state_MASK          0x0000FFFF
1560 #define lpfc_fcf_record_fcf_state_WORD          word8
1561         uint8_t vlan_bitmap[512];
1562         uint32_t word137;
1563 #define lpfc_fcf_record_switch_name_0_SHIFT     0
1564 #define lpfc_fcf_record_switch_name_0_MASK      0x000000FF
1565 #define lpfc_fcf_record_switch_name_0_WORD      word137
1566 #define lpfc_fcf_record_switch_name_1_SHIFT     8
1567 #define lpfc_fcf_record_switch_name_1_MASK      0x000000FF
1568 #define lpfc_fcf_record_switch_name_1_WORD      word137
1569 #define lpfc_fcf_record_switch_name_2_SHIFT     16
1570 #define lpfc_fcf_record_switch_name_2_MASK      0x000000FF
1571 #define lpfc_fcf_record_switch_name_2_WORD      word137
1572 #define lpfc_fcf_record_switch_name_3_SHIFT     24
1573 #define lpfc_fcf_record_switch_name_3_MASK      0x000000FF
1574 #define lpfc_fcf_record_switch_name_3_WORD      word137
1575         uint32_t word138;
1576 #define lpfc_fcf_record_switch_name_4_SHIFT     0
1577 #define lpfc_fcf_record_switch_name_4_MASK      0x000000FF
1578 #define lpfc_fcf_record_switch_name_4_WORD      word138
1579 #define lpfc_fcf_record_switch_name_5_SHIFT     8
1580 #define lpfc_fcf_record_switch_name_5_MASK      0x000000FF
1581 #define lpfc_fcf_record_switch_name_5_WORD      word138
1582 #define lpfc_fcf_record_switch_name_6_SHIFT     16
1583 #define lpfc_fcf_record_switch_name_6_MASK      0x000000FF
1584 #define lpfc_fcf_record_switch_name_6_WORD      word138
1585 #define lpfc_fcf_record_switch_name_7_SHIFT     24
1586 #define lpfc_fcf_record_switch_name_7_MASK      0x000000FF
1587 #define lpfc_fcf_record_switch_name_7_WORD      word138
1588 };
1589
1590 struct lpfc_mbx_read_fcf_tbl {
1591         union lpfc_sli4_cfg_shdr cfg_shdr;
1592         union {
1593                 struct {
1594                         uint32_t word10;
1595 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT        0
1596 #define lpfc_mbx_read_fcf_tbl_indx_MASK         0x0000FFFF
1597 #define lpfc_mbx_read_fcf_tbl_indx_WORD         word10
1598                 } request;
1599                 struct {
1600                         uint32_t eventag;
1601                 } response;
1602         } u;
1603         uint32_t word11;
1604 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT   0
1605 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK    0x0000FFFF
1606 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD    word11
1607 };
1608
1609 struct lpfc_mbx_add_fcf_tbl_entry {
1610         union lpfc_sli4_cfg_shdr cfg_shdr;
1611         uint32_t word10;
1612 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT        0
1613 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK         0x0000FFFF
1614 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD         word10
1615         struct lpfc_mbx_sge fcf_sge;
1616 };
1617
1618 struct lpfc_mbx_del_fcf_tbl_entry {
1619         struct mbox_header header;
1620         uint32_t word10;
1621 #define lpfc_mbx_del_fcf_tbl_count_SHIFT        0
1622 #define lpfc_mbx_del_fcf_tbl_count_MASK         0x0000FFFF
1623 #define lpfc_mbx_del_fcf_tbl_count_WORD         word10
1624 #define lpfc_mbx_del_fcf_tbl_index_SHIFT        16
1625 #define lpfc_mbx_del_fcf_tbl_index_MASK         0x0000FFFF
1626 #define lpfc_mbx_del_fcf_tbl_index_WORD         word10
1627 };
1628
1629 struct lpfc_mbx_redisc_fcf_tbl {
1630         struct mbox_header header;
1631         uint32_t word10;
1632 #define lpfc_mbx_redisc_fcf_count_SHIFT         0
1633 #define lpfc_mbx_redisc_fcf_count_MASK          0x0000FFFF
1634 #define lpfc_mbx_redisc_fcf_count_WORD          word10
1635         uint32_t resvd;
1636         uint32_t word12;
1637 #define lpfc_mbx_redisc_fcf_index_SHIFT         0
1638 #define lpfc_mbx_redisc_fcf_index_MASK          0x0000FFFF
1639 #define lpfc_mbx_redisc_fcf_index_WORD          word12
1640 };
1641
1642 struct lpfc_mbx_query_fw_cfg {
1643         struct mbox_header header;
1644         uint32_t config_number;
1645         uint32_t asic_rev;
1646         uint32_t phys_port;
1647         uint32_t function_mode;
1648 /* firmware Function Mode */
1649 #define lpfc_function_mode_toe_SHIFT            0
1650 #define lpfc_function_mode_toe_MASK             0x00000001
1651 #define lpfc_function_mode_toe_WORD             function_mode
1652 #define lpfc_function_mode_nic_SHIFT            1
1653 #define lpfc_function_mode_nic_MASK             0x00000001
1654 #define lpfc_function_mode_nic_WORD             function_mode
1655 #define lpfc_function_mode_rdma_SHIFT           2
1656 #define lpfc_function_mode_rdma_MASK            0x00000001
1657 #define lpfc_function_mode_rdma_WORD            function_mode
1658 #define lpfc_function_mode_vm_SHIFT             3
1659 #define lpfc_function_mode_vm_MASK              0x00000001
1660 #define lpfc_function_mode_vm_WORD              function_mode
1661 #define lpfc_function_mode_iscsi_i_SHIFT        4
1662 #define lpfc_function_mode_iscsi_i_MASK         0x00000001
1663 #define lpfc_function_mode_iscsi_i_WORD         function_mode
1664 #define lpfc_function_mode_iscsi_t_SHIFT        5
1665 #define lpfc_function_mode_iscsi_t_MASK         0x00000001
1666 #define lpfc_function_mode_iscsi_t_WORD         function_mode
1667 #define lpfc_function_mode_fcoe_i_SHIFT         6
1668 #define lpfc_function_mode_fcoe_i_MASK          0x00000001
1669 #define lpfc_function_mode_fcoe_i_WORD          function_mode
1670 #define lpfc_function_mode_fcoe_t_SHIFT         7
1671 #define lpfc_function_mode_fcoe_t_MASK          0x00000001
1672 #define lpfc_function_mode_fcoe_t_WORD          function_mode
1673 #define lpfc_function_mode_dal_SHIFT            8
1674 #define lpfc_function_mode_dal_MASK             0x00000001
1675 #define lpfc_function_mode_dal_WORD             function_mode
1676 #define lpfc_function_mode_lro_SHIFT            9
1677 #define lpfc_function_mode_lro_MASK             0x00000001
1678 #define lpfc_function_mode_lro_WORD             function_mode
1679 #define lpfc_function_mode_flex10_SHIFT         10
1680 #define lpfc_function_mode_flex10_MASK          0x00000001
1681 #define lpfc_function_mode_flex10_WORD          function_mode
1682 #define lpfc_function_mode_ncsi_SHIFT           11
1683 #define lpfc_function_mode_ncsi_MASK            0x00000001
1684 #define lpfc_function_mode_ncsi_WORD            function_mode
1685 };
1686
1687 /* Status field for embedded SLI_CONFIG mailbox command */
1688 #define STATUS_SUCCESS                                  0x0
1689 #define STATUS_FAILED                                   0x1
1690 #define STATUS_ILLEGAL_REQUEST                          0x2
1691 #define STATUS_ILLEGAL_FIELD                            0x3
1692 #define STATUS_INSUFFICIENT_BUFFER                      0x4
1693 #define STATUS_UNAUTHORIZED_REQUEST                     0x5
1694 #define STATUS_FLASHROM_SAVE_FAILED                     0x17
1695 #define STATUS_FLASHROM_RESTORE_FAILED                  0x18
1696 #define STATUS_ICCBINDEX_ALLOC_FAILED                   0x1a
1697 #define STATUS_IOCTLHANDLE_ALLOC_FAILED                 0x1b
1698 #define STATUS_INVALID_PHY_ADDR_FROM_OSM                0x1c
1699 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM            0x1d
1700 #define STATUS_ASSERT_FAILED                            0x1e
1701 #define STATUS_INVALID_SESSION                          0x1f
1702 #define STATUS_INVALID_CONNECTION                       0x20
1703 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT               0x21
1704 #define STATUS_BTL_NO_FREE_SLOT_PATH                    0x24
1705 #define STATUS_BTL_NO_FREE_SLOT_TGTID                   0x25
1706 #define STATUS_OSM_DEVSLOT_NOT_FOUND                    0x26
1707 #define STATUS_FLASHROM_READ_FAILED                     0x27
1708 #define STATUS_POLL_IOCTL_TIMEOUT                       0x28
1709 #define STATUS_ERROR_ACITMAIN                           0x2a
1710 #define STATUS_REBOOT_REQUIRED                          0x2c
1711 #define STATUS_FCF_IN_USE                               0x3a
1712 #define STATUS_FCF_TABLE_EMPTY                          0x43
1713
1714 struct lpfc_mbx_sli4_config {
1715         struct mbox_header header;
1716 };
1717
1718 struct lpfc_mbx_init_vfi {
1719         uint32_t word1;
1720 #define lpfc_init_vfi_vr_SHIFT          31
1721 #define lpfc_init_vfi_vr_MASK           0x00000001
1722 #define lpfc_init_vfi_vr_WORD           word1
1723 #define lpfc_init_vfi_vt_SHIFT          30
1724 #define lpfc_init_vfi_vt_MASK           0x00000001
1725 #define lpfc_init_vfi_vt_WORD           word1
1726 #define lpfc_init_vfi_vf_SHIFT          29
1727 #define lpfc_init_vfi_vf_MASK           0x00000001
1728 #define lpfc_init_vfi_vf_WORD           word1
1729 #define lpfc_init_vfi_vp_SHIFT          28
1730 #define lpfc_init_vfi_vp_MASK           0x00000001
1731 #define lpfc_init_vfi_vp_WORD           word1
1732 #define lpfc_init_vfi_vfi_SHIFT         0
1733 #define lpfc_init_vfi_vfi_MASK          0x0000FFFF
1734 #define lpfc_init_vfi_vfi_WORD          word1
1735         uint32_t word2;
1736 #define lpfc_init_vfi_vpi_SHIFT         16
1737 #define lpfc_init_vfi_vpi_MASK          0x0000FFFF
1738 #define lpfc_init_vfi_vpi_WORD          word2
1739 #define lpfc_init_vfi_fcfi_SHIFT        0
1740 #define lpfc_init_vfi_fcfi_MASK         0x0000FFFF
1741 #define lpfc_init_vfi_fcfi_WORD         word2
1742         uint32_t word3;
1743 #define lpfc_init_vfi_pri_SHIFT         13
1744 #define lpfc_init_vfi_pri_MASK          0x00000007
1745 #define lpfc_init_vfi_pri_WORD          word3
1746 #define lpfc_init_vfi_vf_id_SHIFT       1
1747 #define lpfc_init_vfi_vf_id_MASK        0x00000FFF
1748 #define lpfc_init_vfi_vf_id_WORD        word3
1749         uint32_t word4;
1750 #define lpfc_init_vfi_hop_count_SHIFT   24
1751 #define lpfc_init_vfi_hop_count_MASK    0x000000FF
1752 #define lpfc_init_vfi_hop_count_WORD    word4
1753 };
1754
1755 struct lpfc_mbx_reg_vfi {
1756         uint32_t word1;
1757 #define lpfc_reg_vfi_vp_SHIFT           28
1758 #define lpfc_reg_vfi_vp_MASK            0x00000001
1759 #define lpfc_reg_vfi_vp_WORD            word1
1760 #define lpfc_reg_vfi_vfi_SHIFT          0
1761 #define lpfc_reg_vfi_vfi_MASK           0x0000FFFF
1762 #define lpfc_reg_vfi_vfi_WORD           word1
1763         uint32_t word2;
1764 #define lpfc_reg_vfi_vpi_SHIFT          16
1765 #define lpfc_reg_vfi_vpi_MASK           0x0000FFFF
1766 #define lpfc_reg_vfi_vpi_WORD           word2
1767 #define lpfc_reg_vfi_fcfi_SHIFT         0
1768 #define lpfc_reg_vfi_fcfi_MASK          0x0000FFFF
1769 #define lpfc_reg_vfi_fcfi_WORD          word2
1770         uint32_t wwn[2];
1771         struct ulp_bde64 bde;
1772         uint32_t e_d_tov;
1773         uint32_t r_a_tov;
1774         uint32_t word10;
1775 #define lpfc_reg_vfi_nport_id_SHIFT             0
1776 #define lpfc_reg_vfi_nport_id_MASK              0x00FFFFFF
1777 #define lpfc_reg_vfi_nport_id_WORD              word10
1778 };
1779
1780 struct lpfc_mbx_init_vpi {
1781         uint32_t word1;
1782 #define lpfc_init_vpi_vfi_SHIFT         16
1783 #define lpfc_init_vpi_vfi_MASK          0x0000FFFF
1784 #define lpfc_init_vpi_vfi_WORD          word1
1785 #define lpfc_init_vpi_vpi_SHIFT         0
1786 #define lpfc_init_vpi_vpi_MASK          0x0000FFFF
1787 #define lpfc_init_vpi_vpi_WORD          word1
1788 };
1789
1790 struct lpfc_mbx_read_vpi {
1791         uint32_t word1_rsvd;
1792         uint32_t word2;
1793 #define lpfc_mbx_read_vpi_vnportid_SHIFT        0
1794 #define lpfc_mbx_read_vpi_vnportid_MASK         0x00FFFFFF
1795 #define lpfc_mbx_read_vpi_vnportid_WORD         word2
1796         uint32_t word3_rsvd;
1797         uint32_t word4;
1798 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT        0
1799 #define lpfc_mbx_read_vpi_acq_alpa_MASK         0x000000FF
1800 #define lpfc_mbx_read_vpi_acq_alpa_WORD         word4
1801 #define lpfc_mbx_read_vpi_pb_SHIFT              15
1802 #define lpfc_mbx_read_vpi_pb_MASK               0x00000001
1803 #define lpfc_mbx_read_vpi_pb_WORD               word4
1804 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT       16
1805 #define lpfc_mbx_read_vpi_spec_alpa_MASK        0x000000FF
1806 #define lpfc_mbx_read_vpi_spec_alpa_WORD        word4
1807 #define lpfc_mbx_read_vpi_ns_SHIFT              30
1808 #define lpfc_mbx_read_vpi_ns_MASK               0x00000001
1809 #define lpfc_mbx_read_vpi_ns_WORD               word4
1810 #define lpfc_mbx_read_vpi_hl_SHIFT              31
1811 #define lpfc_mbx_read_vpi_hl_MASK               0x00000001
1812 #define lpfc_mbx_read_vpi_hl_WORD               word4
1813         uint32_t word5_rsvd;
1814         uint32_t word6;
1815 #define lpfc_mbx_read_vpi_vpi_SHIFT             0
1816 #define lpfc_mbx_read_vpi_vpi_MASK              0x0000FFFF
1817 #define lpfc_mbx_read_vpi_vpi_WORD              word6
1818         uint32_t word7;
1819 #define lpfc_mbx_read_vpi_mac_0_SHIFT           0
1820 #define lpfc_mbx_read_vpi_mac_0_MASK            0x000000FF
1821 #define lpfc_mbx_read_vpi_mac_0_WORD            word7
1822 #define lpfc_mbx_read_vpi_mac_1_SHIFT           8
1823 #define lpfc_mbx_read_vpi_mac_1_MASK            0x000000FF
1824 #define lpfc_mbx_read_vpi_mac_1_WORD            word7
1825 #define lpfc_mbx_read_vpi_mac_2_SHIFT           16
1826 #define lpfc_mbx_read_vpi_mac_2_MASK            0x000000FF
1827 #define lpfc_mbx_read_vpi_mac_2_WORD            word7
1828 #define lpfc_mbx_read_vpi_mac_3_SHIFT           24
1829 #define lpfc_mbx_read_vpi_mac_3_MASK            0x000000FF
1830 #define lpfc_mbx_read_vpi_mac_3_WORD            word7
1831         uint32_t word8;
1832 #define lpfc_mbx_read_vpi_mac_4_SHIFT           0
1833 #define lpfc_mbx_read_vpi_mac_4_MASK            0x000000FF
1834 #define lpfc_mbx_read_vpi_mac_4_WORD            word8
1835 #define lpfc_mbx_read_vpi_mac_5_SHIFT           8
1836 #define lpfc_mbx_read_vpi_mac_5_MASK            0x000000FF
1837 #define lpfc_mbx_read_vpi_mac_5_WORD            word8
1838 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT        16
1839 #define lpfc_mbx_read_vpi_vlan_tag_MASK         0x00000FFF
1840 #define lpfc_mbx_read_vpi_vlan_tag_WORD         word8
1841 #define lpfc_mbx_read_vpi_vv_SHIFT              28
1842 #define lpfc_mbx_read_vpi_vv_MASK               0x0000001
1843 #define lpfc_mbx_read_vpi_vv_WORD               word8
1844 };
1845
1846 struct lpfc_mbx_unreg_vfi {
1847         uint32_t word1_rsvd;
1848         uint32_t word2;
1849 #define lpfc_unreg_vfi_vfi_SHIFT        0
1850 #define lpfc_unreg_vfi_vfi_MASK         0x0000FFFF
1851 #define lpfc_unreg_vfi_vfi_WORD         word2
1852 };
1853
1854 struct lpfc_mbx_resume_rpi {
1855         uint32_t word1;
1856 #define lpfc_resume_rpi_index_SHIFT     0
1857 #define lpfc_resume_rpi_index_MASK      0x0000FFFF
1858 #define lpfc_resume_rpi_index_WORD      word1
1859 #define lpfc_resume_rpi_ii_SHIFT        30
1860 #define lpfc_resume_rpi_ii_MASK         0x00000003
1861 #define lpfc_resume_rpi_ii_WORD         word1
1862 #define RESUME_INDEX_RPI                0
1863 #define RESUME_INDEX_VPI                1
1864 #define RESUME_INDEX_VFI                2
1865 #define RESUME_INDEX_FCFI               3
1866         uint32_t event_tag;
1867 };
1868
1869 #define REG_FCF_INVALID_QID     0xFFFF
1870 struct lpfc_mbx_reg_fcfi {
1871         uint32_t word1;
1872 #define lpfc_reg_fcfi_info_index_SHIFT  0
1873 #define lpfc_reg_fcfi_info_index_MASK   0x0000FFFF
1874 #define lpfc_reg_fcfi_info_index_WORD   word1
1875 #define lpfc_reg_fcfi_fcfi_SHIFT        16
1876 #define lpfc_reg_fcfi_fcfi_MASK         0x0000FFFF
1877 #define lpfc_reg_fcfi_fcfi_WORD         word1
1878         uint32_t word2;
1879 #define lpfc_reg_fcfi_rq_id1_SHIFT      0
1880 #define lpfc_reg_fcfi_rq_id1_MASK       0x0000FFFF
1881 #define lpfc_reg_fcfi_rq_id1_WORD       word2
1882 #define lpfc_reg_fcfi_rq_id0_SHIFT      16
1883 #define lpfc_reg_fcfi_rq_id0_MASK       0x0000FFFF
1884 #define lpfc_reg_fcfi_rq_id0_WORD       word2
1885         uint32_t word3;
1886 #define lpfc_reg_fcfi_rq_id3_SHIFT      0
1887 #define lpfc_reg_fcfi_rq_id3_MASK       0x0000FFFF
1888 #define lpfc_reg_fcfi_rq_id3_WORD       word3
1889 #define lpfc_reg_fcfi_rq_id2_SHIFT      16
1890 #define lpfc_reg_fcfi_rq_id2_MASK       0x0000FFFF
1891 #define lpfc_reg_fcfi_rq_id2_WORD       word3
1892         uint32_t word4;
1893 #define lpfc_reg_fcfi_type_match0_SHIFT 24
1894 #define lpfc_reg_fcfi_type_match0_MASK  0x000000FF
1895 #define lpfc_reg_fcfi_type_match0_WORD  word4
1896 #define lpfc_reg_fcfi_type_mask0_SHIFT  16
1897 #define lpfc_reg_fcfi_type_mask0_MASK   0x000000FF
1898 #define lpfc_reg_fcfi_type_mask0_WORD   word4
1899 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
1900 #define lpfc_reg_fcfi_rctl_match0_MASK  0x000000FF
1901 #define lpfc_reg_fcfi_rctl_match0_WORD  word4
1902 #define lpfc_reg_fcfi_rctl_mask0_SHIFT  0
1903 #define lpfc_reg_fcfi_rctl_mask0_MASK   0x000000FF
1904 #define lpfc_reg_fcfi_rctl_mask0_WORD   word4
1905         uint32_t word5;
1906 #define lpfc_reg_fcfi_type_match1_SHIFT 24
1907 #define lpfc_reg_fcfi_type_match1_MASK  0x000000FF
1908 #define lpfc_reg_fcfi_type_match1_WORD  word5
1909 #define lpfc_reg_fcfi_type_mask1_SHIFT  16
1910 #define lpfc_reg_fcfi_type_mask1_MASK   0x000000FF
1911 #define lpfc_reg_fcfi_type_mask1_WORD   word5
1912 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
1913 #define lpfc_reg_fcfi_rctl_match1_MASK  0x000000FF
1914 #define lpfc_reg_fcfi_rctl_match1_WORD  word5
1915 #define lpfc_reg_fcfi_rctl_mask1_SHIFT  0
1916 #define lpfc_reg_fcfi_rctl_mask1_MASK   0x000000FF
1917 #define lpfc_reg_fcfi_rctl_mask1_WORD   word5
1918         uint32_t word6;
1919 #define lpfc_reg_fcfi_type_match2_SHIFT 24
1920 #define lpfc_reg_fcfi_type_match2_MASK  0x000000FF
1921 #define lpfc_reg_fcfi_type_match2_WORD  word6
1922 #define lpfc_reg_fcfi_type_mask2_SHIFT  16
1923 #define lpfc_reg_fcfi_type_mask2_MASK   0x000000FF
1924 #define lpfc_reg_fcfi_type_mask2_WORD   word6
1925 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
1926 #define lpfc_reg_fcfi_rctl_match2_MASK  0x000000FF
1927 #define lpfc_reg_fcfi_rctl_match2_WORD  word6
1928 #define lpfc_reg_fcfi_rctl_mask2_SHIFT  0
1929 #define lpfc_reg_fcfi_rctl_mask2_MASK   0x000000FF
1930 #define lpfc_reg_fcfi_rctl_mask2_WORD   word6
1931         uint32_t word7;
1932 #define lpfc_reg_fcfi_type_match3_SHIFT 24
1933 #define lpfc_reg_fcfi_type_match3_MASK  0x000000FF
1934 #define lpfc_reg_fcfi_type_match3_WORD  word7
1935 #define lpfc_reg_fcfi_type_mask3_SHIFT  16
1936 #define lpfc_reg_fcfi_type_mask3_MASK   0x000000FF
1937 #define lpfc_reg_fcfi_type_mask3_WORD   word7
1938 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
1939 #define lpfc_reg_fcfi_rctl_match3_MASK  0x000000FF
1940 #define lpfc_reg_fcfi_rctl_match3_WORD  word7
1941 #define lpfc_reg_fcfi_rctl_mask3_SHIFT  0
1942 #define lpfc_reg_fcfi_rctl_mask3_MASK   0x000000FF
1943 #define lpfc_reg_fcfi_rctl_mask3_WORD   word7
1944         uint32_t word8;
1945 #define lpfc_reg_fcfi_mam_SHIFT         13
1946 #define lpfc_reg_fcfi_mam_MASK          0x00000003
1947 #define lpfc_reg_fcfi_mam_WORD          word8
1948 #define LPFC_MAM_BOTH           0       /* Both SPMA and FPMA */
1949 #define LPFC_MAM_SPMA           1       /* Server Provided MAC Address */
1950 #define LPFC_MAM_FPMA           2       /* Fabric Provided MAC Address */
1951 #define lpfc_reg_fcfi_vv_SHIFT          12
1952 #define lpfc_reg_fcfi_vv_MASK           0x00000001
1953 #define lpfc_reg_fcfi_vv_WORD           word8
1954 #define lpfc_reg_fcfi_vlan_tag_SHIFT    0
1955 #define lpfc_reg_fcfi_vlan_tag_MASK     0x00000FFF
1956 #define lpfc_reg_fcfi_vlan_tag_WORD     word8
1957 };
1958
1959 struct lpfc_mbx_unreg_fcfi {
1960         uint32_t word1_rsv;
1961         uint32_t word2;
1962 #define lpfc_unreg_fcfi_SHIFT           0
1963 #define lpfc_unreg_fcfi_MASK            0x0000FFFF
1964 #define lpfc_unreg_fcfi_WORD            word2
1965 };
1966
1967 struct lpfc_mbx_read_rev {
1968         uint32_t word1;
1969 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT           16
1970 #define lpfc_mbx_rd_rev_sli_lvl_MASK            0x0000000F
1971 #define lpfc_mbx_rd_rev_sli_lvl_WORD            word1
1972 #define lpfc_mbx_rd_rev_fcoe_SHIFT              20
1973 #define lpfc_mbx_rd_rev_fcoe_MASK               0x00000001
1974 #define lpfc_mbx_rd_rev_fcoe_WORD               word1
1975 #define lpfc_mbx_rd_rev_cee_ver_SHIFT           21
1976 #define lpfc_mbx_rd_rev_cee_ver_MASK            0x00000003
1977 #define lpfc_mbx_rd_rev_cee_ver_WORD            word1
1978 #define LPFC_PREDCBX_CEE_MODE   0
1979 #define LPFC_DCBX_CEE_MODE      1
1980 #define lpfc_mbx_rd_rev_vpd_SHIFT               29
1981 #define lpfc_mbx_rd_rev_vpd_MASK                0x00000001
1982 #define lpfc_mbx_rd_rev_vpd_WORD                word1
1983         uint32_t first_hw_rev;
1984         uint32_t second_hw_rev;
1985         uint32_t word4_rsvd;
1986         uint32_t third_hw_rev;
1987         uint32_t word6;
1988 #define lpfc_mbx_rd_rev_fcph_low_SHIFT          0
1989 #define lpfc_mbx_rd_rev_fcph_low_MASK           0x000000FF
1990 #define lpfc_mbx_rd_rev_fcph_low_WORD           word6
1991 #define lpfc_mbx_rd_rev_fcph_high_SHIFT         8
1992 #define lpfc_mbx_rd_rev_fcph_high_MASK          0x000000FF
1993 #define lpfc_mbx_rd_rev_fcph_high_WORD          word6
1994 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT       16
1995 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK        0x000000FF
1996 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD        word6
1997 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT      24
1998 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK       0x000000FF
1999 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD       word6
2000         uint32_t word7_rsvd;
2001         uint32_t fw_id_rev;
2002         uint8_t  fw_name[16];
2003         uint32_t ulp_fw_id_rev;
2004         uint8_t  ulp_fw_name[16];
2005         uint32_t word18_47_rsvd[30];
2006         uint32_t word48;
2007 #define lpfc_mbx_rd_rev_avail_len_SHIFT         0
2008 #define lpfc_mbx_rd_rev_avail_len_MASK          0x00FFFFFF
2009 #define lpfc_mbx_rd_rev_avail_len_WORD          word48
2010         uint32_t vpd_paddr_low;
2011         uint32_t vpd_paddr_high;
2012         uint32_t avail_vpd_len;
2013         uint32_t rsvd_52_63[12];
2014 };
2015
2016 struct lpfc_mbx_read_config {
2017         uint32_t word1;
2018 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT     31
2019 #define lpfc_mbx_rd_conf_extnts_inuse_MASK      0x00000001
2020 #define lpfc_mbx_rd_conf_extnts_inuse_WORD      word1
2021         uint32_t word2;
2022 #define lpfc_mbx_rd_conf_topology_SHIFT         24
2023 #define lpfc_mbx_rd_conf_topology_MASK          0x000000FF
2024 #define lpfc_mbx_rd_conf_topology_WORD          word2
2025         uint32_t rsvd_3;
2026         uint32_t word4;
2027 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT          0
2028 #define lpfc_mbx_rd_conf_e_d_tov_MASK           0x0000FFFF
2029 #define lpfc_mbx_rd_conf_e_d_tov_WORD           word4
2030         uint32_t rsvd_5;
2031         uint32_t word6;
2032 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT          0
2033 #define lpfc_mbx_rd_conf_r_a_tov_MASK           0x0000FFFF
2034 #define lpfc_mbx_rd_conf_r_a_tov_WORD           word6
2035         uint32_t rsvd_7;
2036         uint32_t rsvd_8;
2037         uint32_t word9;
2038 #define lpfc_mbx_rd_conf_lmt_SHIFT              0
2039 #define lpfc_mbx_rd_conf_lmt_MASK               0x0000FFFF
2040 #define lpfc_mbx_rd_conf_lmt_WORD               word9
2041         uint32_t rsvd_10;
2042         uint32_t rsvd_11;
2043         uint32_t word12;
2044 #define lpfc_mbx_rd_conf_xri_base_SHIFT         0
2045 #define lpfc_mbx_rd_conf_xri_base_MASK          0x0000FFFF
2046 #define lpfc_mbx_rd_conf_xri_base_WORD          word12
2047 #define lpfc_mbx_rd_conf_xri_count_SHIFT        16
2048 #define lpfc_mbx_rd_conf_xri_count_MASK         0x0000FFFF
2049 #define lpfc_mbx_rd_conf_xri_count_WORD         word12
2050         uint32_t word13;
2051 #define lpfc_mbx_rd_conf_rpi_base_SHIFT         0
2052 #define lpfc_mbx_rd_conf_rpi_base_MASK          0x0000FFFF
2053 #define lpfc_mbx_rd_conf_rpi_base_WORD          word13
2054 #define lpfc_mbx_rd_conf_rpi_count_SHIFT        16
2055 #define lpfc_mbx_rd_conf_rpi_count_MASK         0x0000FFFF
2056 #define lpfc_mbx_rd_conf_rpi_count_WORD         word13
2057         uint32_t word14;
2058 #define lpfc_mbx_rd_conf_vpi_base_SHIFT         0
2059 #define lpfc_mbx_rd_conf_vpi_base_MASK          0x0000FFFF
2060 #define lpfc_mbx_rd_conf_vpi_base_WORD          word14
2061 #define lpfc_mbx_rd_conf_vpi_count_SHIFT        16
2062 #define lpfc_mbx_rd_conf_vpi_count_MASK         0x0000FFFF
2063 #define lpfc_mbx_rd_conf_vpi_count_WORD         word14
2064         uint32_t word15;
2065 #define lpfc_mbx_rd_conf_vfi_base_SHIFT         0
2066 #define lpfc_mbx_rd_conf_vfi_base_MASK          0x0000FFFF
2067 #define lpfc_mbx_rd_conf_vfi_base_WORD          word15
2068 #define lpfc_mbx_rd_conf_vfi_count_SHIFT        16
2069 #define lpfc_mbx_rd_conf_vfi_count_MASK         0x0000FFFF
2070 #define lpfc_mbx_rd_conf_vfi_count_WORD         word15
2071         uint32_t word16;
2072 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT       16
2073 #define lpfc_mbx_rd_conf_fcfi_count_MASK        0x0000FFFF
2074 #define lpfc_mbx_rd_conf_fcfi_count_WORD        word16
2075         uint32_t word17;
2076 #define lpfc_mbx_rd_conf_rq_count_SHIFT         0
2077 #define lpfc_mbx_rd_conf_rq_count_MASK          0x0000FFFF
2078 #define lpfc_mbx_rd_conf_rq_count_WORD          word17
2079 #define lpfc_mbx_rd_conf_eq_count_SHIFT         16
2080 #define lpfc_mbx_rd_conf_eq_count_MASK          0x0000FFFF
2081 #define lpfc_mbx_rd_conf_eq_count_WORD          word17
2082         uint32_t word18;
2083 #define lpfc_mbx_rd_conf_wq_count_SHIFT         0
2084 #define lpfc_mbx_rd_conf_wq_count_MASK          0x0000FFFF
2085 #define lpfc_mbx_rd_conf_wq_count_WORD          word18
2086 #define lpfc_mbx_rd_conf_cq_count_SHIFT         16
2087 #define lpfc_mbx_rd_conf_cq_count_MASK          0x0000FFFF
2088 #define lpfc_mbx_rd_conf_cq_count_WORD          word18
2089 };
2090
2091 struct lpfc_mbx_request_features {
2092         uint32_t word1;
2093 #define lpfc_mbx_rq_ftr_qry_SHIFT               0
2094 #define lpfc_mbx_rq_ftr_qry_MASK                0x00000001
2095 #define lpfc_mbx_rq_ftr_qry_WORD                word1
2096         uint32_t word2;
2097 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT           0
2098 #define lpfc_mbx_rq_ftr_rq_iaab_MASK            0x00000001
2099 #define lpfc_mbx_rq_ftr_rq_iaab_WORD            word2
2100 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT           1
2101 #define lpfc_mbx_rq_ftr_rq_npiv_MASK            0x00000001
2102 #define lpfc_mbx_rq_ftr_rq_npiv_WORD            word2
2103 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT            2
2104 #define lpfc_mbx_rq_ftr_rq_dif_MASK             0x00000001
2105 #define lpfc_mbx_rq_ftr_rq_dif_WORD             word2
2106 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT             3
2107 #define lpfc_mbx_rq_ftr_rq_vf_MASK              0x00000001
2108 #define lpfc_mbx_rq_ftr_rq_vf_WORD              word2
2109 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT           4
2110 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK            0x00000001
2111 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD            word2
2112 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT           5
2113 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK            0x00000001
2114 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD            word2
2115 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT           6
2116 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK            0x00000001
2117 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD            word2
2118 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT           7
2119 #define lpfc_mbx_rq_ftr_rq_ifip_MASK            0x00000001
2120 #define lpfc_mbx_rq_ftr_rq_ifip_WORD            word2
2121 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT          11
2122 #define lpfc_mbx_rq_ftr_rq_perfh_MASK           0x00000001
2123 #define lpfc_mbx_rq_ftr_rq_perfh_WORD           word2
2124         uint32_t word3;
2125 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT          0
2126 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK           0x00000001
2127 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD           word3
2128 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT          1
2129 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK           0x00000001
2130 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD           word3
2131 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT           2
2132 #define lpfc_mbx_rq_ftr_rsp_dif_MASK            0x00000001
2133 #define lpfc_mbx_rq_ftr_rsp_dif_WORD            word3
2134 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT            3
2135 #define lpfc_mbx_rq_ftr_rsp_vf__MASK            0x00000001
2136 #define lpfc_mbx_rq_ftr_rsp_vf_WORD             word3
2137 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT          4
2138 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK           0x00000001
2139 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD           word3
2140 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT          5
2141 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK           0x00000001
2142 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD           word3
2143 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT          6
2144 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK           0x00000001
2145 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD           word3
2146 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT          7
2147 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK           0x00000001
2148 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD           word3
2149 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT         11
2150 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK          0x00000001
2151 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD          word3
2152 };
2153
2154 struct lpfc_mbx_supp_pages {
2155         uint32_t word1;
2156 #define qs_SHIFT                                0
2157 #define qs_MASK                                 0x00000001
2158 #define qs_WORD                                 word1
2159 #define wr_SHIFT                                1
2160 #define wr_MASK                                 0x00000001
2161 #define wr_WORD                                 word1
2162 #define pf_SHIFT                                8
2163 #define pf_MASK                                 0x000000ff
2164 #define pf_WORD                                 word1
2165 #define cpn_SHIFT                               16
2166 #define cpn_MASK                                0x000000ff
2167 #define cpn_WORD                                word1
2168         uint32_t word2;
2169 #define list_offset_SHIFT                       0
2170 #define list_offset_MASK                        0x000000ff
2171 #define list_offset_WORD                        word2
2172 #define next_offset_SHIFT                       8
2173 #define next_offset_MASK                        0x000000ff
2174 #define next_offset_WORD                        word2
2175 #define elem_cnt_SHIFT                          16
2176 #define elem_cnt_MASK                           0x000000ff
2177 #define elem_cnt_WORD                           word2
2178         uint32_t word3;
2179 #define pn_0_SHIFT                              24
2180 #define pn_0_MASK                               0x000000ff
2181 #define pn_0_WORD                               word3
2182 #define pn_1_SHIFT                              16
2183 #define pn_1_MASK                               0x000000ff
2184 #define pn_1_WORD                               word3
2185 #define pn_2_SHIFT                              8
2186 #define pn_2_MASK                               0x000000ff
2187 #define pn_2_WORD                               word3
2188 #define pn_3_SHIFT                              0
2189 #define pn_3_MASK                               0x000000ff
2190 #define pn_3_WORD                               word3
2191         uint32_t word4;
2192 #define pn_4_SHIFT                              24
2193 #define pn_4_MASK                               0x000000ff
2194 #define pn_4_WORD                               word4
2195 #define pn_5_SHIFT                              16
2196 #define pn_5_MASK                               0x000000ff
2197 #define pn_5_WORD                               word4
2198 #define pn_6_SHIFT                              8
2199 #define pn_6_MASK                               0x000000ff
2200 #define pn_6_WORD                               word4
2201 #define pn_7_SHIFT                              0
2202 #define pn_7_MASK                               0x000000ff
2203 #define pn_7_WORD                               word4
2204         uint32_t rsvd[27];
2205 #define LPFC_SUPP_PAGES                 0
2206 #define LPFC_BLOCK_GUARD_PROFILES       1
2207 #define LPFC_SLI4_PARAMETERS            2
2208 };
2209
2210 struct lpfc_mbx_pc_sli4_params {
2211         uint32_t word1;
2212 #define qs_SHIFT                                0
2213 #define qs_MASK                                 0x00000001
2214 #define qs_WORD                                 word1
2215 #define wr_SHIFT                                1
2216 #define wr_MASK                                 0x00000001
2217 #define wr_WORD                                 word1
2218 #define pf_SHIFT                                8
2219 #define pf_MASK                                 0x000000ff
2220 #define pf_WORD                                 word1
2221 #define cpn_SHIFT                               16
2222 #define cpn_MASK                                0x000000ff
2223 #define cpn_WORD                                word1
2224         uint32_t word2;
2225 #define if_type_SHIFT                           0
2226 #define if_type_MASK                            0x00000007
2227 #define if_type_WORD                            word2
2228 #define sli_rev_SHIFT                           4
2229 #define sli_rev_MASK                            0x0000000f
2230 #define sli_rev_WORD                            word2
2231 #define sli_family_SHIFT                        8
2232 #define sli_family_MASK                         0x000000ff
2233 #define sli_family_WORD                         word2
2234 #define featurelevel_1_SHIFT                    16
2235 #define featurelevel_1_MASK                     0x000000ff
2236 #define featurelevel_1_WORD                     word2
2237 #define featurelevel_2_SHIFT                    24
2238 #define featurelevel_2_MASK                     0x0000001f
2239 #define featurelevel_2_WORD                     word2
2240         uint32_t word3;
2241 #define fcoe_SHIFT                              0
2242 #define fcoe_MASK                               0x00000001
2243 #define fcoe_WORD                               word3
2244 #define fc_SHIFT                                1
2245 #define fc_MASK                                 0x00000001
2246 #define fc_WORD                                 word3
2247 #define nic_SHIFT                               2
2248 #define nic_MASK                                0x00000001
2249 #define nic_WORD                                word3
2250 #define iscsi_SHIFT                             3
2251 #define iscsi_MASK                              0x00000001
2252 #define iscsi_WORD                              word3
2253 #define rdma_SHIFT                              4
2254 #define rdma_MASK                               0x00000001
2255 #define rdma_WORD                               word3
2256         uint32_t sge_supp_len;
2257 #define SLI4_PAGE_SIZE 4096
2258         uint32_t word5;
2259 #define if_page_sz_SHIFT                        0
2260 #define if_page_sz_MASK                         0x0000ffff
2261 #define if_page_sz_WORD                         word5
2262 #define loopbk_scope_SHIFT                      24
2263 #define loopbk_scope_MASK                       0x0000000f
2264 #define loopbk_scope_WORD                       word5
2265 #define rq_db_window_SHIFT                      28
2266 #define rq_db_window_MASK                       0x0000000f
2267 #define rq_db_window_WORD                       word5
2268         uint32_t word6;
2269 #define eq_pages_SHIFT                          0
2270 #define eq_pages_MASK                           0x0000000f
2271 #define eq_pages_WORD                           word6
2272 #define eqe_size_SHIFT                          8
2273 #define eqe_size_MASK                           0x000000ff
2274 #define eqe_size_WORD                           word6
2275         uint32_t word7;
2276 #define cq_pages_SHIFT                          0
2277 #define cq_pages_MASK                           0x0000000f
2278 #define cq_pages_WORD                           word7
2279 #define cqe_size_SHIFT                          8
2280 #define cqe_size_MASK                           0x000000ff
2281 #define cqe_size_WORD                           word7
2282         uint32_t word8;
2283 #define mq_pages_SHIFT                          0
2284 #define mq_pages_MASK                           0x0000000f
2285 #define mq_pages_WORD                           word8
2286 #define mqe_size_SHIFT                          8
2287 #define mqe_size_MASK                           0x000000ff
2288 #define mqe_size_WORD                           word8
2289 #define mq_elem_cnt_SHIFT                       16
2290 #define mq_elem_cnt_MASK                        0x000000ff
2291 #define mq_elem_cnt_WORD                        word8
2292         uint32_t word9;
2293 #define wq_pages_SHIFT                          0
2294 #define wq_pages_MASK                           0x0000ffff
2295 #define wq_pages_WORD                           word9
2296 #define wqe_size_SHIFT                          8
2297 #define wqe_size_MASK                           0x000000ff
2298 #define wqe_size_WORD                           word9
2299         uint32_t word10;
2300 #define rq_pages_SHIFT                          0
2301 #define rq_pages_MASK                           0x0000ffff
2302 #define rq_pages_WORD                           word10
2303 #define rqe_size_SHIFT                          8
2304 #define rqe_size_MASK                           0x000000ff
2305 #define rqe_size_WORD                           word10
2306         uint32_t word11;
2307 #define hdr_pages_SHIFT                         0
2308 #define hdr_pages_MASK                          0x0000000f
2309 #define hdr_pages_WORD                          word11
2310 #define hdr_size_SHIFT                          8
2311 #define hdr_size_MASK                           0x0000000f
2312 #define hdr_size_WORD                           word11
2313 #define hdr_pp_align_SHIFT                      16
2314 #define hdr_pp_align_MASK                       0x0000ffff
2315 #define hdr_pp_align_WORD                       word11
2316         uint32_t word12;
2317 #define sgl_pages_SHIFT                         0
2318 #define sgl_pages_MASK                          0x0000000f
2319 #define sgl_pages_WORD                          word12
2320 #define sgl_pp_align_SHIFT                      16
2321 #define sgl_pp_align_MASK                       0x0000ffff
2322 #define sgl_pp_align_WORD                       word12
2323         uint32_t rsvd_13_63[51];
2324 };
2325 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
2326                                &(~((SLI4_PAGE_SIZE)-1)))
2327
2328 struct lpfc_sli4_parameters {
2329         uint32_t word0;
2330 #define cfg_prot_type_SHIFT                     0
2331 #define cfg_prot_type_MASK                      0x000000FF
2332 #define cfg_prot_type_WORD                      word0
2333         uint32_t word1;
2334 #define cfg_ft_SHIFT                            0
2335 #define cfg_ft_MASK                             0x00000001
2336 #define cfg_ft_WORD                             word1
2337 #define cfg_sli_rev_SHIFT                       4
2338 #define cfg_sli_rev_MASK                        0x0000000f
2339 #define cfg_sli_rev_WORD                        word1
2340 #define cfg_sli_family_SHIFT                    8
2341 #define cfg_sli_family_MASK                     0x0000000f
2342 #define cfg_sli_family_WORD                     word1
2343 #define cfg_if_type_SHIFT                       12
2344 #define cfg_if_type_MASK                        0x0000000f
2345 #define cfg_if_type_WORD                        word1
2346 #define cfg_sli_hint_1_SHIFT                    16
2347 #define cfg_sli_hint_1_MASK                     0x000000ff
2348 #define cfg_sli_hint_1_WORD                     word1
2349 #define cfg_sli_hint_2_SHIFT                    24
2350 #define cfg_sli_hint_2_MASK                     0x0000001f
2351 #define cfg_sli_hint_2_WORD                     word1
2352         uint32_t word2;
2353         uint32_t word3;
2354         uint32_t word4;
2355 #define cfg_cqv_SHIFT                           14
2356 #define cfg_cqv_MASK                            0x00000003
2357 #define cfg_cqv_WORD                            word4
2358         uint32_t word5;
2359         uint32_t word6;
2360 #define cfg_mqv_SHIFT                           14
2361 #define cfg_mqv_MASK                            0x00000003
2362 #define cfg_mqv_WORD                            word6
2363         uint32_t word7;
2364         uint32_t word8;
2365 #define cfg_wqv_SHIFT                           14
2366 #define cfg_wqv_MASK                            0x00000003
2367 #define cfg_wqv_WORD                            word8
2368         uint32_t word9;
2369         uint32_t word10;
2370 #define cfg_rqv_SHIFT                           14
2371 #define cfg_rqv_MASK                            0x00000003
2372 #define cfg_rqv_WORD                            word10
2373         uint32_t word11;
2374 #define cfg_rq_db_window_SHIFT                  28
2375 #define cfg_rq_db_window_MASK                   0x0000000f
2376 #define cfg_rq_db_window_WORD                   word11
2377         uint32_t word12;
2378 #define cfg_fcoe_SHIFT                          0
2379 #define cfg_fcoe_MASK                           0x00000001
2380 #define cfg_fcoe_WORD                           word12
2381 #define cfg_ext_SHIFT                           1
2382 #define cfg_ext_MASK                            0x00000001
2383 #define cfg_ext_WORD                            word12
2384 #define cfg_hdrr_SHIFT                          2
2385 #define cfg_hdrr_MASK                           0x00000001
2386 #define cfg_hdrr_WORD                           word12
2387 #define cfg_phwq_SHIFT                          15
2388 #define cfg_phwq_MASK                           0x00000001
2389 #define cfg_phwq_WORD                           word12
2390 #define cfg_loopbk_scope_SHIFT                  28
2391 #define cfg_loopbk_scope_MASK                   0x0000000f
2392 #define cfg_loopbk_scope_WORD                   word12
2393         uint32_t sge_supp_len;
2394         uint32_t word14;
2395 #define cfg_sgl_page_cnt_SHIFT                  0
2396 #define cfg_sgl_page_cnt_MASK                   0x0000000f
2397 #define cfg_sgl_page_cnt_WORD                   word14
2398 #define cfg_sgl_page_size_SHIFT                 8
2399 #define cfg_sgl_page_size_MASK                  0x000000ff
2400 #define cfg_sgl_page_size_WORD                  word14
2401 #define cfg_sgl_pp_align_SHIFT                  16
2402 #define cfg_sgl_pp_align_MASK                   0x000000ff
2403 #define cfg_sgl_pp_align_WORD                   word14
2404         uint32_t word15;
2405         uint32_t word16;
2406         uint32_t word17;
2407         uint32_t word18;
2408         uint32_t word19;
2409 };
2410
2411 struct lpfc_mbx_get_sli4_parameters {
2412         struct mbox_header header;
2413         struct lpfc_sli4_parameters sli4_parameters;
2414 };
2415
2416 struct lpfc_rscr_desc_generic {
2417 #define LPFC_RSRC_DESC_WSIZE                    18
2418         uint32_t desc[LPFC_RSRC_DESC_WSIZE];
2419 };
2420
2421 struct lpfc_rsrc_desc_pcie {
2422         uint32_t word0;
2423 #define lpfc_rsrc_desc_pcie_type_SHIFT          0
2424 #define lpfc_rsrc_desc_pcie_type_MASK           0x000000ff
2425 #define lpfc_rsrc_desc_pcie_type_WORD           word0
2426 #define LPFC_RSRC_DESC_TYPE_PCIE                0x40
2427         uint32_t word1;
2428 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT         0
2429 #define lpfc_rsrc_desc_pcie_pfnum_MASK          0x000000ff
2430 #define lpfc_rsrc_desc_pcie_pfnum_WORD          word1
2431         uint32_t reserved;
2432         uint32_t word3;
2433 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT     0
2434 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK      0x000000ff
2435 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD      word3
2436 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT        8
2437 #define lpfc_rsrc_desc_pcie_pf_sta_MASK         0x000000ff
2438 #define lpfc_rsrc_desc_pcie_pf_sta_WORD         word3
2439 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT       16
2440 #define lpfc_rsrc_desc_pcie_pf_type_MASK        0x000000ff
2441 #define lpfc_rsrc_desc_pcie_pf_type_WORD        word3
2442         uint32_t word4;
2443 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT     0
2444 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK      0x0000ffff
2445 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD      word4
2446 };
2447
2448 struct lpfc_rsrc_desc_fcfcoe {
2449         uint32_t word0;
2450 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT        0
2451 #define lpfc_rsrc_desc_fcfcoe_type_MASK         0x000000ff
2452 #define lpfc_rsrc_desc_fcfcoe_type_WORD         word0
2453 #define LPFC_RSRC_DESC_TYPE_FCFCOE              0x43
2454         uint32_t word1;
2455 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT       0
2456 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK        0x000000ff
2457 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD        word1
2458 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT       16
2459 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK        0x000007ff
2460 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD        word1
2461         uint32_t word2;
2462 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT     0
2463 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK      0x0000ffff
2464 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD      word2
2465 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT     16
2466 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK      0x0000ffff
2467 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD      word2
2468         uint32_t word3;
2469 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT      0
2470 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK       0x0000ffff
2471 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD       word3
2472 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT      16
2473 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK       0x0000ffff
2474 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD       word3
2475         uint32_t word4;
2476 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT      0
2477 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK       0x0000ffff
2478 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD       word4
2479 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT     16
2480 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK      0x0000ffff
2481 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD      word4
2482         uint32_t word5;
2483 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT    0
2484 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK     0x0000ffff
2485 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD     word5
2486 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT     16
2487 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK      0x0000ffff
2488 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD      word5
2489         uint32_t word6;
2490         uint32_t word7;
2491         uint32_t word8;
2492         uint32_t word9;
2493         uint32_t word10;
2494         uint32_t word11;
2495         uint32_t word12;
2496         uint32_t word13;
2497 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT      0
2498 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK       0x0000003f
2499 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD       word13
2500 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT      6
2501 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK       0x00000003
2502 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD       word13
2503 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT         8
2504 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK          0x00000001
2505 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD          word13
2506 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT         9
2507 #define lpfc_rsrc_desc_fcfcoe_lld_MASK          0x00000001
2508 #define lpfc_rsrc_desc_fcfcoe_lld_WORD          word13
2509 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT      16
2510 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK       0x0000ffff
2511 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD       word13
2512 };
2513
2514 struct lpfc_func_cfg {
2515 #define LPFC_RSRC_DESC_MAX_NUM                  2
2516         uint32_t rsrc_desc_count;
2517         struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
2518 };
2519
2520 struct lpfc_mbx_get_func_cfg {
2521         struct mbox_header header;
2522 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE       0x0
2523 #define LPFC_CFG_TYPE_FACTURY_DEFAULT           0x1
2524 #define LPFC_CFG_TYPE_CURRENT_ACTIVE            0x2
2525         struct lpfc_func_cfg func_cfg;
2526 };
2527
2528 struct lpfc_prof_cfg {
2529 #define LPFC_RSRC_DESC_MAX_NUM                  2
2530         uint32_t rsrc_desc_count;
2531         struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
2532 };
2533
2534 struct lpfc_mbx_get_prof_cfg {
2535         struct mbox_header header;
2536 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE       0x0
2537 #define LPFC_CFG_TYPE_FACTURY_DEFAULT           0x1
2538 #define LPFC_CFG_TYPE_CURRENT_ACTIVE            0x2
2539         union {
2540                 struct {
2541                         uint32_t word10;
2542 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT     0
2543 #define lpfc_mbx_get_prof_cfg_prof_id_MASK      0x000000ff
2544 #define lpfc_mbx_get_prof_cfg_prof_id_WORD      word10
2545 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT     8
2546 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK      0x00000003
2547 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD      word10
2548                 } request;
2549                 struct {
2550                         struct lpfc_prof_cfg prof_cfg;
2551                 } response;
2552         } u;
2553 };
2554
2555 /* Mailbox Completion Queue Error Messages */
2556 #define MB_CQE_STATUS_SUCCESS                   0x0
2557 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES   0x1
2558 #define MB_CQE_STATUS_INVALID_PARAMETER         0x2
2559 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES    0x3
2560 #define MB_CEQ_STATUS_QUEUE_FLUSHING            0x4
2561 #define MB_CQE_STATUS_DMA_FAILED                0x5
2562
2563 #define LPFC_MBX_WR_CONFIG_MAX_BDE              8
2564 struct lpfc_mbx_wr_object {
2565         struct mbox_header header;
2566         union {
2567                 struct {
2568                         uint32_t word4;
2569 #define lpfc_wr_object_eof_SHIFT                31
2570 #define lpfc_wr_object_eof_MASK                 0x00000001
2571 #define lpfc_wr_object_eof_WORD                 word4
2572 #define lpfc_wr_object_write_length_SHIFT       0
2573 #define lpfc_wr_object_write_length_MASK        0x00FFFFFF
2574 #define lpfc_wr_object_write_length_WORD        word4
2575                         uint32_t write_offset;
2576                         uint32_t object_name[26];
2577                         uint32_t bde_count;
2578                         struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE];
2579                 } request;
2580                 struct {
2581                         uint32_t actual_write_length;
2582                 } response;
2583         } u;
2584 };
2585
2586 /* mailbox queue entry structure */
2587 struct lpfc_mqe {
2588         uint32_t word0;
2589 #define lpfc_mqe_status_SHIFT           16
2590 #define lpfc_mqe_status_MASK            0x0000FFFF
2591 #define lpfc_mqe_status_WORD            word0
2592 #define lpfc_mqe_command_SHIFT          8
2593 #define lpfc_mqe_command_MASK           0x000000FF
2594 #define lpfc_mqe_command_WORD           word0
2595         union {
2596                 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
2597                 /* sli4 mailbox commands */
2598                 struct lpfc_mbx_sli4_config sli4_config;
2599                 struct lpfc_mbx_init_vfi init_vfi;
2600                 struct lpfc_mbx_reg_vfi reg_vfi;
2601                 struct lpfc_mbx_reg_vfi unreg_vfi;
2602                 struct lpfc_mbx_init_vpi init_vpi;
2603                 struct lpfc_mbx_resume_rpi resume_rpi;
2604                 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
2605                 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
2606                 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
2607                 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
2608                 struct lpfc_mbx_reg_fcfi reg_fcfi;
2609                 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
2610                 struct lpfc_mbx_mq_create mq_create;
2611                 struct lpfc_mbx_mq_create_ext mq_create_ext;
2612                 struct lpfc_mbx_eq_create eq_create;
2613                 struct lpfc_mbx_cq_create cq_create;
2614                 struct lpfc_mbx_wq_create wq_create;
2615                 struct lpfc_mbx_rq_create rq_create;
2616                 struct lpfc_mbx_mq_destroy mq_destroy;
2617                 struct lpfc_mbx_eq_destroy eq_destroy;
2618                 struct lpfc_mbx_cq_destroy cq_destroy;
2619                 struct lpfc_mbx_wq_destroy wq_destroy;
2620                 struct lpfc_mbx_rq_destroy rq_destroy;
2621                 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info;
2622                 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents;
2623                 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents;
2624                 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
2625                 struct lpfc_mbx_nembed_cmd nembed_cmd;
2626                 struct lpfc_mbx_read_rev read_rev;
2627                 struct lpfc_mbx_read_vpi read_vpi;
2628                 struct lpfc_mbx_read_config rd_config;
2629                 struct lpfc_mbx_request_features req_ftrs;
2630                 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
2631                 struct lpfc_mbx_query_fw_cfg query_fw_cfg;
2632                 struct lpfc_mbx_supp_pages supp_pages;
2633                 struct lpfc_mbx_pc_sli4_params sli4_params;
2634                 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
2635                 struct lpfc_mbx_set_link_diag_state link_diag_state;
2636                 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback;
2637                 struct lpfc_mbx_run_link_diag_test link_diag_test;
2638                 struct lpfc_mbx_get_func_cfg get_func_cfg;
2639                 struct lpfc_mbx_get_prof_cfg get_prof_cfg;
2640                 struct lpfc_mbx_nop nop;
2641                 struct lpfc_mbx_wr_object wr_object;
2642         } un;
2643 };
2644
2645 struct lpfc_mcqe {
2646         uint32_t word0;
2647 #define lpfc_mcqe_status_SHIFT          0
2648 #define lpfc_mcqe_status_MASK           0x0000FFFF
2649 #define lpfc_mcqe_status_WORD           word0
2650 #define lpfc_mcqe_ext_status_SHIFT      16
2651 #define lpfc_mcqe_ext_status_MASK       0x0000FFFF
2652 #define lpfc_mcqe_ext_status_WORD       word0
2653         uint32_t mcqe_tag0;
2654         uint32_t mcqe_tag1;
2655         uint32_t trailer;
2656 #define lpfc_trailer_valid_SHIFT        31
2657 #define lpfc_trailer_valid_MASK         0x00000001
2658 #define lpfc_trailer_valid_WORD         trailer
2659 #define lpfc_trailer_async_SHIFT        30
2660 #define lpfc_trailer_async_MASK         0x00000001
2661 #define lpfc_trailer_async_WORD         trailer
2662 #define lpfc_trailer_hpi_SHIFT          29
2663 #define lpfc_trailer_hpi_MASK           0x00000001
2664 #define lpfc_trailer_hpi_WORD           trailer
2665 #define lpfc_trailer_completed_SHIFT    28
2666 #define lpfc_trailer_completed_MASK     0x00000001
2667 #define lpfc_trailer_completed_WORD     trailer
2668 #define lpfc_trailer_consumed_SHIFT     27
2669 #define lpfc_trailer_consumed_MASK      0x00000001
2670 #define lpfc_trailer_consumed_WORD      trailer
2671 #define lpfc_trailer_type_SHIFT         16
2672 #define lpfc_trailer_type_MASK          0x000000FF
2673 #define lpfc_trailer_type_WORD          trailer
2674 #define lpfc_trailer_code_SHIFT         8
2675 #define lpfc_trailer_code_MASK          0x000000FF
2676 #define lpfc_trailer_code_WORD          trailer
2677 #define LPFC_TRAILER_CODE_LINK  0x1
2678 #define LPFC_TRAILER_CODE_FCOE  0x2
2679 #define LPFC_TRAILER_CODE_DCBX  0x3
2680 #define LPFC_TRAILER_CODE_GRP5  0x5
2681 #define LPFC_TRAILER_CODE_FC    0x10
2682 #define LPFC_TRAILER_CODE_SLI   0x11
2683 };
2684
2685 struct lpfc_acqe_link {
2686         uint32_t word0;
2687 #define lpfc_acqe_link_speed_SHIFT              24
2688 #define lpfc_acqe_link_speed_MASK               0x000000FF
2689 #define lpfc_acqe_link_speed_WORD               word0
2690 #define LPFC_ASYNC_LINK_SPEED_ZERO              0x0
2691 #define LPFC_ASYNC_LINK_SPEED_10MBPS            0x1
2692 #define LPFC_ASYNC_LINK_SPEED_100MBPS           0x2
2693 #define LPFC_ASYNC_LINK_SPEED_1GBPS             0x3
2694 #define LPFC_ASYNC_LINK_SPEED_10GBPS            0x4
2695 #define lpfc_acqe_link_duplex_SHIFT             16
2696 #define lpfc_acqe_link_duplex_MASK              0x000000FF
2697 #define lpfc_acqe_link_duplex_WORD              word0
2698 #define LPFC_ASYNC_LINK_DUPLEX_NONE             0x0
2699 #define LPFC_ASYNC_LINK_DUPLEX_HALF             0x1
2700 #define LPFC_ASYNC_LINK_DUPLEX_FULL             0x2
2701 #define lpfc_acqe_link_status_SHIFT             8
2702 #define lpfc_acqe_link_status_MASK              0x000000FF
2703 #define lpfc_acqe_link_status_WORD              word0
2704 #define LPFC_ASYNC_LINK_STATUS_DOWN             0x0
2705 #define LPFC_ASYNC_LINK_STATUS_UP               0x1
2706 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN     0x2
2707 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP       0x3
2708 #define lpfc_acqe_link_type_SHIFT               6
2709 #define lpfc_acqe_link_type_MASK                0x00000003
2710 #define lpfc_acqe_link_type_WORD                word0
2711 #define lpfc_acqe_link_number_SHIFT             0
2712 #define lpfc_acqe_link_number_MASK              0x0000003F
2713 #define lpfc_acqe_link_number_WORD              word0
2714         uint32_t word1;
2715 #define lpfc_acqe_link_fault_SHIFT      0
2716 #define lpfc_acqe_link_fault_MASK       0x000000FF
2717 #define lpfc_acqe_link_fault_WORD       word1
2718 #define LPFC_ASYNC_LINK_FAULT_NONE      0x0
2719 #define LPFC_ASYNC_LINK_FAULT_LOCAL     0x1
2720 #define LPFC_ASYNC_LINK_FAULT_REMOTE    0x2
2721 #define lpfc_acqe_logical_link_speed_SHIFT      16
2722 #define lpfc_acqe_logical_link_speed_MASK       0x0000FFFF
2723 #define lpfc_acqe_logical_link_speed_WORD       word1
2724         uint32_t event_tag;
2725         uint32_t trailer;
2726 #define LPFC_LINK_EVENT_TYPE_PHYSICAL   0x0
2727 #define LPFC_LINK_EVENT_TYPE_VIRTUAL    0x1
2728 };
2729
2730 struct lpfc_acqe_fip {
2731         uint32_t index;
2732         uint32_t word1;
2733 #define lpfc_acqe_fip_fcf_count_SHIFT           0
2734 #define lpfc_acqe_fip_fcf_count_MASK            0x0000FFFF
2735 #define lpfc_acqe_fip_fcf_count_WORD            word1
2736 #define lpfc_acqe_fip_event_type_SHIFT          16
2737 #define lpfc_acqe_fip_event_type_MASK           0x0000FFFF
2738 #define lpfc_acqe_fip_event_type_WORD           word1
2739         uint32_t event_tag;
2740         uint32_t trailer;
2741 #define LPFC_FIP_EVENT_TYPE_NEW_FCF             0x1
2742 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL      0x2
2743 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD            0x3
2744 #define LPFC_FIP_EVENT_TYPE_CVL                 0x4
2745 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD       0x5
2746 };
2747
2748 struct lpfc_acqe_dcbx {
2749         uint32_t tlv_ttl;
2750         uint32_t reserved;
2751         uint32_t event_tag;
2752         uint32_t trailer;
2753 };
2754
2755 struct lpfc_acqe_grp5 {
2756         uint32_t word0;
2757 #define lpfc_acqe_grp5_type_SHIFT               6
2758 #define lpfc_acqe_grp5_type_MASK                0x00000003
2759 #define lpfc_acqe_grp5_type_WORD                word0
2760 #define lpfc_acqe_grp5_number_SHIFT             0
2761 #define lpfc_acqe_grp5_number_MASK              0x0000003F
2762 #define lpfc_acqe_grp5_number_WORD              word0
2763         uint32_t word1;
2764 #define lpfc_acqe_grp5_llink_spd_SHIFT  16
2765 #define lpfc_acqe_grp5_llink_spd_MASK   0x0000FFFF
2766 #define lpfc_acqe_grp5_llink_spd_WORD   word1
2767         uint32_t event_tag;
2768         uint32_t trailer;
2769 };
2770
2771 struct lpfc_acqe_fc_la {
2772         uint32_t word0;
2773 #define lpfc_acqe_fc_la_speed_SHIFT             24
2774 #define lpfc_acqe_fc_la_speed_MASK              0x000000FF
2775 #define lpfc_acqe_fc_la_speed_WORD              word0
2776 #define LPFC_FC_LA_SPEED_UNKOWN         0x0
2777 #define LPFC_FC_LA_SPEED_1G             0x1
2778 #define LPFC_FC_LA_SPEED_2G             0x2
2779 #define LPFC_FC_LA_SPEED_4G             0x4
2780 #define LPFC_FC_LA_SPEED_8G             0x8
2781 #define LPFC_FC_LA_SPEED_10G            0xA
2782 #define LPFC_FC_LA_SPEED_16G            0x10
2783 #define lpfc_acqe_fc_la_topology_SHIFT          16
2784 #define lpfc_acqe_fc_la_topology_MASK           0x000000FF
2785 #define lpfc_acqe_fc_la_topology_WORD           word0
2786 #define LPFC_FC_LA_TOP_UNKOWN           0x0
2787 #define LPFC_FC_LA_TOP_P2P              0x1
2788 #define LPFC_FC_LA_TOP_FCAL             0x2
2789 #define LPFC_FC_LA_TOP_INTERNAL_LOOP    0x3
2790 #define LPFC_FC_LA_TOP_SERDES_LOOP      0x4
2791 #define lpfc_acqe_fc_la_att_type_SHIFT          8
2792 #define lpfc_acqe_fc_la_att_type_MASK           0x000000FF
2793 #define lpfc_acqe_fc_la_att_type_WORD           word0
2794 #define LPFC_FC_LA_TYPE_LINK_UP         0x1
2795 #define LPFC_FC_LA_TYPE_LINK_DOWN       0x2
2796 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA    0x3
2797 #define lpfc_acqe_fc_la_port_type_SHIFT         6
2798 #define lpfc_acqe_fc_la_port_type_MASK          0x00000003
2799 #define lpfc_acqe_fc_la_port_type_WORD          word0
2800 #define LPFC_LINK_TYPE_ETHERNET         0x0
2801 #define LPFC_LINK_TYPE_FC               0x1
2802 #define lpfc_acqe_fc_la_port_number_SHIFT       0
2803 #define lpfc_acqe_fc_la_port_number_MASK        0x0000003F
2804 #define lpfc_acqe_fc_la_port_number_WORD        word0
2805         uint32_t word1;
2806 #define lpfc_acqe_fc_la_llink_spd_SHIFT         16
2807 #define lpfc_acqe_fc_la_llink_spd_MASK          0x0000FFFF
2808 #define lpfc_acqe_fc_la_llink_spd_WORD          word1
2809 #define lpfc_acqe_fc_la_fault_SHIFT             0
2810 #define lpfc_acqe_fc_la_fault_MASK              0x000000FF
2811 #define lpfc_acqe_fc_la_fault_WORD              word1
2812 #define LPFC_FC_LA_FAULT_NONE           0x0
2813 #define LPFC_FC_LA_FAULT_LOCAL          0x1
2814 #define LPFC_FC_LA_FAULT_REMOTE         0x2
2815         uint32_t event_tag;
2816         uint32_t trailer;
2817 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK           0x1
2818 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK       0x2
2819 };
2820
2821 struct lpfc_acqe_sli {
2822         uint32_t event_data1;
2823         uint32_t event_data2;
2824         uint32_t reserved;
2825         uint32_t trailer;
2826 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR          0x1
2827 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP           0x2
2828 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP           0x3
2829 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST          0x4
2830 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP           0x5
2831 };
2832
2833 /*
2834  * Define the bootstrap mailbox (bmbx) region used to communicate
2835  * mailbox command between the host and port. The mailbox consists
2836  * of a payload area of 256 bytes and a completion queue of length
2837  * 16 bytes.
2838  */
2839 struct lpfc_bmbx_create {
2840         struct lpfc_mqe mqe;
2841         struct lpfc_mcqe mcqe;
2842 };
2843
2844 #define SGL_ALIGN_SZ 64
2845 #define SGL_PAGE_SIZE 4096
2846 /* align SGL addr on a size boundary - adjust address up */
2847 #define NO_XRI  0xffff
2848
2849 struct wqe_common {
2850         uint32_t word6;
2851 #define wqe_xri_tag_SHIFT     0
2852 #define wqe_xri_tag_MASK      0x0000FFFF
2853 #define wqe_xri_tag_WORD      word6
2854 #define wqe_ctxt_tag_SHIFT    16
2855 #define wqe_ctxt_tag_MASK     0x0000FFFF
2856 #define wqe_ctxt_tag_WORD     word6
2857         uint32_t word7;
2858 #define wqe_ct_SHIFT          2
2859 #define wqe_ct_MASK           0x00000003
2860 #define wqe_ct_WORD           word7
2861 #define wqe_status_SHIFT      4
2862 #define wqe_status_MASK       0x0000000f
2863 #define wqe_status_WORD       word7
2864 #define wqe_cmnd_SHIFT        8
2865 #define wqe_cmnd_MASK         0x000000ff
2866 #define wqe_cmnd_WORD         word7
2867 #define wqe_class_SHIFT       16
2868 #define wqe_class_MASK        0x00000007
2869 #define wqe_class_WORD        word7
2870 #define wqe_pu_SHIFT          20
2871 #define wqe_pu_MASK           0x00000003
2872 #define wqe_pu_WORD           word7
2873 #define wqe_erp_SHIFT         22
2874 #define wqe_erp_MASK          0x00000001
2875 #define wqe_erp_WORD          word7
2876 #define wqe_lnk_SHIFT         23
2877 #define wqe_lnk_MASK          0x00000001
2878 #define wqe_lnk_WORD          word7
2879 #define wqe_tmo_SHIFT         24
2880 #define wqe_tmo_MASK          0x000000ff
2881 #define wqe_tmo_WORD          word7
2882         uint32_t abort_tag; /* word 8 in WQE */
2883         uint32_t word9;
2884 #define wqe_reqtag_SHIFT      0
2885 #define wqe_reqtag_MASK       0x0000FFFF
2886 #define wqe_reqtag_WORD       word9
2887 #define wqe_temp_rpi_SHIFT    16
2888 #define wqe_temp_rpi_MASK     0x0000FFFF
2889 #define wqe_temp_rpi_WORD     word9
2890 #define wqe_rcvoxid_SHIFT     16
2891 #define wqe_rcvoxid_MASK      0x0000FFFF
2892 #define wqe_rcvoxid_WORD      word9
2893         uint32_t word10;
2894 #define wqe_ebde_cnt_SHIFT    0
2895 #define wqe_ebde_cnt_MASK     0x0000000f
2896 #define wqe_ebde_cnt_WORD     word10
2897 #define wqe_lenloc_SHIFT      7
2898 #define wqe_lenloc_MASK       0x00000003
2899 #define wqe_lenloc_WORD       word10
2900 #define LPFC_WQE_LENLOC_NONE            0
2901 #define LPFC_WQE_LENLOC_WORD3   1
2902 #define LPFC_WQE_LENLOC_WORD12  2
2903 #define LPFC_WQE_LENLOC_WORD4   3
2904 #define wqe_qosd_SHIFT        9
2905 #define wqe_qosd_MASK         0x00000001
2906 #define wqe_qosd_WORD         word10
2907 #define wqe_xbl_SHIFT         11
2908 #define wqe_xbl_MASK          0x00000001
2909 #define wqe_xbl_WORD          word10
2910 #define wqe_iod_SHIFT         13
2911 #define wqe_iod_MASK          0x00000001
2912 #define wqe_iod_WORD          word10
2913 #define LPFC_WQE_IOD_WRITE      0
2914 #define LPFC_WQE_IOD_READ       1
2915 #define wqe_dbde_SHIFT        14
2916 #define wqe_dbde_MASK         0x00000001
2917 #define wqe_dbde_WORD         word10
2918 #define wqe_wqes_SHIFT        15
2919 #define wqe_wqes_MASK         0x00000001
2920 #define wqe_wqes_WORD         word10
2921 /* Note that this field overlaps above fields */
2922 #define wqe_wqid_SHIFT        1
2923 #define wqe_wqid_MASK         0x00007fff
2924 #define wqe_wqid_WORD         word10
2925 #define wqe_pri_SHIFT         16
2926 #define wqe_pri_MASK          0x00000007
2927 #define wqe_pri_WORD          word10
2928 #define wqe_pv_SHIFT          19
2929 #define wqe_pv_MASK           0x00000001
2930 #define wqe_pv_WORD           word10
2931 #define wqe_xc_SHIFT          21
2932 #define wqe_xc_MASK           0x00000001
2933 #define wqe_xc_WORD           word10
2934 #define wqe_ccpe_SHIFT        23
2935 #define wqe_ccpe_MASK         0x00000001
2936 #define wqe_ccpe_WORD         word10
2937 #define wqe_ccp_SHIFT         24
2938 #define wqe_ccp_MASK          0x000000ff
2939 #define wqe_ccp_WORD          word10
2940         uint32_t word11;
2941 #define wqe_cmd_type_SHIFT    0
2942 #define wqe_cmd_type_MASK     0x0000000f
2943 #define wqe_cmd_type_WORD     word11
2944 #define wqe_els_id_SHIFT      4
2945 #define wqe_els_id_MASK       0x00000003
2946 #define wqe_els_id_WORD       word11
2947 #define LPFC_ELS_ID_FLOGI       3
2948 #define LPFC_ELS_ID_FDISC       2
2949 #define LPFC_ELS_ID_LOGO        1
2950 #define LPFC_ELS_ID_DEFAULT     0
2951 #define wqe_wqec_SHIFT        7
2952 #define wqe_wqec_MASK         0x00000001
2953 #define wqe_wqec_WORD         word11
2954 #define wqe_cqid_SHIFT        16
2955 #define wqe_cqid_MASK         0x0000ffff
2956 #define wqe_cqid_WORD         word11
2957 #define LPFC_WQE_CQ_ID_DEFAULT  0xffff
2958 };
2959
2960 struct wqe_did {
2961         uint32_t word5;
2962 #define wqe_els_did_SHIFT         0
2963 #define wqe_els_did_MASK          0x00FFFFFF
2964 #define wqe_els_did_WORD          word5
2965 #define wqe_xmit_bls_pt_SHIFT         28
2966 #define wqe_xmit_bls_pt_MASK          0x00000003
2967 #define wqe_xmit_bls_pt_WORD          word5
2968 #define wqe_xmit_bls_ar_SHIFT         30
2969 #define wqe_xmit_bls_ar_MASK          0x00000001
2970 #define wqe_xmit_bls_ar_WORD          word5
2971 #define wqe_xmit_bls_xo_SHIFT         31
2972 #define wqe_xmit_bls_xo_MASK          0x00000001
2973 #define wqe_xmit_bls_xo_WORD          word5
2974 };
2975
2976 struct lpfc_wqe_generic{
2977         struct ulp_bde64 bde;
2978         uint32_t word3;
2979         uint32_t word4;
2980         uint32_t word5;
2981         struct wqe_common wqe_com;
2982         uint32_t payload[4];
2983 };
2984
2985 struct els_request64_wqe {
2986         struct ulp_bde64 bde;
2987         uint32_t payload_len;
2988         uint32_t word4;
2989 #define els_req64_sid_SHIFT         0
2990 #define els_req64_sid_MASK          0x00FFFFFF
2991 #define els_req64_sid_WORD          word4
2992 #define els_req64_sp_SHIFT          24
2993 #define els_req64_sp_MASK           0x00000001
2994 #define els_req64_sp_WORD           word4
2995 #define els_req64_vf_SHIFT          25
2996 #define els_req64_vf_MASK           0x00000001
2997 #define els_req64_vf_WORD           word4
2998         struct wqe_did  wqe_dest;
2999         struct wqe_common wqe_com; /* words 6-11 */
3000         uint32_t word12;
3001 #define els_req64_vfid_SHIFT        1
3002 #define els_req64_vfid_MASK         0x00000FFF
3003 #define els_req64_vfid_WORD         word12
3004 #define els_req64_pri_SHIFT         13
3005 #define els_req64_pri_MASK          0x00000007
3006 #define els_req64_pri_WORD          word12
3007         uint32_t word13;
3008 #define els_req64_hopcnt_SHIFT      24
3009 #define els_req64_hopcnt_MASK       0x000000ff
3010 #define els_req64_hopcnt_WORD       word13
3011         uint32_t reserved[2];
3012 };
3013
3014 struct xmit_els_rsp64_wqe {
3015         struct ulp_bde64 bde;
3016         uint32_t response_payload_len;
3017         uint32_t rsvd4;
3018         struct wqe_did wqe_dest;
3019         struct wqe_common wqe_com; /* words 6-11 */
3020         uint32_t word12;
3021 #define wqe_rsp_temp_rpi_SHIFT    0
3022 #define wqe_rsp_temp_rpi_MASK     0x0000FFFF
3023 #define wqe_rsp_temp_rpi_WORD     word12
3024         uint32_t rsvd_13_15[3];
3025 };
3026
3027 struct xmit_bls_rsp64_wqe {
3028         uint32_t payload0;
3029 /* Payload0 for BA_ACC */
3030 #define xmit_bls_rsp64_acc_seq_id_SHIFT        16
3031 #define xmit_bls_rsp64_acc_seq_id_MASK         0x000000ff
3032 #define xmit_bls_rsp64_acc_seq_id_WORD         payload0
3033 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT   24
3034 #define xmit_bls_rsp64_acc_seq_id_vald_MASK    0x000000ff
3035 #define xmit_bls_rsp64_acc_seq_id_vald_WORD    payload0
3036 /* Payload0 for BA_RJT */
3037 #define xmit_bls_rsp64_rjt_vspec_SHIFT   0
3038 #define xmit_bls_rsp64_rjt_vspec_MASK    0x000000ff
3039 #define xmit_bls_rsp64_rjt_vspec_WORD    payload0
3040 #define xmit_bls_rsp64_rjt_expc_SHIFT    8
3041 #define xmit_bls_rsp64_rjt_expc_MASK     0x000000ff
3042 #define xmit_bls_rsp64_rjt_expc_WORD     payload0
3043 #define xmit_bls_rsp64_rjt_rsnc_SHIFT    16
3044 #define xmit_bls_rsp64_rjt_rsnc_MASK     0x000000ff
3045 #define xmit_bls_rsp64_rjt_rsnc_WORD     payload0
3046         uint32_t word1;
3047 #define xmit_bls_rsp64_rxid_SHIFT  0
3048 #define xmit_bls_rsp64_rxid_MASK   0x0000ffff
3049 #define xmit_bls_rsp64_rxid_WORD   word1
3050 #define xmit_bls_rsp64_oxid_SHIFT  16
3051 #define xmit_bls_rsp64_oxid_MASK   0x0000ffff
3052 #define xmit_bls_rsp64_oxid_WORD   word1
3053         uint32_t word2;
3054 #define xmit_bls_rsp64_seqcnthi_SHIFT  0
3055 #define xmit_bls_rsp64_seqcnthi_MASK   0x0000ffff
3056 #define xmit_bls_rsp64_seqcnthi_WORD   word2
3057 #define xmit_bls_rsp64_seqcntlo_SHIFT  16
3058 #define xmit_bls_rsp64_seqcntlo_MASK   0x0000ffff
3059 #define xmit_bls_rsp64_seqcntlo_WORD   word2
3060         uint32_t rsrvd3;
3061         uint32_t rsrvd4;
3062         struct wqe_did  wqe_dest;
3063         struct wqe_common wqe_com; /* words 6-11 */
3064         uint32_t rsvd_12_15[4];
3065 };
3066
3067 struct wqe_rctl_dfctl {
3068         uint32_t word5;
3069 #define wqe_si_SHIFT 2
3070 #define wqe_si_MASK  0x000000001
3071 #define wqe_si_WORD  word5
3072 #define wqe_la_SHIFT 3
3073 #define wqe_la_MASK  0x000000001
3074 #define wqe_la_WORD  word5
3075 #define wqe_ls_SHIFT 7
3076 #define wqe_ls_MASK  0x000000001
3077 #define wqe_ls_WORD  word5
3078 #define wqe_dfctl_SHIFT 8
3079 #define wqe_dfctl_MASK  0x0000000ff
3080 #define wqe_dfctl_WORD  word5
3081 #define wqe_type_SHIFT 16
3082 #define wqe_type_MASK  0x0000000ff
3083 #define wqe_type_WORD  word5
3084 #define wqe_rctl_SHIFT 24
3085 #define wqe_rctl_MASK  0x0000000ff
3086 #define wqe_rctl_WORD  word5
3087 };
3088
3089 struct xmit_seq64_wqe {
3090         struct ulp_bde64 bde;
3091         uint32_t rsvd3;
3092         uint32_t relative_offset;
3093         struct wqe_rctl_dfctl wge_ctl;
3094         struct wqe_common wqe_com; /* words 6-11 */
3095         uint32_t xmit_len;
3096         uint32_t rsvd_12_15[3];
3097 };
3098 struct xmit_bcast64_wqe {
3099         struct ulp_bde64 bde;
3100         uint32_t seq_payload_len;
3101         uint32_t rsvd4;
3102         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
3103         struct wqe_common wqe_com;     /* words 6-11 */
3104         uint32_t rsvd_12_15[4];
3105 };
3106
3107 struct gen_req64_wqe {
3108         struct ulp_bde64 bde;
3109         uint32_t request_payload_len;
3110         uint32_t relative_offset;
3111         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
3112         struct wqe_common wqe_com;     /* words 6-11 */
3113         uint32_t rsvd_12_15[4];
3114 };
3115
3116 struct create_xri_wqe {
3117         uint32_t rsrvd[5];           /* words 0-4 */
3118         struct wqe_did  wqe_dest;  /* word 5 */
3119         struct wqe_common wqe_com; /* words 6-11 */
3120         uint32_t rsvd_12_15[4];         /* word 12-15 */
3121 };
3122
3123 #define T_REQUEST_TAG 3
3124 #define T_XRI_TAG 1
3125
3126 struct abort_cmd_wqe {
3127         uint32_t rsrvd[3];
3128         uint32_t word3;
3129 #define abort_cmd_ia_SHIFT  0
3130 #define abort_cmd_ia_MASK  0x000000001
3131 #define abort_cmd_ia_WORD  word3
3132 #define abort_cmd_criteria_SHIFT  8
3133 #define abort_cmd_criteria_MASK  0x0000000ff
3134 #define abort_cmd_criteria_WORD  word3
3135         uint32_t rsrvd4;
3136         uint32_t rsrvd5;
3137         struct wqe_common wqe_com;     /* words 6-11 */
3138         uint32_t rsvd_12_15[4];         /* word 12-15 */
3139 };
3140
3141 struct fcp_iwrite64_wqe {
3142         struct ulp_bde64 bde;
3143         uint32_t payload_offset_len;
3144         uint32_t total_xfer_len;
3145         uint32_t initial_xfer_len;
3146         struct wqe_common wqe_com;     /* words 6-11 */
3147         uint32_t rsrvd12;
3148         struct ulp_bde64 ph_bde;       /* words 13-15 */
3149 };
3150
3151 struct fcp_iread64_wqe {
3152         struct ulp_bde64 bde;
3153         uint32_t payload_offset_len;   /* word 3 */
3154         uint32_t total_xfer_len;       /* word 4 */
3155         uint32_t rsrvd5;               /* word 5 */
3156         struct wqe_common wqe_com;     /* words 6-11 */
3157         uint32_t rsrvd12;
3158         struct ulp_bde64 ph_bde;       /* words 13-15 */
3159 };
3160
3161 struct fcp_icmnd64_wqe {
3162         struct ulp_bde64 bde;          /* words 0-2 */
3163         uint32_t rsrvd3;               /* word 3 */
3164         uint32_t rsrvd4;               /* word 4 */
3165         uint32_t rsrvd5;               /* word 5 */
3166         struct wqe_common wqe_com;     /* words 6-11 */
3167         uint32_t rsvd_12_15[4];        /* word 12-15 */
3168 };
3169
3170
3171 union lpfc_wqe {
3172         uint32_t words[16];
3173         struct lpfc_wqe_generic generic;
3174         struct fcp_icmnd64_wqe fcp_icmd;
3175         struct fcp_iread64_wqe fcp_iread;
3176         struct fcp_iwrite64_wqe fcp_iwrite;
3177         struct abort_cmd_wqe abort_cmd;
3178         struct create_xri_wqe create_xri;
3179         struct xmit_bcast64_wqe xmit_bcast64;
3180         struct xmit_seq64_wqe xmit_sequence;
3181         struct xmit_bls_rsp64_wqe xmit_bls_rsp;
3182         struct xmit_els_rsp64_wqe xmit_els_rsp;
3183         struct els_request64_wqe els_req;
3184         struct gen_req64_wqe gen_req;
3185 };
3186
3187 #define LPFC_GROUP_OJECT_MAGIC_NUM              0xfeaa0001
3188 #define LPFC_FILE_TYPE_GROUP                    0xf7
3189 #define LPFC_FILE_ID_GROUP                      0xa2
3190 struct lpfc_grp_hdr {
3191         uint32_t size;
3192         uint32_t magic_number;
3193         uint32_t word2;
3194 #define lpfc_grp_hdr_file_type_SHIFT    24
3195 #define lpfc_grp_hdr_file_type_MASK     0x000000FF
3196 #define lpfc_grp_hdr_file_type_WORD     word2
3197 #define lpfc_grp_hdr_id_SHIFT           16
3198 #define lpfc_grp_hdr_id_MASK            0x000000FF
3199 #define lpfc_grp_hdr_id_WORD            word2
3200         uint8_t rev_name[128];
3201 };
3202
3203 #define FCP_COMMAND 0x0
3204 #define FCP_COMMAND_DATA_OUT 0x1
3205 #define ELS_COMMAND_NON_FIP 0xC
3206 #define ELS_COMMAND_FIP 0xD
3207 #define OTHER_COMMAND 0x8
3208
3209 #define LPFC_FW_DUMP    1
3210 #define LPFC_FW_RESET   2
3211 #define LPFC_DV_RESET   3