drivers/scsi/isci/phy.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * GPL LICENSE SUMMARY
   6  *
   7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * BSD LICENSE
  25  *
  26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  27  * All rights reserved.
  28  *
  29  * Redistribution and use in source and binary forms, with or without
  30  * modification, are permitted provided that the following conditions
  31  * are met:
  32  *
  33  *   * Redistributions of source code must retain the above copyright
  34  *     notice, this list of conditions and the following disclaimer.
  35  *   * Redistributions in binary form must reproduce the above copyright
  36  *     notice, this list of conditions and the following disclaimer in
  37  *     the documentation and/or other materials provided with the
  38  *     distribution.
  39  *   * Neither the name of Intel Corporation nor the names of its
  40  *     contributors may be used to endorse or promote products derived
  41  *     from this software without specific prior written permission.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  */
  55
  56 #include "isci.h"
  57 #include "host.h"
  58 #include "phy.h"
  59 #include "scu_event_codes.h"
  60 #include "probe_roms.h"
  61
  62 /* Maximum arbitration wait time in micro-seconds */
  63 #define SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME  (700)
  64
  65 enum sas_linkrate sci_phy_linkrate(struct isci_phy *iphy)
  66 {
  67         return iphy->max_negotiated_speed;
  68 }
  69
  70 /*
  71  * *****************************************************************************
  72  * * SCIC SDS PHY Internal Methods
  73  * ***************************************************************************** */
  74
  75 /**
  76  * This method will initialize the phy transport layer registers
  77  * @sci_phy:
  78  * @transport_layer_registers
  79  *
  80  * enum sci_status
  81  */
  82 static enum sci_status scic_sds_phy_transport_layer_initialization(
  83         struct isci_phy *iphy,
  84         struct scu_transport_layer_registers __iomem *transport_layer_registers)
  85 {
  86         u32 tl_control;
  87
  88         iphy->transport_layer_registers = transport_layer_registers;
  89
  90         writel(SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX,
  91                 &iphy->transport_layer_registers->stp_rni);
  92
  93         /*
  94          * Hardware team recommends that we enable the STP prefetch for all
  95          * transports
  96          */
  97         tl_control = readl(&iphy->transport_layer_registers->control);
  98         tl_control |= SCU_TLCR_GEN_BIT(STP_WRITE_DATA_PREFETCH);
  99         writel(tl_control, &iphy->transport_layer_registers->control);
 100
 101         return SCI_SUCCESS;
 102 }
 103
 104 /**
 105  * This method will initialize the phy link layer registers
 106  * @sci_phy:
 107  * @link_layer_registers:
 108  *
 109  * enum sci_status
 110  */
 111 static enum sci_status
 112 scic_sds_phy_link_layer_initialization(struct isci_phy *iphy,
 113                                        struct scu_link_layer_registers __iomem *link_layer_registers)
 114 {
 115         struct isci_host *ihost =
 116                 iphy->owning_port->owning_controller;
 117         int phy_idx = iphy->phy_index;
 118         struct sci_phy_user_params *phy_user =
 119                 &ihost->user_parameters.sds1.phys[phy_idx];
 120         struct sci_phy_oem_params *phy_oem =
 121                 &ihost->oem_parameters.sds1.phys[phy_idx];
 122         u32 phy_configuration;
 123         struct scic_phy_cap phy_cap;
 124         u32 parity_check = 0;
 125         u32 parity_count = 0;
 126         u32 llctl, link_rate;
 127         u32 clksm_value = 0;
 128
 129         iphy->link_layer_registers = link_layer_registers;
 130
 131         /* Set our IDENTIFY frame data */
 132         #define SCI_END_DEVICE 0x01
 133
 134         writel(SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR) |
 135                SCU_SAS_TIID_GEN_BIT(SSP_INITIATOR) |
 136                SCU_SAS_TIID_GEN_BIT(STP_INITIATOR) |
 137                SCU_SAS_TIID_GEN_BIT(DA_SATA_HOST) |
 138                SCU_SAS_TIID_GEN_VAL(DEVICE_TYPE, SCI_END_DEVICE),
 139                &iphy->link_layer_registers->transmit_identification);
 140
 141         /* Write the device SAS Address */
 142         writel(0xFEDCBA98,
 143                &iphy->link_layer_registers->sas_device_name_high);
 144         writel(phy_idx, &iphy->link_layer_registers->sas_device_name_low);
 145
 146         /* Write the source SAS Address */
 147         writel(phy_oem->sas_address.high,
 148                 &iphy->link_layer_registers->source_sas_address_high);
 149         writel(phy_oem->sas_address.low,
 150                 &iphy->link_layer_registers->source_sas_address_low);
 151
 152         /* Clear and Set the PHY Identifier */
 153         writel(0, &iphy->link_layer_registers->identify_frame_phy_id);
 154         writel(SCU_SAS_TIPID_GEN_VALUE(ID, phy_idx),
 155                 &iphy->link_layer_registers->identify_frame_phy_id);
 156
 157         /* Change the initial state of the phy configuration register */
 158         phy_configuration =
 159                 readl(&iphy->link_layer_registers->phy_configuration);
 160
 161         /* Hold OOB state machine in reset */
 162         phy_configuration |=  SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
 163         writel(phy_configuration,
 164                 &iphy->link_layer_registers->phy_configuration);
 165
 166         /* Configure the SNW capabilities */
 167         phy_cap.all = 0;
 168         phy_cap.start = 1;
 169         phy_cap.gen3_no_ssc = 1;
 170         phy_cap.gen2_no_ssc = 1;
 171         phy_cap.gen1_no_ssc = 1;
 172         if (ihost->oem_parameters.sds1.controller.do_enable_ssc == true) {
 173                 phy_cap.gen3_ssc = 1;
 174                 phy_cap.gen2_ssc = 1;
 175                 phy_cap.gen1_ssc = 1;
 176         }
 177
 178         /*
 179          * The SAS specification indicates that the phy_capabilities that
 180          * are transmitted shall have an even parity.  Calculate the parity. */
 181         parity_check = phy_cap.all;
 182         while (parity_check != 0) {
 183                 if (parity_check & 0x1)
 184                         parity_count++;
 185                 parity_check >>= 1;
 186         }
 187
 188         /*
 189          * If parity indicates there are an odd number of bits set, then
 190          * set the parity bit to 1 in the phy capabilities. */
 191         if ((parity_count % 2) != 0)
 192                 phy_cap.parity = 1;
 193
 194         writel(phy_cap.all, &iphy->link_layer_registers->phy_capabilities);
 195
 196         /* Set the enable spinup period but disable the ability to send
 197          * notify enable spinup
 198          */
 199         writel(SCU_ENSPINUP_GEN_VAL(COUNT,
 200                         phy_user->notify_enable_spin_up_insertion_frequency),
 201                 &iphy->link_layer_registers->notify_enable_spinup_control);
 202
 203         /* Write the ALIGN Insertion Ferequency for connected phy and
 204          * inpendent of connected state
 205          */
 206         clksm_value = SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(CONNECTED,
 207                         phy_user->in_connection_align_insertion_frequency);
 208
 209         clksm_value |= SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(GENERAL,
 210                         phy_user->align_insertion_frequency);
 211
 212         writel(clksm_value, &iphy->link_layer_registers->clock_skew_management);
 213
 214         /* @todo Provide a way to write this register correctly */
 215         writel(0x02108421,
 216                 &iphy->link_layer_registers->afe_lookup_table_control);
 217
 218         llctl = SCU_SAS_LLCTL_GEN_VAL(NO_OUTBOUND_TASK_TIMEOUT,
 219                 (u8)ihost->user_parameters.sds1.no_outbound_task_timeout);
 220
 221         switch(phy_user->max_speed_generation) {
 222         case SCIC_SDS_PARM_GEN3_SPEED:
 223                 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3;
 224                 break;
 225         case SCIC_SDS_PARM_GEN2_SPEED:
 226                 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2;
 227                 break;
 228         default:
 229                 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1;
 230                 break;
 231         }
 232         llctl |= SCU_SAS_LLCTL_GEN_VAL(MAX_LINK_RATE, link_rate);
 233         writel(llctl, &iphy->link_layer_registers->link_layer_control);
 234
 235         if (is_a0() || is_a2()) {
 236                 /* Program the max ARB time for the PHY to 700us so we inter-operate with
 237                  * the PMC expander which shuts down PHYs if the expander PHY generates too
 238                  * many breaks.  This time value will guarantee that the initiator PHY will
 239                  * generate the break.
 240                  */
 241                 writel(SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME,
 242                         &iphy->link_layer_registers->maximum_arbitration_wait_timer_timeout);
 243         }
 244
 245         /* Disable link layer hang detection, rely on the OS timeout for I/O timeouts. */
 246         writel(0, &iphy->link_layer_registers->link_layer_hang_detection_timeout);
 247
 248         /* We can exit the initial state to the stopped state */
 249         sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
 250
 251         return SCI_SUCCESS;
 252 }
 253
 254 static void phy_sata_timeout(unsigned long data)
 255 {
 256         struct sci_timer *tmr = (struct sci_timer *)data;
 257         struct isci_phy *iphy = container_of(tmr, typeof(*iphy), sata_timer);
 258         struct isci_host *ihost = iphy->owning_port->owning_controller;
 259         unsigned long flags;
 260
 261         spin_lock_irqsave(&ihost->scic_lock, flags);
 262
 263         if (tmr->cancel)
 264                 goto done;
 265
 266         dev_dbg(sciphy_to_dev(iphy),
 267                  "%s: SCIC SDS Phy 0x%p did not receive signature fis before "
 268                  "timeout.\n",
 269                  __func__,
 270                  iphy);
 271
 272         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 273 done:
 274         spin_unlock_irqrestore(&ihost->scic_lock, flags);
 275 }
 276
 277 /**
 278  * This method returns the port currently containing this phy. If the phy is
 279  *    currently contained by the dummy port, then the phy is considered to not
 280  *    be part of a port.
 281  * @sci_phy: This parameter specifies the phy for which to retrieve the
 282  *    containing port.
 283  *
 284  * This method returns a handle to a port that contains the supplied phy.
 285  * NULL This value is returned if the phy is not part of a real
 286  * port (i.e. it's contained in the dummy port). !NULL All other
 287  * values indicate a handle/pointer to the port containing the phy.
 288  */
 289 struct isci_port *phy_get_non_dummy_port(
 290         struct isci_phy *iphy)
 291 {
 292         if (scic_sds_port_get_index(iphy->owning_port) == SCIC_SDS_DUMMY_PORT)
 293                 return NULL;
 294
 295         return iphy->owning_port;
 296 }
 297
 298 /**
 299  * This method will assign a port to the phy object.
 300  * @out]: iphy This parameter specifies the phy for which to assign a port
 301  *    object.
 302  *
 303  *
 304  */
 305 void scic_sds_phy_set_port(
 306         struct isci_phy *iphy,
 307         struct isci_port *iport)
 308 {
 309         iphy->owning_port = iport;
 310
 311         if (iphy->bcn_received_while_port_unassigned) {
 312                 iphy->bcn_received_while_port_unassigned = false;
 313                 scic_sds_port_broadcast_change_received(iphy->owning_port, iphy);
 314         }
 315 }
 316
 317 /**
 318  * This method will initialize the constructed phy
 319  * @sci_phy:
 320  * @link_layer_registers:
 321  *
 322  * enum sci_status
 323  */
 324 enum sci_status scic_sds_phy_initialize(
 325         struct isci_phy *iphy,
 326         struct scu_transport_layer_registers __iomem *transport_layer_registers,
 327         struct scu_link_layer_registers __iomem *link_layer_registers)
 328 {
 329         /* Perfrom the initialization of the TL hardware */
 330         scic_sds_phy_transport_layer_initialization(
 331                         iphy,
 332                         transport_layer_registers);
 333
 334         /* Perofrm the initialization of the PE hardware */
 335         scic_sds_phy_link_layer_initialization(iphy, link_layer_registers);
 336
 337         /*
 338          * There is nothing that needs to be done in this state just
 339          * transition to the stopped state. */
 340         sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
 341
 342         return SCI_SUCCESS;
 343 }
 344
 345 /**
 346  * This method assigns the direct attached device ID for this phy.
 347  *
 348  * @iphy The phy for which the direct attached device id is to
 349  *       be assigned.
 350  * @device_id The direct attached device ID to assign to the phy.
 351  *       This will either be the RNi for the device or an invalid RNi if there
 352  *       is no current device assigned to the phy.
 353  */
 354 void scic_sds_phy_setup_transport(
 355         struct isci_phy *iphy,
 356         u32 device_id)
 357 {
 358         u32 tl_control;
 359
 360         writel(device_id, &iphy->transport_layer_registers->stp_rni);
 361
 362         /*
 363          * The read should guarantee that the first write gets posted
 364          * before the next write
 365          */
 366         tl_control = readl(&iphy->transport_layer_registers->control);
 367         tl_control |= SCU_TLCR_GEN_BIT(CLEAR_TCI_NCQ_MAPPING_TABLE);
 368         writel(tl_control, &iphy->transport_layer_registers->control);
 369 }
 370
 371 /**
 372  *
 373  * @sci_phy: The phy object to be suspended.
 374  *
 375  * This function will perform the register reads/writes to suspend the SCU
 376  * hardware protocol engine. none
 377  */
 378 static void scic_sds_phy_suspend(
 379         struct isci_phy *iphy)
 380 {
 381         u32 scu_sas_pcfg_value;
 382
 383         scu_sas_pcfg_value =
 384                 readl(&iphy->link_layer_registers->phy_configuration);
 385         scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
 386         writel(scu_sas_pcfg_value,
 387                 &iphy->link_layer_registers->phy_configuration);
 388
 389         scic_sds_phy_setup_transport(
 390                         iphy,
 391                         SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX);
 392 }
 393
 394 void scic_sds_phy_resume(struct isci_phy *iphy)
 395 {
 396         u32 scu_sas_pcfg_value;
 397
 398         scu_sas_pcfg_value =
 399                 readl(&iphy->link_layer_registers->phy_configuration);
 400         scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
 401         writel(scu_sas_pcfg_value,
 402                 &iphy->link_layer_registers->phy_configuration);
 403 }
 404
 405 void scic_sds_phy_get_sas_address(struct isci_phy *iphy,
 406                                   struct sci_sas_address *sas_address)
 407 {
 408         sas_address->high = readl(&iphy->link_layer_registers->source_sas_address_high);
 409         sas_address->low = readl(&iphy->link_layer_registers->source_sas_address_low);
 410 }
 411
 412 void scic_sds_phy_get_attached_sas_address(struct isci_phy *iphy,
 413                                            struct sci_sas_address *sas_address)
 414 {
 415         struct sas_identify_frame *iaf;
 416
 417         iaf = &iphy->frame_rcvd.iaf;
 418         memcpy(sas_address, iaf->sas_addr, SAS_ADDR_SIZE);
 419 }
 420
 421 void scic_sds_phy_get_protocols(struct isci_phy *iphy,
 422                                 struct scic_phy_proto *protocols)
 423 {
 424         protocols->all =
 425                 (u16)(readl(&iphy->
 426                         link_layer_registers->transmit_identification) &
 427                                 0x0000FFFF);
 428 }
 429
 430 enum sci_status scic_sds_phy_start(struct isci_phy *iphy)
 431 {
 432         enum scic_sds_phy_states state = iphy->sm.current_state_id;
 433
 434         if (state != SCI_PHY_STOPPED) {
 435                 dev_dbg(sciphy_to_dev(iphy),
 436                          "%s: in wrong state: %d\n", __func__, state);
 437                 return SCI_FAILURE_INVALID_STATE;
 438         }
 439
 440         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 441         return SCI_SUCCESS;
 442 }
 443
 444 enum sci_status scic_sds_phy_stop(struct isci_phy *iphy)
 445 {
 446         enum scic_sds_phy_states state = iphy->sm.current_state_id;
 447
 448         switch (state) {
 449         case SCI_PHY_SUB_INITIAL:
 450         case SCI_PHY_SUB_AWAIT_OSSP_EN:
 451         case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
 452         case SCI_PHY_SUB_AWAIT_SAS_POWER:
 453         case SCI_PHY_SUB_AWAIT_SATA_POWER:
 454         case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
 455         case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
 456         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
 457         case SCI_PHY_SUB_FINAL:
 458         case SCI_PHY_READY:
 459                 break;
 460         default:
 461                 dev_dbg(sciphy_to_dev(iphy),
 462                         "%s: in wrong state: %d\n", __func__, state);
 463                 return SCI_FAILURE_INVALID_STATE;
 464         }
 465
 466         sci_change_state(&iphy->sm, SCI_PHY_STOPPED);
 467         return SCI_SUCCESS;
 468 }
 469
 470 enum sci_status scic_sds_phy_reset(struct isci_phy *iphy)
 471 {
 472         enum scic_sds_phy_states state = iphy->sm.current_state_id;
 473
 474         if (state != SCI_PHY_READY) {
 475                 dev_dbg(sciphy_to_dev(iphy),
 476                         "%s: in wrong state: %d\n", __func__, state);
 477                 return SCI_FAILURE_INVALID_STATE;
 478         }
 479
 480         sci_change_state(&iphy->sm, SCI_PHY_RESETTING);
 481         return SCI_SUCCESS;
 482 }
 483
 484 enum sci_status scic_sds_phy_consume_power_handler(struct isci_phy *iphy)
 485 {
 486         enum scic_sds_phy_states state = iphy->sm.current_state_id;
 487
 488         switch (state) {
 489         case SCI_PHY_SUB_AWAIT_SAS_POWER: {
 490                 u32 enable_spinup;
 491
 492                 enable_spinup = readl(&iphy->link_layer_registers->notify_enable_spinup_control);
 493                 enable_spinup |= SCU_ENSPINUP_GEN_BIT(ENABLE);
 494                 writel(enable_spinup, &iphy->link_layer_registers->notify_enable_spinup_control);
 495
 496                 /* Change state to the final state this substate machine has run to completion */
 497                 sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL);
 498
 499                 return SCI_SUCCESS;
 500         }
 501         case SCI_PHY_SUB_AWAIT_SATA_POWER: {
 502                 u32 scu_sas_pcfg_value;
 503
 504                 /* Release the spinup hold state and reset the OOB state machine */
 505                 scu_sas_pcfg_value =
 506                         readl(&iphy->link_layer_registers->phy_configuration);
 507                 scu_sas_pcfg_value &=
 508                         ~(SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD) | SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE));
 509                 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
 510                 writel(scu_sas_pcfg_value,
 511                         &iphy->link_layer_registers->phy_configuration);
 512
 513                 /* Now restart the OOB operation */
 514                 scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
 515                 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
 516                 writel(scu_sas_pcfg_value,
 517                         &iphy->link_layer_registers->phy_configuration);
 518
 519                 /* Change state to the final state this substate machine has run to completion */
 520                 sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_PHY_EN);
 521
 522                 return SCI_SUCCESS;
 523         }
 524         default:
 525                 dev_dbg(sciphy_to_dev(iphy),
 526                         "%s: in wrong state: %d\n", __func__, state);
 527                 return SCI_FAILURE_INVALID_STATE;
 528         }
 529 }
 530
 531 /*
 532  * *****************************************************************************
 533  * * SCIC SDS PHY HELPER FUNCTIONS
 534  * ***************************************************************************** */
 535
 536
 537 /**
 538  *
 539  * @sci_phy: The phy object that received SAS PHY DETECTED.
 540  *
 541  * This method continues the link training for the phy as if it were a SAS PHY
 542  * instead of a SATA PHY. This is done because the completion queue had a SAS
 543  * PHY DETECTED event when the state machine was expecting a SATA PHY event.
 544  * none
 545  */
 546 static void scic_sds_phy_start_sas_link_training(
 547         struct isci_phy *iphy)
 548 {
 549         u32 phy_control;
 550
 551         phy_control =
 552                 readl(&iphy->link_layer_registers->phy_configuration);
 553         phy_control |= SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD);
 554         writel(phy_control,
 555                 &iphy->link_layer_registers->phy_configuration);
 556
 557         sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SAS_SPEED_EN);
 558
 559         iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SAS;
 560 }
 561
 562 /**
 563  *
 564  * @sci_phy: The phy object that received a SATA SPINUP HOLD event
 565  *
 566  * This method continues the link training for the phy as if it were a SATA PHY
 567  * instead of a SAS PHY.  This is done because the completion queue had a SATA
 568  * SPINUP HOLD event when the state machine was expecting a SAS PHY event. none
 569  */
 570 static void scic_sds_phy_start_sata_link_training(
 571         struct isci_phy *iphy)
 572 {
 573         sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_POWER);
 574
 575         iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA;
 576 }
 577
 578 /**
 579  * scic_sds_phy_complete_link_training - perform processing common to
 580  *    all protocols upon completion of link training.
 581  * @sci_phy: This parameter specifies the phy object for which link training
 582  *    has completed.
 583  * @max_link_rate: This parameter specifies the maximum link rate to be
 584  *    associated with this phy.
 585  * @next_state: This parameter specifies the next state for the phy's starting
 586  *    sub-state machine.
 587  *
 588  */
 589 static void scic_sds_phy_complete_link_training(
 590         struct isci_phy *iphy,
 591         enum sas_linkrate max_link_rate,
 592         u32 next_state)
 593 {
 594         iphy->max_negotiated_speed = max_link_rate;
 595
 596         sci_change_state(&iphy->sm, next_state);
 597 }
 598
 599 enum sci_status scic_sds_phy_event_handler(struct isci_phy *iphy,
 600                                            u32 event_code)
 601 {
 602         enum scic_sds_phy_states state = iphy->sm.current_state_id;
 603
 604         switch (state) {
 605         case SCI_PHY_SUB_AWAIT_OSSP_EN:
 606                 switch (scu_get_event_code(event_code)) {
 607                 case SCU_EVENT_SAS_PHY_DETECTED:
 608                         scic_sds_phy_start_sas_link_training(iphy);
 609                         iphy->is_in_link_training = true;
 610                         break;
 611                 case SCU_EVENT_SATA_SPINUP_HOLD:
 612                         scic_sds_phy_start_sata_link_training(iphy);
 613                         iphy->is_in_link_training = true;
 614                         break;
 615                 default:
 616                         dev_dbg(sciphy_to_dev(iphy),
 617                                 "%s: PHY starting substate machine received "
 618                                 "unexpected event_code %x\n",
 619                                 __func__,
 620                                 event_code);
 621                         return SCI_FAILURE;
 622                 }
 623                 return SCI_SUCCESS;
 624         case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
 625                 switch (scu_get_event_code(event_code)) {
 626                 case SCU_EVENT_SAS_PHY_DETECTED:
 627                         /*
 628                          * Why is this being reported again by the controller?
 629                          * We would re-enter this state so just stay here */
 630                         break;
 631                 case SCU_EVENT_SAS_15:
 632                 case SCU_EVENT_SAS_15_SSC:
 633                         scic_sds_phy_complete_link_training(
 634                                 iphy,
 635                                 SAS_LINK_RATE_1_5_GBPS,
 636                                 SCI_PHY_SUB_AWAIT_IAF_UF);
 637                         break;
 638                 case SCU_EVENT_SAS_30:
 639                 case SCU_EVENT_SAS_30_SSC:
 640                         scic_sds_phy_complete_link_training(
 641                                 iphy,
 642                                 SAS_LINK_RATE_3_0_GBPS,
 643                                 SCI_PHY_SUB_AWAIT_IAF_UF);
 644                         break;
 645                 case SCU_EVENT_SAS_60:
 646                 case SCU_EVENT_SAS_60_SSC:
 647                         scic_sds_phy_complete_link_training(
 648                                 iphy,
 649                                 SAS_LINK_RATE_6_0_GBPS,
 650                                 SCI_PHY_SUB_AWAIT_IAF_UF);
 651                         break;
 652                 case SCU_EVENT_SATA_SPINUP_HOLD:
 653                         /*
 654                          * We were doing SAS PHY link training and received a SATA PHY event
 655                          * continue OOB/SN as if this were a SATA PHY */
 656                         scic_sds_phy_start_sata_link_training(iphy);
 657                         break;
 658                 case SCU_EVENT_LINK_FAILURE:
 659                         /* Link failure change state back to the starting state */
 660                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 661                         break;
 662                 default:
 663                         dev_warn(sciphy_to_dev(iphy),
 664                                  "%s: PHY starting substate machine received "
 665                                  "unexpected event_code %x\n",
 666                                  __func__, event_code);
 667
 668                         return SCI_FAILURE;
 669                         break;
 670                 }
 671                 return SCI_SUCCESS;
 672         case SCI_PHY_SUB_AWAIT_IAF_UF:
 673                 switch (scu_get_event_code(event_code)) {
 674                 case SCU_EVENT_SAS_PHY_DETECTED:
 675                         /* Backup the state machine */
 676                         scic_sds_phy_start_sas_link_training(iphy);
 677                         break;
 678                 case SCU_EVENT_SATA_SPINUP_HOLD:
 679                         /* We were doing SAS PHY link training and received a
 680                          * SATA PHY event continue OOB/SN as if this were a
 681                          * SATA PHY
 682                          */
 683                         scic_sds_phy_start_sata_link_training(iphy);
 684                         break;
 685                 case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
 686                 case SCU_EVENT_LINK_FAILURE:
 687                 case SCU_EVENT_HARD_RESET_RECEIVED:
 688                         /* Start the oob/sn state machine over again */
 689                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 690                         break;
 691                 default:
 692                         dev_warn(sciphy_to_dev(iphy),
 693                                  "%s: PHY starting substate machine received "
 694                                  "unexpected event_code %x\n",
 695                                  __func__, event_code);
 696                         return SCI_FAILURE;
 697                 }
 698                 return SCI_SUCCESS;
 699         case SCI_PHY_SUB_AWAIT_SAS_POWER:
 700                 switch (scu_get_event_code(event_code)) {
 701                 case SCU_EVENT_LINK_FAILURE:
 702                         /* Link failure change state back to the starting state */
 703                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 704                         break;
 705                 default:
 706                         dev_warn(sciphy_to_dev(iphy),
 707                                 "%s: PHY starting substate machine received unexpected "
 708                                 "event_code %x\n",
 709                                 __func__,
 710                                 event_code);
 711                         return SCI_FAILURE;
 712                 }
 713                 return SCI_SUCCESS;
 714         case SCI_PHY_SUB_AWAIT_SATA_POWER:
 715                 switch (scu_get_event_code(event_code)) {
 716                 case SCU_EVENT_LINK_FAILURE:
 717                         /* Link failure change state back to the starting state */
 718                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 719                         break;
 720                 case SCU_EVENT_SATA_SPINUP_HOLD:
 721                         /* These events are received every 10ms and are
 722                          * expected while in this state
 723                          */
 724                         break;
 725
 726                 case SCU_EVENT_SAS_PHY_DETECTED:
 727                         /* There has been a change in the phy type before OOB/SN for the
 728                          * SATA finished start down the SAS link traning path.
 729                          */
 730                         scic_sds_phy_start_sas_link_training(iphy);
 731                         break;
 732
 733                 default:
 734                         dev_warn(sciphy_to_dev(iphy),
 735                                  "%s: PHY starting substate machine received "
 736                                  "unexpected event_code %x\n",
 737                                  __func__, event_code);
 738
 739                         return SCI_FAILURE;
 740                 }
 741                 return SCI_SUCCESS;
 742         case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
 743                 switch (scu_get_event_code(event_code)) {
 744                 case SCU_EVENT_LINK_FAILURE:
 745                         /* Link failure change state back to the starting state */
 746                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 747                         break;
 748                 case SCU_EVENT_SATA_SPINUP_HOLD:
 749                         /* These events might be received since we dont know how many may be in
 750                          * the completion queue while waiting for power
 751                          */
 752                         break;
 753                 case SCU_EVENT_SATA_PHY_DETECTED:
 754                         iphy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA;
 755
 756                         /* We have received the SATA PHY notification change state */
 757                         sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
 758                         break;
 759                 case SCU_EVENT_SAS_PHY_DETECTED:
 760                         /* There has been a change in the phy type before OOB/SN for the
 761                          * SATA finished start down the SAS link traning path.
 762                          */
 763                         scic_sds_phy_start_sas_link_training(iphy);
 764                         break;
 765                 default:
 766                         dev_warn(sciphy_to_dev(iphy),
 767                                  "%s: PHY starting substate machine received "
 768                                  "unexpected event_code %x\n",
 769                                  __func__,
 770                                  event_code);
 771
 772                         return SCI_FAILURE;;
 773                 }
 774                 return SCI_SUCCESS;
 775         case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
 776                 switch (scu_get_event_code(event_code)) {
 777                 case SCU_EVENT_SATA_PHY_DETECTED:
 778                         /*
 779                          * The hardware reports multiple SATA PHY detected events
 780                          * ignore the extras */
 781                         break;
 782                 case SCU_EVENT_SATA_15:
 783                 case SCU_EVENT_SATA_15_SSC:
 784                         scic_sds_phy_complete_link_training(
 785                                 iphy,
 786                                 SAS_LINK_RATE_1_5_GBPS,
 787                                 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
 788                         break;
 789                 case SCU_EVENT_SATA_30:
 790                 case SCU_EVENT_SATA_30_SSC:
 791                         scic_sds_phy_complete_link_training(
 792                                 iphy,
 793                                 SAS_LINK_RATE_3_0_GBPS,
 794                                 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
 795                         break;
 796                 case SCU_EVENT_SATA_60:
 797                 case SCU_EVENT_SATA_60_SSC:
 798                         scic_sds_phy_complete_link_training(
 799                                 iphy,
 800                                 SAS_LINK_RATE_6_0_GBPS,
 801                                 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
 802                         break;
 803                 case SCU_EVENT_LINK_FAILURE:
 804                         /* Link failure change state back to the starting state */
 805                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 806                         break;
 807                 case SCU_EVENT_SAS_PHY_DETECTED:
 808                         /*
 809                          * There has been a change in the phy type before OOB/SN for the
 810                          * SATA finished start down the SAS link traning path. */
 811                         scic_sds_phy_start_sas_link_training(iphy);
 812                         break;
 813                 default:
 814                         dev_warn(sciphy_to_dev(iphy),
 815                                  "%s: PHY starting substate machine received "
 816                                  "unexpected event_code %x\n",
 817                                  __func__, event_code);
 818
 819                         return SCI_FAILURE;
 820                 }
 821
 822                 return SCI_SUCCESS;
 823         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
 824                 switch (scu_get_event_code(event_code)) {
 825                 case SCU_EVENT_SATA_PHY_DETECTED:
 826                         /* Backup the state machine */
 827                         sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
 828                         break;
 829
 830                 case SCU_EVENT_LINK_FAILURE:
 831                         /* Link failure change state back to the starting state */
 832                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 833                         break;
 834
 835                 default:
 836                         dev_warn(sciphy_to_dev(iphy),
 837                                  "%s: PHY starting substate machine received "
 838                                  "unexpected event_code %x\n",
 839                                  __func__,
 840                                  event_code);
 841
 842                         return SCI_FAILURE;
 843                 }
 844                 return SCI_SUCCESS;
 845         case SCI_PHY_READY:
 846                 switch (scu_get_event_code(event_code)) {
 847                 case SCU_EVENT_LINK_FAILURE:
 848                         /* Link failure change state back to the starting state */
 849                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 850                         break;
 851                 case SCU_EVENT_BROADCAST_CHANGE:
 852                         /* Broadcast change received. Notify the port. */
 853                         if (phy_get_non_dummy_port(iphy) != NULL)
 854                                 scic_sds_port_broadcast_change_received(iphy->owning_port, iphy);
 855                         else
 856                                 iphy->bcn_received_while_port_unassigned = true;
 857                         break;
 858                 default:
 859                         dev_warn(sciphy_to_dev(iphy),
 860                                  "%sP SCIC PHY 0x%p ready state machine received "
 861                                  "unexpected event_code %x\n",
 862                                  __func__, iphy, event_code);
 863                         return SCI_FAILURE_INVALID_STATE;
 864                 }
 865                 return SCI_SUCCESS;
 866         case SCI_PHY_RESETTING:
 867                 switch (scu_get_event_code(event_code)) {
 868                 case SCU_EVENT_HARD_RESET_TRANSMITTED:
 869                         /* Link failure change state back to the starting state */
 870                         sci_change_state(&iphy->sm, SCI_PHY_STARTING);
 871                         break;
 872                 default:
 873                         dev_warn(sciphy_to_dev(iphy),
 874                                  "%s: SCIC PHY 0x%p resetting state machine received "
 875                                  "unexpected event_code %x\n",
 876                                  __func__, iphy, event_code);
 877
 878                         return SCI_FAILURE_INVALID_STATE;
 879                         break;
 880                 }
 881                 return SCI_SUCCESS;
 882         default:
 883                 dev_dbg(sciphy_to_dev(iphy),
 884                         "%s: in wrong state: %d\n", __func__, state);
 885                 return SCI_FAILURE_INVALID_STATE;
 886         }
 887 }
 888
 889 enum sci_status scic_sds_phy_frame_handler(struct isci_phy *iphy,
 890                                            u32 frame_index)
 891 {
 892         enum scic_sds_phy_states state = iphy->sm.current_state_id;
 893         struct isci_host *ihost = iphy->owning_port->owning_controller;
 894         enum sci_status result;
 895         unsigned long flags;
 896
 897         switch (state) {
 898         case SCI_PHY_SUB_AWAIT_IAF_UF: {
 899                 u32 *frame_words;
 900                 struct sas_identify_frame iaf;
 901
 902                 result = scic_sds_unsolicited_frame_control_get_header(&ihost->uf_control,
 903                                                                        frame_index,
 904                                                                        (void **)&frame_words);
 905
 906                 if (result != SCI_SUCCESS)
 907                         return result;
 908
 909                 sci_swab32_cpy(&iaf, frame_words, sizeof(iaf) / sizeof(u32));
 910                 if (iaf.frame_type == 0) {
 911                         u32 state;
 912
 913                         spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags);
 914                         memcpy(&iphy->frame_rcvd.iaf, &iaf, sizeof(iaf));
 915                         spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags);
 916                         if (iaf.smp_tport) {
 917                                 /* We got the IAF for an expander PHY go to the final
 918                                  * state since there are no power requirements for
 919                                  * expander phys.
 920                                  */
 921                                 state = SCI_PHY_SUB_FINAL;
 922                         } else {
 923                                 /* We got the IAF we can now go to the await spinup
 924                                  * semaphore state
 925                                  */
 926                                 state = SCI_PHY_SUB_AWAIT_SAS_POWER;
 927                         }
 928                         sci_change_state(&iphy->sm, state);
 929                         result = SCI_SUCCESS;
 930                 } else
 931                         dev_warn(sciphy_to_dev(iphy),
 932                                 "%s: PHY starting substate machine received "
 933                                 "unexpected frame id %x\n",
 934                                 __func__, frame_index);
 935
 936                 scic_sds_controller_release_frame(ihost, frame_index);
 937                 return result;
 938         }
 939         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: {
 940                 struct dev_to_host_fis *frame_header;
 941                 u32 *fis_frame_data;
 942
 943                 result = scic_sds_unsolicited_frame_control_get_header(
 944                         &(scic_sds_phy_get_controller(iphy)->uf_control),
 945                         frame_index,
 946                         (void **)&frame_header);
 947
 948                 if (result != SCI_SUCCESS)
 949                         return result;
 950
 951                 if ((frame_header->fis_type == FIS_REGD2H) &&
 952                     !(frame_header->status & ATA_BUSY)) {
 953                         scic_sds_unsolicited_frame_control_get_buffer(&ihost->uf_control,
 954                                                                       frame_index,
 955                                                                       (void **)&fis_frame_data);
 956
 957                         spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags);
 958                         scic_sds_controller_copy_sata_response(&iphy->frame_rcvd.fis,
 959                                                                frame_header,
 960                                                                fis_frame_data);
 961                         spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags);
 962
 963                         /* got IAF we can now go to the await spinup semaphore state */
 964                         sci_change_state(&iphy->sm, SCI_PHY_SUB_FINAL);
 965
 966                         result = SCI_SUCCESS;
 967                 } else
 968                         dev_warn(sciphy_to_dev(iphy),
 969                                  "%s: PHY starting substate machine received "
 970                                  "unexpected frame id %x\n",
 971                                  __func__, frame_index);
 972
 973                 /* Regardless of the result we are done with this frame with it */
 974                 scic_sds_controller_release_frame(ihost, frame_index);
 975
 976                 return result;
 977         }
 978         default:
 979                 dev_dbg(sciphy_to_dev(iphy),
 980                         "%s: in wrong state: %d\n", __func__, state);
 981                 return SCI_FAILURE_INVALID_STATE;
 982         }
 983
 984 }
 985
 986 static void scic_sds_phy_starting_initial_substate_enter(struct sci_base_state_machine *sm)
 987 {
 988         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
 989
 990         /* This is just an temporary state go off to the starting state */
 991         sci_change_state(&iphy->sm, SCI_PHY_SUB_AWAIT_OSSP_EN);
 992 }
 993
 994 static void scic_sds_phy_starting_await_sas_power_substate_enter(struct sci_base_state_machine *sm)
 995 {
 996         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
 997         struct isci_host *ihost = iphy->owning_port->owning_controller;
 998
 999         scic_sds_controller_power_control_queue_insert(ihost, iphy);
1000 }
1001
1002 static void scic_sds_phy_starting_await_sas_power_substate_exit(struct sci_base_state_machine *sm)
1003 {
1004         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1005         struct isci_host *ihost = iphy->owning_port->owning_controller;
1006
1007         scic_sds_controller_power_control_queue_remove(ihost, iphy);
1008 }
1009
1010 static void scic_sds_phy_starting_await_sata_power_substate_enter(struct sci_base_state_machine *sm)
1011 {
1012         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1013         struct isci_host *ihost = iphy->owning_port->owning_controller;
1014
1015         scic_sds_controller_power_control_queue_insert(ihost, iphy);
1016 }
1017
1018 static void scic_sds_phy_starting_await_sata_power_substate_exit(struct sci_base_state_machine *sm)
1019 {
1020         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1021         struct isci_host *ihost = iphy->owning_port->owning_controller;
1022
1023         scic_sds_controller_power_control_queue_remove(ihost, iphy);
1024 }
1025
1026 static void scic_sds_phy_starting_await_sata_phy_substate_enter(struct sci_base_state_machine *sm)
1027 {
1028         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1029
1030         sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
1031 }
1032
1033 static void scic_sds_phy_starting_await_sata_phy_substate_exit(struct sci_base_state_machine *sm)
1034 {
1035         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1036
1037         sci_del_timer(&iphy->sata_timer);
1038 }
1039
1040 static void scic_sds_phy_starting_await_sata_speed_substate_enter(struct sci_base_state_machine *sm)
1041 {
1042         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1043
1044         sci_mod_timer(&iphy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
1045 }
1046
1047 static void scic_sds_phy_starting_await_sata_speed_substate_exit(struct sci_base_state_machine *sm)
1048 {
1049         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1050
1051         sci_del_timer(&iphy->sata_timer);
1052 }
1053
1054 static void scic_sds_phy_starting_await_sig_fis_uf_substate_enter(struct sci_base_state_machine *sm)
1055 {
1056         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1057
1058         if (scic_sds_port_link_detected(iphy->owning_port, iphy)) {
1059
1060                 /*
1061                  * Clear the PE suspend condition so we can actually
1062                  * receive SIG FIS
1063                  * The hardware will not respond to the XRDY until the PE
1064                  * suspend condition is cleared.
1065                  */
1066                 scic_sds_phy_resume(iphy);
1067
1068                 sci_mod_timer(&iphy->sata_timer,
1069                               SCIC_SDS_SIGNATURE_FIS_TIMEOUT);
1070         } else
1071                 iphy->is_in_link_training = false;
1072 }
1073
1074 static void scic_sds_phy_starting_await_sig_fis_uf_substate_exit(struct sci_base_state_machine *sm)
1075 {
1076         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1077
1078         sci_del_timer(&iphy->sata_timer);
1079 }
1080
1081 static void scic_sds_phy_starting_final_substate_enter(struct sci_base_state_machine *sm)
1082 {
1083         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1084
1085         /* State machine has run to completion so exit out and change
1086          * the base state machine to the ready state
1087          */
1088         sci_change_state(&iphy->sm, SCI_PHY_READY);
1089 }
1090
1091 /**
1092  *
1093  * @sci_phy: This is the struct isci_phy object to stop.
1094  *
1095  * This method will stop the struct isci_phy object. This does not reset the
1096  * protocol engine it just suspends it and places it in a state where it will
1097  * not cause the end device to power up. none
1098  */
1099 static void scu_link_layer_stop_protocol_engine(
1100         struct isci_phy *iphy)
1101 {
1102         u32 scu_sas_pcfg_value;
1103         u32 enable_spinup_value;
1104
1105         /* Suspend the protocol engine and place it in a sata spinup hold state */
1106         scu_sas_pcfg_value =
1107                 readl(&iphy->link_layer_registers->phy_configuration);
1108         scu_sas_pcfg_value |=
1109                 (SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1110                  SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE) |
1111                  SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD));
1112         writel(scu_sas_pcfg_value,
1113                &iphy->link_layer_registers->phy_configuration);
1114
1115         /* Disable the notify enable spinup primitives */
1116         enable_spinup_value = readl(&iphy->link_layer_registers->notify_enable_spinup_control);
1117         enable_spinup_value &= ~SCU_ENSPINUP_GEN_BIT(ENABLE);
1118         writel(enable_spinup_value, &iphy->link_layer_registers->notify_enable_spinup_control);
1119 }
1120
1121 /**
1122  *
1123  *
1124  * This method will start the OOB/SN state machine for this struct isci_phy object.
1125  */
1126 static void scu_link_layer_start_oob(
1127         struct isci_phy *iphy)
1128 {
1129         u32 scu_sas_pcfg_value;
1130
1131         scu_sas_pcfg_value =
1132                 readl(&iphy->link_layer_registers->phy_configuration);
1133         scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1134         scu_sas_pcfg_value &=
1135                 ~(SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1136                 SCU_SAS_PCFG_GEN_BIT(HARD_RESET));
1137         writel(scu_sas_pcfg_value,
1138                &iphy->link_layer_registers->phy_configuration);
1139 }
1140
1141 /**
1142  *
1143  *
1144  * This method will transmit a hard reset request on the specified phy. The SCU
1145  * hardware requires that we reset the OOB state machine and set the hard reset
1146  * bit in the phy configuration register. We then must start OOB over with the
1147  * hard reset bit set.
1148  */
1149 static void scu_link_layer_tx_hard_reset(
1150         struct isci_phy *iphy)
1151 {
1152         u32 phy_configuration_value;
1153
1154         /*
1155          * SAS Phys must wait for the HARD_RESET_TX event notification to transition
1156          * to the starting state. */
1157         phy_configuration_value =
1158                 readl(&iphy->link_layer_registers->phy_configuration);
1159         phy_configuration_value |=
1160                 (SCU_SAS_PCFG_GEN_BIT(HARD_RESET) |
1161                  SCU_SAS_PCFG_GEN_BIT(OOB_RESET));
1162         writel(phy_configuration_value,
1163                &iphy->link_layer_registers->phy_configuration);
1164
1165         /* Now take the OOB state machine out of reset */
1166         phy_configuration_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1167         phy_configuration_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
1168         writel(phy_configuration_value,
1169                &iphy->link_layer_registers->phy_configuration);
1170 }
1171
1172 static void scic_sds_phy_stopped_state_enter(struct sci_base_state_machine *sm)
1173 {
1174         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1175
1176         /*
1177          * @todo We need to get to the controller to place this PE in a
1178          * reset state
1179          */
1180         sci_del_timer(&iphy->sata_timer);
1181
1182         scu_link_layer_stop_protocol_engine(iphy);
1183
1184         if (iphy->sm.previous_state_id != SCI_PHY_INITIAL)
1185                 scic_sds_controller_link_down(scic_sds_phy_get_controller(iphy),
1186                                               phy_get_non_dummy_port(iphy),
1187                                               iphy);
1188 }
1189
1190 static void scic_sds_phy_starting_state_enter(struct sci_base_state_machine *sm)
1191 {
1192         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1193
1194         scu_link_layer_stop_protocol_engine(iphy);
1195         scu_link_layer_start_oob(iphy);
1196
1197         /* We don't know what kind of phy we are going to be just yet */
1198         iphy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN;
1199         iphy->bcn_received_while_port_unassigned = false;
1200
1201         if (iphy->sm.previous_state_id == SCI_PHY_READY)
1202                 scic_sds_controller_link_down(scic_sds_phy_get_controller(iphy),
1203                                               phy_get_non_dummy_port(iphy),
1204                                               iphy);
1205
1206         sci_change_state(&iphy->sm, SCI_PHY_SUB_INITIAL);
1207 }
1208
1209 static void scic_sds_phy_ready_state_enter(struct sci_base_state_machine *sm)
1210 {
1211         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1212
1213         scic_sds_controller_link_up(scic_sds_phy_get_controller(iphy),
1214                                     phy_get_non_dummy_port(iphy),
1215                                     iphy);
1216
1217 }
1218
1219 static void scic_sds_phy_ready_state_exit(struct sci_base_state_machine *sm)
1220 {
1221         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1222
1223         scic_sds_phy_suspend(iphy);
1224 }
1225
1226 static void scic_sds_phy_resetting_state_enter(struct sci_base_state_machine *sm)
1227 {
1228         struct isci_phy *iphy = container_of(sm, typeof(*iphy), sm);
1229
1230         /* The phy is being reset, therefore deactivate it from the port.  In
1231          * the resetting state we don't notify the user regarding link up and
1232          * link down notifications
1233          */
1234         scic_sds_port_deactivate_phy(iphy->owning_port, iphy, false);
1235
1236         if (iphy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS) {
1237                 scu_link_layer_tx_hard_reset(iphy);
1238         } else {
1239                 /* The SCU does not need to have a discrete reset state so
1240                  * just go back to the starting state.
1241                  */
1242                 sci_change_state(&iphy->sm, SCI_PHY_STARTING);
1243         }
1244 }
1245
1246 static const struct sci_base_state scic_sds_phy_state_table[] = {
1247         [SCI_PHY_INITIAL] = { },
1248         [SCI_PHY_STOPPED] = {
1249                 .enter_state = scic_sds_phy_stopped_state_enter,
1250         },
1251         [SCI_PHY_STARTING] = {
1252                 .enter_state = scic_sds_phy_starting_state_enter,
1253         },
1254         [SCI_PHY_SUB_INITIAL] = {
1255                 .enter_state = scic_sds_phy_starting_initial_substate_enter,
1256         },
1257         [SCI_PHY_SUB_AWAIT_OSSP_EN] = { },
1258         [SCI_PHY_SUB_AWAIT_SAS_SPEED_EN] = { },
1259         [SCI_PHY_SUB_AWAIT_IAF_UF] = { },
1260         [SCI_PHY_SUB_AWAIT_SAS_POWER] = {
1261                 .enter_state = scic_sds_phy_starting_await_sas_power_substate_enter,
1262                 .exit_state  = scic_sds_phy_starting_await_sas_power_substate_exit,
1263         },
1264         [SCI_PHY_SUB_AWAIT_SATA_POWER] = {
1265                 .enter_state = scic_sds_phy_starting_await_sata_power_substate_enter,
1266                 .exit_state  = scic_sds_phy_starting_await_sata_power_substate_exit
1267         },
1268         [SCI_PHY_SUB_AWAIT_SATA_PHY_EN] = {
1269                 .enter_state = scic_sds_phy_starting_await_sata_phy_substate_enter,
1270                 .exit_state  = scic_sds_phy_starting_await_sata_phy_substate_exit
1271         },
1272         [SCI_PHY_SUB_AWAIT_SATA_SPEED_EN] = {
1273                 .enter_state = scic_sds_phy_starting_await_sata_speed_substate_enter,
1274                 .exit_state  = scic_sds_phy_starting_await_sata_speed_substate_exit
1275         },
1276         [SCI_PHY_SUB_AWAIT_SIG_FIS_UF] = {
1277                 .enter_state = scic_sds_phy_starting_await_sig_fis_uf_substate_enter,
1278                 .exit_state  = scic_sds_phy_starting_await_sig_fis_uf_substate_exit
1279         },
1280         [SCI_PHY_SUB_FINAL] = {
1281                 .enter_state = scic_sds_phy_starting_final_substate_enter,
1282         },
1283         [SCI_PHY_READY] = {
1284                 .enter_state = scic_sds_phy_ready_state_enter,
1285                 .exit_state = scic_sds_phy_ready_state_exit,
1286         },
1287         [SCI_PHY_RESETTING] = {
1288                 .enter_state = scic_sds_phy_resetting_state_enter,
1289         },
1290         [SCI_PHY_FINAL] = { },
1291 };
1292
1293 void scic_sds_phy_construct(struct isci_phy *iphy,
1294                             struct isci_port *iport, u8 phy_index)
1295 {
1296         sci_init_sm(&iphy->sm, scic_sds_phy_state_table, SCI_PHY_INITIAL);
1297
1298         /* Copy the rest of the input data to our locals */
1299         iphy->owning_port = iport;
1300         iphy->phy_index = phy_index;
1301         iphy->bcn_received_while_port_unassigned = false;
1302         iphy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN;
1303         iphy->link_layer_registers = NULL;
1304         iphy->max_negotiated_speed = SAS_LINK_RATE_UNKNOWN;
1305
1306         /* Create the SIGNATURE FIS Timeout timer for this phy */
1307         sci_init_timer(&iphy->sata_timer, phy_sata_timeout);
1308 }
1309
1310 void isci_phy_init(struct isci_phy *iphy, struct isci_host *ihost, int index)
1311 {
1312         union scic_oem_parameters oem;
1313         u64 sci_sas_addr;
1314         __be64 sas_addr;
1315
1316         scic_oem_parameters_get(ihost, &oem);
1317         sci_sas_addr = oem.sds1.phys[index].sas_address.high;
1318         sci_sas_addr <<= 32;
1319         sci_sas_addr |= oem.sds1.phys[index].sas_address.low;
1320         sas_addr = cpu_to_be64(sci_sas_addr);
1321         memcpy(iphy->sas_addr, &sas_addr, sizeof(sas_addr));
1322
1323         iphy->isci_port = NULL;
1324         iphy->sas_phy.enabled = 0;
1325         iphy->sas_phy.id = index;
1326         iphy->sas_phy.sas_addr = &iphy->sas_addr[0];
1327         iphy->sas_phy.frame_rcvd = (u8 *)&iphy->frame_rcvd;
1328         iphy->sas_phy.ha = &ihost->sas_ha;
1329         iphy->sas_phy.lldd_phy = iphy;
1330         iphy->sas_phy.enabled = 1;
1331         iphy->sas_phy.class = SAS;
1332         iphy->sas_phy.iproto = SAS_PROTOCOL_ALL;
1333         iphy->sas_phy.tproto = 0;
1334         iphy->sas_phy.type = PHY_TYPE_PHYSICAL;
1335         iphy->sas_phy.role = PHY_ROLE_INITIATOR;
1336         iphy->sas_phy.oob_mode = OOB_NOT_CONNECTED;
1337         iphy->sas_phy.linkrate = SAS_LINK_RATE_UNKNOWN;
1338         memset(&iphy->frame_rcvd, 0, sizeof(iphy->frame_rcvd));
1339 }
1340
1341
1342 /**
1343  * isci_phy_control() - This function is one of the SAS Domain Template
1344  *    functions. This is a phy management function.
1345  * @phy: This parameter specifies the sphy being controlled.
1346  * @func: This parameter specifies the phy control function being invoked.
1347  * @buf: This parameter is specific to the phy function being invoked.
1348  *
1349  * status, zero indicates success.
1350  */
1351 int isci_phy_control(struct asd_sas_phy *sas_phy,
1352                      enum phy_func func,
1353                      void *buf)
1354 {
1355         int ret = 0;
1356         struct isci_phy *iphy = sas_phy->lldd_phy;
1357         struct isci_port *iport = iphy->isci_port;
1358         struct isci_host *ihost = sas_phy->ha->lldd_ha;
1359         unsigned long flags;
1360
1361         dev_dbg(&ihost->pdev->dev,
1362                 "%s: phy %p; func %d; buf %p; isci phy %p, port %p\n",
1363                 __func__, sas_phy, func, buf, iphy, iport);
1364
1365         switch (func) {
1366         case PHY_FUNC_DISABLE:
1367                 spin_lock_irqsave(&ihost->scic_lock, flags);
1368                 scic_sds_phy_stop(iphy);
1369                 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1370                 break;
1371
1372         case PHY_FUNC_LINK_RESET:
1373                 spin_lock_irqsave(&ihost->scic_lock, flags);
1374                 scic_sds_phy_stop(iphy);
1375                 scic_sds_phy_start(iphy);
1376                 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1377                 break;
1378
1379         case PHY_FUNC_HARD_RESET:
1380                 if (!iport)
1381                         return -ENODEV;
1382
1383                 /* Perform the port reset. */
1384                 ret = isci_port_perform_hard_reset(ihost, iport, iphy);
1385
1386                 break;
1387
1388         default:
1389                 dev_dbg(&ihost->pdev->dev,
1390                            "%s: phy %p; func %d NOT IMPLEMENTED!\n",
1391                            __func__, sas_phy, func);
1392                 ret = -ENOSYS;
1393                 break;
1394         }
1395         return ret;
1396 }