drivers/scsi/isci/host.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * GPL LICENSE SUMMARY
   6  *
   7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * BSD LICENSE
  25  *
  26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  27  * All rights reserved.
  28  *
  29  * Redistribution and use in source and binary forms, with or without
  30  * modification, are permitted provided that the following conditions
  31  * are met:
  32  *
  33  *   * Redistributions of source code must retain the above copyright
  34  *     notice, this list of conditions and the following disclaimer.
  35  *   * Redistributions in binary form must reproduce the above copyright
  36  *     notice, this list of conditions and the following disclaimer in
  37  *     the documentation and/or other materials provided with the
  38  *     distribution.
  39  *   * Neither the name of Intel Corporation nor the names of its
  40  *     contributors may be used to endorse or promote products derived
  41  *     from this software without specific prior written permission.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  */
  55 #include <linux/circ_buf.h>
  56 #include <linux/device.h>
  57 #include <scsi/sas.h>
  58 #include "host.h"
  59 #include "isci.h"
  60 #include "port.h"
  61 #include "host.h"
  62 #include "probe_roms.h"
  63 #include "remote_device.h"
  64 #include "request.h"
  65 #include "scu_completion_codes.h"
  66 #include "scu_event_codes.h"
  67 #include "registers.h"
  68 #include "scu_remote_node_context.h"
  69 #include "scu_task_context.h"
  70 #include "scu_unsolicited_frame.h"
  71
  72 #define SCU_CONTEXT_RAM_INIT_STALL_TIME      200
  73
  74 #define smu_max_ports(dcc_value) \
  75         (\
  76                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
  77                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
  78         )
  79
  80 #define smu_max_task_contexts(dcc_value)        \
  81         (\
  82                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
  83                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
  84         )
  85
  86 #define smu_max_rncs(dcc_value) \
  87         (\
  88                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
  89                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
  90         )
  91
  92 #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT      100
  93
  94 /**
  95  *
  96  *
  97  * The number of milliseconds to wait while a given phy is consuming power
  98  * before allowing another set of phys to consume power. Ultimately, this will
  99  * be specified by OEM parameter.
 100  */
 101 #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
 102
 103 /**
 104  * NORMALIZE_PUT_POINTER() -
 105  *
 106  * This macro will normalize the completion queue put pointer so its value can
 107  * be used as an array inde
 108  */
 109 #define NORMALIZE_PUT_POINTER(x) \
 110         ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
 111
 112
 113 /**
 114  * NORMALIZE_EVENT_POINTER() -
 115  *
 116  * This macro will normalize the completion queue event entry so its value can
 117  * be used as an index.
 118  */
 119 #define NORMALIZE_EVENT_POINTER(x) \
 120         (\
 121                 ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
 122                 >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
 123         )
 124
 125 /**
 126  * NORMALIZE_GET_POINTER() -
 127  *
 128  * This macro will normalize the completion queue get pointer so its value can
 129  * be used as an index into an array
 130  */
 131 #define NORMALIZE_GET_POINTER(x) \
 132         ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
 133
 134 /**
 135  * NORMALIZE_GET_POINTER_CYCLE_BIT() -
 136  *
 137  * This macro will normalize the completion queue cycle pointer so it matches
 138  * the completion queue cycle bit
 139  */
 140 #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
 141         ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
 142
 143 /**
 144  * COMPLETION_QUEUE_CYCLE_BIT() -
 145  *
 146  * This macro will return the cycle bit of the completion queue entry
 147  */
 148 #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
 149
 150 /* Init the state machine and call the state entry function (if any) */
 151 void sci_init_sm(struct sci_base_state_machine *sm,
 152                  const struct sci_base_state *state_table, u32 initial_state)
 153 {
 154         sci_state_transition_t handler;
 155
 156         sm->initial_state_id    = initial_state;
 157         sm->previous_state_id   = initial_state;
 158         sm->current_state_id    = initial_state;
 159         sm->state_table         = state_table;
 160
 161         handler = sm->state_table[initial_state].enter_state;
 162         if (handler)
 163                 handler(sm);
 164 }
 165
 166 /* Call the state exit fn, update the current state, call the state entry fn */
 167 void sci_change_state(struct sci_base_state_machine *sm, u32 next_state)
 168 {
 169         sci_state_transition_t handler;
 170
 171         handler = sm->state_table[sm->current_state_id].exit_state;
 172         if (handler)
 173                 handler(sm);
 174
 175         sm->previous_state_id = sm->current_state_id;
 176         sm->current_state_id = next_state;
 177
 178         handler = sm->state_table[sm->current_state_id].enter_state;
 179         if (handler)
 180                 handler(sm);
 181 }
 182
 183 static bool scic_sds_controller_completion_queue_has_entries(
 184         struct scic_sds_controller *scic)
 185 {
 186         u32 get_value = scic->completion_queue_get;
 187         u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
 188
 189         if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) ==
 190             COMPLETION_QUEUE_CYCLE_BIT(scic->completion_queue[get_index]))
 191                 return true;
 192
 193         return false;
 194 }
 195
 196 static bool scic_sds_controller_isr(struct scic_sds_controller *scic)
 197 {
 198         if (scic_sds_controller_completion_queue_has_entries(scic)) {
 199                 return true;
 200         } else {
 201                 /*
 202                  * we have a spurious interrupt it could be that we have already
 203                  * emptied the completion queue from a previous interrupt */
 204                 writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status);
 205
 206                 /*
 207                  * There is a race in the hardware that could cause us not to be notified
 208                  * of an interrupt completion if we do not take this step.  We will mask
 209                  * then unmask the interrupts so if there is another interrupt pending
 210                  * the clearing of the interrupt source we get the next interrupt message. */
 211                 writel(0xFF000000, &scic->smu_registers->interrupt_mask);
 212                 writel(0, &scic->smu_registers->interrupt_mask);
 213         }
 214
 215         return false;
 216 }
 217
 218 irqreturn_t isci_msix_isr(int vec, void *data)
 219 {
 220         struct isci_host *ihost = data;
 221
 222         if (scic_sds_controller_isr(&ihost->sci))
 223                 tasklet_schedule(&ihost->completion_tasklet);
 224
 225         return IRQ_HANDLED;
 226 }
 227
 228 static bool scic_sds_controller_error_isr(struct scic_sds_controller *scic)
 229 {
 230         u32 interrupt_status;
 231
 232         interrupt_status =
 233                 readl(&scic->smu_registers->interrupt_status);
 234         interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
 235
 236         if (interrupt_status != 0) {
 237                 /*
 238                  * There is an error interrupt pending so let it through and handle
 239                  * in the callback */
 240                 return true;
 241         }
 242
 243         /*
 244          * There is a race in the hardware that could cause us not to be notified
 245          * of an interrupt completion if we do not take this step.  We will mask
 246          * then unmask the error interrupts so if there was another interrupt
 247          * pending we will be notified.
 248          * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
 249         writel(0xff, &scic->smu_registers->interrupt_mask);
 250         writel(0, &scic->smu_registers->interrupt_mask);
 251
 252         return false;
 253 }
 254
 255 static void scic_sds_controller_task_completion(struct scic_sds_controller *scic,
 256                                                 u32 completion_entry)
 257 {
 258         u32 index = SCU_GET_COMPLETION_INDEX(completion_entry);
 259         struct isci_host *ihost = scic_to_ihost(scic);
 260         struct isci_request *ireq = ihost->reqs[index];
 261
 262         /* Make sure that we really want to process this IO request */
 263         if (test_bit(IREQ_ACTIVE, &ireq->flags) &&
 264             ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG &&
 265             ISCI_TAG_SEQ(ireq->io_tag) == scic->io_request_sequence[index])
 266                 /* Yep this is a valid io request pass it along to the io request handler */
 267                 scic_sds_io_request_tc_completion(ireq, completion_entry);
 268 }
 269
 270 static void scic_sds_controller_sdma_completion(struct scic_sds_controller *scic,
 271                                                 u32 completion_entry)
 272 {
 273         u32 index;
 274         struct isci_request *ireq;
 275         struct scic_sds_remote_device *device;
 276
 277         index = SCU_GET_COMPLETION_INDEX(completion_entry);
 278
 279         switch (scu_get_command_request_type(completion_entry)) {
 280         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
 281         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
 282                 ireq = scic_to_ihost(scic)->reqs[index];
 283                 dev_warn(scic_to_dev(scic), "%s: %x for io request %p\n",
 284                          __func__, completion_entry, ireq);
 285                 /* @todo For a post TC operation we need to fail the IO
 286                  * request
 287                  */
 288                 break;
 289         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
 290         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
 291         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
 292                 device = scic->device_table[index];
 293                 dev_warn(scic_to_dev(scic), "%s: %x for device %p\n",
 294                          __func__, completion_entry, device);
 295                 /* @todo For a port RNC operation we need to fail the
 296                  * device
 297                  */
 298                 break;
 299         default:
 300                 dev_warn(scic_to_dev(scic), "%s: unknown completion type %x\n",
 301                          __func__, completion_entry);
 302                 break;
 303         }
 304 }
 305
 306 static void scic_sds_controller_unsolicited_frame(struct scic_sds_controller *scic,
 307                                                   u32 completion_entry)
 308 {
 309         u32 index;
 310         u32 frame_index;
 311
 312         struct isci_host *ihost = scic_to_ihost(scic);
 313         struct scu_unsolicited_frame_header *frame_header;
 314         struct scic_sds_phy *phy;
 315         struct scic_sds_remote_device *device;
 316
 317         enum sci_status result = SCI_FAILURE;
 318
 319         frame_index = SCU_GET_FRAME_INDEX(completion_entry);
 320
 321         frame_header = scic->uf_control.buffers.array[frame_index].header;
 322         scic->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE;
 323
 324         if (SCU_GET_FRAME_ERROR(completion_entry)) {
 325                 /*
 326                  * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
 327                  * /       this cause a problem? We expect the phy initialization will
 328                  * /       fail if there is an error in the frame. */
 329                 scic_sds_controller_release_frame(scic, frame_index);
 330                 return;
 331         }
 332
 333         if (frame_header->is_address_frame) {
 334                 index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
 335                 phy = &ihost->phys[index].sci;
 336                 result = scic_sds_phy_frame_handler(phy, frame_index);
 337         } else {
 338
 339                 index = SCU_GET_COMPLETION_INDEX(completion_entry);
 340
 341                 if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
 342                         /*
 343                          * This is a signature fis or a frame from a direct attached SATA
 344                          * device that has not yet been created.  In either case forwared
 345                          * the frame to the PE and let it take care of the frame data. */
 346                         index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
 347                         phy = &ihost->phys[index].sci;
 348                         result = scic_sds_phy_frame_handler(phy, frame_index);
 349                 } else {
 350                         if (index < scic->remote_node_entries)
 351                                 device = scic->device_table[index];
 352                         else
 353                                 device = NULL;
 354
 355                         if (device != NULL)
 356                                 result = scic_sds_remote_device_frame_handler(device, frame_index);
 357                         else
 358                                 scic_sds_controller_release_frame(scic, frame_index);
 359                 }
 360         }
 361
 362         if (result != SCI_SUCCESS) {
 363                 /*
 364                  * / @todo Is there any reason to report some additional error message
 365                  * /       when we get this failure notifiction? */
 366         }
 367 }
 368
 369 static void scic_sds_controller_event_completion(struct scic_sds_controller *scic,
 370                                                  u32 completion_entry)
 371 {
 372         struct isci_host *ihost = scic_to_ihost(scic);
 373         struct scic_sds_remote_device *device;
 374         struct isci_request *ireq;
 375         struct scic_sds_phy *phy;
 376         u32 index;
 377
 378         index = SCU_GET_COMPLETION_INDEX(completion_entry);
 379
 380         switch (scu_get_event_type(completion_entry)) {
 381         case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
 382                 /* / @todo The driver did something wrong and we need to fix the condtion. */
 383                 dev_err(scic_to_dev(scic),
 384                         "%s: SCIC Controller 0x%p received SMU command error "
 385                         "0x%x\n",
 386                         __func__,
 387                         scic,
 388                         completion_entry);
 389                 break;
 390
 391         case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
 392         case SCU_EVENT_TYPE_SMU_ERROR:
 393         case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
 394                 /*
 395                  * / @todo This is a hardware failure and its likely that we want to
 396                  * /       reset the controller. */
 397                 dev_err(scic_to_dev(scic),
 398                         "%s: SCIC Controller 0x%p received fatal controller "
 399                         "event  0x%x\n",
 400                         __func__,
 401                         scic,
 402                         completion_entry);
 403                 break;
 404
 405         case SCU_EVENT_TYPE_TRANSPORT_ERROR:
 406                 ireq = ihost->reqs[index];
 407                 scic_sds_io_request_event_handler(ireq, completion_entry);
 408                 break;
 409
 410         case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
 411                 switch (scu_get_event_specifier(completion_entry)) {
 412                 case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
 413                 case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
 414                         ireq = ihost->reqs[index];
 415                         if (ireq != NULL)
 416                                 scic_sds_io_request_event_handler(ireq, completion_entry);
 417                         else
 418                                 dev_warn(scic_to_dev(scic),
 419                                          "%s: SCIC Controller 0x%p received "
 420                                          "event 0x%x for io request object "
 421                                          "that doesnt exist.\n",
 422                                          __func__,
 423                                          scic,
 424                                          completion_entry);
 425
 426                         break;
 427
 428                 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
 429                         device = scic->device_table[index];
 430                         if (device != NULL)
 431                                 scic_sds_remote_device_event_handler(device, completion_entry);
 432                         else
 433                                 dev_warn(scic_to_dev(scic),
 434                                          "%s: SCIC Controller 0x%p received "
 435                                          "event 0x%x for remote device object "
 436                                          "that doesnt exist.\n",
 437                                          __func__,
 438                                          scic,
 439                                          completion_entry);
 440
 441                         break;
 442                 }
 443                 break;
 444
 445         case SCU_EVENT_TYPE_BROADCAST_CHANGE:
 446         /*
 447          * direct the broadcast change event to the phy first and then let
 448          * the phy redirect the broadcast change to the port object */
 449         case SCU_EVENT_TYPE_ERR_CNT_EVENT:
 450         /*
 451          * direct error counter event to the phy object since that is where
 452          * we get the event notification.  This is a type 4 event. */
 453         case SCU_EVENT_TYPE_OSSP_EVENT:
 454                 index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
 455                 phy = &ihost->phys[index].sci;
 456                 scic_sds_phy_event_handler(phy, completion_entry);
 457                 break;
 458
 459         case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
 460         case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
 461         case SCU_EVENT_TYPE_RNC_OPS_MISC:
 462                 if (index < scic->remote_node_entries) {
 463                         device = scic->device_table[index];
 464
 465                         if (device != NULL)
 466                                 scic_sds_remote_device_event_handler(device, completion_entry);
 467                 } else
 468                         dev_err(scic_to_dev(scic),
 469                                 "%s: SCIC Controller 0x%p received event 0x%x "
 470                                 "for remote device object 0x%0x that doesnt "
 471                                 "exist.\n",
 472                                 __func__,
 473                                 scic,
 474                                 completion_entry,
 475                                 index);
 476
 477                 break;
 478
 479         default:
 480                 dev_warn(scic_to_dev(scic),
 481                          "%s: SCIC Controller received unknown event code %x\n",
 482                          __func__,
 483                          completion_entry);
 484                 break;
 485         }
 486 }
 487
 488 static void scic_sds_controller_process_completions(struct scic_sds_controller *scic)
 489 {
 490         u32 completion_count = 0;
 491         u32 completion_entry;
 492         u32 get_index;
 493         u32 get_cycle;
 494         u32 event_get;
 495         u32 event_cycle;
 496
 497         dev_dbg(scic_to_dev(scic),
 498                 "%s: completion queue begining get:0x%08x\n",
 499                 __func__,
 500                 scic->completion_queue_get);
 501
 502         /* Get the component parts of the completion queue */
 503         get_index = NORMALIZE_GET_POINTER(scic->completion_queue_get);
 504         get_cycle = SMU_CQGR_CYCLE_BIT & scic->completion_queue_get;
 505
 506         event_get = NORMALIZE_EVENT_POINTER(scic->completion_queue_get);
 507         event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & scic->completion_queue_get;
 508
 509         while (
 510                 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
 511                 == COMPLETION_QUEUE_CYCLE_BIT(scic->completion_queue[get_index])
 512                 ) {
 513                 completion_count++;
 514
 515                 completion_entry = scic->completion_queue[get_index];
 516
 517                 /* increment the get pointer and check for rollover to toggle the cycle bit */
 518                 get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) <<
 519                              (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT);
 520                 get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1);
 521
 522                 dev_dbg(scic_to_dev(scic),
 523                         "%s: completion queue entry:0x%08x\n",
 524                         __func__,
 525                         completion_entry);
 526
 527                 switch (SCU_GET_COMPLETION_TYPE(completion_entry)) {
 528                 case SCU_COMPLETION_TYPE_TASK:
 529                         scic_sds_controller_task_completion(scic, completion_entry);
 530                         break;
 531
 532                 case SCU_COMPLETION_TYPE_SDMA:
 533                         scic_sds_controller_sdma_completion(scic, completion_entry);
 534                         break;
 535
 536                 case SCU_COMPLETION_TYPE_UFI:
 537                         scic_sds_controller_unsolicited_frame(scic, completion_entry);
 538                         break;
 539
 540                 case SCU_COMPLETION_TYPE_EVENT:
 541                 case SCU_COMPLETION_TYPE_NOTIFY: {
 542                         event_cycle ^= ((event_get+1) & SCU_MAX_EVENTS) <<
 543                                        (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT);
 544                         event_get = (event_get+1) & (SCU_MAX_EVENTS-1);
 545
 546                         scic_sds_controller_event_completion(scic, completion_entry);
 547                         break;
 548                 }
 549                 default:
 550                         dev_warn(scic_to_dev(scic),
 551                                  "%s: SCIC Controller received unknown "
 552                                  "completion type %x\n",
 553                                  __func__,
 554                                  completion_entry);
 555                         break;
 556                 }
 557         }
 558
 559         /* Update the get register if we completed one or more entries */
 560         if (completion_count > 0) {
 561                 scic->completion_queue_get =
 562                         SMU_CQGR_GEN_BIT(ENABLE) |
 563                         SMU_CQGR_GEN_BIT(EVENT_ENABLE) |
 564                         event_cycle |
 565                         SMU_CQGR_GEN_VAL(EVENT_POINTER, event_get) |
 566                         get_cycle |
 567                         SMU_CQGR_GEN_VAL(POINTER, get_index);
 568
 569                 writel(scic->completion_queue_get,
 570                        &scic->smu_registers->completion_queue_get);
 571
 572         }
 573
 574         dev_dbg(scic_to_dev(scic),
 575                 "%s: completion queue ending get:0x%08x\n",
 576                 __func__,
 577                 scic->completion_queue_get);
 578
 579 }
 580
 581 static void scic_sds_controller_error_handler(struct scic_sds_controller *scic)
 582 {
 583         u32 interrupt_status;
 584
 585         interrupt_status =
 586                 readl(&scic->smu_registers->interrupt_status);
 587
 588         if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
 589             scic_sds_controller_completion_queue_has_entries(scic)) {
 590
 591                 scic_sds_controller_process_completions(scic);
 592                 writel(SMU_ISR_QUEUE_SUSPEND, &scic->smu_registers->interrupt_status);
 593         } else {
 594                 dev_err(scic_to_dev(scic), "%s: status: %#x\n", __func__,
 595                         interrupt_status);
 596
 597                 sci_change_state(&scic->sm, SCIC_FAILED);
 598
 599                 return;
 600         }
 601
 602         /* If we dont process any completions I am not sure that we want to do this.
 603          * We are in the middle of a hardware fault and should probably be reset.
 604          */
 605         writel(0, &scic->smu_registers->interrupt_mask);
 606 }
 607
 608 irqreturn_t isci_intx_isr(int vec, void *data)
 609 {
 610         irqreturn_t ret = IRQ_NONE;
 611         struct isci_host *ihost = data;
 612         struct scic_sds_controller *scic = &ihost->sci;
 613
 614         if (scic_sds_controller_isr(scic)) {
 615                 writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status);
 616                 tasklet_schedule(&ihost->completion_tasklet);
 617                 ret = IRQ_HANDLED;
 618         } else if (scic_sds_controller_error_isr(scic)) {
 619                 spin_lock(&ihost->scic_lock);
 620                 scic_sds_controller_error_handler(scic);
 621                 spin_unlock(&ihost->scic_lock);
 622                 ret = IRQ_HANDLED;
 623         }
 624
 625         return ret;
 626 }
 627
 628 irqreturn_t isci_error_isr(int vec, void *data)
 629 {
 630         struct isci_host *ihost = data;
 631
 632         if (scic_sds_controller_error_isr(&ihost->sci))
 633                 scic_sds_controller_error_handler(&ihost->sci);
 634
 635         return IRQ_HANDLED;
 636 }
 637
 638 /**
 639  * isci_host_start_complete() - This function is called by the core library,
 640  *    through the ISCI Module, to indicate controller start status.
 641  * @isci_host: This parameter specifies the ISCI host object
 642  * @completion_status: This parameter specifies the completion status from the
 643  *    core library.
 644  *
 645  */
 646 static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status)
 647 {
 648         if (completion_status != SCI_SUCCESS)
 649                 dev_info(&ihost->pdev->dev,
 650                         "controller start timed out, continuing...\n");
 651         isci_host_change_state(ihost, isci_ready);
 652         clear_bit(IHOST_START_PENDING, &ihost->flags);
 653         wake_up(&ihost->eventq);
 654 }
 655
 656 int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time)
 657 {
 658         struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
 659
 660         if (test_bit(IHOST_START_PENDING, &ihost->flags))
 661                 return 0;
 662
 663         /* todo: use sas_flush_discovery once it is upstream */
 664         scsi_flush_work(shost);
 665
 666         scsi_flush_work(shost);
 667
 668         dev_dbg(&ihost->pdev->dev,
 669                 "%s: ihost->status = %d, time = %ld\n",
 670                  __func__, isci_host_get_state(ihost), time);
 671
 672         return 1;
 673
 674 }
 675
 676 /**
 677  * scic_controller_get_suggested_start_timeout() - This method returns the
 678  *    suggested scic_controller_start() timeout amount.  The user is free to
 679  *    use any timeout value, but this method provides the suggested minimum
 680  *    start timeout value.  The returned value is based upon empirical
 681  *    information determined as a result of interoperability testing.
 682  * @controller: the handle to the controller object for which to return the
 683  *    suggested start timeout.
 684  *
 685  * This method returns the number of milliseconds for the suggested start
 686  * operation timeout.
 687  */
 688 static u32 scic_controller_get_suggested_start_timeout(
 689         struct scic_sds_controller *sc)
 690 {
 691         /* Validate the user supplied parameters. */
 692         if (sc == NULL)
 693                 return 0;
 694
 695         /*
 696          * The suggested minimum timeout value for a controller start operation:
 697          *
 698          *     Signature FIS Timeout
 699          *   + Phy Start Timeout
 700          *   + Number of Phy Spin Up Intervals
 701          *   ---------------------------------
 702          *   Number of milliseconds for the controller start operation.
 703          *
 704          * NOTE: The number of phy spin up intervals will be equivalent
 705          *       to the number of phys divided by the number phys allowed
 706          *       per interval - 1 (once OEM parameters are supported).
 707          *       Currently we assume only 1 phy per interval. */
 708
 709         return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
 710                 + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
 711                 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
 712 }
 713
 714 static void scic_controller_enable_interrupts(
 715         struct scic_sds_controller *scic)
 716 {
 717         BUG_ON(scic->smu_registers == NULL);
 718         writel(0, &scic->smu_registers->interrupt_mask);
 719 }
 720
 721 void scic_controller_disable_interrupts(
 722         struct scic_sds_controller *scic)
 723 {
 724         BUG_ON(scic->smu_registers == NULL);
 725         writel(0xffffffff, &scic->smu_registers->interrupt_mask);
 726 }
 727
 728 static void scic_sds_controller_enable_port_task_scheduler(
 729         struct scic_sds_controller *scic)
 730 {
 731         u32 port_task_scheduler_value;
 732
 733         port_task_scheduler_value =
 734                 readl(&scic->scu_registers->peg0.ptsg.control);
 735         port_task_scheduler_value |=
 736                 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
 737                  SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
 738         writel(port_task_scheduler_value,
 739                &scic->scu_registers->peg0.ptsg.control);
 740 }
 741
 742 static void scic_sds_controller_assign_task_entries(struct scic_sds_controller *scic)
 743 {
 744         u32 task_assignment;
 745
 746         /*
 747          * Assign all the TCs to function 0
 748          * TODO: Do we actually need to read this register to write it back?
 749          */
 750
 751         task_assignment =
 752                 readl(&scic->smu_registers->task_context_assignment[0]);
 753
 754         task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
 755                 (SMU_TCA_GEN_VAL(ENDING,  scic->task_context_entries - 1)) |
 756                 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
 757
 758         writel(task_assignment,
 759                 &scic->smu_registers->task_context_assignment[0]);
 760
 761 }
 762
 763 static void scic_sds_controller_initialize_completion_queue(struct scic_sds_controller *scic)
 764 {
 765         u32 index;
 766         u32 completion_queue_control_value;
 767         u32 completion_queue_get_value;
 768         u32 completion_queue_put_value;
 769
 770         scic->completion_queue_get = 0;
 771
 772         completion_queue_control_value =
 773                 (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) |
 774                  SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1));
 775
 776         writel(completion_queue_control_value,
 777                &scic->smu_registers->completion_queue_control);
 778
 779
 780         /* Set the completion queue get pointer and enable the queue */
 781         completion_queue_get_value = (
 782                 (SMU_CQGR_GEN_VAL(POINTER, 0))
 783                 | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
 784                 | (SMU_CQGR_GEN_BIT(ENABLE))
 785                 | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
 786                 );
 787
 788         writel(completion_queue_get_value,
 789                &scic->smu_registers->completion_queue_get);
 790
 791         /* Set the completion queue put pointer */
 792         completion_queue_put_value = (
 793                 (SMU_CQPR_GEN_VAL(POINTER, 0))
 794                 | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
 795                 );
 796
 797         writel(completion_queue_put_value,
 798                &scic->smu_registers->completion_queue_put);
 799
 800         /* Initialize the cycle bit of the completion queue entries */
 801         for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) {
 802                 /*
 803                  * If get.cycle_bit != completion_queue.cycle_bit
 804                  * its not a valid completion queue entry
 805                  * so at system start all entries are invalid */
 806                 scic->completion_queue[index] = 0x80000000;
 807         }
 808 }
 809
 810 static void scic_sds_controller_initialize_unsolicited_frame_queue(struct scic_sds_controller *scic)
 811 {
 812         u32 frame_queue_control_value;
 813         u32 frame_queue_get_value;
 814         u32 frame_queue_put_value;
 815
 816         /* Write the queue size */
 817         frame_queue_control_value =
 818                 SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES);
 819
 820         writel(frame_queue_control_value,
 821                &scic->scu_registers->sdma.unsolicited_frame_queue_control);
 822
 823         /* Setup the get pointer for the unsolicited frame queue */
 824         frame_queue_get_value = (
 825                 SCU_UFQGP_GEN_VAL(POINTER, 0)
 826                 |  SCU_UFQGP_GEN_BIT(ENABLE_BIT)
 827                 );
 828
 829         writel(frame_queue_get_value,
 830                &scic->scu_registers->sdma.unsolicited_frame_get_pointer);
 831         /* Setup the put pointer for the unsolicited frame queue */
 832         frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
 833         writel(frame_queue_put_value,
 834                &scic->scu_registers->sdma.unsolicited_frame_put_pointer);
 835 }
 836
 837 /**
 838  * This method will attempt to transition into the ready state for the
 839  *    controller and indicate that the controller start operation has completed
 840  *    if all criteria are met.
 841  * @scic: This parameter indicates the controller object for which
 842  *    to transition to ready.
 843  * @status: This parameter indicates the status value to be pass into the call
 844  *    to scic_cb_controller_start_complete().
 845  *
 846  * none.
 847  */
 848 static void scic_sds_controller_transition_to_ready(
 849         struct scic_sds_controller *scic,
 850         enum sci_status status)
 851 {
 852         struct isci_host *ihost = scic_to_ihost(scic);
 853
 854         if (scic->sm.current_state_id == SCIC_STARTING) {
 855                 /*
 856                  * We move into the ready state, because some of the phys/ports
 857                  * may be up and operational.
 858                  */
 859                 sci_change_state(&scic->sm, SCIC_READY);
 860
 861                 isci_host_start_complete(ihost, status);
 862         }
 863 }
 864
 865 static bool is_phy_starting(struct scic_sds_phy *sci_phy)
 866 {
 867         enum scic_sds_phy_states state;
 868
 869         state = sci_phy->sm.current_state_id;
 870         switch (state) {
 871         case SCI_PHY_STARTING:
 872         case SCI_PHY_SUB_INITIAL:
 873         case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
 874         case SCI_PHY_SUB_AWAIT_IAF_UF:
 875         case SCI_PHY_SUB_AWAIT_SAS_POWER:
 876         case SCI_PHY_SUB_AWAIT_SATA_POWER:
 877         case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
 878         case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
 879         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
 880         case SCI_PHY_SUB_FINAL:
 881                 return true;
 882         default:
 883                 return false;
 884         }
 885 }
 886
 887 /**
 888  * scic_sds_controller_start_next_phy - start phy
 889  * @scic: controller
 890  *
 891  * If all the phys have been started, then attempt to transition the
 892  * controller to the READY state and inform the user
 893  * (scic_cb_controller_start_complete()).
 894  */
 895 static enum sci_status scic_sds_controller_start_next_phy(struct scic_sds_controller *scic)
 896 {
 897         struct isci_host *ihost = scic_to_ihost(scic);
 898         struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1;
 899         struct scic_sds_phy *sci_phy;
 900         enum sci_status status;
 901
 902         status = SCI_SUCCESS;
 903
 904         if (scic->phy_startup_timer_pending)
 905                 return status;
 906
 907         if (scic->next_phy_to_start >= SCI_MAX_PHYS) {
 908                 bool is_controller_start_complete = true;
 909                 u32 state;
 910                 u8 index;
 911
 912                 for (index = 0; index < SCI_MAX_PHYS; index++) {
 913                         sci_phy = &ihost->phys[index].sci;
 914                         state = sci_phy->sm.current_state_id;
 915
 916                         if (!phy_get_non_dummy_port(sci_phy))
 917                                 continue;
 918
 919                         /* The controller start operation is complete iff:
 920                          * - all links have been given an opportunity to start
 921                          * - have no indication of a connected device
 922                          * - have an indication of a connected device and it has
 923                          *   finished the link training process.
 924                          */
 925                         if ((sci_phy->is_in_link_training == false && state == SCI_PHY_INITIAL) ||
 926                             (sci_phy->is_in_link_training == false && state == SCI_PHY_STOPPED) ||
 927                             (sci_phy->is_in_link_training == true && is_phy_starting(sci_phy))) {
 928                                 is_controller_start_complete = false;
 929                                 break;
 930                         }
 931                 }
 932
 933                 /*
 934                  * The controller has successfully finished the start process.
 935                  * Inform the SCI Core user and transition to the READY state. */
 936                 if (is_controller_start_complete == true) {
 937                         scic_sds_controller_transition_to_ready(scic, SCI_SUCCESS);
 938                         sci_del_timer(&scic->phy_timer);
 939                         scic->phy_startup_timer_pending = false;
 940                 }
 941         } else {
 942                 sci_phy = &ihost->phys[scic->next_phy_to_start].sci;
 943
 944                 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
 945                         if (phy_get_non_dummy_port(sci_phy) == NULL) {
 946                                 scic->next_phy_to_start++;
 947
 948                                 /* Caution recursion ahead be forwarned
 949                                  *
 950                                  * The PHY was never added to a PORT in MPC mode
 951                                  * so start the next phy in sequence This phy
 952                                  * will never go link up and will not draw power
 953                                  * the OEM parameters either configured the phy
 954                                  * incorrectly for the PORT or it was never
 955                                  * assigned to a PORT
 956                                  */
 957                                 return scic_sds_controller_start_next_phy(scic);
 958                         }
 959                 }
 960
 961                 status = scic_sds_phy_start(sci_phy);
 962
 963                 if (status == SCI_SUCCESS) {
 964                         sci_mod_timer(&scic->phy_timer,
 965                                       SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT);
 966                         scic->phy_startup_timer_pending = true;
 967                 } else {
 968                         dev_warn(scic_to_dev(scic),
 969                                  "%s: Controller stop operation failed "
 970                                  "to stop phy %d because of status "
 971                                  "%d.\n",
 972                                  __func__,
 973                                  ihost->phys[scic->next_phy_to_start].sci.phy_index,
 974                                  status);
 975                 }
 976
 977                 scic->next_phy_to_start++;
 978         }
 979
 980         return status;
 981 }
 982
 983 static void phy_startup_timeout(unsigned long data)
 984 {
 985         struct sci_timer *tmr = (struct sci_timer *)data;
 986         struct scic_sds_controller *scic = container_of(tmr, typeof(*scic), phy_timer);
 987         struct isci_host *ihost = scic_to_ihost(scic);
 988         unsigned long flags;
 989         enum sci_status status;
 990
 991         spin_lock_irqsave(&ihost->scic_lock, flags);
 992
 993         if (tmr->cancel)
 994                 goto done;
 995
 996         scic->phy_startup_timer_pending = false;
 997
 998         do {
 999                 status = scic_sds_controller_start_next_phy(scic);
1000         } while (status != SCI_SUCCESS);
1001
1002 done:
1003         spin_unlock_irqrestore(&ihost->scic_lock, flags);
1004 }
1005
1006 static u16 isci_tci_active(struct isci_host *ihost)
1007 {
1008         return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
1009 }
1010
1011 static enum sci_status scic_controller_start(struct scic_sds_controller *scic,
1012                                              u32 timeout)
1013 {
1014         struct isci_host *ihost = scic_to_ihost(scic);
1015         enum sci_status result;
1016         u16 index;
1017
1018         if (scic->sm.current_state_id != SCIC_INITIALIZED) {
1019                 dev_warn(scic_to_dev(scic),
1020                          "SCIC Controller start operation requested in "
1021                          "invalid state\n");
1022                 return SCI_FAILURE_INVALID_STATE;
1023         }
1024
1025         /* Build the TCi free pool */
1026         BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8);
1027         ihost->tci_head = 0;
1028         ihost->tci_tail = 0;
1029         for (index = 0; index < scic->task_context_entries; index++)
1030                 isci_tci_free(ihost, index);
1031
1032         /* Build the RNi free pool */
1033         scic_sds_remote_node_table_initialize(
1034                         &scic->available_remote_nodes,
1035                         scic->remote_node_entries);
1036
1037         /*
1038          * Before anything else lets make sure we will not be
1039          * interrupted by the hardware.
1040          */
1041         scic_controller_disable_interrupts(scic);
1042
1043         /* Enable the port task scheduler */
1044         scic_sds_controller_enable_port_task_scheduler(scic);
1045
1046         /* Assign all the task entries to scic physical function */
1047         scic_sds_controller_assign_task_entries(scic);
1048
1049         /* Now initialize the completion queue */
1050         scic_sds_controller_initialize_completion_queue(scic);
1051
1052         /* Initialize the unsolicited frame queue for use */
1053         scic_sds_controller_initialize_unsolicited_frame_queue(scic);
1054
1055         /* Start all of the ports on this controller */
1056         for (index = 0; index < scic->logical_port_entries; index++) {
1057                 struct scic_sds_port *sci_port = &ihost->ports[index].sci;
1058
1059                 result = scic_sds_port_start(sci_port);
1060                 if (result)
1061                         return result;
1062         }
1063
1064         scic_sds_controller_start_next_phy(scic);
1065
1066         sci_mod_timer(&scic->timer, timeout);
1067
1068         sci_change_state(&scic->sm, SCIC_STARTING);
1069
1070         return SCI_SUCCESS;
1071 }
1072
1073 void isci_host_scan_start(struct Scsi_Host *shost)
1074 {
1075         struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
1076         unsigned long tmo = scic_controller_get_suggested_start_timeout(&ihost->sci);
1077
1078         set_bit(IHOST_START_PENDING, &ihost->flags);
1079
1080         spin_lock_irq(&ihost->scic_lock);
1081         scic_controller_start(&ihost->sci, tmo);
1082         scic_controller_enable_interrupts(&ihost->sci);
1083         spin_unlock_irq(&ihost->scic_lock);
1084 }
1085
1086 static void isci_host_stop_complete(struct isci_host *ihost, enum sci_status completion_status)
1087 {
1088         isci_host_change_state(ihost, isci_stopped);
1089         scic_controller_disable_interrupts(&ihost->sci);
1090         clear_bit(IHOST_STOP_PENDING, &ihost->flags);
1091         wake_up(&ihost->eventq);
1092 }
1093
1094 static void scic_sds_controller_completion_handler(struct scic_sds_controller *scic)
1095 {
1096         /* Empty out the completion queue */
1097         if (scic_sds_controller_completion_queue_has_entries(scic))
1098                 scic_sds_controller_process_completions(scic);
1099
1100         /* Clear the interrupt and enable all interrupts again */
1101         writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status);
1102         /* Could we write the value of SMU_ISR_COMPLETION? */
1103         writel(0xFF000000, &scic->smu_registers->interrupt_mask);
1104         writel(0, &scic->smu_registers->interrupt_mask);
1105 }
1106
1107 /**
1108  * isci_host_completion_routine() - This function is the delayed service
1109  *    routine that calls the sci core library's completion handler. It's
1110  *    scheduled as a tasklet from the interrupt service routine when interrupts
1111  *    in use, or set as the timeout function in polled mode.
1112  * @data: This parameter specifies the ISCI host object
1113  *
1114  */
1115 static void isci_host_completion_routine(unsigned long data)
1116 {
1117         struct isci_host *isci_host = (struct isci_host *)data;
1118         struct list_head    completed_request_list;
1119         struct list_head    errored_request_list;
1120         struct list_head    *current_position;
1121         struct list_head    *next_position;
1122         struct isci_request *request;
1123         struct isci_request *next_request;
1124         struct sas_task     *task;
1125
1126         INIT_LIST_HEAD(&completed_request_list);
1127         INIT_LIST_HEAD(&errored_request_list);
1128
1129         spin_lock_irq(&isci_host->scic_lock);
1130
1131         scic_sds_controller_completion_handler(&isci_host->sci);
1132
1133         /* Take the lists of completed I/Os from the host. */
1134
1135         list_splice_init(&isci_host->requests_to_complete,
1136                          &completed_request_list);
1137
1138         /* Take the list of errored I/Os from the host. */
1139         list_splice_init(&isci_host->requests_to_errorback,
1140                          &errored_request_list);
1141
1142         spin_unlock_irq(&isci_host->scic_lock);
1143
1144         /* Process any completions in the lists. */
1145         list_for_each_safe(current_position, next_position,
1146                            &completed_request_list) {
1147
1148                 request = list_entry(current_position, struct isci_request,
1149                                      completed_node);
1150                 task = isci_request_access_task(request);
1151
1152                 /* Normal notification (task_done) */
1153                 dev_dbg(&isci_host->pdev->dev,
1154                         "%s: Normal - request/task = %p/%p\n",
1155                         __func__,
1156                         request,
1157                         task);
1158
1159                 /* Return the task to libsas */
1160                 if (task != NULL) {
1161
1162                         task->lldd_task = NULL;
1163                         if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1164
1165                                 /* If the task is already in the abort path,
1166                                 * the task_done callback cannot be called.
1167                                 */
1168                                 task->task_done(task);
1169                         }
1170                 }
1171
1172                 spin_lock_irq(&isci_host->scic_lock);
1173                 isci_free_tag(isci_host, request->io_tag);
1174                 spin_unlock_irq(&isci_host->scic_lock);
1175         }
1176         list_for_each_entry_safe(request, next_request, &errored_request_list,
1177                                  completed_node) {
1178
1179                 task = isci_request_access_task(request);
1180
1181                 /* Use sas_task_abort */
1182                 dev_warn(&isci_host->pdev->dev,
1183                          "%s: Error - request/task = %p/%p\n",
1184                          __func__,
1185                          request,
1186                          task);
1187
1188                 if (task != NULL) {
1189
1190                         /* Put the task into the abort path if it's not there
1191                          * already.
1192                          */
1193                         if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED))
1194                                 sas_task_abort(task);
1195
1196                 } else {
1197                         /* This is a case where the request has completed with a
1198                          * status such that it needed further target servicing,
1199                          * but the sas_task reference has already been removed
1200                          * from the request.  Since it was errored, it was not
1201                          * being aborted, so there is nothing to do except free
1202                          * it.
1203                          */
1204
1205                         spin_lock_irq(&isci_host->scic_lock);
1206                         /* Remove the request from the remote device's list
1207                         * of pending requests.
1208                         */
1209                         list_del_init(&request->dev_node);
1210                         isci_free_tag(isci_host, request->io_tag);
1211                         spin_unlock_irq(&isci_host->scic_lock);
1212                 }
1213         }
1214
1215 }
1216
1217 /**
1218  * scic_controller_stop() - This method will stop an individual controller
1219  *    object.This method will invoke the associated user callback upon
1220  *    completion.  The completion callback is called when the following
1221  *    conditions are met: -# the method return status is SCI_SUCCESS. -# the
1222  *    controller has been quiesced. This method will ensure that all IO
1223  *    requests are quiesced, phys are stopped, and all additional operation by
1224  *    the hardware is halted.
1225  * @controller: the handle to the controller object to stop.
1226  * @timeout: This parameter specifies the number of milliseconds in which the
1227  *    stop operation should complete.
1228  *
1229  * The controller must be in the STARTED or STOPPED state. Indicate if the
1230  * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
1231  * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
1232  * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
1233  * controller is not either in the STARTED or STOPPED states.
1234  */
1235 static enum sci_status scic_controller_stop(struct scic_sds_controller *scic,
1236                                             u32 timeout)
1237 {
1238         if (scic->sm.current_state_id != SCIC_READY) {
1239                 dev_warn(scic_to_dev(scic),
1240                          "SCIC Controller stop operation requested in "
1241                          "invalid state\n");
1242                 return SCI_FAILURE_INVALID_STATE;
1243         }
1244
1245         sci_mod_timer(&scic->timer, timeout);
1246         sci_change_state(&scic->sm, SCIC_STOPPING);
1247         return SCI_SUCCESS;
1248 }
1249
1250 /**
1251  * scic_controller_reset() - This method will reset the supplied core
1252  *    controller regardless of the state of said controller.  This operation is
1253  *    considered destructive.  In other words, all current operations are wiped
1254  *    out.  No IO completions for outstanding devices occur.  Outstanding IO
1255  *    requests are not aborted or completed at the actual remote device.
1256  * @controller: the handle to the controller object to reset.
1257  *
1258  * Indicate if the controller reset method succeeded or failed in some way.
1259  * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
1260  * the controller reset operation is unable to complete.
1261  */
1262 static enum sci_status scic_controller_reset(struct scic_sds_controller *scic)
1263 {
1264         switch (scic->sm.current_state_id) {
1265         case SCIC_RESET:
1266         case SCIC_READY:
1267         case SCIC_STOPPED:
1268         case SCIC_FAILED:
1269                 /*
1270                  * The reset operation is not a graceful cleanup, just
1271                  * perform the state transition.
1272                  */
1273                 sci_change_state(&scic->sm, SCIC_RESETTING);
1274                 return SCI_SUCCESS;
1275         default:
1276                 dev_warn(scic_to_dev(scic),
1277                          "SCIC Controller reset operation requested in "
1278                          "invalid state\n");
1279                 return SCI_FAILURE_INVALID_STATE;
1280         }
1281 }
1282
1283 void isci_host_deinit(struct isci_host *ihost)
1284 {
1285         int i;
1286
1287         isci_host_change_state(ihost, isci_stopping);
1288         for (i = 0; i < SCI_MAX_PORTS; i++) {
1289                 struct isci_port *iport = &ihost->ports[i];
1290                 struct isci_remote_device *idev, *d;
1291
1292                 list_for_each_entry_safe(idev, d, &iport->remote_dev_list, node) {
1293                         if (test_bit(IDEV_ALLOCATED, &idev->flags))
1294                                 isci_remote_device_stop(ihost, idev);
1295                 }
1296         }
1297
1298         set_bit(IHOST_STOP_PENDING, &ihost->flags);
1299
1300         spin_lock_irq(&ihost->scic_lock);
1301         scic_controller_stop(&ihost->sci, SCIC_CONTROLLER_STOP_TIMEOUT);
1302         spin_unlock_irq(&ihost->scic_lock);
1303
1304         wait_for_stop(ihost);
1305         scic_controller_reset(&ihost->sci);
1306
1307         /* Cancel any/all outstanding port timers */
1308         for (i = 0; i < ihost->sci.logical_port_entries; i++) {
1309                 struct scic_sds_port *sci_port = &ihost->ports[i].sci;
1310                 del_timer_sync(&sci_port->timer.timer);
1311         }
1312
1313         /* Cancel any/all outstanding phy timers */
1314         for (i = 0; i < SCI_MAX_PHYS; i++) {
1315                 struct scic_sds_phy *sci_phy = &ihost->phys[i].sci;
1316                 del_timer_sync(&sci_phy->sata_timer.timer);
1317         }
1318
1319         del_timer_sync(&ihost->sci.port_agent.timer.timer);
1320
1321         del_timer_sync(&ihost->sci.power_control.timer.timer);
1322
1323         del_timer_sync(&ihost->sci.timer.timer);
1324
1325         del_timer_sync(&ihost->sci.phy_timer.timer);
1326 }
1327
1328 static void __iomem *scu_base(struct isci_host *isci_host)
1329 {
1330         struct pci_dev *pdev = isci_host->pdev;
1331         int id = isci_host->id;
1332
1333         return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id;
1334 }
1335
1336 static void __iomem *smu_base(struct isci_host *isci_host)
1337 {
1338         struct pci_dev *pdev = isci_host->pdev;
1339         int id = isci_host->id;
1340
1341         return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id;
1342 }
1343
1344 static void isci_user_parameters_get(
1345                 struct isci_host *isci_host,
1346                 union scic_user_parameters *scic_user_params)
1347 {
1348         struct scic_sds_user_parameters *u = &scic_user_params->sds1;
1349         int i;
1350
1351         for (i = 0; i < SCI_MAX_PHYS; i++) {
1352                 struct sci_phy_user_params *u_phy = &u->phys[i];
1353
1354                 u_phy->max_speed_generation = phy_gen;
1355
1356                 /* we are not exporting these for now */
1357                 u_phy->align_insertion_frequency = 0x7f;
1358                 u_phy->in_connection_align_insertion_frequency = 0xff;
1359                 u_phy->notify_enable_spin_up_insertion_frequency = 0x33;
1360         }
1361
1362         u->stp_inactivity_timeout = stp_inactive_to;
1363         u->ssp_inactivity_timeout = ssp_inactive_to;
1364         u->stp_max_occupancy_timeout = stp_max_occ_to;
1365         u->ssp_max_occupancy_timeout = ssp_max_occ_to;
1366         u->no_outbound_task_timeout = no_outbound_task_to;
1367         u->max_number_concurrent_device_spin_up = max_concurr_spinup;
1368 }
1369
1370 static void scic_sds_controller_initial_state_enter(struct sci_base_state_machine *sm)
1371 {
1372         struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm);
1373
1374         sci_change_state(&scic->sm, SCIC_RESET);
1375 }
1376
1377 static inline void scic_sds_controller_starting_state_exit(struct sci_base_state_machine *sm)
1378 {
1379         struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm);
1380
1381         sci_del_timer(&scic->timer);
1382 }
1383
1384 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
1385 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
1386 #define INTERRUPT_COALESCE_TIMEOUT_MAX_US                    2700000
1387 #define INTERRUPT_COALESCE_NUMBER_MAX                        256
1388 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN                7
1389 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX                28
1390
1391 /**
1392  * scic_controller_set_interrupt_coalescence() - This method allows the user to
1393  *    configure the interrupt coalescence.
1394  * @controller: This parameter represents the handle to the controller object
1395  *    for which its interrupt coalesce register is overridden.
1396  * @coalesce_number: Used to control the number of entries in the Completion
1397  *    Queue before an interrupt is generated. If the number of entries exceed
1398  *    this number, an interrupt will be generated. The valid range of the input
1399  *    is [0, 256]. A setting of 0 results in coalescing being disabled.
1400  * @coalesce_timeout: Timeout value in microseconds. The valid range of the
1401  *    input is [0, 2700000] . A setting of 0 is allowed and results in no
1402  *    interrupt coalescing timeout.
1403  *
1404  * Indicate if the user successfully set the interrupt coalesce parameters.
1405  * SCI_SUCCESS The user successfully updated the interrutp coalescence.
1406  * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
1407  */
1408 static enum sci_status scic_controller_set_interrupt_coalescence(
1409         struct scic_sds_controller *scic_controller,
1410         u32 coalesce_number,
1411         u32 coalesce_timeout)
1412 {
1413         u8 timeout_encode = 0;
1414         u32 min = 0;
1415         u32 max = 0;
1416
1417         /* Check if the input parameters fall in the range. */
1418         if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
1419                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1420
1421         /*
1422          *  Defined encoding for interrupt coalescing timeout:
1423          *              Value   Min      Max     Units
1424          *              -----   ---      ---     -----
1425          *              0       -        -       Disabled
1426          *              1       13.3     20.0    ns
1427          *              2       26.7     40.0
1428          *              3       53.3     80.0
1429          *              4       106.7    160.0
1430          *              5       213.3    320.0
1431          *              6       426.7    640.0
1432          *              7       853.3    1280.0
1433          *              8       1.7      2.6     us
1434          *              9       3.4      5.1
1435          *              10      6.8      10.2
1436          *              11      13.7     20.5
1437          *              12      27.3     41.0
1438          *              13      54.6     81.9
1439          *              14      109.2    163.8
1440          *              15      218.5    327.7
1441          *              16      436.9    655.4
1442          *              17      873.8    1310.7
1443          *              18      1.7      2.6     ms
1444          *              19      3.5      5.2
1445          *              20      7.0      10.5
1446          *              21      14.0     21.0
1447          *              22      28.0     41.9
1448          *              23      55.9     83.9
1449          *              24      111.8    167.8
1450          *              25      223.7    335.5
1451          *              26      447.4    671.1
1452          *              27      894.8    1342.2
1453          *              28      1.8      2.7     s
1454          *              Others Undefined */
1455
1456         /*
1457          * Use the table above to decide the encode of interrupt coalescing timeout
1458          * value for register writing. */
1459         if (coalesce_timeout == 0)
1460                 timeout_encode = 0;
1461         else{
1462                 /* make the timeout value in unit of (10 ns). */
1463                 coalesce_timeout = coalesce_timeout * 100;
1464                 min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
1465                 max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
1466
1467                 /* get the encode of timeout for register writing. */
1468                 for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
1469                       timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
1470                       timeout_encode++) {
1471                         if (min <= coalesce_timeout &&  max > coalesce_timeout)
1472                                 break;
1473                         else if (coalesce_timeout >= max && coalesce_timeout < min * 2
1474                                  && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
1475                                 if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
1476                                         break;
1477                                 else{
1478                                         timeout_encode++;
1479                                         break;
1480                                 }
1481                         } else {
1482                                 max = max * 2;
1483                                 min = min * 2;
1484                         }
1485                 }
1486
1487                 if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
1488                         /* the value is out of range. */
1489                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1490         }
1491
1492         writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
1493                SMU_ICC_GEN_VAL(TIMER, timeout_encode),
1494                &scic_controller->smu_registers->interrupt_coalesce_control);
1495
1496
1497         scic_controller->interrupt_coalesce_number = (u16)coalesce_number;
1498         scic_controller->interrupt_coalesce_timeout = coalesce_timeout / 100;
1499
1500         return SCI_SUCCESS;
1501 }
1502
1503
1504 static void scic_sds_controller_ready_state_enter(struct sci_base_state_machine *sm)
1505 {
1506         struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm);
1507
1508         /* set the default interrupt coalescence number and timeout value. */
1509         scic_controller_set_interrupt_coalescence(scic, 0x10, 250);
1510 }
1511
1512 static void scic_sds_controller_ready_state_exit(struct sci_base_state_machine *sm)
1513 {
1514         struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm);
1515
1516         /* disable interrupt coalescence. */
1517         scic_controller_set_interrupt_coalescence(scic, 0, 0);
1518 }
1519
1520 static enum sci_status scic_sds_controller_stop_phys(struct scic_sds_controller *scic)
1521 {
1522         u32 index;
1523         enum sci_status status;
1524         enum sci_status phy_status;
1525         struct isci_host *ihost = scic_to_ihost(scic);
1526
1527         status = SCI_SUCCESS;
1528
1529         for (index = 0; index < SCI_MAX_PHYS; index++) {
1530                 phy_status = scic_sds_phy_stop(&ihost->phys[index].sci);
1531
1532                 if (phy_status != SCI_SUCCESS &&
1533                     phy_status != SCI_FAILURE_INVALID_STATE) {
1534                         status = SCI_FAILURE;
1535
1536                         dev_warn(scic_to_dev(scic),
1537                                  "%s: Controller stop operation failed to stop "
1538                                  "phy %d because of status %d.\n",
1539                                  __func__,
1540                                  ihost->phys[index].sci.phy_index, phy_status);
1541                 }
1542         }
1543
1544         return status;
1545 }
1546
1547 static enum sci_status scic_sds_controller_stop_ports(struct scic_sds_controller *scic)
1548 {
1549         u32 index;
1550         enum sci_status port_status;
1551         enum sci_status status = SCI_SUCCESS;
1552         struct isci_host *ihost = scic_to_ihost(scic);
1553
1554         for (index = 0; index < scic->logical_port_entries; index++) {
1555                 struct scic_sds_port *sci_port = &ihost->ports[index].sci;
1556
1557                 port_status = scic_sds_port_stop(sci_port);
1558
1559                 if ((port_status != SCI_SUCCESS) &&
1560                     (port_status != SCI_FAILURE_INVALID_STATE)) {
1561                         status = SCI_FAILURE;
1562
1563                         dev_warn(scic_to_dev(scic),
1564                                  "%s: Controller stop operation failed to "
1565                                  "stop port %d because of status %d.\n",
1566                                  __func__,
1567                                  sci_port->logical_port_index,
1568                                  port_status);
1569                 }
1570         }
1571
1572         return status;
1573 }
1574
1575 static enum sci_status scic_sds_controller_stop_devices(struct scic_sds_controller *scic)
1576 {
1577         u32 index;
1578         enum sci_status status;
1579         enum sci_status device_status;
1580
1581         status = SCI_SUCCESS;
1582
1583         for (index = 0; index < scic->remote_node_entries; index++) {
1584                 if (scic->device_table[index] != NULL) {
1585                         /* / @todo What timeout value do we want to provide to this request? */
1586                         device_status = scic_remote_device_stop(scic->device_table[index], 0);
1587
1588                         if ((device_status != SCI_SUCCESS) &&
1589                             (device_status != SCI_FAILURE_INVALID_STATE)) {
1590                                 dev_warn(scic_to_dev(scic),
1591                                          "%s: Controller stop operation failed "
1592                                          "to stop device 0x%p because of "
1593                                          "status %d.\n",
1594                                          __func__,
1595                                          scic->device_table[index], device_status);
1596                         }
1597                 }
1598         }
1599
1600         return status;
1601 }
1602
1603 static void scic_sds_controller_stopping_state_enter(struct sci_base_state_machine *sm)
1604 {
1605         struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm);
1606
1607         /* Stop all of the components for this controller */
1608         scic_sds_controller_stop_phys(scic);
1609         scic_sds_controller_stop_ports(scic);
1610         scic_sds_controller_stop_devices(scic);
1611 }
1612
1613 static void scic_sds_controller_stopping_state_exit(struct sci_base_state_machine *sm)
1614 {
1615         struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm);
1616
1617         sci_del_timer(&scic->timer);
1618 }
1619
1620
1621 /**
1622  * scic_sds_controller_reset_hardware() -
1623  *
1624  * This method will reset the controller hardware.
1625  */
1626 static void scic_sds_controller_reset_hardware(struct scic_sds_controller *scic)
1627 {
1628         /* Disable interrupts so we dont take any spurious interrupts */
1629         scic_controller_disable_interrupts(scic);
1630
1631         /* Reset the SCU */
1632         writel(0xFFFFFFFF, &scic->smu_registers->soft_reset_control);
1633
1634         /* Delay for 1ms to before clearing the CQP and UFQPR. */
1635         udelay(1000);
1636
1637         /* The write to the CQGR clears the CQP */
1638         writel(0x00000000, &scic->smu_registers->completion_queue_get);
1639
1640         /* The write to the UFQGP clears the UFQPR */
1641         writel(0, &scic->scu_registers->sdma.unsolicited_frame_get_pointer);
1642 }
1643
1644 static void scic_sds_controller_resetting_state_enter(struct sci_base_state_machine *sm)
1645 {
1646         struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm);
1647
1648         scic_sds_controller_reset_hardware(scic);
1649         sci_change_state(&scic->sm, SCIC_RESET);
1650 }
1651
1652 static const struct sci_base_state scic_sds_controller_state_table[] = {
1653         [SCIC_INITIAL] = {
1654                 .enter_state = scic_sds_controller_initial_state_enter,
1655         },
1656         [SCIC_RESET] = {},
1657         [SCIC_INITIALIZING] = {},
1658         [SCIC_INITIALIZED] = {},
1659         [SCIC_STARTING] = {
1660                 .exit_state  = scic_sds_controller_starting_state_exit,
1661         },
1662         [SCIC_READY] = {
1663                 .enter_state = scic_sds_controller_ready_state_enter,
1664                 .exit_state  = scic_sds_controller_ready_state_exit,
1665         },
1666         [SCIC_RESETTING] = {
1667                 .enter_state = scic_sds_controller_resetting_state_enter,
1668         },
1669         [SCIC_STOPPING] = {
1670                 .enter_state = scic_sds_controller_stopping_state_enter,
1671                 .exit_state = scic_sds_controller_stopping_state_exit,
1672         },
1673         [SCIC_STOPPED] = {},
1674         [SCIC_FAILED] = {}
1675 };
1676
1677 static void scic_sds_controller_set_default_config_parameters(struct scic_sds_controller *scic)
1678 {
1679         /* these defaults are overridden by the platform / firmware */
1680         struct isci_host *ihost = scic_to_ihost(scic);
1681         u16 index;
1682
1683         /* Default to APC mode. */
1684         scic->oem_parameters.sds1.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
1685
1686         /* Default to APC mode. */
1687         scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up = 1;
1688
1689         /* Default to no SSC operation. */
1690         scic->oem_parameters.sds1.controller.do_enable_ssc = false;
1691
1692         /* Initialize all of the port parameter information to narrow ports. */
1693         for (index = 0; index < SCI_MAX_PORTS; index++) {
1694                 scic->oem_parameters.sds1.ports[index].phy_mask = 0;
1695         }
1696
1697         /* Initialize all of the phy parameter information. */
1698         for (index = 0; index < SCI_MAX_PHYS; index++) {
1699                 /* Default to 6G (i.e. Gen 3) for now. */
1700                 scic->user_parameters.sds1.phys[index].max_speed_generation = 3;
1701
1702                 /* the frequencies cannot be 0 */
1703                 scic->user_parameters.sds1.phys[index].align_insertion_frequency = 0x7f;
1704                 scic->user_parameters.sds1.phys[index].in_connection_align_insertion_frequency = 0xff;
1705                 scic->user_parameters.sds1.phys[index].notify_enable_spin_up_insertion_frequency = 0x33;
1706
1707                 /*
1708                  * Previous Vitesse based expanders had a arbitration issue that
1709                  * is worked around by having the upper 32-bits of SAS address
1710                  * with a value greater then the Vitesse company identifier.
1711                  * Hence, usage of 0x5FCFFFFF. */
1712                 scic->oem_parameters.sds1.phys[index].sas_address.low = 0x1 + ihost->id;
1713                 scic->oem_parameters.sds1.phys[index].sas_address.high = 0x5FCFFFFF;
1714         }
1715
1716         scic->user_parameters.sds1.stp_inactivity_timeout = 5;
1717         scic->user_parameters.sds1.ssp_inactivity_timeout = 5;
1718         scic->user_parameters.sds1.stp_max_occupancy_timeout = 5;
1719         scic->user_parameters.sds1.ssp_max_occupancy_timeout = 20;
1720         scic->user_parameters.sds1.no_outbound_task_timeout = 20;
1721 }
1722
1723 static void controller_timeout(unsigned long data)
1724 {
1725         struct sci_timer *tmr = (struct sci_timer *)data;
1726         struct scic_sds_controller *scic = container_of(tmr, typeof(*scic), timer);
1727         struct isci_host *ihost = scic_to_ihost(scic);
1728         struct sci_base_state_machine *sm = &scic->sm;
1729         unsigned long flags;
1730
1731         spin_lock_irqsave(&ihost->scic_lock, flags);
1732
1733         if (tmr->cancel)
1734                 goto done;
1735
1736         if (sm->current_state_id == SCIC_STARTING)
1737                 scic_sds_controller_transition_to_ready(scic, SCI_FAILURE_TIMEOUT);
1738         else if (sm->current_state_id == SCIC_STOPPING) {
1739                 sci_change_state(sm, SCIC_FAILED);
1740                 isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT);
1741         } else  /* / @todo Now what do we want to do in this case? */
1742                 dev_err(scic_to_dev(scic),
1743                         "%s: Controller timer fired when controller was not "
1744                         "in a state being timed.\n",
1745                         __func__);
1746
1747 done:
1748         spin_unlock_irqrestore(&ihost->scic_lock, flags);
1749 }
1750
1751 /**
1752  * scic_controller_construct() - This method will attempt to construct a
1753  *    controller object utilizing the supplied parameter information.
1754  * @c: This parameter specifies the controller to be constructed.
1755  * @scu_base: mapped base address of the scu registers
1756  * @smu_base: mapped base address of the smu registers
1757  *
1758  * Indicate if the controller was successfully constructed or if it failed in
1759  * some way. SCI_SUCCESS This value is returned if the controller was
1760  * successfully constructed. SCI_WARNING_TIMER_CONFLICT This value is returned
1761  * if the interrupt coalescence timer may cause SAS compliance issues for SMP
1762  * Target mode response processing. SCI_FAILURE_UNSUPPORTED_CONTROLLER_TYPE
1763  * This value is returned if the controller does not support the supplied type.
1764  * SCI_FAILURE_UNSUPPORTED_INIT_DATA_VERSION This value is returned if the
1765  * controller does not support the supplied initialization data version.
1766  */
1767 static enum sci_status scic_controller_construct(struct scic_sds_controller *scic,
1768                                           void __iomem *scu_base,
1769                                           void __iomem *smu_base)
1770 {
1771         struct isci_host *ihost = scic_to_ihost(scic);
1772         u8 i;
1773
1774         sci_init_sm(&scic->sm, scic_sds_controller_state_table, SCIC_INITIAL);
1775
1776         scic->scu_registers = scu_base;
1777         scic->smu_registers = smu_base;
1778
1779         scic_sds_port_configuration_agent_construct(&scic->port_agent);
1780
1781         /* Construct the ports for this controller */
1782         for (i = 0; i < SCI_MAX_PORTS; i++)
1783                 scic_sds_port_construct(&ihost->ports[i].sci, i, scic);
1784         scic_sds_port_construct(&ihost->ports[i].sci, SCIC_SDS_DUMMY_PORT, scic);
1785
1786         /* Construct the phys for this controller */
1787         for (i = 0; i < SCI_MAX_PHYS; i++) {
1788                 /* Add all the PHYs to the dummy port */
1789                 scic_sds_phy_construct(&ihost->phys[i].sci,
1790                                        &ihost->ports[SCI_MAX_PORTS].sci, i);
1791         }
1792
1793         scic->invalid_phy_mask = 0;
1794
1795         sci_init_timer(&scic->timer, controller_timeout);
1796
1797         /* Initialize the User and OEM parameters to default values. */
1798         scic_sds_controller_set_default_config_parameters(scic);
1799
1800         return scic_controller_reset(scic);
1801 }
1802
1803 int scic_oem_parameters_validate(struct scic_sds_oem_params *oem)
1804 {
1805         int i;
1806
1807         for (i = 0; i < SCI_MAX_PORTS; i++)
1808                 if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX)
1809                         return -EINVAL;
1810
1811         for (i = 0; i < SCI_MAX_PHYS; i++)
1812                 if (oem->phys[i].sas_address.high == 0 &&
1813                     oem->phys[i].sas_address.low == 0)
1814                         return -EINVAL;
1815
1816         if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) {
1817                 for (i = 0; i < SCI_MAX_PHYS; i++)
1818                         if (oem->ports[i].phy_mask != 0)
1819                                 return -EINVAL;
1820         } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
1821                 u8 phy_mask = 0;
1822
1823                 for (i = 0; i < SCI_MAX_PHYS; i++)
1824                         phy_mask |= oem->ports[i].phy_mask;
1825
1826                 if (phy_mask == 0)
1827                         return -EINVAL;
1828         } else
1829                 return -EINVAL;
1830
1831         if (oem->controller.max_concurrent_dev_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT)
1832                 return -EINVAL;
1833
1834         return 0;
1835 }
1836
1837 static enum sci_status scic_oem_parameters_set(struct scic_sds_controller *scic,
1838                                         union scic_oem_parameters *scic_parms)
1839 {
1840         u32 state = scic->sm.current_state_id;
1841
1842         if (state == SCIC_RESET ||
1843             state == SCIC_INITIALIZING ||
1844             state == SCIC_INITIALIZED) {
1845
1846                 if (scic_oem_parameters_validate(&scic_parms->sds1))
1847                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1848                 scic->oem_parameters.sds1 = scic_parms->sds1;
1849
1850                 return SCI_SUCCESS;
1851         }
1852
1853         return SCI_FAILURE_INVALID_STATE;
1854 }
1855
1856 void scic_oem_parameters_get(
1857         struct scic_sds_controller *scic,
1858         union scic_oem_parameters *scic_parms)
1859 {
1860         memcpy(scic_parms, (&scic->oem_parameters), sizeof(*scic_parms));
1861 }
1862
1863 static void power_control_timeout(unsigned long data)
1864 {
1865         struct sci_timer *tmr = (struct sci_timer *)data;
1866         struct scic_sds_controller *scic = container_of(tmr, typeof(*scic), power_control.timer);
1867         struct isci_host *ihost = scic_to_ihost(scic);
1868         struct scic_sds_phy *sci_phy;
1869         unsigned long flags;
1870         u8 i;
1871
1872         spin_lock_irqsave(&ihost->scic_lock, flags);
1873
1874         if (tmr->cancel)
1875                 goto done;
1876
1877         scic->power_control.phys_granted_power = 0;
1878
1879         if (scic->power_control.phys_waiting == 0) {
1880                 scic->power_control.timer_started = false;
1881                 goto done;
1882         }
1883
1884         for (i = 0; i < SCI_MAX_PHYS; i++) {
1885
1886                 if (scic->power_control.phys_waiting == 0)
1887                         break;
1888
1889                 sci_phy = scic->power_control.requesters[i];
1890                 if (sci_phy == NULL)
1891                         continue;
1892
1893                 if (scic->power_control.phys_granted_power >=
1894                     scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up)
1895                         break;
1896
1897                 scic->power_control.requesters[i] = NULL;
1898                 scic->power_control.phys_waiting--;
1899                 scic->power_control.phys_granted_power++;
1900                 scic_sds_phy_consume_power_handler(sci_phy);
1901         }
1902
1903         /*
1904          * It doesn't matter if the power list is empty, we need to start the
1905          * timer in case another phy becomes ready.
1906          */
1907         sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1908         scic->power_control.timer_started = true;
1909
1910 done:
1911         spin_unlock_irqrestore(&ihost->scic_lock, flags);
1912 }
1913
1914 /**
1915  * This method inserts the phy in the stagger spinup control queue.
1916  * @scic:
1917  *
1918  *
1919  */
1920 void scic_sds_controller_power_control_queue_insert(
1921         struct scic_sds_controller *scic,
1922         struct scic_sds_phy *sci_phy)
1923 {
1924         BUG_ON(sci_phy == NULL);
1925
1926         if (scic->power_control.phys_granted_power <
1927             scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up) {
1928                 scic->power_control.phys_granted_power++;
1929                 scic_sds_phy_consume_power_handler(sci_phy);
1930
1931                 /*
1932                  * stop and start the power_control timer. When the timer fires, the
1933                  * no_of_phys_granted_power will be set to 0
1934                  */
1935                 if (scic->power_control.timer_started)
1936                         sci_del_timer(&scic->power_control.timer);
1937
1938                 sci_mod_timer(&scic->power_control.timer,
1939                                  SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1940                 scic->power_control.timer_started = true;
1941
1942         } else {
1943                 /* Add the phy in the waiting list */
1944                 scic->power_control.requesters[sci_phy->phy_index] = sci_phy;
1945                 scic->power_control.phys_waiting++;
1946         }
1947 }
1948
1949 /**
1950  * This method removes the phy from the stagger spinup control queue.
1951  * @scic:
1952  *
1953  *
1954  */
1955 void scic_sds_controller_power_control_queue_remove(
1956         struct scic_sds_controller *scic,
1957         struct scic_sds_phy *sci_phy)
1958 {
1959         BUG_ON(sci_phy == NULL);
1960
1961         if (scic->power_control.requesters[sci_phy->phy_index] != NULL) {
1962                 scic->power_control.phys_waiting--;
1963         }
1964
1965         scic->power_control.requesters[sci_phy->phy_index] = NULL;
1966 }
1967
1968 #define AFE_REGISTER_WRITE_DELAY 10
1969
1970 /* Initialize the AFE for this phy index. We need to read the AFE setup from
1971  * the OEM parameters
1972  */
1973 static void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic)
1974 {
1975         const struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1;
1976         u32 afe_status;
1977         u32 phy_id;
1978
1979         /* Clear DFX Status registers */
1980         writel(0x0081000f, &scic->scu_registers->afe.afe_dfx_master_control0);
1981         udelay(AFE_REGISTER_WRITE_DELAY);
1982
1983         if (is_b0()) {
1984                 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
1985                  * Timer, PM Stagger Timer */
1986                 writel(0x0007BFFF, &scic->scu_registers->afe.afe_pmsn_master_control2);
1987                 udelay(AFE_REGISTER_WRITE_DELAY);
1988         }
1989
1990         /* Configure bias currents to normal */
1991         if (is_a0())
1992                 writel(0x00005500, &scic->scu_registers->afe.afe_bias_control);
1993         else if (is_a2())
1994                 writel(0x00005A00, &scic->scu_registers->afe.afe_bias_control);
1995         else if (is_b0() || is_c0())
1996                 writel(0x00005F00, &scic->scu_registers->afe.afe_bias_control);
1997
1998         udelay(AFE_REGISTER_WRITE_DELAY);
1999
2000         /* Enable PLL */
2001         if (is_b0() || is_c0())
2002                 writel(0x80040A08, &scic->scu_registers->afe.afe_pll_control0);
2003         else
2004                 writel(0x80040908, &scic->scu_registers->afe.afe_pll_control0);
2005
2006         udelay(AFE_REGISTER_WRITE_DELAY);
2007
2008         /* Wait for the PLL to lock */
2009         do {
2010                 afe_status = readl(&scic->scu_registers->afe.afe_common_block_status);
2011                 udelay(AFE_REGISTER_WRITE_DELAY);
2012         } while ((afe_status & 0x00001000) == 0);
2013
2014         if (is_a0() || is_a2()) {
2015                 /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */
2016                 writel(0x7bcc96ad, &scic->scu_registers->afe.afe_pmsn_master_control0);
2017                 udelay(AFE_REGISTER_WRITE_DELAY);
2018         }
2019
2020         for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
2021                 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
2022
2023                 if (is_b0()) {
2024                          /* Configure transmitter SSC parameters */
2025                         writel(0x00030000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
2026                         udelay(AFE_REGISTER_WRITE_DELAY);
2027                 } else if (is_c0()) {
2028                          /* Configure transmitter SSC parameters */
2029                         writel(0x0003000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
2030                         udelay(AFE_REGISTER_WRITE_DELAY);
2031
2032                         /*
2033                          * All defaults, except the Receive Word Alignament/Comma Detect
2034                          * Enable....(0xe800) */
2035                         writel(0x00004500, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
2036                         udelay(AFE_REGISTER_WRITE_DELAY);
2037                 } else {
2038                         /*
2039                          * All defaults, except the Receive Word Alignament/Comma Detect
2040                          * Enable....(0xe800) */
2041                         writel(0x00004512, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
2042                         udelay(AFE_REGISTER_WRITE_DELAY);
2043
2044                         writel(0x0050100F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control1);
2045                         udelay(AFE_REGISTER_WRITE_DELAY);
2046                 }
2047
2048                 /*
2049                  * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
2050                  * & increase TX int & ext bias 20%....(0xe85c) */
2051                 if (is_a0())
2052                         writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2053                 else if (is_a2())
2054                         writel(0x000003F0, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2055                 else if (is_b0()) {
2056                          /* Power down TX and RX (PWRDNTX and PWRDNRX) */
2057                         writel(0x000003D7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2058                         udelay(AFE_REGISTER_WRITE_DELAY);
2059
2060                         /*
2061                          * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
2062                          * & increase TX int & ext bias 20%....(0xe85c) */
2063                         writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2064                 } else {
2065                         writel(0x000001E7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2066                         udelay(AFE_REGISTER_WRITE_DELAY);
2067
2068                         /*
2069                          * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
2070                          * & increase TX int & ext bias 20%....(0xe85c) */
2071                         writel(0x000001E4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2072                 }
2073                 udelay(AFE_REGISTER_WRITE_DELAY);
2074
2075                 if (is_a0() || is_a2()) {
2076                         /* Enable TX equalization (0xe824) */
2077                         writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2078                         udelay(AFE_REGISTER_WRITE_DELAY);
2079                 }
2080
2081                 /*
2082                  * RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On),
2083                  * RDD=0x0(RX Detect Enabled) ....(0xe800) */
2084                 writel(0x00004100, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
2085                 udelay(AFE_REGISTER_WRITE_DELAY);
2086
2087                 /* Leave DFE/FFE on */
2088                 if (is_a0())
2089                         writel(0x3F09983F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2090                 else if (is_a2())
2091                         writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2092                 else if (is_b0()) {
2093                         writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2094                         udelay(AFE_REGISTER_WRITE_DELAY);
2095                         /* Enable TX equalization (0xe824) */
2096                         writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2097                 } else {
2098                         writel(0x0140DF0F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control1);
2099                         udelay(AFE_REGISTER_WRITE_DELAY);
2100
2101                         writel(0x3F6F103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2102                         udelay(AFE_REGISTER_WRITE_DELAY);
2103
2104                         /* Enable TX equalization (0xe824) */
2105                         writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2106                 }
2107
2108                 udelay(AFE_REGISTER_WRITE_DELAY);
2109
2110                 writel(oem_phy->afe_tx_amp_control0,
2111                         &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control0);
2112                 udelay(AFE_REGISTER_WRITE_DELAY);
2113
2114                 writel(oem_phy->afe_tx_amp_control1,
2115                         &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control1);
2116                 udelay(AFE_REGISTER_WRITE_DELAY);
2117
2118                 writel(oem_phy->afe_tx_amp_control2,
2119                         &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control2);
2120                 udelay(AFE_REGISTER_WRITE_DELAY);
2121
2122                 writel(oem_phy->afe_tx_amp_control3,
2123                         &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control3);
2124                 udelay(AFE_REGISTER_WRITE_DELAY);
2125         }
2126
2127         /* Transfer control to the PEs */
2128         writel(0x00010f00, &scic->scu_registers->afe.afe_dfx_master_control0);
2129         udelay(AFE_REGISTER_WRITE_DELAY);
2130 }
2131
2132 static void scic_sds_controller_initialize_power_control(struct scic_sds_controller *scic)
2133 {
2134         sci_init_timer(&scic->power_control.timer, power_control_timeout);
2135
2136         memset(scic->power_control.requesters, 0,
2137                sizeof(scic->power_control.requesters));
2138
2139         scic->power_control.phys_waiting = 0;
2140         scic->power_control.phys_granted_power = 0;
2141 }
2142
2143 static enum sci_status scic_controller_initialize(struct scic_sds_controller *scic)
2144 {
2145         struct sci_base_state_machine *sm = &scic->sm;
2146         struct isci_host *ihost = scic_to_ihost(scic);
2147         enum sci_status result = SCI_FAILURE;
2148         unsigned long i, state, val;
2149
2150         if (scic->sm.current_state_id != SCIC_RESET) {
2151                 dev_warn(scic_to_dev(scic),
2152                          "SCIC Controller initialize operation requested "
2153                          "in invalid state\n");
2154                 return SCI_FAILURE_INVALID_STATE;
2155         }
2156
2157         sci_change_state(sm, SCIC_INITIALIZING);
2158
2159         sci_init_timer(&scic->phy_timer, phy_startup_timeout);
2160
2161         scic->next_phy_to_start = 0;
2162         scic->phy_startup_timer_pending = false;
2163
2164         scic_sds_controller_initialize_power_control(scic);
2165
2166         /*
2167          * There is nothing to do here for B0 since we do not have to
2168          * program the AFE registers.
2169          * / @todo The AFE settings are supposed to be correct for the B0 but
2170          * /       presently they seem to be wrong. */
2171         scic_sds_controller_afe_initialization(scic);
2172
2173
2174         /* Take the hardware out of reset */
2175         writel(0, &scic->smu_registers->soft_reset_control);
2176
2177         /*
2178          * / @todo Provide meaningfull error code for hardware failure
2179          * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
2180         for (i = 100; i >= 1; i--) {
2181                 u32 status;
2182
2183                 /* Loop until the hardware reports success */
2184                 udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
2185                 status = readl(&scic->smu_registers->control_status);
2186
2187                 if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED)
2188                         break;
2189         }
2190         if (i == 0)
2191                 goto out;
2192
2193         /*
2194          * Determine what are the actaul device capacities that the
2195          * hardware will support */
2196         val = readl(&scic->smu_registers->device_context_capacity);
2197
2198         /* Record the smaller of the two capacity values */
2199         scic->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS);
2200         scic->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS);
2201         scic->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES);
2202
2203         /*
2204          * Make all PEs that are unassigned match up with the
2205          * logical ports
2206          */
2207         for (i = 0; i < scic->logical_port_entries; i++) {
2208                 struct scu_port_task_scheduler_group_registers __iomem
2209                         *ptsg = &scic->scu_registers->peg0.ptsg;
2210
2211                 writel(i, &ptsg->protocol_engine[i]);
2212         }
2213
2214         /* Initialize hardware PCI Relaxed ordering in DMA engines */
2215         val = readl(&scic->scu_registers->sdma.pdma_configuration);
2216         val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2217         writel(val, &scic->scu_registers->sdma.pdma_configuration);
2218
2219         val = readl(&scic->scu_registers->sdma.cdma_configuration);
2220         val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2221         writel(val, &scic->scu_registers->sdma.cdma_configuration);
2222
2223         /*
2224          * Initialize the PHYs before the PORTs because the PHY registers
2225          * are accessed during the port initialization.
2226          */
2227         for (i = 0; i < SCI_MAX_PHYS; i++) {
2228                 result = scic_sds_phy_initialize(&ihost->phys[i].sci,
2229                                                  &scic->scu_registers->peg0.pe[i].tl,
2230                                                  &scic->scu_registers->peg0.pe[i].ll);
2231                 if (result != SCI_SUCCESS)
2232                         goto out;
2233         }
2234
2235         for (i = 0; i < scic->logical_port_entries; i++) {
2236                 result = scic_sds_port_initialize(&ihost->ports[i].sci,
2237                                                   &scic->scu_registers->peg0.ptsg.port[i],
2238                                                   &scic->scu_registers->peg0.ptsg.protocol_engine,
2239                                                   &scic->scu_registers->peg0.viit[i]);
2240
2241                 if (result != SCI_SUCCESS)
2242                         goto out;
2243         }
2244
2245         result = scic_sds_port_configuration_agent_initialize(scic, &scic->port_agent);
2246
2247  out:
2248         /* Advance the controller state machine */
2249         if (result == SCI_SUCCESS)
2250                 state = SCIC_INITIALIZED;
2251         else
2252                 state = SCIC_FAILED;
2253         sci_change_state(sm, state);
2254
2255         return result;
2256 }
2257
2258 static enum sci_status scic_user_parameters_set(
2259         struct scic_sds_controller *scic,
2260         union scic_user_parameters *scic_parms)
2261 {
2262         u32 state = scic->sm.current_state_id;
2263
2264         if (state == SCIC_RESET ||
2265             state == SCIC_INITIALIZING ||
2266             state == SCIC_INITIALIZED) {
2267                 u16 index;
2268
2269                 /*
2270                  * Validate the user parameters.  If they are not legal, then
2271                  * return a failure.
2272                  */
2273                 for (index = 0; index < SCI_MAX_PHYS; index++) {
2274                         struct sci_phy_user_params *user_phy;
2275
2276                         user_phy = &scic_parms->sds1.phys[index];
2277
2278                         if (!((user_phy->max_speed_generation <=
2279                                                 SCIC_SDS_PARM_MAX_SPEED) &&
2280                               (user_phy->max_speed_generation >
2281                                                 SCIC_SDS_PARM_NO_SPEED)))
2282                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2283
2284                         if (user_phy->in_connection_align_insertion_frequency <
2285                                         3)
2286                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2287
2288                         if ((user_phy->in_connection_align_insertion_frequency <
2289                                                 3) ||
2290                             (user_phy->align_insertion_frequency == 0) ||
2291                             (user_phy->
2292                                 notify_enable_spin_up_insertion_frequency ==
2293                                                 0))
2294                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2295                 }
2296
2297                 if ((scic_parms->sds1.stp_inactivity_timeout == 0) ||
2298                     (scic_parms->sds1.ssp_inactivity_timeout == 0) ||
2299                     (scic_parms->sds1.stp_max_occupancy_timeout == 0) ||
2300                     (scic_parms->sds1.ssp_max_occupancy_timeout == 0) ||
2301                     (scic_parms->sds1.no_outbound_task_timeout == 0))
2302                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2303
2304                 memcpy(&scic->user_parameters, scic_parms, sizeof(*scic_parms));
2305
2306                 return SCI_SUCCESS;
2307         }
2308
2309         return SCI_FAILURE_INVALID_STATE;
2310 }
2311
2312 static int scic_controller_mem_init(struct scic_sds_controller *scic)
2313 {
2314         struct device *dev = scic_to_dev(scic);
2315         dma_addr_t dma;
2316         size_t size;
2317         int err;
2318
2319         size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32);
2320         scic->completion_queue = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL);
2321         if (!scic->completion_queue)
2322                 return -ENOMEM;
2323
2324         writel(lower_32_bits(dma), &scic->smu_registers->completion_queue_lower);
2325         writel(upper_32_bits(dma), &scic->smu_registers->completion_queue_upper);
2326
2327         size = scic->remote_node_entries * sizeof(union scu_remote_node_context);
2328         scic->remote_node_context_table = dmam_alloc_coherent(dev, size, &dma,
2329                                                               GFP_KERNEL);
2330         if (!scic->remote_node_context_table)
2331                 return -ENOMEM;
2332
2333         writel(lower_32_bits(dma), &scic->smu_registers->remote_node_context_lower);
2334         writel(upper_32_bits(dma), &scic->smu_registers->remote_node_context_upper);
2335
2336         size = scic->task_context_entries * sizeof(struct scu_task_context),
2337         scic->task_context_table = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL);
2338         if (!scic->task_context_table)
2339                 return -ENOMEM;
2340
2341         scic->task_context_dma = dma;
2342         writel(lower_32_bits(dma), &scic->smu_registers->host_task_table_lower);
2343         writel(upper_32_bits(dma), &scic->smu_registers->host_task_table_upper);
2344
2345         err = scic_sds_unsolicited_frame_control_construct(scic);
2346         if (err)
2347                 return err;
2348
2349         /*
2350          * Inform the silicon as to the location of the UF headers and
2351          * address table.
2352          */
2353         writel(lower_32_bits(scic->uf_control.headers.physical_address),
2354                 &scic->scu_registers->sdma.uf_header_base_address_lower);
2355         writel(upper_32_bits(scic->uf_control.headers.physical_address),
2356                 &scic->scu_registers->sdma.uf_header_base_address_upper);
2357
2358         writel(lower_32_bits(scic->uf_control.address_table.physical_address),
2359                 &scic->scu_registers->sdma.uf_address_table_lower);
2360         writel(upper_32_bits(scic->uf_control.address_table.physical_address),
2361                 &scic->scu_registers->sdma.uf_address_table_upper);
2362
2363         return 0;
2364 }
2365
2366 int isci_host_init(struct isci_host *isci_host)
2367 {
2368         int err = 0, i;
2369         enum sci_status status;
2370         union scic_oem_parameters oem;
2371         union scic_user_parameters scic_user_params;
2372         struct isci_pci_info *pci_info = to_pci_info(isci_host->pdev);
2373
2374         spin_lock_init(&isci_host->state_lock);
2375         spin_lock_init(&isci_host->scic_lock);
2376         init_waitqueue_head(&isci_host->eventq);
2377
2378         isci_host_change_state(isci_host, isci_starting);
2379
2380         status = scic_controller_construct(&isci_host->sci, scu_base(isci_host),
2381                                            smu_base(isci_host));
2382
2383         if (status != SCI_SUCCESS) {
2384                 dev_err(&isci_host->pdev->dev,
2385                         "%s: scic_controller_construct failed - status = %x\n",
2386                         __func__,
2387                         status);
2388                 return -ENODEV;
2389         }
2390
2391         isci_host->sas_ha.dev = &isci_host->pdev->dev;
2392         isci_host->sas_ha.lldd_ha = isci_host;
2393
2394         /*
2395          * grab initial values stored in the controller object for OEM and USER
2396          * parameters
2397          */
2398         isci_user_parameters_get(isci_host, &scic_user_params);
2399         status = scic_user_parameters_set(&isci_host->sci,
2400                                           &scic_user_params);
2401         if (status != SCI_SUCCESS) {
2402                 dev_warn(&isci_host->pdev->dev,
2403                          "%s: scic_user_parameters_set failed\n",
2404                          __func__);
2405                 return -ENODEV;
2406         }
2407
2408         scic_oem_parameters_get(&isci_host->sci, &oem);
2409
2410         /* grab any OEM parameters specified in orom */
2411         if (pci_info->orom) {
2412                 status = isci_parse_oem_parameters(&oem,
2413                                                    pci_info->orom,
2414                                                    isci_host->id);
2415                 if (status != SCI_SUCCESS) {
2416                         dev_warn(&isci_host->pdev->dev,
2417                                  "parsing firmware oem parameters failed\n");
2418                         return -EINVAL;
2419                 }
2420         }
2421
2422         status = scic_oem_parameters_set(&isci_host->sci, &oem);
2423         if (status != SCI_SUCCESS) {
2424                 dev_warn(&isci_host->pdev->dev,
2425                                 "%s: scic_oem_parameters_set failed\n",
2426                                 __func__);
2427                 return -ENODEV;
2428         }
2429
2430         tasklet_init(&isci_host->completion_tasklet,
2431                      isci_host_completion_routine, (unsigned long)isci_host);
2432
2433         INIT_LIST_HEAD(&isci_host->requests_to_complete);
2434         INIT_LIST_HEAD(&isci_host->requests_to_errorback);
2435
2436         spin_lock_irq(&isci_host->scic_lock);
2437         status = scic_controller_initialize(&isci_host->sci);
2438         spin_unlock_irq(&isci_host->scic_lock);
2439         if (status != SCI_SUCCESS) {
2440                 dev_warn(&isci_host->pdev->dev,
2441                          "%s: scic_controller_initialize failed -"
2442                          " status = 0x%x\n",
2443                          __func__, status);
2444                 return -ENODEV;
2445         }
2446
2447         err = scic_controller_mem_init(&isci_host->sci);
2448         if (err)
2449                 return err;
2450
2451         for (i = 0; i < SCI_MAX_PORTS; i++)
2452                 isci_port_init(&isci_host->ports[i], isci_host, i);
2453
2454         for (i = 0; i < SCI_MAX_PHYS; i++)
2455                 isci_phy_init(&isci_host->phys[i], isci_host, i);
2456
2457         for (i = 0; i < SCI_MAX_REMOTE_DEVICES; i++) {
2458                 struct isci_remote_device *idev = &isci_host->devices[i];
2459
2460                 INIT_LIST_HEAD(&idev->reqs_in_process);
2461                 INIT_LIST_HEAD(&idev->node);
2462         }
2463
2464         for (i = 0; i < SCI_MAX_IO_REQUESTS; i++) {
2465                 struct isci_request *ireq;
2466                 dma_addr_t dma;
2467
2468                 ireq = dmam_alloc_coherent(&isci_host->pdev->dev,
2469                                            sizeof(struct isci_request), &dma,
2470                                            GFP_KERNEL);
2471                 if (!ireq)
2472                         return -ENOMEM;
2473
2474                 ireq->tc = &isci_host->sci.task_context_table[i];
2475                 ireq->owning_controller = &isci_host->sci;
2476                 spin_lock_init(&ireq->state_lock);
2477                 ireq->request_daddr = dma;
2478                 ireq->isci_host = isci_host;
2479
2480                 isci_host->reqs[i] = ireq;
2481         }
2482
2483         return 0;
2484 }
2485
2486 void scic_sds_controller_link_up(struct scic_sds_controller *scic,
2487                 struct scic_sds_port *port, struct scic_sds_phy *phy)
2488 {
2489         switch (scic->sm.current_state_id) {
2490         case SCIC_STARTING:
2491                 sci_del_timer(&scic->phy_timer);
2492                 scic->phy_startup_timer_pending = false;
2493                 scic->port_agent.link_up_handler(scic, &scic->port_agent,
2494                                                  port, phy);
2495                 scic_sds_controller_start_next_phy(scic);
2496                 break;
2497         case SCIC_READY:
2498                 scic->port_agent.link_up_handler(scic, &scic->port_agent,
2499                                                  port, phy);
2500                 break;
2501         default:
2502                 dev_dbg(scic_to_dev(scic),
2503                         "%s: SCIC Controller linkup event from phy %d in "
2504                         "unexpected state %d\n", __func__, phy->phy_index,
2505                         scic->sm.current_state_id);
2506         }
2507 }
2508
2509 void scic_sds_controller_link_down(struct scic_sds_controller *scic,
2510                 struct scic_sds_port *port, struct scic_sds_phy *phy)
2511 {
2512         switch (scic->sm.current_state_id) {
2513         case SCIC_STARTING:
2514         case SCIC_READY:
2515                 scic->port_agent.link_down_handler(scic, &scic->port_agent,
2516                                                    port, phy);
2517                 break;
2518         default:
2519                 dev_dbg(scic_to_dev(scic),
2520                         "%s: SCIC Controller linkdown event from phy %d in "
2521                         "unexpected state %d\n",
2522                         __func__,
2523                         phy->phy_index,
2524                         scic->sm.current_state_id);
2525         }
2526 }
2527
2528 /**
2529  * This is a helper method to determine if any remote devices on this
2530  * controller are still in the stopping state.
2531  *
2532  */
2533 static bool scic_sds_controller_has_remote_devices_stopping(
2534         struct scic_sds_controller *controller)
2535 {
2536         u32 index;
2537
2538         for (index = 0; index < controller->remote_node_entries; index++) {
2539                 if ((controller->device_table[index] != NULL) &&
2540                    (controller->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING))
2541                         return true;
2542         }
2543
2544         return false;
2545 }
2546
2547 /**
2548  * This method is called by the remote device to inform the controller
2549  * object that the remote device has stopped.
2550  */
2551 void scic_sds_controller_remote_device_stopped(struct scic_sds_controller *scic,
2552                                                struct scic_sds_remote_device *sci_dev)
2553 {
2554         if (scic->sm.current_state_id != SCIC_STOPPING) {
2555                 dev_dbg(scic_to_dev(scic),
2556                         "SCIC Controller 0x%p remote device stopped event "
2557                         "from device 0x%p in unexpected state %d\n",
2558                         scic, sci_dev,
2559                         scic->sm.current_state_id);
2560                 return;
2561         }
2562
2563         if (!scic_sds_controller_has_remote_devices_stopping(scic)) {
2564                 sci_change_state(&scic->sm, SCIC_STOPPED);
2565         }
2566 }
2567
2568 /**
2569  * This method will write to the SCU PCP register the request value. The method
2570  *    is used to suspend/resume ports, devices, and phys.
2571  * @scic:
2572  *
2573  *
2574  */
2575 void scic_sds_controller_post_request(
2576         struct scic_sds_controller *scic,
2577         u32 request)
2578 {
2579         dev_dbg(scic_to_dev(scic),
2580                 "%s: SCIC Controller 0x%p post request 0x%08x\n",
2581                 __func__,
2582                 scic,
2583                 request);
2584
2585         writel(request, &scic->smu_registers->post_context_port);
2586 }
2587
2588 struct isci_request *scic_request_by_tag(struct scic_sds_controller *scic, u16 io_tag)
2589 {
2590         u16 task_index;
2591         u16 task_sequence;
2592
2593         task_index = ISCI_TAG_TCI(io_tag);
2594
2595         if (task_index < scic->task_context_entries) {
2596                 struct isci_request *ireq = scic_to_ihost(scic)->reqs[task_index];
2597
2598                 if (test_bit(IREQ_ACTIVE, &ireq->flags)) {
2599                         task_sequence = ISCI_TAG_SEQ(io_tag);
2600
2601                         if (task_sequence == scic->io_request_sequence[task_index])
2602                                 return ireq;
2603                 }
2604         }
2605
2606         return NULL;
2607 }
2608
2609 /**
2610  * This method allocates remote node index and the reserves the remote node
2611  *    context space for use. This method can fail if there are no more remote
2612  *    node index available.
2613  * @scic: This is the controller object which contains the set of
2614  *    free remote node ids
2615  * @sci_dev: This is the device object which is requesting the a remote node
2616  *    id
2617  * @node_id: This is the remote node id that is assinged to the device if one
2618  *    is available
2619  *
2620  * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
2621  * node index available.
2622  */
2623 enum sci_status scic_sds_controller_allocate_remote_node_context(
2624         struct scic_sds_controller *scic,
2625         struct scic_sds_remote_device *sci_dev,
2626         u16 *node_id)
2627 {
2628         u16 node_index;
2629         u32 remote_node_count = scic_sds_remote_device_node_count(sci_dev);
2630
2631         node_index = scic_sds_remote_node_table_allocate_remote_node(
2632                 &scic->available_remote_nodes, remote_node_count
2633                 );
2634
2635         if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
2636                 scic->device_table[node_index] = sci_dev;
2637
2638                 *node_id = node_index;
2639
2640                 return SCI_SUCCESS;
2641         }
2642
2643         return SCI_FAILURE_INSUFFICIENT_RESOURCES;
2644 }
2645
2646 /**
2647  * This method frees the remote node index back to the available pool.  Once
2648  *    this is done the remote node context buffer is no longer valid and can
2649  *    not be used.
2650  * @scic:
2651  * @sci_dev:
2652  * @node_id:
2653  *
2654  */
2655 void scic_sds_controller_free_remote_node_context(
2656         struct scic_sds_controller *scic,
2657         struct scic_sds_remote_device *sci_dev,
2658         u16 node_id)
2659 {
2660         u32 remote_node_count = scic_sds_remote_device_node_count(sci_dev);
2661
2662         if (scic->device_table[node_id] == sci_dev) {
2663                 scic->device_table[node_id] = NULL;
2664
2665                 scic_sds_remote_node_table_release_remote_node_index(
2666                         &scic->available_remote_nodes, remote_node_count, node_id
2667                         );
2668         }
2669 }
2670
2671 /**
2672  * This method returns the union scu_remote_node_context for the specified remote
2673  *    node id.
2674  * @scic:
2675  * @node_id:
2676  *
2677  * union scu_remote_node_context*
2678  */
2679 union scu_remote_node_context *scic_sds_controller_get_remote_node_context_buffer(
2680         struct scic_sds_controller *scic,
2681         u16 node_id
2682         ) {
2683         if (
2684                 (node_id < scic->remote_node_entries)
2685                 && (scic->device_table[node_id] != NULL)
2686                 ) {
2687                 return &scic->remote_node_context_table[node_id];
2688         }
2689
2690         return NULL;
2691 }
2692
2693 /**
2694  *
2695  * @resposne_buffer: This is the buffer into which the D2H register FIS will be
2696  *    constructed.
2697  * @frame_header: This is the frame header returned by the hardware.
2698  * @frame_buffer: This is the frame buffer returned by the hardware.
2699  *
2700  * This method will combind the frame header and frame buffer to create a SATA
2701  * D2H register FIS none
2702  */
2703 void scic_sds_controller_copy_sata_response(
2704         void *response_buffer,
2705         void *frame_header,
2706         void *frame_buffer)
2707 {
2708         memcpy(response_buffer, frame_header, sizeof(u32));
2709
2710         memcpy(response_buffer + sizeof(u32),
2711                frame_buffer,
2712                sizeof(struct dev_to_host_fis) - sizeof(u32));
2713 }
2714
2715 /**
2716  * This method releases the frame once this is done the frame is available for
2717  *    re-use by the hardware.  The data contained in the frame header and frame
2718  *    buffer is no longer valid. The UF queue get pointer is only updated if UF
2719  *    control indicates this is appropriate.
2720  * @scic:
2721  * @frame_index:
2722  *
2723  */
2724 void scic_sds_controller_release_frame(
2725         struct scic_sds_controller *scic,
2726         u32 frame_index)
2727 {
2728         if (scic_sds_unsolicited_frame_control_release_frame(
2729                     &scic->uf_control, frame_index) == true)
2730                 writel(scic->uf_control.get,
2731                         &scic->scu_registers->sdma.unsolicited_frame_get_pointer);
2732 }
2733
2734 void isci_tci_free(struct isci_host *ihost, u16 tci)
2735 {
2736         u16 tail = ihost->tci_tail & (SCI_MAX_IO_REQUESTS-1);
2737
2738         ihost->tci_pool[tail] = tci;
2739         ihost->tci_tail = tail + 1;
2740 }
2741
2742 static u16 isci_tci_alloc(struct isci_host *ihost)
2743 {
2744         u16 head = ihost->tci_head & (SCI_MAX_IO_REQUESTS-1);
2745         u16 tci = ihost->tci_pool[head];
2746
2747         ihost->tci_head = head + 1;
2748         return tci;
2749 }
2750
2751 static u16 isci_tci_space(struct isci_host *ihost)
2752 {
2753         return CIRC_SPACE(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
2754 }
2755
2756 u16 isci_alloc_tag(struct isci_host *ihost)
2757 {
2758         if (isci_tci_space(ihost)) {
2759                 u16 tci = isci_tci_alloc(ihost);
2760                 u8 seq = ihost->sci.io_request_sequence[tci];
2761
2762                 return ISCI_TAG(seq, tci);
2763         }
2764
2765         return SCI_CONTROLLER_INVALID_IO_TAG;
2766 }
2767
2768 enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag)
2769 {
2770         struct scic_sds_controller *scic = &ihost->sci;
2771         u16 tci = ISCI_TAG_TCI(io_tag);
2772         u16 seq = ISCI_TAG_SEQ(io_tag);
2773
2774         /* prevent tail from passing head */
2775         if (isci_tci_active(ihost) == 0)
2776                 return SCI_FAILURE_INVALID_IO_TAG;
2777
2778         if (seq == scic->io_request_sequence[tci]) {
2779                 scic->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1);
2780
2781                 isci_tci_free(ihost, tci);
2782
2783                 return SCI_SUCCESS;
2784         }
2785         return SCI_FAILURE_INVALID_IO_TAG;
2786 }
2787
2788 /**
2789  * scic_controller_start_io() - This method is called by the SCI user to
2790  *    send/start an IO request. If the method invocation is successful, then
2791  *    the IO request has been queued to the hardware for processing.
2792  * @controller: the handle to the controller object for which to start an IO
2793  *    request.
2794  * @remote_device: the handle to the remote device object for which to start an
2795  *    IO request.
2796  * @io_request: the handle to the io request object to start.
2797  * @io_tag: This parameter specifies a previously allocated IO tag that the
2798  *    user desires to be utilized for this request.
2799  */
2800 enum sci_status scic_controller_start_io(struct scic_sds_controller *scic,
2801                                          struct scic_sds_remote_device *rdev,
2802                                          struct isci_request *ireq)
2803 {
2804         enum sci_status status;
2805
2806         if (scic->sm.current_state_id != SCIC_READY) {
2807                 dev_warn(scic_to_dev(scic), "invalid state to start I/O");
2808                 return SCI_FAILURE_INVALID_STATE;
2809         }
2810
2811         status = scic_sds_remote_device_start_io(scic, rdev, ireq);
2812         if (status != SCI_SUCCESS)
2813                 return status;
2814
2815         set_bit(IREQ_ACTIVE, &ireq->flags);
2816         scic_sds_controller_post_request(scic, scic_sds_request_get_post_context(ireq));
2817         return SCI_SUCCESS;
2818 }
2819
2820 /**
2821  * scic_controller_terminate_request() - This method is called by the SCI Core
2822  *    user to terminate an ongoing (i.e. started) core IO request.  This does
2823  *    not abort the IO request at the target, but rather removes the IO request
2824  *    from the host controller.
2825  * @controller: the handle to the controller object for which to terminate a
2826  *    request.
2827  * @remote_device: the handle to the remote device object for which to
2828  *    terminate a request.
2829  * @request: the handle to the io or task management request object to
2830  *    terminate.
2831  *
2832  * Indicate if the controller successfully began the terminate process for the
2833  * IO request. SCI_SUCCESS if the terminate process was successfully started
2834  * for the request. Determine the failure situations and return values.
2835  */
2836 enum sci_status scic_controller_terminate_request(
2837         struct scic_sds_controller *scic,
2838         struct scic_sds_remote_device *rdev,
2839         struct isci_request *ireq)
2840 {
2841         enum sci_status status;
2842
2843         if (scic->sm.current_state_id != SCIC_READY) {
2844                 dev_warn(scic_to_dev(scic),
2845                          "invalid state to terminate request\n");
2846                 return SCI_FAILURE_INVALID_STATE;
2847         }
2848
2849         status = scic_sds_io_request_terminate(ireq);
2850         if (status != SCI_SUCCESS)
2851                 return status;
2852
2853         /*
2854          * Utilize the original post context command and or in the POST_TC_ABORT
2855          * request sub-type.
2856          */
2857         scic_sds_controller_post_request(scic,
2858                 scic_sds_request_get_post_context(ireq) |
2859                 SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT);
2860         return SCI_SUCCESS;
2861 }
2862
2863 /**
2864  * scic_controller_complete_io() - This method will perform core specific
2865  *    completion operations for an IO request.  After this method is invoked,
2866  *    the user should consider the IO request as invalid until it is properly
2867  *    reused (i.e. re-constructed).
2868  * @controller: The handle to the controller object for which to complete the
2869  *    IO request.
2870  * @remote_device: The handle to the remote device object for which to complete
2871  *    the IO request.
2872  * @io_request: the handle to the io request object to complete.
2873  */
2874 enum sci_status scic_controller_complete_io(
2875         struct scic_sds_controller *scic,
2876         struct scic_sds_remote_device *rdev,
2877         struct isci_request *ireq)
2878 {
2879         enum sci_status status;
2880         u16 index;
2881
2882         switch (scic->sm.current_state_id) {
2883         case SCIC_STOPPING:
2884                 /* XXX: Implement this function */
2885                 return SCI_FAILURE;
2886         case SCIC_READY:
2887                 status = scic_sds_remote_device_complete_io(scic, rdev, ireq);
2888                 if (status != SCI_SUCCESS)
2889                         return status;
2890
2891                 index = ISCI_TAG_TCI(ireq->io_tag);
2892                 clear_bit(IREQ_ACTIVE, &ireq->flags);
2893                 return SCI_SUCCESS;
2894         default:
2895                 dev_warn(scic_to_dev(scic), "invalid state to complete I/O");
2896                 return SCI_FAILURE_INVALID_STATE;
2897         }
2898
2899 }
2900
2901 enum sci_status scic_controller_continue_io(struct isci_request *ireq)
2902 {
2903         struct scic_sds_controller *scic = ireq->owning_controller;
2904
2905         if (scic->sm.current_state_id != SCIC_READY) {
2906                 dev_warn(scic_to_dev(scic), "invalid state to continue I/O");
2907                 return SCI_FAILURE_INVALID_STATE;
2908         }
2909
2910         set_bit(IREQ_ACTIVE, &ireq->flags);
2911         scic_sds_controller_post_request(scic, scic_sds_request_get_post_context(ireq));
2912         return SCI_SUCCESS;
2913 }
2914
2915 /**
2916  * scic_controller_start_task() - This method is called by the SCIC user to
2917  *    send/start a framework task management request.
2918  * @controller: the handle to the controller object for which to start the task
2919  *    management request.
2920  * @remote_device: the handle to the remote device object for which to start
2921  *    the task management request.
2922  * @task_request: the handle to the task request object to start.
2923  */
2924 enum sci_task_status scic_controller_start_task(
2925         struct scic_sds_controller *scic,
2926         struct scic_sds_remote_device *rdev,
2927         struct isci_request *ireq)
2928 {
2929         enum sci_status status;
2930
2931         if (scic->sm.current_state_id != SCIC_READY) {
2932                 dev_warn(scic_to_dev(scic),
2933                          "%s: SCIC Controller starting task from invalid "
2934                          "state\n",
2935                          __func__);
2936                 return SCI_TASK_FAILURE_INVALID_STATE;
2937         }
2938
2939         status = scic_sds_remote_device_start_task(scic, rdev, ireq);
2940         switch (status) {
2941         case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS:
2942                 set_bit(IREQ_ACTIVE, &ireq->flags);
2943
2944                 /*
2945                  * We will let framework know this task request started successfully,
2946                  * although core is still woring on starting the request (to post tc when
2947                  * RNC is resumed.)
2948                  */
2949                 return SCI_SUCCESS;
2950         case SCI_SUCCESS:
2951                 set_bit(IREQ_ACTIVE, &ireq->flags);
2952
2953                 scic_sds_controller_post_request(scic,
2954                         scic_sds_request_get_post_context(ireq));
2955                 break;
2956         default:
2957                 break;
2958         }
2959
2960         return status;
2961 }