2 * ipr.h -- driver for IBM Power Linux RAID adapters
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
6 * Copyright (C) 2003, 2004 IBM Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
29 #include <linux/types.h>
30 #include <linux/completion.h>
31 #include <linux/libata.h>
32 #include <linux/list.h>
33 #include <linux/kref.h>
34 #include <scsi/scsi.h>
35 #include <scsi/scsi_cmnd.h>
40 #define IPR_DRIVER_VERSION "2.4.3"
41 #define IPR_DRIVER_DATE "(June 10, 2009)"
44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
45 * ops per device for devices not running tagged command queuing.
46 * This can be adjusted at runtime through sysfs device attributes.
48 #define IPR_MAX_CMD_PER_LUN 6
49 #define IPR_MAX_CMD_PER_ATA_LUN 1
52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
53 * ops the mid-layer can send to the adapter.
55 #define IPR_NUM_BASE_CMD_BLKS 100
57 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
58 #define PCI_DEVICE_ID_IBM_SCAMP_E 0x034A
60 #define IPR_SUBS_DEV_ID_2780 0x0264
61 #define IPR_SUBS_DEV_ID_5702 0x0266
62 #define IPR_SUBS_DEV_ID_5703 0x0278
63 #define IPR_SUBS_DEV_ID_572E 0x028D
64 #define IPR_SUBS_DEV_ID_573E 0x02D3
65 #define IPR_SUBS_DEV_ID_573D 0x02D4
66 #define IPR_SUBS_DEV_ID_571A 0x02C0
67 #define IPR_SUBS_DEV_ID_571B 0x02BE
68 #define IPR_SUBS_DEV_ID_571E 0x02BF
69 #define IPR_SUBS_DEV_ID_571F 0x02D5
70 #define IPR_SUBS_DEV_ID_572A 0x02C1
71 #define IPR_SUBS_DEV_ID_572B 0x02C2
72 #define IPR_SUBS_DEV_ID_572F 0x02C3
73 #define IPR_SUBS_DEV_ID_574D 0x030B
74 #define IPR_SUBS_DEV_ID_574E 0x030A
75 #define IPR_SUBS_DEV_ID_575B 0x030D
76 #define IPR_SUBS_DEV_ID_575C 0x0338
77 #define IPR_SUBS_DEV_ID_575D 0x033E
78 #define IPR_SUBS_DEV_ID_57B3 0x033A
79 #define IPR_SUBS_DEV_ID_57B7 0x0360
80 #define IPR_SUBS_DEV_ID_57B8 0x02C2
82 #define IPR_NAME "ipr"
87 #define IPR_RC_JOB_CONTINUE 1
88 #define IPR_RC_JOB_RETURN 2
93 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
94 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
95 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
96 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
97 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
98 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
99 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
100 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
101 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
102 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
103 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
104 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
105 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
106 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
107 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
109 #define IPR_FIRST_DRIVER_IOASC 0x10000000
110 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
111 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
113 /* Driver data flags */
114 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
115 #define IPR_USE_PCI_WARM_RESET 0x00000002
117 #define IPR_DEFAULT_MAX_ERROR_DUMP 984
118 #define IPR_NUM_LOG_HCAMS 2
119 #define IPR_NUM_CFG_CHG_HCAMS 2
120 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
122 #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
123 #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
125 #define IPR_MAX_NUM_TARGETS_PER_BUS 256
126 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
127 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
128 #define IPR_VSET_BUS 0xff
129 #define IPR_IOA_BUS 0xff
130 #define IPR_IOA_TARGET 0xff
131 #define IPR_IOA_LUN 0xff
132 #define IPR_MAX_NUM_BUSES 16
133 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
135 #define IPR_NUM_RESET_RELOAD_RETRIES 3
137 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
138 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
139 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3)
141 #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
142 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
143 IPR_NUM_INTERNAL_CMD_BLKS)
145 #define IPR_MAX_PHYSICAL_DEVS 192
146 #define IPR_DEFAULT_SIS64_DEVS 1024
147 #define IPR_MAX_SIS64_DEVS 4096
149 #define IPR_MAX_SGLIST 64
150 #define IPR_IOA_MAX_SECTORS 32767
151 #define IPR_VSET_MAX_SECTORS 512
152 #define IPR_MAX_CDB_LEN 16
153 #define IPR_MAX_HRRQ_RETRIES 3
155 #define IPR_DEFAULT_BUS_WIDTH 16
156 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
157 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
158 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
159 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
161 #define IPR_IOA_RES_HANDLE 0xffffffff
162 #define IPR_INVALID_RES_HANDLE 0
163 #define IPR_IOA_RES_ADDR 0x00ffffff
168 #define IPR_QUERY_RSRC_STATE 0xC2
169 #define IPR_RESET_DEVICE 0xC3
170 #define IPR_RESET_TYPE_SELECT 0x80
171 #define IPR_LUN_RESET 0x40
172 #define IPR_TARGET_RESET 0x20
173 #define IPR_BUS_RESET 0x10
174 #define IPR_ATA_PHY_RESET 0x80
175 #define IPR_ID_HOST_RR_Q 0xC4
176 #define IPR_QUERY_IOA_CONFIG 0xC5
177 #define IPR_CANCEL_ALL_REQUESTS 0xCE
178 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
179 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
180 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
181 #define IPR_SET_SUPPORTED_DEVICES 0xFB
182 #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
183 #define IPR_IOA_SHUTDOWN 0xF7
184 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
189 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
190 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
191 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
192 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
193 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
194 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
195 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
196 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
197 #define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
198 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
199 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
200 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
201 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
202 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
203 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
204 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
205 #define IPR_PCI_RESET_TIMEOUT (HZ / 2)
206 #define IPR_DUMP_TIMEOUT (15 * HZ)
211 #define IPR_VENDOR_ID_LEN 8
212 #define IPR_PROD_ID_LEN 16
213 #define IPR_SERIAL_NUM_LEN 8
218 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
219 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
220 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
221 #define IPR_GET_FMT2_BAR_SEL(mbx) \
222 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
223 #define IPR_SDT_FMT2_BAR0_SEL 0x0
224 #define IPR_SDT_FMT2_BAR1_SEL 0x1
225 #define IPR_SDT_FMT2_BAR2_SEL 0x2
226 #define IPR_SDT_FMT2_BAR3_SEL 0x3
227 #define IPR_SDT_FMT2_BAR4_SEL 0x4
228 #define IPR_SDT_FMT2_BAR5_SEL 0x5
229 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
230 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
231 #define IPR_DOORBELL 0x82800000
232 #define IPR_RUNTIME_RESET 0x40000000
234 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
235 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
236 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
237 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
238 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
239 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
240 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
241 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
242 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
243 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
244 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
246 #define IPR_PCII_ERROR_INTERRUPTS \
247 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
248 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
250 #define IPR_PCII_OPER_INTERRUPTS \
251 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
253 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
254 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
256 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
257 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
262 #define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
263 #define IPR_NUM_SDT_ENTRIES 511
264 #define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
269 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
272 * Adapter interface types
275 struct ipr_res_addr {
280 #define IPR_GET_PHYS_LOC(res_addr) \
281 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
282 }__attribute__((packed, aligned (4)));
284 struct ipr_std_inq_vpids {
285 u8 vendor_id[IPR_VENDOR_ID_LEN];
286 u8 product_id[IPR_PROD_ID_LEN];
287 }__attribute__((packed));
290 struct ipr_std_inq_vpids vpids;
291 u8 sn[IPR_SERIAL_NUM_LEN];
292 }__attribute__((packed));
297 }__attribute__((packed));
299 struct ipr_std_inq_data {
300 u8 peri_qual_dev_type;
301 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
302 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
304 u8 removeable_medium_rsvd;
305 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
307 #define IPR_IS_DASD_DEVICE(std_inq) \
308 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
309 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
311 #define IPR_IS_SES_DEVICE(std_inq) \
312 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
321 struct ipr_std_inq_vpids vpids;
323 u8 ros_rsvd_ram_rsvd[4];
325 u8 serial_num[IPR_SERIAL_NUM_LEN];
326 }__attribute__ ((packed));
328 #define IPR_RES_TYPE_AF_DASD 0x00
329 #define IPR_RES_TYPE_GENERIC_SCSI 0x01
330 #define IPR_RES_TYPE_VOLUME_SET 0x02
331 #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
332 #define IPR_RES_TYPE_GENERIC_ATA 0x04
333 #define IPR_RES_TYPE_ARRAY 0x05
334 #define IPR_RES_TYPE_IOAFP 0xff
336 struct ipr_config_table_entry {
338 #define IPR_PROTO_SATA 0x02
339 #define IPR_PROTO_SATA_ATAPI 0x03
340 #define IPR_PROTO_SAS_STP 0x06
341 #define IPR_PROTO_SAS_STP_ATAPI 0x07
344 #define IPR_IS_IOA_RESOURCE 0x80
347 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
348 #define IPR_QUEUE_FROZEN_MODEL 0
349 #define IPR_QUEUE_NACA_MODEL 1
351 struct ipr_res_addr res_addr;
354 struct ipr_std_inq_data std_inq_data;
355 }__attribute__ ((packed, aligned (4)));
357 struct ipr_config_table_entry64 {
364 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
371 #define IPR_MAX_RES_PATH_LENGTH 24
373 struct ipr_std_inq_data std_inq_data;
375 __be64 reserved3[2]; // description text
377 }__attribute__ ((packed, aligned (8)));
379 struct ipr_config_table_hdr {
382 #define IPR_UCODE_DOWNLOAD_REQ 0x10
384 }__attribute__((packed, aligned (4)));
386 struct ipr_config_table_hdr64 {
391 }__attribute__((packed, aligned (4)));
393 struct ipr_config_table {
394 struct ipr_config_table_hdr hdr;
395 struct ipr_config_table_entry dev[0];
396 }__attribute__((packed, aligned (4)));
398 struct ipr_config_table64 {
399 struct ipr_config_table_hdr64 hdr64;
400 struct ipr_config_table_entry64 dev[0];
401 }__attribute__((packed, aligned (8)));
403 struct ipr_config_table_entry_wrapper {
405 struct ipr_config_table_entry *cfgte;
406 struct ipr_config_table_entry64 *cfgte64;
410 struct ipr_hostrcb_cfg_ch_not {
412 struct ipr_config_table_entry cfgte;
413 struct ipr_config_table_entry64 cfgte64;
416 }__attribute__((packed, aligned (4)));
418 struct ipr_supported_device {
422 struct ipr_std_inq_vpids vpids;
424 }__attribute__((packed, aligned (4)));
426 /* Command packet structure */
428 __be16 reserved; /* Reserved by IOA */
430 #define IPR_RQTYPE_SCSICDB 0x00
431 #define IPR_RQTYPE_IOACMD 0x01
432 #define IPR_RQTYPE_HCAM 0x02
433 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
438 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
439 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
440 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
441 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
442 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
445 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
446 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
447 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
448 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
449 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
450 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
451 #define IPR_FLAGS_LO_ACA_TASK 0x08
455 }__attribute__ ((packed, aligned(4)));
457 struct ipr_ioarcb_ata_regs { /* 22 bytes */
459 #define IPR_ATA_FLAG_PACKET_CMD 0x80
460 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
461 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
479 }__attribute__ ((packed, aligned(4)));
481 struct ipr_ioadl_desc {
482 __be32 flags_and_data_len;
483 #define IPR_IOADL_FLAGS_MASK 0xff000000
484 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
485 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
486 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
487 #define IPR_IOADL_FLAGS_READ 0x48000000
488 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
489 #define IPR_IOADL_FLAGS_WRITE 0x68000000
490 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
491 #define IPR_IOADL_FLAGS_LAST 0x01000000
494 }__attribute__((packed, aligned (8)));
496 struct ipr_ioadl64_desc {
500 }__attribute__((packed, aligned (16)));
502 struct ipr_ata64_ioadl {
503 struct ipr_ioarcb_ata_regs regs;
505 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
506 }__attribute__((packed, aligned (16)));
508 struct ipr_ioarcb_add_data {
510 struct ipr_ioarcb_ata_regs regs;
511 struct ipr_ioadl_desc ioadl[5];
512 __be32 add_cmd_parms[10];
514 }__attribute__ ((packed, aligned (4)));
516 struct ipr_ioarcb_sis64_add_addr_ecb {
517 __be64 ioasa_host_pci_addr;
518 __be64 data_ioadl_addr;
520 __be32 ext_control_buf[4];
521 }__attribute__((packed, aligned (8)));
523 /* IOA Request Control Block 128 bytes */
526 __be32 ioarcb_host_pci_addr;
527 __be64 ioarcb_host_pci_addr64;
530 __be32 host_response_handle;
535 __be32 data_transfer_length;
536 __be32 read_data_transfer_length;
537 __be32 write_ioadl_addr;
539 __be32 read_ioadl_addr;
540 __be32 read_ioadl_len;
542 __be32 ioasa_host_pci_addr;
546 struct ipr_cmd_pkt cmd_pkt;
548 __be16 add_cmd_parms_offset;
549 __be16 add_cmd_parms_len;
552 struct ipr_ioarcb_add_data add_data;
553 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
556 }__attribute__((packed, aligned (4)));
558 struct ipr_ioasa_vset {
559 __be32 failing_lba_hi;
560 __be32 failing_lba_lo;
562 }__attribute__((packed, aligned (4)));
564 struct ipr_ioasa_af_dasd {
567 }__attribute__((packed, aligned (4)));
569 struct ipr_ioasa_gpdd {
574 }__attribute__((packed, aligned (4)));
576 struct ipr_ioasa_gata {
578 u8 nsect; /* Interrupt reason */
584 u8 alt_status; /* ATA CTL */
589 }__attribute__((packed, aligned (4)));
591 struct ipr_auto_sense {
592 __be16 auto_sense_len;
594 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
599 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
600 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
601 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
602 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
604 __be16 ret_stat_len; /* Length of the returned IOASA */
606 __be16 avail_stat_len; /* Total Length of status available. */
608 __be32 residual_data_len; /* number of bytes in the host data */
609 /* buffers that were not used by the IOARCB command. */
612 #define IPR_NO_ILID 0
613 #define IPR_DRIVER_ILID 0xffffffff
617 __be32 fd_phys_locator;
619 __be32 fd_res_handle;
621 __be32 ioasc_specific; /* status code specific field */
622 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
623 #define IPR_AUTOSENSE_VALID 0x40000000
624 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000
625 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
626 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
627 #define IPR_FIELD_POINTER_MASK 0x0000ffff
630 struct ipr_ioasa_vset vset;
631 struct ipr_ioasa_af_dasd dasd;
632 struct ipr_ioasa_gpdd gpdd;
633 struct ipr_ioasa_gata gata;
636 struct ipr_auto_sense auto_sense;
637 }__attribute__((packed, aligned (4)));
639 struct ipr_mode_parm_hdr {
642 u8 device_spec_parms;
644 }__attribute__((packed));
646 struct ipr_mode_pages {
647 struct ipr_mode_parm_hdr hdr;
648 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
649 }__attribute__((packed));
651 struct ipr_mode_page_hdr {
653 #define IPR_MODE_PAGE_PS 0x80
654 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
656 }__attribute__ ((packed));
658 struct ipr_dev_bus_entry {
659 struct ipr_res_addr res_addr;
661 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
662 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
663 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
664 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
665 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
666 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
667 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
671 u8 extended_reset_delay;
672 #define IPR_EXTENDED_RESET_DELAY 7
674 __be32 max_xfer_rate;
679 }__attribute__((packed, aligned (4)));
681 struct ipr_mode_page28 {
682 struct ipr_mode_page_hdr hdr;
685 struct ipr_dev_bus_entry bus[0];
686 }__attribute__((packed));
688 struct ipr_mode_page24 {
689 struct ipr_mode_page_hdr hdr;
691 #define IPR_ENABLE_DUAL_IOA_AF 0x80
692 }__attribute__((packed));
695 struct ipr_std_inq_data std_inq_data;
696 u8 ascii_part_num[12];
698 u8 ascii_plant_code[4];
699 }__attribute__((packed));
701 struct ipr_inquiry_page3 {
702 u8 peri_qual_dev_type;
714 }__attribute__((packed));
716 struct ipr_inquiry_cap {
717 u8 peri_qual_dev_type;
725 #define IPR_CAP_DUAL_IOA_RAID 0x80
727 }__attribute__((packed));
729 #define IPR_INQUIRY_PAGE0_ENTRIES 20
730 struct ipr_inquiry_page0 {
731 u8 peri_qual_dev_type;
735 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
736 }__attribute__((packed));
738 struct ipr_hostrcb_device_data_entry {
740 struct ipr_res_addr dev_res_addr;
741 struct ipr_vpd new_vpd;
742 struct ipr_vpd ioa_last_with_dev_vpd;
743 struct ipr_vpd cfc_last_with_dev_vpd;
745 }__attribute__((packed, aligned (4)));
747 struct ipr_hostrcb_device_data_entry_enhanced {
748 struct ipr_ext_vpd vpd;
750 struct ipr_res_addr dev_res_addr;
751 struct ipr_ext_vpd new_vpd;
753 struct ipr_ext_vpd ioa_last_with_dev_vpd;
754 struct ipr_ext_vpd cfc_last_with_dev_vpd;
755 }__attribute__((packed, aligned (4)));
757 struct ipr_hostrcb64_device_data_entry_enhanced {
758 struct ipr_ext_vpd vpd;
761 struct ipr_ext_vpd new_vpd;
763 struct ipr_ext_vpd ioa_last_with_dev_vpd;
764 struct ipr_ext_vpd cfc_last_with_dev_vpd;
765 }__attribute__((packed, aligned (4)));
767 struct ipr_hostrcb_array_data_entry {
769 struct ipr_res_addr expected_dev_res_addr;
770 struct ipr_res_addr dev_res_addr;
771 }__attribute__((packed, aligned (4)));
773 struct ipr_hostrcb64_array_data_entry {
774 struct ipr_ext_vpd vpd;
776 u8 expected_res_path[8];
778 }__attribute__((packed, aligned (4)));
780 struct ipr_hostrcb_array_data_entry_enhanced {
781 struct ipr_ext_vpd vpd;
783 struct ipr_res_addr expected_dev_res_addr;
784 struct ipr_res_addr dev_res_addr;
785 }__attribute__((packed, aligned (4)));
787 struct ipr_hostrcb_type_ff_error {
788 __be32 ioa_data[502];
789 }__attribute__((packed, aligned (4)));
791 struct ipr_hostrcb_type_01_error {
795 __be32 ioa_data[236];
796 }__attribute__((packed, aligned (4)));
798 struct ipr_hostrcb_type_02_error {
799 struct ipr_vpd ioa_vpd;
800 struct ipr_vpd cfc_vpd;
801 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
802 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
804 }__attribute__((packed, aligned (4)));
806 struct ipr_hostrcb_type_12_error {
807 struct ipr_ext_vpd ioa_vpd;
808 struct ipr_ext_vpd cfc_vpd;
809 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
810 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
812 }__attribute__((packed, aligned (4)));
814 struct ipr_hostrcb_type_03_error {
815 struct ipr_vpd ioa_vpd;
816 struct ipr_vpd cfc_vpd;
817 __be32 errors_detected;
818 __be32 errors_logged;
820 struct ipr_hostrcb_device_data_entry dev[3];
821 }__attribute__((packed, aligned (4)));
823 struct ipr_hostrcb_type_13_error {
824 struct ipr_ext_vpd ioa_vpd;
825 struct ipr_ext_vpd cfc_vpd;
826 __be32 errors_detected;
827 __be32 errors_logged;
828 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
829 }__attribute__((packed, aligned (4)));
831 struct ipr_hostrcb_type_23_error {
832 struct ipr_ext_vpd ioa_vpd;
833 struct ipr_ext_vpd cfc_vpd;
834 __be32 errors_detected;
835 __be32 errors_logged;
836 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
837 }__attribute__((packed, aligned (4)));
839 struct ipr_hostrcb_type_04_error {
840 struct ipr_vpd ioa_vpd;
841 struct ipr_vpd cfc_vpd;
843 struct ipr_hostrcb_array_data_entry array_member[10];
844 __be32 exposed_mode_adn;
846 struct ipr_vpd incomp_dev_vpd;
848 struct ipr_hostrcb_array_data_entry array_member2[8];
849 struct ipr_res_addr last_func_vset_res_addr;
850 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
851 u8 protection_level[8];
852 }__attribute__((packed, aligned (4)));
854 struct ipr_hostrcb_type_14_error {
855 struct ipr_ext_vpd ioa_vpd;
856 struct ipr_ext_vpd cfc_vpd;
857 __be32 exposed_mode_adn;
859 struct ipr_res_addr last_func_vset_res_addr;
860 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
861 u8 protection_level[8];
863 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
864 }__attribute__((packed, aligned (4)));
866 struct ipr_hostrcb_type_24_error {
867 struct ipr_ext_vpd ioa_vpd;
868 struct ipr_ext_vpd cfc_vpd;
871 #define IPR_INVALID_ARRAY_DEV_NUM 0xff
874 u8 protection_level[8];
875 struct ipr_ext_vpd array_vpd;
879 struct ipr_hostrcb64_array_data_entry array_member[32];
880 }__attribute__((packed, aligned (4)));
882 struct ipr_hostrcb_type_07_error {
883 u8 failure_reason[64];
886 }__attribute__((packed, aligned (4)));
888 struct ipr_hostrcb_type_17_error {
889 u8 failure_reason[64];
890 struct ipr_ext_vpd vpd;
892 }__attribute__((packed, aligned (4)));
894 struct ipr_hostrcb_config_element {
896 #define IPR_PATH_CFG_TYPE_MASK 0xF0
897 #define IPR_PATH_CFG_NOT_EXIST 0x00
898 #define IPR_PATH_CFG_IOA_PORT 0x10
899 #define IPR_PATH_CFG_EXP_PORT 0x20
900 #define IPR_PATH_CFG_DEVICE_PORT 0x30
901 #define IPR_PATH_CFG_DEVICE_LUN 0x40
903 #define IPR_PATH_CFG_STATUS_MASK 0x0F
904 #define IPR_PATH_CFG_NO_PROB 0x00
905 #define IPR_PATH_CFG_DEGRADED 0x01
906 #define IPR_PATH_CFG_FAILED 0x02
907 #define IPR_PATH_CFG_SUSPECT 0x03
908 #define IPR_PATH_NOT_DETECTED 0x04
909 #define IPR_PATH_INCORRECT_CONN 0x05
911 u8 cascaded_expander;
914 #define IPR_PHY_LINK_RATE_MASK 0x0F
917 }__attribute__((packed, aligned (4)));
919 struct ipr_hostrcb64_config_element {
922 #define IPR_DESCRIPTOR_MASK 0xC0
923 #define IPR_DESCRIPTOR_SIS64 0x00
933 }__attribute__((packed, aligned (8)));
935 struct ipr_hostrcb_fabric_desc {
938 u8 cascaded_expander;
941 #define IPR_PATH_ACTIVE_MASK 0xC0
942 #define IPR_PATH_NO_INFO 0x00
943 #define IPR_PATH_ACTIVE 0x40
944 #define IPR_PATH_NOT_ACTIVE 0x80
946 #define IPR_PATH_STATE_MASK 0x0F
947 #define IPR_PATH_STATE_NO_INFO 0x00
948 #define IPR_PATH_HEALTHY 0x01
949 #define IPR_PATH_DEGRADED 0x02
950 #define IPR_PATH_FAILED 0x03
953 struct ipr_hostrcb_config_element elem[1];
954 }__attribute__((packed, aligned (4)));
956 struct ipr_hostrcb64_fabric_desc {
967 struct ipr_hostrcb64_config_element elem[1];
968 }__attribute__((packed, aligned (8)));
970 #define for_each_fabric_cfg(fabric, cfg) \
971 for (cfg = (fabric)->elem; \
972 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
975 struct ipr_hostrcb_type_20_error {
976 u8 failure_reason[64];
979 struct ipr_hostrcb_fabric_desc desc[1];
980 }__attribute__((packed, aligned (4)));
982 struct ipr_hostrcb_type_30_error {
983 u8 failure_reason[64];
986 struct ipr_hostrcb64_fabric_desc desc[1];
987 }__attribute__((packed, aligned (4)));
989 struct ipr_hostrcb_error {
991 struct ipr_res_addr fd_res_addr;
992 __be32 fd_res_handle;
995 struct ipr_hostrcb_type_ff_error type_ff_error;
996 struct ipr_hostrcb_type_01_error type_01_error;
997 struct ipr_hostrcb_type_02_error type_02_error;
998 struct ipr_hostrcb_type_03_error type_03_error;
999 struct ipr_hostrcb_type_04_error type_04_error;
1000 struct ipr_hostrcb_type_07_error type_07_error;
1001 struct ipr_hostrcb_type_12_error type_12_error;
1002 struct ipr_hostrcb_type_13_error type_13_error;
1003 struct ipr_hostrcb_type_14_error type_14_error;
1004 struct ipr_hostrcb_type_17_error type_17_error;
1005 struct ipr_hostrcb_type_20_error type_20_error;
1007 }__attribute__((packed, aligned (4)));
1009 struct ipr_hostrcb64_error {
1011 __be32 ioa_fw_level;
1012 __be32 fd_res_handle;
1020 struct ipr_hostrcb_type_ff_error type_ff_error;
1021 struct ipr_hostrcb_type_12_error type_12_error;
1022 struct ipr_hostrcb_type_17_error type_17_error;
1023 struct ipr_hostrcb_type_23_error type_23_error;
1024 struct ipr_hostrcb_type_24_error type_24_error;
1025 struct ipr_hostrcb_type_30_error type_30_error;
1027 }__attribute__((packed, aligned (8)));
1029 struct ipr_hostrcb_raw {
1030 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1031 }__attribute__((packed, aligned (4)));
1035 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1036 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1039 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1040 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1041 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1042 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1043 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1045 u8 notifications_lost;
1046 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1047 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1050 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
1051 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1054 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1055 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1056 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1057 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1058 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1059 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1060 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1061 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1062 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1063 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1064 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1065 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1066 #define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1067 #define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1068 #define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1069 #define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1070 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1074 __be32 time_since_last_ioa_reset;
1079 struct ipr_hostrcb_error error;
1080 struct ipr_hostrcb64_error error64;
1081 struct ipr_hostrcb_cfg_ch_not ccn;
1082 struct ipr_hostrcb_raw raw;
1084 }__attribute__((packed, aligned (4)));
1086 struct ipr_hostrcb {
1087 struct ipr_hcam hcam;
1088 dma_addr_t hostrcb_dma;
1089 struct list_head queue;
1090 struct ipr_ioa_cfg *ioa_cfg;
1091 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1094 /* IPR smart dump table structures */
1095 struct ipr_sdt_entry {
1096 __be32 bar_str_offset;
1102 #define IPR_SDT_ENDIAN 0x80
1103 #define IPR_SDT_VALID_ENTRY 0x20
1107 }__attribute__((packed, aligned (4)));
1109 struct ipr_sdt_header {
1112 __be32 num_entries_used;
1114 }__attribute__((packed, aligned (4)));
1117 struct ipr_sdt_header hdr;
1118 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
1119 }__attribute__((packed, aligned (4)));
1122 struct ipr_sdt_header hdr;
1123 struct ipr_sdt_entry entry[1];
1124 }__attribute__((packed, aligned (4)));
1129 struct ipr_bus_attributes {
1137 struct ipr_sata_port {
1138 struct ipr_ioa_cfg *ioa_cfg;
1139 struct ata_port *ap;
1140 struct ipr_resource_entry *res;
1141 struct ipr_ioasa_gata ioasa;
1144 struct ipr_resource_entry {
1145 u8 needs_sync_complete:1;
1149 u8 resetting_device:1;
1151 u32 bus; /* AKA channel */
1152 u32 target; /* AKA id */
1154 #define IPR_ARRAY_VIRTUAL_BUS 0x1
1155 #define IPR_VSET_VIRTUAL_BUS 0x2
1156 #define IPR_IOAFP_VIRTUAL_BUS 0x3
1158 #define IPR_GET_RES_PHYS_LOC(res) \
1159 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1169 struct ipr_std_inq_data std_inq_data;
1173 struct scsi_lun dev_lun;
1176 struct ipr_ioa_cfg *ioa_cfg;
1177 struct scsi_device *sdev;
1178 struct ipr_sata_port *sata_port;
1179 struct list_head queue;
1180 }; /* struct ipr_resource_entry */
1182 struct ipr_resource_hdr {
1187 struct ipr_misc_cbs {
1188 struct ipr_ioa_vpd ioa_vpd;
1189 struct ipr_inquiry_page0 page0_data;
1190 struct ipr_inquiry_page3 page3_data;
1191 struct ipr_inquiry_cap cap;
1192 struct ipr_mode_pages mode_pages;
1193 struct ipr_supported_device supp_dev;
1196 struct ipr_interrupt_offsets {
1197 unsigned long set_interrupt_mask_reg;
1198 unsigned long clr_interrupt_mask_reg;
1199 unsigned long sense_interrupt_mask_reg;
1200 unsigned long clr_interrupt_reg;
1202 unsigned long sense_interrupt_reg;
1203 unsigned long ioarrin_reg;
1204 unsigned long sense_uproc_interrupt_reg;
1205 unsigned long set_uproc_interrupt_reg;
1206 unsigned long clr_uproc_interrupt_reg;
1209 struct ipr_interrupts {
1210 void __iomem *set_interrupt_mask_reg;
1211 void __iomem *clr_interrupt_mask_reg;
1212 void __iomem *sense_interrupt_mask_reg;
1213 void __iomem *clr_interrupt_reg;
1215 void __iomem *sense_interrupt_reg;
1216 void __iomem *ioarrin_reg;
1217 void __iomem *sense_uproc_interrupt_reg;
1218 void __iomem *set_uproc_interrupt_reg;
1219 void __iomem *clr_uproc_interrupt_reg;
1222 struct ipr_chip_cfg_t {
1225 struct ipr_interrupt_offsets regs;
1232 #define IPR_USE_LSI 0x00
1233 #define IPR_USE_MSI 0x01
1235 #define IPR_SIS32 0x00
1236 #define IPR_SIS64 0x01
1237 const struct ipr_chip_cfg_t *cfg;
1240 enum ipr_shutdown_type {
1241 IPR_SHUTDOWN_NORMAL = 0x00,
1242 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1243 IPR_SHUTDOWN_ABBREV = 0x80,
1244 IPR_SHUTDOWN_NONE = 0x100
1247 struct ipr_trace_entry {
1253 #define IPR_TRACE_START 0x00
1254 #define IPR_TRACE_FINISH 0xff
1270 struct scatterlist scatterlist[1];
1273 enum ipr_sdt_state {
1281 enum ipr_cache_state {
1288 /* Per-controller data */
1289 struct ipr_ioa_cfg {
1290 char eye_catcher[8];
1291 #define IPR_EYECATCHER "iprcfg"
1293 struct list_head queue;
1295 u8 allow_interrupts:1;
1296 u8 in_reset_reload:1;
1297 u8 in_ioa_bringdown:1;
1298 u8 ioa_unit_checked:1;
1302 u8 allow_ml_add_del:1;
1303 u8 needs_hard_reset:1;
1305 u8 needs_warm_reset:1;
1312 * Bitmaps for SIS64 generated target values
1314 unsigned long *target_ids;
1315 unsigned long *array_ids;
1316 unsigned long *vset_ids;
1318 enum ipr_cache_state cache_state;
1319 u16 type; /* CCIN of the card */
1322 #define IPR_MAX_LOG_LEVEL 4
1323 #define IPR_DEFAULT_LOG_LEVEL 2
1325 #define IPR_NUM_TRACE_INDEX_BITS 8
1326 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1327 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1328 char trace_start[8];
1329 #define IPR_TRACE_START_LABEL "trace"
1330 struct ipr_trace_entry *trace;
1331 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1334 * Queue for free command blocks
1336 char ipr_free_label[8];
1337 #define IPR_FREEQ_LABEL "free-q"
1338 struct list_head free_q;
1341 * Queue for command blocks outstanding to the adapter
1343 char ipr_pending_label[8];
1344 #define IPR_PENDQ_LABEL "pend-q"
1345 struct list_head pending_q;
1347 char cfg_table_start[8];
1348 #define IPR_CFG_TBL_START "cfg"
1350 struct ipr_config_table *cfg_table;
1351 struct ipr_config_table64 *cfg_table64;
1353 dma_addr_t cfg_table_dma;
1355 u32 max_devs_supported;
1357 char resource_table_label[8];
1358 #define IPR_RES_TABLE_LABEL "res_tbl"
1359 struct ipr_resource_entry *res_entries;
1360 struct list_head free_res_q;
1361 struct list_head used_res_q;
1363 char ipr_hcam_label[8];
1364 #define IPR_HCAM_LABEL "hcams"
1365 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1366 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1367 struct list_head hostrcb_free_q;
1368 struct list_head hostrcb_pending_q;
1371 dma_addr_t host_rrq_dma;
1372 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1373 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
1374 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
1375 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1376 volatile __be32 *hrrq_start;
1377 volatile __be32 *hrrq_end;
1378 volatile __be32 *hrrq_curr;
1379 volatile u32 toggle_bit;
1381 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1383 unsigned int transop_timeout;
1384 const struct ipr_chip_cfg_t *chip_cfg;
1385 const struct ipr_chip_t *ipr_chip;
1387 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1388 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1389 void __iomem *ioa_mailbox;
1390 struct ipr_interrupts regs;
1392 u16 saved_pcix_cmd_reg;
1398 struct Scsi_Host *host;
1399 struct pci_dev *pdev;
1400 struct ipr_sglist *ucode_sglist;
1401 u8 saved_mode_page_len;
1403 struct work_struct work_q;
1405 wait_queue_head_t reset_wait_q;
1406 wait_queue_head_t msi_wait_q;
1408 struct ipr_dump *dump;
1409 enum ipr_sdt_state sdt_state;
1411 struct ipr_misc_cbs *vpd_cbs;
1412 dma_addr_t vpd_cbs_dma;
1414 struct pci_pool *ipr_cmd_pool;
1416 struct ipr_cmnd *reset_cmd;
1417 int (*reset) (struct ipr_cmnd *);
1419 struct ata_host ata_host;
1420 char ipr_cmd_label[8];
1421 #define IPR_CMD_LABEL "ipr_cmd"
1422 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
1423 dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1424 }; /* struct ipr_ioa_cfg */
1427 struct ipr_ioarcb ioarcb;
1429 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1430 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1431 struct ipr_ata64_ioadl ata_ioadl;
1433 struct ipr_ioasa ioasa;
1434 struct list_head queue;
1435 struct scsi_cmnd *scsi_cmd;
1436 struct ata_queued_cmd *qc;
1437 struct completion completion;
1438 struct timer_list timer;
1439 void (*done) (struct ipr_cmnd *);
1440 int (*job_step) (struct ipr_cmnd *);
1441 int (*job_step_failed) (struct ipr_cmnd *);
1443 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1444 dma_addr_t sense_buffer_dma;
1445 unsigned short dma_use_sg;
1446 dma_addr_t dma_addr;
1447 struct ipr_cmnd *sibling;
1449 enum ipr_shutdown_type shutdown_type;
1450 struct ipr_hostrcb *hostrcb;
1451 unsigned long time_left;
1452 unsigned long scratch;
1453 struct ipr_resource_entry *res;
1454 struct scsi_device *sdev;
1457 struct ipr_ioa_cfg *ioa_cfg;
1460 struct ipr_ses_table_entry {
1461 char product_id[17];
1462 char compare_product_id_byte[17];
1463 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1466 struct ipr_dump_header {
1468 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1471 u32 first_entry_offset;
1473 #define IPR_DUMP_STATUS_SUCCESS 0
1474 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1475 #define IPR_DUMP_STATUS_FAILED 0xffffffff
1477 #define IPR_DUMP_OS_LINUX 0x4C4E5558
1479 #define IPR_DUMP_DRIVER_NAME 0x49505232
1480 }__attribute__((packed, aligned (4)));
1482 struct ipr_dump_entry_header {
1484 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1489 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1490 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1492 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1493 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1494 #define IPR_DUMP_TRACE_ID 0x54524143
1495 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1496 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1497 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1498 #define IPR_DUMP_PEND_OPS 0x414F5053
1500 }__attribute__((packed, aligned (4)));
1502 struct ipr_dump_location_entry {
1503 struct ipr_dump_entry_header hdr;
1505 }__attribute__((packed));
1507 struct ipr_dump_trace_entry {
1508 struct ipr_dump_entry_header hdr;
1509 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1510 }__attribute__((packed, aligned (4)));
1512 struct ipr_dump_version_entry {
1513 struct ipr_dump_entry_header hdr;
1514 u8 version[sizeof(IPR_DRIVER_VERSION)];
1517 struct ipr_dump_ioa_type_entry {
1518 struct ipr_dump_entry_header hdr;
1523 struct ipr_driver_dump {
1524 struct ipr_dump_header hdr;
1525 struct ipr_dump_version_entry version_entry;
1526 struct ipr_dump_location_entry location_entry;
1527 struct ipr_dump_ioa_type_entry ioa_type_entry;
1528 struct ipr_dump_trace_entry trace_entry;
1529 }__attribute__((packed));
1531 struct ipr_ioa_dump {
1532 struct ipr_dump_entry_header hdr;
1534 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1536 u32 next_page_index;
1539 #define IPR_SDT_FMT2 2
1540 #define IPR_SDT_UNKNOWN 3
1541 }__attribute__((packed, aligned (4)));
1545 struct ipr_ioa_cfg *ioa_cfg;
1546 struct ipr_driver_dump driver_dump;
1547 struct ipr_ioa_dump ioa_dump;
1550 struct ipr_error_table_t {
1557 struct ipr_software_inq_lid_info {
1559 __be32 timestamp[3];
1560 }__attribute__((packed, aligned (4)));
1562 struct ipr_ucode_image_header {
1563 __be32 header_length;
1564 __be32 lid_table_offset;
1567 u8 minor_release[2];
1569 char eyecatcher[16];
1571 struct ipr_software_inq_lid_info lid[1];
1572 }__attribute__((packed, aligned (4)));
1577 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1579 #ifdef CONFIG_SCSI_IPR_TRACE
1580 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1581 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1583 #define ipr_create_trace_file(kobj, attr) 0
1584 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1587 #ifdef CONFIG_SCSI_IPR_DUMP
1588 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1589 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1591 #define ipr_create_dump_file(kobj, attr) 0
1592 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1596 * Error logging macros
1598 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1599 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1600 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1602 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1603 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1604 bus, target, lun, ##__VA_ARGS__)
1606 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1607 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1609 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1610 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1611 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1613 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1614 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1616 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1618 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1619 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1621 ipr_err(fmt": %d:%d:%d:%d\n", \
1622 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1623 (res).bus, (res).target, (res).lun); \
1627 #define ipr_hcam_err(hostrcb, fmt, ...) \
1629 if (ipr_is_device(hostrcb)) { \
1630 if ((hostrcb)->ioa_cfg->sis64) { \
1631 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1632 ipr_format_resource_path(&hostrcb->hcam.u.error64.fd_res_path[0], \
1633 &hostrcb->rp_buffer[0]), \
1636 ipr_ra_err((hostrcb)->ioa_cfg, \
1637 (hostrcb)->hcam.u.error.fd_res_addr, \
1638 fmt, __VA_ARGS__); \
1641 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1645 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1646 __FILE__, __func__, __LINE__)
1648 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1649 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1651 #define ipr_err_separator \
1652 ipr_err("----------------------------------------------------------\n")
1660 * ipr_is_ioa_resource - Determine if a resource is the IOA
1661 * @res: resource entry struct
1664 * 1 if IOA / 0 if not IOA
1666 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1668 return res->type == IPR_RES_TYPE_IOAFP;
1672 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1673 * @res: resource entry struct
1676 * 1 if AF DASD / 0 if not AF DASD
1678 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1680 return res->type == IPR_RES_TYPE_AF_DASD ||
1681 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1685 * ipr_is_vset_device - Determine if a resource is a VSET
1686 * @res: resource entry struct
1689 * 1 if VSET / 0 if not VSET
1691 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1693 return res->type == IPR_RES_TYPE_VOLUME_SET;
1697 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1698 * @res: resource entry struct
1701 * 1 if GSCSI / 0 if not GSCSI
1703 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1705 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1709 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1710 * @res: resource entry struct
1713 * 1 if SCSI disk / 0 if not SCSI disk
1715 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1717 if (ipr_is_af_dasd_device(res) ||
1718 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1725 * ipr_is_gata - Determine if a resource is a generic ATA resource
1726 * @res: resource entry struct
1729 * 1 if GATA / 0 if not GATA
1731 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1733 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1737 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1738 * @res: resource entry struct
1741 * 1 if NACA queueing model / 0 if not NACA queueing model
1743 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1745 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1751 * ipr_is_device - Determine if the hostrcb structure is related to a device
1752 * @hostrcb: host resource control blocks struct
1755 * 1 if AF / 0 if not AF
1757 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1759 struct ipr_res_addr *res_addr;
1762 if (hostrcb->ioa_cfg->sis64) {
1763 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1764 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1765 res_path[0] == 0x81) && res_path[2] != 0xFF)
1768 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1770 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1771 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1778 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1779 * @sdt_word: SDT address
1782 * 1 if format 2 / 0 if not
1784 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1786 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1789 case IPR_SDT_FMT2_BAR0_SEL:
1790 case IPR_SDT_FMT2_BAR1_SEL:
1791 case IPR_SDT_FMT2_BAR2_SEL:
1792 case IPR_SDT_FMT2_BAR3_SEL:
1793 case IPR_SDT_FMT2_BAR4_SEL:
1794 case IPR_SDT_FMT2_BAR5_SEL:
1795 case IPR_SDT_FMT2_EXP_ROM_SEL: