2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
24 /* general boundary defintions */
25 #define SENSEINFOBYTES 32 /* may vary between hbas */
26 #define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */
27 #define HPSA_SG_CHAIN 0x80000000
28 #define HPSA_SG_LAST 0x40000000
29 #define MAXREPLYQS 256
31 /* Command Status value */
32 #define CMD_SUCCESS 0x0000
33 #define CMD_TARGET_STATUS 0x0001
34 #define CMD_DATA_UNDERRUN 0x0002
35 #define CMD_DATA_OVERRUN 0x0003
36 #define CMD_INVALID 0x0004
37 #define CMD_PROTOCOL_ERR 0x0005
38 #define CMD_HARDWARE_ERR 0x0006
39 #define CMD_CONNECTION_LOST 0x0007
40 #define CMD_ABORTED 0x0008
41 #define CMD_ABORT_FAILED 0x0009
42 #define CMD_UNSOLICITED_ABORT 0x000A
43 #define CMD_TIMEOUT 0x000B
44 #define CMD_UNABORTABLE 0x000C
45 #define CMD_IOACCEL_DISABLED 0x000E
48 /* Unit Attentions ASC's as defined for the MSA2012sa */
49 #define POWER_OR_RESET 0x29
50 #define STATE_CHANGED 0x2a
51 #define UNIT_ATTENTION_CLEARED 0x2f
52 #define LUN_FAILED 0x3e
53 #define REPORT_LUNS_CHANGED 0x3f
55 /* Unit Attentions ASCQ's as defined for the MSA2012sa */
57 /* These ASCQ's defined for ASC = POWER_OR_RESET */
58 #define POWER_ON_RESET 0x00
59 #define POWER_ON_REBOOT 0x01
60 #define SCSI_BUS_RESET 0x02
61 #define MSA_TARGET_RESET 0x03
62 #define CONTROLLER_FAILOVER 0x04
63 #define TRANSCEIVER_SE 0x05
64 #define TRANSCEIVER_LVD 0x06
66 /* These ASCQ's defined for ASC = STATE_CHANGED */
67 #define RESERVATION_PREEMPTED 0x03
68 #define ASYM_ACCESS_CHANGED 0x06
69 #define LUN_CAPACITY_CHANGED 0x09
71 /* transfer direction */
72 #define XFER_NONE 0x00
73 #define XFER_WRITE 0x01
74 #define XFER_READ 0x02
75 #define XFER_RSVD 0x03
78 #define ATTR_UNTAGGED 0x00
79 #define ATTR_SIMPLE 0x04
80 #define ATTR_HEADOFQUEUE 0x05
81 #define ATTR_ORDERED 0x06
87 #define TYPE_IOACCEL2_CMD 0x81 /* 0x81 is not used by hardware */
90 #define HPSA_TASK_MANAGEMENT 0x00
91 #define HPSA_RESET 0x01
92 #define HPSA_SCAN 0x02
93 #define HPSA_NOOP 0x03
95 #define HPSA_CTLR_RESET_TYPE 0x00
96 #define HPSA_BUS_RESET_TYPE 0x01
97 #define HPSA_TARGET_RESET_TYPE 0x03
98 #define HPSA_LUN_RESET_TYPE 0x04
99 #define HPSA_NEXUS_RESET_TYPE 0x05
101 /* Task Management Functions */
102 #define HPSA_TMF_ABORT_TASK 0x00
103 #define HPSA_TMF_ABORT_TASK_SET 0x01
104 #define HPSA_TMF_CLEAR_ACA 0x02
105 #define HPSA_TMF_CLEAR_TASK_SET 0x03
106 #define HPSA_TMF_QUERY_TASK 0x04
107 #define HPSA_TMF_QUERY_TASK_SET 0x05
108 #define HPSA_TMF_QUERY_ASYNCEVENT 0x06
112 /* config space register offsets */
113 #define CFG_VENDORID 0x00
114 #define CFG_DEVICEID 0x02
115 #define CFG_I2OBAR 0x10
116 #define CFG_MEM1BAR 0x14
118 /* i2o space register offsets */
119 #define I2O_IBDB_SET 0x20
120 #define I2O_IBDB_CLEAR 0x70
121 #define I2O_INT_STATUS 0x30
122 #define I2O_INT_MASK 0x34
123 #define I2O_IBPOST_Q 0x40
124 #define I2O_OBPOST_Q 0x44
125 #define I2O_DMA1_CFG 0x214
127 /* Configuration Table */
128 #define CFGTBL_ChangeReq 0x00000001l
129 #define CFGTBL_AccCmds 0x00000001l
130 #define DOORBELL_CTLR_RESET 0x00000004l
131 #define DOORBELL_CTLR_RESET2 0x00000020l
132 #define DOORBELL_CLEAR_EVENTS 0x00000040l
134 #define CFGTBL_Trans_Simple 0x00000002l
135 #define CFGTBL_Trans_Performant 0x00000004l
136 #define CFGTBL_Trans_io_accel1 0x00000080l
137 #define CFGTBL_Trans_io_accel2 0x00000100l
138 #define CFGTBL_Trans_use_short_tags 0x20000000l
139 #define CFGTBL_Trans_enable_directed_msix (1 << 30)
141 #define CFGTBL_BusType_Ultra2 0x00000001l
142 #define CFGTBL_BusType_Ultra3 0x00000002l
143 #define CFGTBL_BusType_Fibre1G 0x00000100l
144 #define CFGTBL_BusType_Fibre2G 0x00000200l
146 /* VPD Inquiry types */
147 #define HPSA_VPD_SUPPORTED_PAGES 0x00
148 #define HPSA_VPD_LV_DEVICE_GEOMETRY 0xC1
149 #define HPSA_VPD_LV_IOACCEL_STATUS 0xC2
150 #define HPSA_VPD_LV_STATUS 0xC3
151 #define HPSA_VPD_HEADER_SZ 4
153 /* Logical volume states */
154 #define HPSA_VPD_LV_STATUS_UNSUPPORTED 0xff
155 #define HPSA_LV_OK 0x0
156 #define HPSA_LV_UNDERGOING_ERASE 0x0F
157 #define HPSA_LV_UNDERGOING_RPI 0x12
158 #define HPSA_LV_PENDING_RPI 0x13
159 #define HPSA_LV_ENCRYPTED_NO_KEY 0x14
160 #define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15
161 #define HPSA_LV_UNDERGOING_ENCRYPTION 0x16
162 #define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17
163 #define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18
164 #define HPSA_LV_PENDING_ENCRYPTION 0x19
165 #define HPSA_LV_PENDING_ENCRYPTION_REKEYING 0x1A
177 /* FIXME this is a per controller value (barf!) */
178 #define HPSA_MAX_LUN 1024
179 #define HPSA_MAX_PHYS_LUN 1024
180 #define MAX_EXT_TARGETS 32
181 #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \
182 MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */
184 /* SCSI-3 Commands */
187 #define HPSA_INQUIRY 0x12
192 #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */
193 #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */
194 #define HPSA_REPORT_PHYS_EXTENDED 0x02
195 #define HPSA_CISS_READ 0xc0 /* CISS Read */
196 #define HPSA_GET_RAID_MAP 0xc8 /* CISS Get RAID Layout Map */
198 #define RAID_MAP_MAX_ENTRIES 256
200 struct raid_map_disk_data {
201 u32 ioaccel_handle; /**< Handle to access this disk via the
203 u8 xor_mult[2]; /**< XOR multipliers for this position,
204 * valid for data disks only */
208 struct raid_map_data {
209 u32 structure_size; /* Size of entire structure in bytes */
210 u32 volume_blk_size; /* bytes / block in the volume */
211 u64 volume_blk_cnt; /* logical blocks on the volume */
212 u8 phys_blk_shift; /* Shift factor to convert between
213 * units of logical blocks and physical
215 u8 parity_rotation_shift; /* Shift factor to convert between units
216 * of logical stripes and physical
218 u16 strip_size; /* blocks used on each disk / stripe */
219 u64 disk_starting_blk; /* First disk block used in volume */
220 u64 disk_blk_cnt; /* disk blocks used by volume / disk */
221 u16 data_disks_per_row; /* data disk entries / row in the map */
222 u16 metadata_disks_per_row; /* mirror/parity disk entries / row
224 u16 row_cnt; /* rows in each layout map */
225 u16 layout_map_count; /* layout maps (1 map per mirror/parity
227 u16 flags; /* Bit 0 set if encryption enabled */
228 #define RAID_MAP_FLAG_ENCRYPT_ON 0x01
229 u16 dekindex; /* Data encryption key index. */
231 struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES];
234 struct ReportLUNdata {
236 u8 extended_response_flag;
238 u8 LUN[HPSA_MAX_LUN][8];
241 struct ext_report_lun_entry {
246 u8 lun_count; /* multi-lun device, how many luns */
248 u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */
251 struct ReportExtendedLUNdata {
253 u8 extended_response_flag;
255 struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN];
258 struct SenseSubsystem_info {
265 #define BMIC_READ 0x26
266 #define BMIC_WRITE 0x27
267 #define BMIC_CACHE_FLUSH 0xc2
268 #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */
269 #define BMIC_FLASH_FIRMWARE 0xF7
270 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
272 /* Command List Structure */
296 /* 2 level target device addr */
297 union SCSI3Addr Target[2];
308 union SCSI3Addr SCSI3Lun[4];
309 struct PhysDevAddr PhysDev;
310 struct LogDevAddr LogDev;
313 struct CommandListHeader {
321 struct RequestBlock {
326 * attr: middle 3 bits
330 #define TYPE_ATTR_DIR(t, a, d) ((((d) & 0x03) << 6) |\
331 (((a) & 0x07) << 3) |\
333 #define GET_TYPE(tad) ((tad) & 0x07)
334 #define GET_ATTR(tad) (((tad) >> 3) & 0x07)
335 #define GET_DIR(tad) (((tad) >> 6) & 0x03)
340 struct ErrDescriptor {
345 struct SGDescriptor {
359 u8 offense_size; /* size of offending entry */
360 u8 offense_num; /* byte # of offense 0-base */
369 union MoreErrInfo MoreErrInfo;
370 u8 SenseInfo[SENSEINFOBYTES];
373 #define CMD_IOCTL_PEND 0x01
374 #define CMD_SCSI 0x03
375 #define CMD_IOACCEL1 0x04
376 #define CMD_IOACCEL2 0x05
378 #define DIRECT_LOOKUP_SHIFT 5
379 #define DIRECT_LOOKUP_BIT 0x10
380 #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1))
382 #define HPSA_ERROR_BIT 0x02
383 struct ctlr_info; /* defined in hpsa.h */
384 /* The size of this structure needs to be divisible by 32
385 * on all architectures because low 5 bits of the addresses
386 * are used as follows:
388 * bit 0: to device, used to indicate "performant mode" command
389 * from device, indidcates error status.
390 * bit 1-3: to device, indicates block fetch table entry for
391 * reducing DMA in fetching commands from host memory.
392 * bit 4: used to indicate whether tag is "direct lookup" (index),
396 #define COMMANDLIST_ALIGNMENT 128
398 struct CommandListHeader Header;
399 struct RequestBlock Request;
400 struct ErrDescriptor ErrDesc;
401 struct SGDescriptor SG[SG_ENTRIES_IN_CMD];
402 /* information associated with the command */
403 u32 busaddr; /* physical addr of this record */
404 struct ErrorInfo *err_info; /* pointer to the allocated mem */
408 struct list_head list;
409 struct completion *waiting;
411 } __aligned(COMMANDLIST_ALIGNMENT);
413 /* Max S/G elements in I/O accelerator command */
414 #define IOACCEL1_MAXSGENTRIES 24
415 #define IOACCEL2_MAXSGENTRIES 28
418 * Structure for I/O accelerator (mode 1) commands.
419 * Note that this structure must be 128-byte aligned in size.
421 #define IOACCEL1_COMMANDLIST_ALIGNMENT 128
422 struct io_accel1_cmd {
423 u16 dev_handle; /* 0x00 - 0x01 */
424 u8 reserved1; /* 0x02 */
425 u8 function; /* 0x03 */
426 u8 reserved2[8]; /* 0x04 - 0x0B */
427 u32 err_info; /* 0x0C - 0x0F */
428 u8 reserved3[2]; /* 0x10 - 0x11 */
429 u8 err_info_len; /* 0x12 */
430 u8 reserved4; /* 0x13 */
431 u8 sgl_offset; /* 0x14 */
432 u8 reserved5[7]; /* 0x15 - 0x1B */
433 u32 transfer_len; /* 0x1C - 0x1F */
434 u8 reserved6[4]; /* 0x20 - 0x23 */
435 u16 io_flags; /* 0x24 - 0x25 */
436 u8 reserved7[14]; /* 0x26 - 0x33 */
437 u8 LUN[8]; /* 0x34 - 0x3B */
438 u32 control; /* 0x3C - 0x3F */
439 u8 CDB[16]; /* 0x40 - 0x4F */
440 u8 reserved8[16]; /* 0x50 - 0x5F */
441 u16 host_context_flags; /* 0x60 - 0x61 */
442 u16 timeout_sec; /* 0x62 - 0x63 */
443 u8 ReplyQueue; /* 0x64 */
444 u8 reserved9[3]; /* 0x65 - 0x67 */
445 u64 tag; /* 0x68 - 0x6F */
446 u64 host_addr; /* 0x70 - 0x77 */
447 u8 CISS_LUN[8]; /* 0x78 - 0x7F */
448 struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES];
449 } __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT);
451 #define IOACCEL1_FUNCTION_SCSIIO 0x00
452 #define IOACCEL1_SGLOFFSET 32
454 #define IOACCEL1_IOFLAGS_IO_REQ 0x4000
455 #define IOACCEL1_IOFLAGS_CDBLEN_MASK 0x001F
456 #define IOACCEL1_IOFLAGS_CDBLEN_MAX 16
458 #define IOACCEL1_CONTROL_NODATAXFER 0x00000000
459 #define IOACCEL1_CONTROL_DATA_OUT 0x01000000
460 #define IOACCEL1_CONTROL_DATA_IN 0x02000000
461 #define IOACCEL1_CONTROL_TASKPRIO_MASK 0x00007800
462 #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11
463 #define IOACCEL1_CONTROL_SIMPLEQUEUE 0x00000000
464 #define IOACCEL1_CONTROL_HEADOFQUEUE 0x00000100
465 #define IOACCEL1_CONTROL_ORDEREDQUEUE 0x00000200
466 #define IOACCEL1_CONTROL_ACA 0x00000400
468 #define IOACCEL1_HCFLAGS_CISS_FORMAT 0x0013
470 #define IOACCEL1_BUSADDR_CMDTYPE 0x00000060
472 struct ioaccel2_sg_element {
477 #define IOACCEL2_CHAIN 0x80
481 * SCSI Response Format structure for IO Accelerator Mode 2
483 struct io_accel2_scsi_response {
485 #define IOACCEL2_IU_TYPE_SRF 0x60
487 u8 req_id[4]; /* request identifier */
489 u8 serv_response; /* service response */
490 #define IOACCEL2_SERV_RESPONSE_COMPLETE 0x000
491 #define IOACCEL2_SERV_RESPONSE_FAILURE 0x001
492 #define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE 0x002
493 #define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS 0x003
494 #define IOACCEL2_SERV_RESPONSE_TMF_REJECTED 0x004
495 #define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN 0x005
496 u8 status; /* status */
497 #define IOACCEL2_STATUS_SR_TASK_COMP_GOOD 0x00
498 #define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND 0x02
499 #define IOACCEL2_STATUS_SR_TASK_COMP_BUSY 0x08
500 #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON 0x18
501 #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL 0x28
502 #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED 0x40
503 #define IOACCEL2_STATUS_SR_IOACCEL_DISABLED 0x0E
504 u8 data_present; /* low 2 bits */
505 #define IOACCEL2_NO_DATAPRESENT 0x000
506 #define IOACCEL2_RESPONSE_DATAPRESENT 0x001
507 #define IOACCEL2_SENSE_DATA_PRESENT 0x002
508 #define IOACCEL2_RESERVED 0x003
509 u8 sense_data_len; /* sense/response data length */
510 u8 resid_cnt[4]; /* residual count */
511 u8 sense_data_buff[32]; /* sense/response data buffer */
515 * Structure for I/O accelerator (mode 2 or m2) commands.
516 * Note that this structure must be 128-byte aligned in size.
518 #define IOACCEL2_COMMANDLIST_ALIGNMENT 128
519 struct io_accel2_cmd {
520 u8 IU_type; /* IU Type */
521 u8 direction; /* direction, memtype, and encryption */
522 #define IOACCEL2_DIRECTION_MASK 0x03 /* bits 0,1: direction */
523 #define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */
524 /* 0b=PCIe, 1b=DDR */
525 #define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */
527 u8 reply_queue; /* Reply Queue ID */
528 u8 reserved1; /* Reserved */
529 u32 scsi_nexus; /* Device Handle */
530 u32 Tag; /* cciss tag, lower 4 bytes only */
531 u32 tweak_lower; /* Encryption tweak, lower 4 bytes */
532 u8 cdb[16]; /* SCSI Command Descriptor Block */
533 u8 cciss_lun[8]; /* 8 byte SCSI address */
534 u32 data_len; /* Total bytes to transfer */
535 u8 cmd_priority_task_attr; /* priority and task attrs */
536 #define IOACCEL2_PRIORITY_MASK 0x78
537 #define IOACCEL2_ATTR_MASK 0x07
538 u8 sg_count; /* Number of sg elements */
539 u16 dekindex; /* Data encryption key index */
540 u64 err_ptr; /* Error Pointer */
541 u32 err_len; /* Error Length*/
542 u32 tweak_upper; /* Encryption tweak, upper 4 bytes */
543 struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES];
544 struct io_accel2_scsi_response error_data;
545 } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT);
548 * defines for Mode 2 command struct
549 * FIXME: this can't be all I need mfm
551 #define IOACCEL2_IU_TYPE 0x40
552 #define IOACCEL2_IU_TMF_TYPE 0x41
553 #define IOACCEL2_DIR_NO_DATA 0x00
554 #define IOACCEL2_DIR_DATA_IN 0x01
555 #define IOACCEL2_DIR_DATA_OUT 0x02
557 * SCSI Task Management Request format for Accelerator Mode 2
559 struct hpsa_tmf_struct {
560 u8 iu_type; /* Information Unit Type */
561 u8 reply_queue; /* Reply Queue ID */
562 u8 tmf; /* Task Management Function */
563 u8 reserved1; /* byte 3 Reserved */
564 u32 it_nexus; /* SCSI I-T Nexus */
565 u8 lun_id[8]; /* LUN ID for TMF request */
566 u64 tag; /* cciss tag associated w/ request */
567 u64 abort_tag; /* cciss tag of SCSI cmd or task to abort */
568 u64 error_ptr; /* Error Pointer */
569 u32 error_len; /* Error Length */
572 /* Configuration Table Structure */
574 u32 TransportRequest;
575 u32 command_pool_addr_hi;
580 #define SIMPLE_MODE 0x02
581 #define PERFORMANT_MODE 0x04
582 #define MEMQ_MODE 0x08
583 #define IOACCEL_MODE_1 0x80
585 #define DRIVER_SUPPORT_UA_ENABLE 0x00000001
590 u32 TransportSupport;
592 struct HostWrite HostWrite;
595 u32 TransMethodOffset;
599 #define ENABLE_SCSI_PREFETCH 0x100
600 #define ENABLE_UNIT_ATTN 0x01
601 u32 MaxScatterGatherElements;
603 u32 MaxPhysicalDevices;
604 u32 MaxPhysicalDrivesPerLogicalUnit;
605 u32 MaxPerformantModeCommands;
607 u32 PowerConservationSupport;
608 u32 PowerConservationEnable;
611 u8 reserved[0x78 - 0x70];
612 u32 misc_fw_support; /* offset 0x78 */
613 #define MISC_FW_DOORBELL_RESET (0x02)
614 #define MISC_FW_DOORBELL_RESET2 (0x010)
615 #define MISC_FW_RAID_OFFLOAD_BASIC (0x020)
616 #define MISC_FW_EVENT_NOTIFY (0x080)
617 u8 driver_version[32];
618 u32 max_cached_write_size;
619 u8 driver_scratchpad[16];
620 u32 max_error_info_length;
621 u32 io_accel_max_embedded_sg_count;
622 u32 io_accel_request_size_offset;
624 #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30)
625 #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31)
626 u32 clear_event_notify;
629 #define NUM_BLOCKFETCH_ENTRIES 8
630 struct TransTable_struct {
631 u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES];
634 u32 RepQCtrAddrLow32;
635 u32 RepQCtrAddrHigh32;
636 #define MAX_REPLY_QUEUES 64
637 struct vals32 RepQAddr[MAX_REPLY_QUEUES];
640 struct hpsa_pci_info {
642 unsigned char dev_fn;
643 unsigned short domain;
648 #endif /* HPSA_CMD_H */