2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
24 #include <scsi/scsicam.h>
31 struct access_method {
32 void (*submit_command)(struct ctlr_info *h,
33 struct CommandList *c);
34 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
35 unsigned long (*fifo_full)(struct ctlr_info *h);
36 bool (*intr_pending)(struct ctlr_info *h);
37 unsigned long (*command_completed)(struct ctlr_info *h);
40 struct hpsa_scsi_dev_t {
42 int bus, target, lun; /* as presented to the OS */
43 unsigned char scsi3addr[8]; /* as presented to the HW */
44 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
45 unsigned char device_id[16]; /* from inquiry pg. 0x83 */
46 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
47 unsigned char model[16]; /* bytes 16-31 of inquiry data */
48 unsigned char raid_level; /* from inquiry page 0xC1 */
59 int nr_cmds; /* Number of commands allowed on this controller */
60 struct CfgTable __iomem *cfgtable;
62 int interrupts_enabled;
65 int commands_outstanding;
66 int max_outstanding; /* Debug */
67 int usage_count; /* number of opens all all minor devices */
68 # define PERF_MODE_INT 0
69 # define DOORBELL_INT 1
70 # define SIMPLE_MODE_INT 2
71 # define MEMQ_MODE_INT 3
73 unsigned int msix_vector;
74 unsigned int msi_vector;
75 int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
76 struct access_method access;
78 /* queue and queue Info */
79 struct list_head reqQ;
80 struct list_head cmpQ;
82 unsigned int maxQsinceinit;
86 u8 max_cmd_sg_entries;
88 struct SGDescriptor **cmd_sg_list;
90 /* pointers to command and error info pool */
91 struct CommandList *cmd_pool;
92 dma_addr_t cmd_pool_dhandle;
93 struct ErrorInfo *errinfo_pool;
94 dma_addr_t errinfo_pool_dhandle;
95 unsigned long *cmd_pool_bits;
100 wait_queue_head_t scan_wait_queue;
102 struct Scsi_Host *scsi_host;
103 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
104 int ndevices; /* number of used elements in .dev[] array. */
105 struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
107 * Performant mode tables.
111 struct TransTable_struct *transtable;
112 unsigned long transMethod;
115 * Performant mode completion buffer
118 dma_addr_t reply_pool_dhandle;
119 u64 *reply_pool_head;
120 size_t reply_pool_size;
121 unsigned char reply_pool_wraparound;
122 u32 *blockFetchTable;
123 unsigned char *hba_inquiry_data;
124 u64 last_intr_timestamp;
126 u64 last_heartbeat_timestamp;
127 u32 heartbeat_sample_interval;
128 atomic_t firmware_flash_in_progress;
130 struct list_head lockup_list;
132 #define HPSA_ABORT_MSG 0
133 #define HPSA_DEVICE_RESET_MSG 1
134 #define HPSA_RESET_TYPE_CONTROLLER 0x00
135 #define HPSA_RESET_TYPE_BUS 0x01
136 #define HPSA_RESET_TYPE_TARGET 0x03
137 #define HPSA_RESET_TYPE_LUN 0x04
138 #define HPSA_MSG_SEND_RETRY_LIMIT 10
139 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
141 /* Maximum time in seconds driver will wait for command completions
142 * when polling before giving up.
144 #define HPSA_MAX_POLL_TIME_SECS (20)
146 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
147 * how many times to retry TEST UNIT READY on a device
148 * while waiting for it to become ready before giving up.
149 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
150 * between sending TURs while waiting for a device
153 #define HPSA_TUR_RETRY_LIMIT (20)
154 #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
156 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
157 * to become ready, in seconds, before giving up on it.
158 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
159 * between polling the board to see if it is ready, in
160 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
161 * HPSA_BOARD_READY_ITERATIONS are derived from those.
163 #define HPSA_BOARD_READY_WAIT_SECS (120)
164 #define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
165 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
166 #define HPSA_BOARD_READY_POLL_INTERVAL \
167 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
168 #define HPSA_BOARD_READY_ITERATIONS \
169 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
170 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
171 #define HPSA_BOARD_NOT_READY_ITERATIONS \
172 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
173 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
174 #define HPSA_POST_RESET_PAUSE_MSECS (3000)
175 #define HPSA_POST_RESET_NOOP_RETRIES (12)
177 /* Defining the diffent access_menthods */
179 * Memory mapped FIFO interface (SMART 53xx cards)
181 #define SA5_DOORBELL 0x20
182 #define SA5_REQUEST_PORT_OFFSET 0x40
183 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
184 #define SA5_REPLY_PORT_OFFSET 0x44
185 #define SA5_INTR_STATUS 0x30
186 #define SA5_SCRATCHPAD_OFFSET 0xB0
188 #define SA5_CTCFG_OFFSET 0xB4
189 #define SA5_CTMEM_OFFSET 0xB8
191 #define SA5_INTR_OFF 0x08
192 #define SA5B_INTR_OFF 0x04
193 #define SA5_INTR_PENDING 0x08
194 #define SA5B_INTR_PENDING 0x04
195 #define FIFO_EMPTY 0xffffffff
196 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
198 #define HPSA_ERROR_BIT 0x02
200 /* Performant mode flags */
201 #define SA5_PERF_INTR_PENDING 0x04
202 #define SA5_PERF_INTR_OFF 0x05
203 #define SA5_OUTDB_STATUS_PERF_BIT 0x01
204 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
205 #define SA5_OUTDB_CLEAR 0xA0
206 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
207 #define SA5_OUTDB_STATUS 0x9C
210 #define HPSA_INTR_ON 1
211 #define HPSA_INTR_OFF 0
213 Send the command to the hardware
215 static void SA5_submit_command(struct ctlr_info *h,
216 struct CommandList *c)
218 dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
219 c->Header.Tag.lower);
220 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
221 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
222 h->commands_outstanding++;
223 if (h->commands_outstanding > h->max_outstanding)
224 h->max_outstanding = h->commands_outstanding;
228 * This card is the opposite of the other cards.
229 * 0 turns interrupts on...
230 * 0x08 turns them off...
232 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
234 if (val) { /* Turn interrupts on */
235 h->interrupts_enabled = 1;
236 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
237 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
238 } else { /* Turn them off */
239 h->interrupts_enabled = 0;
241 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
242 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
246 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
248 if (val) { /* turn on interrupts */
249 h->interrupts_enabled = 1;
250 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
251 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
253 h->interrupts_enabled = 0;
254 writel(SA5_PERF_INTR_OFF,
255 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
256 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
260 static unsigned long SA5_performant_completed(struct ctlr_info *h)
262 unsigned long register_value = FIFO_EMPTY;
264 /* flush the controller write of the reply queue by reading
265 * outbound doorbell status register.
267 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
268 /* msi auto clears the interrupt pending bit. */
269 if (!(h->msi_vector || h->msix_vector)) {
270 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
271 /* Do a read in order to flush the write to the controller
274 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
277 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
278 register_value = *(h->reply_pool_head);
279 (h->reply_pool_head)++;
280 h->commands_outstanding--;
282 register_value = FIFO_EMPTY;
284 /* Check for wraparound */
285 if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
286 h->reply_pool_head = h->reply_pool;
287 h->reply_pool_wraparound ^= 1;
290 return register_value;
294 * Returns true if fifo is full.
297 static unsigned long SA5_fifo_full(struct ctlr_info *h)
299 if (h->commands_outstanding >= h->max_commands)
306 * returns value read from hardware.
307 * returns FIFO_EMPTY if there is nothing to read
309 static unsigned long SA5_completed(struct ctlr_info *h)
311 unsigned long register_value
312 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
314 if (register_value != FIFO_EMPTY)
315 h->commands_outstanding--;
318 if (register_value != FIFO_EMPTY)
319 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
322 dev_dbg(&h->pdev->dev, "hpsa: FIFO Empty read\n");
325 return register_value;
328 * Returns true if an interrupt is pending..
330 static bool SA5_intr_pending(struct ctlr_info *h)
332 unsigned long register_value =
333 readl(h->vaddr + SA5_INTR_STATUS);
334 dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
335 return register_value & SA5_INTR_PENDING;
338 static bool SA5_performant_intr_pending(struct ctlr_info *h)
340 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
345 if (h->msi_vector || h->msix_vector)
348 /* Read outbound doorbell to flush */
349 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
350 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
353 static struct access_method SA5_access = {
361 static struct access_method SA5_performant_access = {
363 SA5_performant_intr_mask,
365 SA5_performant_intr_pending,
366 SA5_performant_completed,
372 struct access_method *access;