drivers/scsi/bnx2fc/57xx_hsi_bnx2fc.h

   1 #ifndef __57XX_FCOE_HSI_LINUX_LE__
   2 #define __57XX_FCOE_HSI_LINUX_LE__
   3
   4 /*
   5  * common data for all protocols
   6  */
   7 struct b577xx_doorbell_hdr {
   8         u8 header;
   9 #define B577XX_DOORBELL_HDR_RX (0x1<<0)
  10 #define B577XX_DOORBELL_HDR_RX_SHIFT 0
  11 #define B577XX_DOORBELL_HDR_DB_TYPE (0x1<<1)
  12 #define B577XX_DOORBELL_HDR_DB_TYPE_SHIFT 1
  13 #define B577XX_DOORBELL_HDR_DPM_SIZE (0x3<<2)
  14 #define B577XX_DOORBELL_HDR_DPM_SIZE_SHIFT 2
  15 #define B577XX_DOORBELL_HDR_CONN_TYPE (0xF<<4)
  16 #define B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT 4
  17 };
  18
  19 /*
  20  * doorbell message sent to the chip
  21  */
  22 struct b577xx_doorbell_set_prod {
  23 #if defined(__BIG_ENDIAN)
  24         u16 prod;
  25         u8 zero_fill1;
  26         struct b577xx_doorbell_hdr header;
  27 #elif defined(__LITTLE_ENDIAN)
  28         struct b577xx_doorbell_hdr header;
  29         u8 zero_fill1;
  30         u16 prod;
  31 #endif
  32 };
  33
  34
  35 struct regpair {
  36         __le32 lo;
  37         __le32 hi;
  38 };
  39
  40
  41 /*
  42  * Fixed size structure in order to plant it in Union structure
  43  */
  44 struct fcoe_abts_rsp_union {
  45         u32 r_ctl;
  46         u32 abts_rsp_payload[7];
  47 };
  48
  49
  50 /*
  51  * 4 regs size
  52  */
  53 struct fcoe_bd_ctx {
  54         u32 buf_addr_hi;
  55         u32 buf_addr_lo;
  56 #if defined(__BIG_ENDIAN)
  57         u16 rsrv0;
  58         u16 buf_len;
  59 #elif defined(__LITTLE_ENDIAN)
  60         u16 buf_len;
  61         u16 rsrv0;
  62 #endif
  63 #if defined(__BIG_ENDIAN)
  64         u16 rsrv1;
  65         u16 flags;
  66 #elif defined(__LITTLE_ENDIAN)
  67         u16 flags;
  68         u16 rsrv1;
  69 #endif
  70 };
  71
  72
  73 struct fcoe_cleanup_flow_info {
  74 #if defined(__BIG_ENDIAN)
  75         u16 reserved1;
  76         u16 task_id;
  77 #elif defined(__LITTLE_ENDIAN)
  78         u16 task_id;
  79         u16 reserved1;
  80 #endif
  81         u32 reserved2[7];
  82 };
  83
  84
  85 struct fcoe_fcp_cmd_payload {
  86         u32 opaque[8];
  87 };
  88
  89 struct fcoe_fc_hdr {
  90 #if defined(__BIG_ENDIAN)
  91         u8 cs_ctl;
  92         u8 s_id[3];
  93 #elif defined(__LITTLE_ENDIAN)
  94         u8 s_id[3];
  95         u8 cs_ctl;
  96 #endif
  97 #if defined(__BIG_ENDIAN)
  98         u8 r_ctl;
  99         u8 d_id[3];
 100 #elif defined(__LITTLE_ENDIAN)
 101         u8 d_id[3];
 102         u8 r_ctl;
 103 #endif
 104 #if defined(__BIG_ENDIAN)
 105         u8 seq_id;
 106         u8 df_ctl;
 107         u16 seq_cnt;
 108 #elif defined(__LITTLE_ENDIAN)
 109         u16 seq_cnt;
 110         u8 df_ctl;
 111         u8 seq_id;
 112 #endif
 113 #if defined(__BIG_ENDIAN)
 114         u8 type;
 115         u8 f_ctl[3];
 116 #elif defined(__LITTLE_ENDIAN)
 117         u8 f_ctl[3];
 118         u8 type;
 119 #endif
 120         u32 parameters;
 121 #if defined(__BIG_ENDIAN)
 122         u16 ox_id;
 123         u16 rx_id;
 124 #elif defined(__LITTLE_ENDIAN)
 125         u16 rx_id;
 126         u16 ox_id;
 127 #endif
 128 };
 129
 130 struct fcoe_fc_frame {
 131         struct fcoe_fc_hdr fc_hdr;
 132         u32 reserved0[2];
 133 };
 134
 135 union fcoe_cmd_flow_info {
 136         struct fcoe_fcp_cmd_payload fcp_cmd_payload;
 137         struct fcoe_fc_frame mp_fc_frame;
 138 };
 139
 140
 141
 142 struct fcoe_fcp_rsp_flags {
 143         u8 flags;
 144 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
 145 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0
 146 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1)
 147 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1
 148 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2)
 149 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2
 150 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3)
 151 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3
 152 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4)
 153 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4
 154 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5)
 155 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
 156 };
 157
 158
 159 struct fcoe_fcp_rsp_payload {
 160         struct regpair reserved0;
 161         u32 fcp_resid;
 162 #if defined(__BIG_ENDIAN)
 163         u16 retry_delay_timer;
 164         struct fcoe_fcp_rsp_flags fcp_flags;
 165         u8 scsi_status_code;
 166 #elif defined(__LITTLE_ENDIAN)
 167         u8 scsi_status_code;
 168         struct fcoe_fcp_rsp_flags fcp_flags;
 169         u16 retry_delay_timer;
 170 #endif
 171         u32 fcp_rsp_len;
 172         u32 fcp_sns_len;
 173 };
 174
 175
 176 /*
 177  * Fixed size structure in order to plant it in Union structure
 178  */
 179 struct fcoe_fcp_rsp_union {
 180         struct fcoe_fcp_rsp_payload payload;
 181         struct regpair reserved0;
 182 };
 183
 184
 185 struct fcoe_fcp_xfr_rdy_payload {
 186         u32 burst_len;
 187         u32 data_ro;
 188 };
 189
 190 struct fcoe_read_flow_info {
 191         struct fcoe_fc_hdr fc_data_in_hdr;
 192         u32 reserved[2];
 193 };
 194
 195 struct fcoe_write_flow_info {
 196         struct fcoe_fc_hdr fc_data_out_hdr;
 197         struct fcoe_fcp_xfr_rdy_payload fcp_xfr_payload;
 198 };
 199
 200 union fcoe_rsp_flow_info {
 201         struct fcoe_fcp_rsp_union fcp_rsp;
 202         struct fcoe_abts_rsp_union abts_rsp;
 203 };
 204
 205 /*
 206  * 32 bytes used for general purposes
 207  */
 208 union fcoe_general_task_ctx {
 209         union fcoe_cmd_flow_info cmd_info;
 210         struct fcoe_read_flow_info read_info;
 211         struct fcoe_write_flow_info write_info;
 212         union fcoe_rsp_flow_info rsp_info;
 213         struct fcoe_cleanup_flow_info cleanup_info;
 214         u32 comp_info[8];
 215 };
 216
 217
 218 /*
 219  * FCoE KCQ CQE parameters
 220  */
 221 union fcoe_kcqe_params {
 222         u32 reserved0[4];
 223 };
 224
 225 /*
 226  * FCoE KCQ CQE
 227  */
 228 struct fcoe_kcqe {
 229         u32 fcoe_conn_id;
 230         u32 completion_status;
 231         u32 fcoe_conn_context_id;
 232         union fcoe_kcqe_params params;
 233 #if defined(__BIG_ENDIAN)
 234         u8 flags;
 235 #define FCOE_KCQE_RESERVED0 (0x7<<0)
 236 #define FCOE_KCQE_RESERVED0_SHIFT 0
 237 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
 238 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
 239 #define FCOE_KCQE_LAYER_CODE (0x7<<4)
 240 #define FCOE_KCQE_LAYER_CODE_SHIFT 4
 241 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
 242 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
 243         u8 op_code;
 244         u16 qe_self_seq;
 245 #elif defined(__LITTLE_ENDIAN)
 246         u16 qe_self_seq;
 247         u8 op_code;
 248         u8 flags;
 249 #define FCOE_KCQE_RESERVED0 (0x7<<0)
 250 #define FCOE_KCQE_RESERVED0_SHIFT 0
 251 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
 252 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
 253 #define FCOE_KCQE_LAYER_CODE (0x7<<4)
 254 #define FCOE_KCQE_LAYER_CODE_SHIFT 4
 255 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
 256 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
 257 #endif
 258 };
 259
 260 /*
 261  * FCoE KWQE header
 262  */
 263 struct fcoe_kwqe_header {
 264 #if defined(__BIG_ENDIAN)
 265         u8 flags;
 266 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
 267 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
 268 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
 269 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
 270 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
 271 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
 272         u8 op_code;
 273 #elif defined(__LITTLE_ENDIAN)
 274         u8 op_code;
 275         u8 flags;
 276 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
 277 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
 278 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
 279 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
 280 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
 281 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
 282 #endif
 283 };
 284
 285 /*
 286  * FCoE firmware init request 1
 287  */
 288 struct fcoe_kwqe_init1 {
 289 #if defined(__BIG_ENDIAN)
 290         struct fcoe_kwqe_header hdr;
 291         u16 num_tasks;
 292 #elif defined(__LITTLE_ENDIAN)
 293         u16 num_tasks;
 294         struct fcoe_kwqe_header hdr;
 295 #endif
 296         u32 task_list_pbl_addr_lo;
 297         u32 task_list_pbl_addr_hi;
 298         u32 dummy_buffer_addr_lo;
 299         u32 dummy_buffer_addr_hi;
 300 #if defined(__BIG_ENDIAN)
 301         u16 rq_num_wqes;
 302         u16 sq_num_wqes;
 303 #elif defined(__LITTLE_ENDIAN)
 304         u16 sq_num_wqes;
 305         u16 rq_num_wqes;
 306 #endif
 307 #if defined(__BIG_ENDIAN)
 308         u16 cq_num_wqes;
 309         u16 rq_buffer_log_size;
 310 #elif defined(__LITTLE_ENDIAN)
 311         u16 rq_buffer_log_size;
 312         u16 cq_num_wqes;
 313 #endif
 314 #if defined(__BIG_ENDIAN)
 315         u8 flags;
 316 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
 317 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
 318 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
 319 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
 320 #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
 321 #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
 322         u8 num_sessions_log;
 323         u16 mtu;
 324 #elif defined(__LITTLE_ENDIAN)
 325         u16 mtu;
 326         u8 num_sessions_log;
 327         u8 flags;
 328 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
 329 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
 330 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
 331 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
 332 #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
 333 #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
 334 #endif
 335 };
 336
 337 /*
 338  * FCoE firmware init request 2
 339  */
 340 struct fcoe_kwqe_init2 {
 341 #if defined(__BIG_ENDIAN)
 342         struct fcoe_kwqe_header hdr;
 343         u16 reserved0;
 344 #elif defined(__LITTLE_ENDIAN)
 345         u16 reserved0;
 346         struct fcoe_kwqe_header hdr;
 347 #endif
 348         u32 hash_tbl_pbl_addr_lo;
 349         u32 hash_tbl_pbl_addr_hi;
 350         u32 t2_hash_tbl_addr_lo;
 351         u32 t2_hash_tbl_addr_hi;
 352         u32 t2_ptr_hash_tbl_addr_lo;
 353         u32 t2_ptr_hash_tbl_addr_hi;
 354         u32 free_list_count;
 355 };
 356
 357 /*
 358  * FCoE firmware init request 3
 359  */
 360 struct fcoe_kwqe_init3 {
 361 #if defined(__BIG_ENDIAN)
 362         struct fcoe_kwqe_header hdr;
 363         u16 reserved0;
 364 #elif defined(__LITTLE_ENDIAN)
 365         u16 reserved0;
 366         struct fcoe_kwqe_header hdr;
 367 #endif
 368         u32 error_bit_map_lo;
 369         u32 error_bit_map_hi;
 370 #if defined(__BIG_ENDIAN)
 371         u8 reserved21[3];
 372         u8 cached_session_enable;
 373 #elif defined(__LITTLE_ENDIAN)
 374         u8 cached_session_enable;
 375         u8 reserved21[3];
 376 #endif
 377         u32 reserved2[4];
 378 };
 379
 380 /*
 381  * FCoE connection offload request 1
 382  */
 383 struct fcoe_kwqe_conn_offload1 {
 384 #if defined(__BIG_ENDIAN)
 385         struct fcoe_kwqe_header hdr;
 386         u16 fcoe_conn_id;
 387 #elif defined(__LITTLE_ENDIAN)
 388         u16 fcoe_conn_id;
 389         struct fcoe_kwqe_header hdr;
 390 #endif
 391         u32 sq_addr_lo;
 392         u32 sq_addr_hi;
 393         u32 rq_pbl_addr_lo;
 394         u32 rq_pbl_addr_hi;
 395         u32 rq_first_pbe_addr_lo;
 396         u32 rq_first_pbe_addr_hi;
 397 #if defined(__BIG_ENDIAN)
 398         u16 reserved0;
 399         u16 rq_prod;
 400 #elif defined(__LITTLE_ENDIAN)
 401         u16 rq_prod;
 402         u16 reserved0;
 403 #endif
 404 };
 405
 406 /*
 407  * FCoE connection offload request 2
 408  */
 409 struct fcoe_kwqe_conn_offload2 {
 410 #if defined(__BIG_ENDIAN)
 411         struct fcoe_kwqe_header hdr;
 412         u16 tx_max_fc_pay_len;
 413 #elif defined(__LITTLE_ENDIAN)
 414         u16 tx_max_fc_pay_len;
 415         struct fcoe_kwqe_header hdr;
 416 #endif
 417         u32 cq_addr_lo;
 418         u32 cq_addr_hi;
 419         u32 xferq_addr_lo;
 420         u32 xferq_addr_hi;
 421         u32 conn_db_addr_lo;
 422         u32 conn_db_addr_hi;
 423         u32 reserved1;
 424 };
 425
 426 /*
 427  * FCoE connection offload request 3
 428  */
 429 struct fcoe_kwqe_conn_offload3 {
 430 #if defined(__BIG_ENDIAN)
 431         struct fcoe_kwqe_header hdr;
 432         u16 vlan_tag;
 433 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
 434 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
 435 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
 436 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
 437 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
 438 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
 439 #elif defined(__LITTLE_ENDIAN)
 440         u16 vlan_tag;
 441 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
 442 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
 443 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
 444 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
 445 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
 446 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
 447         struct fcoe_kwqe_header hdr;
 448 #endif
 449 #if defined(__BIG_ENDIAN)
 450         u8 tx_max_conc_seqs_c3;
 451         u8 s_id[3];
 452 #elif defined(__LITTLE_ENDIAN)
 453         u8 s_id[3];
 454         u8 tx_max_conc_seqs_c3;
 455 #endif
 456 #if defined(__BIG_ENDIAN)
 457         u8 flags;
 458 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
 459 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
 460 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
 461 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
 462 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
 463 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
 464 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
 465 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
 466 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
 467 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
 468 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
 469 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
 470 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
 471 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
 472 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
 473 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
 474         u8 d_id[3];
 475 #elif defined(__LITTLE_ENDIAN)
 476         u8 d_id[3];
 477         u8 flags;
 478 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
 479 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
 480 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
 481 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
 482 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
 483 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
 484 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
 485 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
 486 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
 487 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
 488 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
 489 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
 490 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
 491 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
 492 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
 493 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
 494 #endif
 495         u32 reserved;
 496         u32 confq_first_pbe_addr_lo;
 497         u32 confq_first_pbe_addr_hi;
 498 #if defined(__BIG_ENDIAN)
 499         u16 rx_max_fc_pay_len;
 500         u16 tx_total_conc_seqs;
 501 #elif defined(__LITTLE_ENDIAN)
 502         u16 tx_total_conc_seqs;
 503         u16 rx_max_fc_pay_len;
 504 #endif
 505 #if defined(__BIG_ENDIAN)
 506         u8 rx_open_seqs_exch_c3;
 507         u8 rx_max_conc_seqs_c3;
 508         u16 rx_total_conc_seqs;
 509 #elif defined(__LITTLE_ENDIAN)
 510         u16 rx_total_conc_seqs;
 511         u8 rx_max_conc_seqs_c3;
 512         u8 rx_open_seqs_exch_c3;
 513 #endif
 514 };
 515
 516 /*
 517  * FCoE connection offload request 4
 518  */
 519 struct fcoe_kwqe_conn_offload4 {
 520 #if defined(__BIG_ENDIAN)
 521         struct fcoe_kwqe_header hdr;
 522         u8 reserved2;
 523         u8 e_d_tov_timer_val;
 524 #elif defined(__LITTLE_ENDIAN)
 525         u8 e_d_tov_timer_val;
 526         u8 reserved2;
 527         struct fcoe_kwqe_header hdr;
 528 #endif
 529         u8 src_mac_addr_lo32[4];
 530 #if defined(__BIG_ENDIAN)
 531         u8 dst_mac_addr_hi16[2];
 532         u8 src_mac_addr_hi16[2];
 533 #elif defined(__LITTLE_ENDIAN)
 534         u8 src_mac_addr_hi16[2];
 535         u8 dst_mac_addr_hi16[2];
 536 #endif
 537         u8 dst_mac_addr_lo32[4];
 538         u32 lcq_addr_lo;
 539         u32 lcq_addr_hi;
 540         u32 confq_pbl_base_addr_lo;
 541         u32 confq_pbl_base_addr_hi;
 542 };
 543
 544 /*
 545  * FCoE connection enable request
 546  */
 547 struct fcoe_kwqe_conn_enable_disable {
 548 #if defined(__BIG_ENDIAN)
 549         struct fcoe_kwqe_header hdr;
 550         u16 reserved0;
 551 #elif defined(__LITTLE_ENDIAN)
 552         u16 reserved0;
 553         struct fcoe_kwqe_header hdr;
 554 #endif
 555         u8 src_mac_addr_lo32[4];
 556 #if defined(__BIG_ENDIAN)
 557         u16 vlan_tag;
 558 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
 559 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
 560 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
 561 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
 562 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
 563 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
 564         u8 src_mac_addr_hi16[2];
 565 #elif defined(__LITTLE_ENDIAN)
 566         u8 src_mac_addr_hi16[2];
 567         u16 vlan_tag;
 568 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
 569 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
 570 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
 571 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
 572 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
 573 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
 574 #endif
 575         u8 dst_mac_addr_lo32[4];
 576 #if defined(__BIG_ENDIAN)
 577         u16 reserved1;
 578         u8 dst_mac_addr_hi16[2];
 579 #elif defined(__LITTLE_ENDIAN)
 580         u8 dst_mac_addr_hi16[2];
 581         u16 reserved1;
 582 #endif
 583 #if defined(__BIG_ENDIAN)
 584         u8 vlan_flag;
 585         u8 s_id[3];
 586 #elif defined(__LITTLE_ENDIAN)
 587         u8 s_id[3];
 588         u8 vlan_flag;
 589 #endif
 590 #if defined(__BIG_ENDIAN)
 591         u8 reserved3;
 592         u8 d_id[3];
 593 #elif defined(__LITTLE_ENDIAN)
 594         u8 d_id[3];
 595         u8 reserved3;
 596 #endif
 597         u32 context_id;
 598         u32 conn_id;
 599         u32 reserved4;
 600 };
 601
 602 /*
 603  * FCoE connection destroy request
 604  */
 605 struct fcoe_kwqe_conn_destroy {
 606 #if defined(__BIG_ENDIAN)
 607         struct fcoe_kwqe_header hdr;
 608         u16 reserved0;
 609 #elif defined(__LITTLE_ENDIAN)
 610         u16 reserved0;
 611         struct fcoe_kwqe_header hdr;
 612 #endif
 613         u32 context_id;
 614         u32 conn_id;
 615         u32 reserved1[5];
 616 };
 617
 618 /*
 619  * FCoe destroy request
 620  */
 621 struct fcoe_kwqe_destroy {
 622 #if defined(__BIG_ENDIAN)
 623         struct fcoe_kwqe_header hdr;
 624         u16 reserved0;
 625 #elif defined(__LITTLE_ENDIAN)
 626         u16 reserved0;
 627         struct fcoe_kwqe_header hdr;
 628 #endif
 629         u32 reserved1[7];
 630 };
 631
 632 /*
 633  * FCoe statistics request
 634  */
 635 struct fcoe_kwqe_stat {
 636 #if defined(__BIG_ENDIAN)
 637         struct fcoe_kwqe_header hdr;
 638         u16 reserved0;
 639 #elif defined(__LITTLE_ENDIAN)
 640         u16 reserved0;
 641         struct fcoe_kwqe_header hdr;
 642 #endif
 643         u32 stat_params_addr_lo;
 644         u32 stat_params_addr_hi;
 645         u32 reserved1[5];
 646 };
 647
 648 /*
 649  * FCoE KWQ WQE
 650  */
 651 union fcoe_kwqe {
 652         struct fcoe_kwqe_init1 init1;
 653         struct fcoe_kwqe_init2 init2;
 654         struct fcoe_kwqe_init3 init3;
 655         struct fcoe_kwqe_conn_offload1 conn_offload1;
 656         struct fcoe_kwqe_conn_offload2 conn_offload2;
 657         struct fcoe_kwqe_conn_offload3 conn_offload3;
 658         struct fcoe_kwqe_conn_offload4 conn_offload4;
 659         struct fcoe_kwqe_conn_enable_disable conn_enable_disable;
 660         struct fcoe_kwqe_conn_destroy conn_destroy;
 661         struct fcoe_kwqe_destroy destroy;
 662         struct fcoe_kwqe_stat statistics;
 663 };
 664
 665 struct fcoe_mul_sges_ctx {
 666         struct regpair cur_sge_addr;
 667 #if defined(__BIG_ENDIAN)
 668         u8 sgl_size;
 669         u8 cur_sge_idx;
 670         u16 cur_sge_off;
 671 #elif defined(__LITTLE_ENDIAN)
 672         u16 cur_sge_off;
 673         u8 cur_sge_idx;
 674         u8 sgl_size;
 675 #endif
 676 };
 677
 678 struct fcoe_s_stat_ctx {
 679         u8 flags;
 680 #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0)
 681 #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0
 682 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1)
 683 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1
 684 #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2)
 685 #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2
 686 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3)
 687 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3
 688 #define FCOE_S_STAT_CTX_P_RJT (0x1<<4)
 689 #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4
 690 #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5)
 691 #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5
 692 #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6)
 693 #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
 694 };
 695
 696 struct fcoe_seq_ctx {
 697 #if defined(__BIG_ENDIAN)
 698         u16 low_seq_cnt;
 699         struct fcoe_s_stat_ctx s_stat;
 700         u8 seq_id;
 701 #elif defined(__LITTLE_ENDIAN)
 702         u8 seq_id;
 703         struct fcoe_s_stat_ctx s_stat;
 704         u16 low_seq_cnt;
 705 #endif
 706 #if defined(__BIG_ENDIAN)
 707         u16 err_seq_cnt;
 708         u16 high_seq_cnt;
 709 #elif defined(__LITTLE_ENDIAN)
 710         u16 high_seq_cnt;
 711         u16 err_seq_cnt;
 712 #endif
 713         u32 low_exp_ro;
 714         u32 high_exp_ro;
 715 };
 716
 717
 718 struct fcoe_single_sge_ctx {
 719         struct regpair cur_buf_addr;
 720 #if defined(__BIG_ENDIAN)
 721         u16 reserved0;
 722         u16 cur_buf_rem;
 723 #elif defined(__LITTLE_ENDIAN)
 724         u16 cur_buf_rem;
 725         u16 reserved0;
 726 #endif
 727 };
 728
 729 union fcoe_sgl_ctx {
 730         struct fcoe_single_sge_ctx single_sge;
 731         struct fcoe_mul_sges_ctx mul_sges;
 732 };
 733
 734
 735
 736 /*
 737  * FCoE SQ element
 738  */
 739 struct fcoe_sqe {
 740         u16 wqe;
 741 #define FCOE_SQE_TASK_ID (0x7FFF<<0)
 742 #define FCOE_SQE_TASK_ID_SHIFT 0
 743 #define FCOE_SQE_TOGGLE_BIT (0x1<<15)
 744 #define FCOE_SQE_TOGGLE_BIT_SHIFT 15
 745 };
 746
 747
 748
 749 struct fcoe_task_ctx_entry_tx_only {
 750         union fcoe_sgl_ctx sgl_ctx;
 751 };
 752
 753 struct fcoe_task_ctx_entry_txwr_rxrd {
 754 #if defined(__BIG_ENDIAN)
 755         u16 verify_tx_seq;
 756         u8 init_flags;
 757 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0)
 758 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0
 759 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3)
 760 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3
 761 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4)
 762 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4
 763 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5)
 764 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5
 765 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6)
 766 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6
 767         u8 tx_flags;
 768 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0)
 769 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0
 770 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4)
 771 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4
 772 #elif defined(__LITTLE_ENDIAN)
 773         u8 tx_flags;
 774 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0)
 775 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0
 776 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4)
 777 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4
 778         u8 init_flags;
 779 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0)
 780 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0
 781 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3)
 782 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3
 783 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4)
 784 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4
 785 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5)
 786 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5
 787 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6)
 788 #define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6
 789         u16 verify_tx_seq;
 790 #endif
 791 };
 792
 793 /*
 794  * Common section. Both TX and RX processing might write and read from it in
 795  * different flows
 796  */
 797 struct fcoe_task_ctx_entry_tx_rx_cmn {
 798         u32 data_2_trns;
 799         union fcoe_general_task_ctx general;
 800 #if defined(__BIG_ENDIAN)
 801         u16 tx_low_seq_cnt;
 802         struct fcoe_s_stat_ctx tx_s_stat;
 803         u8 tx_seq_id;
 804 #elif defined(__LITTLE_ENDIAN)
 805         u8 tx_seq_id;
 806         struct fcoe_s_stat_ctx tx_s_stat;
 807         u16 tx_low_seq_cnt;
 808 #endif
 809         u32 common_flags;
 810 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID (0xFFFFFF<<0)
 811 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT 0
 812 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID (0x1<<24)
 813 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT 24
 814 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT (0x1<<25)
 815 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT_SHIFT 25
 816 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER (0x1<<26)
 817 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER_SHIFT 26
 818 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF (0x1<<27)
 819 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF_SHIFT 27
 820 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME (0x1<<28)
 821 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT 28
 822 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV (0x7<<29)
 823 #define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV_SHIFT 29
 824 };
 825
 826 struct fcoe_task_ctx_entry_rxwr_txrd {
 827 #if defined(__BIG_ENDIAN)
 828         u16 rx_id;
 829         u16 rx_flags;
 830 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0)
 831 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0
 832 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4)
 833 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4
 834 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7)
 835 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7
 836 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8)
 837 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8
 838 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9)
 839 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9
 840 #elif defined(__LITTLE_ENDIAN)
 841         u16 rx_flags;
 842 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0)
 843 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0
 844 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4)
 845 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4
 846 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7)
 847 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7
 848 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8)
 849 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8
 850 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9)
 851 #define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9
 852         u16 rx_id;
 853 #endif
 854 };
 855
 856 struct fcoe_task_ctx_entry_rx_only {
 857         struct fcoe_seq_ctx seq_ctx;
 858         struct fcoe_seq_ctx ooo_seq_ctx;
 859         u32 rsrv3;
 860         union fcoe_sgl_ctx sgl_ctx;
 861 };
 862
 863 struct fcoe_task_ctx_entry {
 864         struct fcoe_task_ctx_entry_tx_only tx_wr_only;
 865         struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd;
 866         struct fcoe_task_ctx_entry_tx_rx_cmn cmn;
 867         struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd;
 868         struct fcoe_task_ctx_entry_rx_only rx_wr_only;
 869         u32 reserved[4];
 870 };
 871
 872
 873 /*
 874  * FCoE XFRQ element
 875  */
 876 struct fcoe_xfrqe {
 877         u16 wqe;
 878 #define FCOE_XFRQE_TASK_ID (0x7FFF<<0)
 879 #define FCOE_XFRQE_TASK_ID_SHIFT 0
 880 #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15)
 881 #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15
 882 };
 883
 884
 885 /*
 886  * FCoE CONFQ element
 887  */
 888 struct fcoe_confqe {
 889 #if defined(__BIG_ENDIAN)
 890         u16 rx_id;
 891         u16 ox_id;
 892 #elif defined(__LITTLE_ENDIAN)
 893         u16 ox_id;
 894         u16 rx_id;
 895 #endif
 896         u32 param;
 897 };
 898
 899
 900 /*
 901  * FCoE conection data base
 902  */
 903 struct fcoe_conn_db {
 904 #if defined(__BIG_ENDIAN)
 905         u16 rsrv0;
 906         u16 rq_prod;
 907 #elif defined(__LITTLE_ENDIAN)
 908         u16 rq_prod;
 909         u16 rsrv0;
 910 #endif
 911         u32 rsrv1;
 912         struct regpair cq_arm;
 913 };
 914
 915
 916 /*
 917  * FCoE CQ element
 918  */
 919 struct fcoe_cqe {
 920         u16 wqe;
 921 #define FCOE_CQE_CQE_INFO (0x3FFF<<0)
 922 #define FCOE_CQE_CQE_INFO_SHIFT 0
 923 #define FCOE_CQE_CQE_TYPE (0x1<<14)
 924 #define FCOE_CQE_CQE_TYPE_SHIFT 14
 925 #define FCOE_CQE_TOGGLE_BIT (0x1<<15)
 926 #define FCOE_CQE_TOGGLE_BIT_SHIFT 15
 927 };
 928
 929
 930 /*
 931  * FCoE error/warning resporting entry
 932  */
 933 struct fcoe_err_report_entry {
 934         u32 err_warn_bitmap_lo;
 935         u32 err_warn_bitmap_hi;
 936         u32 tx_buf_off;
 937         u32 rx_buf_off;
 938         struct fcoe_fc_hdr fc_hdr;
 939 };
 940
 941
 942 /*
 943  * FCoE hash table entry (32 bytes)
 944  */
 945 struct fcoe_hash_table_entry {
 946 #if defined(__BIG_ENDIAN)
 947         u8 d_id_0;
 948         u8 s_id_2;
 949         u8 s_id_1;
 950         u8 s_id_0;
 951 #elif defined(__LITTLE_ENDIAN)
 952         u8 s_id_0;
 953         u8 s_id_1;
 954         u8 s_id_2;
 955         u8 d_id_0;
 956 #endif
 957 #if defined(__BIG_ENDIAN)
 958         u16 dst_mac_addr_hi;
 959         u8 d_id_2;
 960         u8 d_id_1;
 961 #elif defined(__LITTLE_ENDIAN)
 962         u8 d_id_1;
 963         u8 d_id_2;
 964         u16 dst_mac_addr_hi;
 965 #endif
 966         u32 dst_mac_addr_lo;
 967 #if defined(__BIG_ENDIAN)
 968         u16 vlan_id;
 969         u16 src_mac_addr_hi;
 970 #elif defined(__LITTLE_ENDIAN)
 971         u16 src_mac_addr_hi;
 972         u16 vlan_id;
 973 #endif
 974         u32 src_mac_addr_lo;
 975 #if defined(__BIG_ENDIAN)
 976         u16 reserved1;
 977         u8 reserved0;
 978         u8 vlan_flag;
 979 #elif defined(__LITTLE_ENDIAN)
 980         u8 vlan_flag;
 981         u8 reserved0;
 982         u16 reserved1;
 983 #endif
 984         u32 reserved2;
 985         u32 field_id;
 986 #define FCOE_HASH_TABLE_ENTRY_CID (0xFFFFFF<<0)
 987 #define FCOE_HASH_TABLE_ENTRY_CID_SHIFT 0
 988 #define FCOE_HASH_TABLE_ENTRY_RESERVED3 (0x7F<<24)
 989 #define FCOE_HASH_TABLE_ENTRY_RESERVED3_SHIFT 24
 990 #define FCOE_HASH_TABLE_ENTRY_VALID (0x1<<31)
 991 #define FCOE_HASH_TABLE_ENTRY_VALID_SHIFT 31
 992 };
 993
 994 /*
 995  * FCoE pending work request CQE
 996  */
 997 struct fcoe_pend_wq_cqe {
 998         u16 wqe;
 999 #define FCOE_PEND_WQ_CQE_TASK_ID (0x3FFF<<0)
1000 #define FCOE_PEND_WQ_CQE_TASK_ID_SHIFT 0
1001 #define FCOE_PEND_WQ_CQE_CQE_TYPE (0x1<<14)
1002 #define FCOE_PEND_WQ_CQE_CQE_TYPE_SHIFT 14
1003 #define FCOE_PEND_WQ_CQE_TOGGLE_BIT (0x1<<15)
1004 #define FCOE_PEND_WQ_CQE_TOGGLE_BIT_SHIFT 15
1005 };
1006
1007
1008 /*
1009  * FCoE RX statistics parameters section#0
1010  */
1011 struct fcoe_rx_stat_params_section0 {
1012         u32 fcoe_ver_cnt;
1013         u32 fcoe_rx_pkt_cnt;
1014         u32 fcoe_rx_byte_cnt;
1015         u32 fcoe_rx_drop_pkt_cnt;
1016 };
1017
1018
1019 /*
1020  * FCoE RX statistics parameters section#1
1021  */
1022 struct fcoe_rx_stat_params_section1 {
1023         u32 fc_crc_cnt;
1024         u32 eofa_del_cnt;
1025         u32 miss_frame_cnt;
1026         u32 seq_timeout_cnt;
1027         u32 drop_seq_cnt;
1028         u32 fcoe_rx_drop_pkt_cnt;
1029         u32 fcp_rx_pkt_cnt;
1030         u32 reserved0;
1031 };
1032
1033
1034 /*
1035  * FCoE TX statistics parameters
1036  */
1037 struct fcoe_tx_stat_params {
1038         u32 fcoe_tx_pkt_cnt;
1039         u32 fcoe_tx_byte_cnt;
1040         u32 fcp_tx_pkt_cnt;
1041         u32 reserved0;
1042 };
1043
1044 /*
1045  * FCoE statistics parameters
1046  */
1047 struct fcoe_statistics_params {
1048         struct fcoe_tx_stat_params tx_stat;
1049         struct fcoe_rx_stat_params_section0 rx_stat0;
1050         struct fcoe_rx_stat_params_section1 rx_stat1;
1051 };
1052
1053
1054 /*
1055  * FCoE t2 hash table entry (64 bytes)
1056  */
1057 struct fcoe_t2_hash_table_entry {
1058         struct fcoe_hash_table_entry data;
1059         struct regpair next;
1060         struct regpair reserved0[3];
1061 };
1062
1063 /*
1064  * FCoE unsolicited CQE
1065  */
1066 struct fcoe_unsolicited_cqe {
1067         u16 wqe;
1068 #define FCOE_UNSOLICITED_CQE_SUBTYPE (0x3<<0)
1069 #define FCOE_UNSOLICITED_CQE_SUBTYPE_SHIFT 0
1070 #define FCOE_UNSOLICITED_CQE_PKT_LEN (0xFFF<<2)
1071 #define FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT 2
1072 #define FCOE_UNSOLICITED_CQE_CQE_TYPE (0x1<<14)
1073 #define FCOE_UNSOLICITED_CQE_CQE_TYPE_SHIFT 14
1074 #define FCOE_UNSOLICITED_CQE_TOGGLE_BIT (0x1<<15)
1075 #define FCOE_UNSOLICITED_CQE_TOGGLE_BIT_SHIFT 15
1076 };
1077
1078
1079
1080 #endif /* __57XX_FCOE_HSI_LINUX_LE__ */