2 * Core routines and tables shareable across OS platforms.
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2003 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#250 $
44 #include "aic79xx_osm.h"
45 #include "aic79xx_inline.h"
46 #include "aicasm/aicasm_insformat.h"
48 #include <dev/aic7xxx/aic79xx_osm.h>
49 #include <dev/aic7xxx/aic79xx_inline.h>
50 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
54 /***************************** Lookup Tables **********************************/
55 char *ahd_chip_names[] =
62 static const u_int num_chip_names = NUM_ELEMENTS(ahd_chip_names);
65 * Hardware error codes.
67 struct ahd_hard_error_entry {
72 static struct ahd_hard_error_entry ahd_hard_errors[] = {
73 { DSCTMOUT, "Discard Timer has timed out" },
74 { ILLOPCODE, "Illegal Opcode in sequencer program" },
75 { SQPARERR, "Sequencer Parity Error" },
76 { DPARERR, "Data-path Parity Error" },
77 { MPARERR, "Scratch or SCB Memory Parity Error" },
78 { CIOPARERR, "CIOBUS Parity Error" },
80 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors);
82 static struct ahd_phase_table_entry ahd_phase_table[] =
84 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
85 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
86 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
87 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
88 { P_COMMAND, MSG_NOOP, "in Command phase" },
89 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
90 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
91 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
92 { P_BUSFREE, MSG_NOOP, "while idle" },
93 { 0, MSG_NOOP, "in unknown phase" }
97 * In most cases we only wish to itterate over real phases, so
98 * exclude the last element from the count.
100 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1;
102 /* Our Sequencer Program */
103 #include "aic79xx_seq.h"
105 /**************************** Function Declarations ***************************/
106 static void ahd_handle_transmission_error(struct ahd_softc *ahd);
107 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd,
109 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd,
111 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd);
112 static void ahd_handle_proto_violation(struct ahd_softc *ahd);
113 static void ahd_force_renegotiation(struct ahd_softc *ahd,
114 struct ahd_devinfo *devinfo);
116 static struct ahd_tmode_tstate*
117 ahd_alloc_tstate(struct ahd_softc *ahd,
118 u_int scsi_id, char channel);
119 #ifdef AHD_TARGET_MODE
120 static void ahd_free_tstate(struct ahd_softc *ahd,
121 u_int scsi_id, char channel, int force);
123 static void ahd_devlimited_syncrate(struct ahd_softc *ahd,
124 struct ahd_initiator_tinfo *,
128 static void ahd_update_neg_table(struct ahd_softc *ahd,
129 struct ahd_devinfo *devinfo,
130 struct ahd_transinfo *tinfo);
131 static void ahd_update_pending_scbs(struct ahd_softc *ahd);
132 static void ahd_fetch_devinfo(struct ahd_softc *ahd,
133 struct ahd_devinfo *devinfo);
134 static void ahd_scb_devinfo(struct ahd_softc *ahd,
135 struct ahd_devinfo *devinfo,
137 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd,
138 struct ahd_devinfo *devinfo,
140 static void ahd_build_transfer_msg(struct ahd_softc *ahd,
141 struct ahd_devinfo *devinfo);
142 static void ahd_construct_sdtr(struct ahd_softc *ahd,
143 struct ahd_devinfo *devinfo,
144 u_int period, u_int offset);
145 static void ahd_construct_wdtr(struct ahd_softc *ahd,
146 struct ahd_devinfo *devinfo,
148 static void ahd_construct_ppr(struct ahd_softc *ahd,
149 struct ahd_devinfo *devinfo,
150 u_int period, u_int offset,
151 u_int bus_width, u_int ppr_options);
152 static void ahd_clear_msg_state(struct ahd_softc *ahd);
153 static void ahd_handle_message_phase(struct ahd_softc *ahd);
159 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type,
160 u_int msgval, int full);
161 static int ahd_parse_msg(struct ahd_softc *ahd,
162 struct ahd_devinfo *devinfo);
163 static int ahd_handle_msg_reject(struct ahd_softc *ahd,
164 struct ahd_devinfo *devinfo);
165 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd,
166 struct ahd_devinfo *devinfo);
167 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd);
168 static void ahd_handle_devreset(struct ahd_softc *ahd,
169 struct ahd_devinfo *devinfo,
170 u_int lun, cam_status status,
171 char *message, int verbose_level);
172 #ifdef AHD_TARGET_MODE
173 static void ahd_setup_target_msgin(struct ahd_softc *ahd,
174 struct ahd_devinfo *devinfo,
178 static u_int ahd_sglist_size(struct ahd_softc *ahd);
179 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd);
180 static bus_dmamap_callback_t
182 static void ahd_initialize_hscbs(struct ahd_softc *ahd);
183 static int ahd_init_scbdata(struct ahd_softc *ahd);
184 static void ahd_fini_scbdata(struct ahd_softc *ahd);
185 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd);
186 static void ahd_iocell_first_selection(struct ahd_softc *ahd);
187 static void ahd_add_col_list(struct ahd_softc *ahd,
188 struct scb *scb, u_int col_idx);
189 static void ahd_rem_col_list(struct ahd_softc *ahd,
191 static void ahd_chip_init(struct ahd_softc *ahd);
192 static void ahd_qinfifo_requeue(struct ahd_softc *ahd,
193 struct scb *prev_scb,
195 static int ahd_qinfifo_count(struct ahd_softc *ahd);
196 static int ahd_search_scb_list(struct ahd_softc *ahd, int target,
197 char channel, int lun, u_int tag,
198 role_t role, uint32_t status,
199 ahd_search_action action,
200 u_int *list_head, u_int *list_tail,
202 static void ahd_stitch_tid_list(struct ahd_softc *ahd,
203 u_int tid_prev, u_int tid_cur,
205 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd,
207 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
208 u_int prev, u_int next, u_int tid);
209 static void ahd_reset_current_bus(struct ahd_softc *ahd);
210 static ahd_callback_t ahd_reset_poll;
211 static ahd_callback_t ahd_stat_timer;
213 static void ahd_dumpseq(struct ahd_softc *ahd);
215 static void ahd_loadseq(struct ahd_softc *ahd);
216 static int ahd_check_patch(struct ahd_softc *ahd,
217 struct patch **start_patch,
218 u_int start_instr, u_int *skip_addr);
219 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd,
221 static void ahd_download_instr(struct ahd_softc *ahd,
222 u_int instrptr, uint8_t *dconsts);
223 static int ahd_probe_stack_size(struct ahd_softc *ahd);
224 static int ahd_scb_active_in_fifo(struct ahd_softc *ahd,
226 static void ahd_run_data_fifo(struct ahd_softc *ahd,
229 #ifdef AHD_TARGET_MODE
230 static void ahd_queue_lstate_event(struct ahd_softc *ahd,
231 struct ahd_tmode_lstate *lstate,
235 static void ahd_update_scsiid(struct ahd_softc *ahd,
237 static int ahd_handle_target_cmd(struct ahd_softc *ahd,
238 struct target_cmd *cmd);
241 /******************************** Private Inlines *****************************/
242 static __inline void ahd_assert_atn(struct ahd_softc *ahd);
243 static __inline int ahd_currently_packetized(struct ahd_softc *ahd);
244 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd);
247 ahd_assert_atn(struct ahd_softc *ahd)
249 ahd_outb(ahd, SCSISIGO, ATNO);
253 * Determine if the current connection has a packetized
254 * agreement. This does not necessarily mean that we
255 * are currently in a packetized transfer. We could
256 * just as easily be sending or receiving a message.
259 ahd_currently_packetized(struct ahd_softc *ahd)
261 ahd_mode_state saved_modes;
264 saved_modes = ahd_save_modes(ahd);
265 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) {
267 * The packetized bit refers to the last
268 * connection, not the current one. Check
269 * for non-zero LQISTATE instead.
271 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
272 packetized = ahd_inb(ahd, LQISTATE) != 0;
274 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
275 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED;
277 ahd_restore_modes(ahd, saved_modes);
282 ahd_set_active_fifo(struct ahd_softc *ahd)
286 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
287 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
288 switch (active_fifo) {
291 ahd_set_modes(ahd, active_fifo, active_fifo);
298 /************************* Sequencer Execution Control ************************/
300 * Restart the sequencer program from address zero
303 ahd_restart(struct ahd_softc *ahd)
308 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
310 /* No more pending messages */
311 ahd_clear_msg_state(ahd);
312 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */
313 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */
314 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET);
315 ahd_outb(ahd, SEQINTCTL, 0);
316 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
317 ahd_outb(ahd, SEQ_FLAGS, 0);
318 ahd_outb(ahd, SAVED_SCSIID, 0xFF);
319 ahd_outb(ahd, SAVED_LUN, 0xFF);
322 * Ensure that the sequencer's idea of TQINPOS
323 * matches our own. The sequencer increments TQINPOS
324 * only after it sees a DMA complete and a reset could
325 * occur before the increment leaving the kernel to believe
326 * the command arrived but the sequencer to not.
328 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
330 /* Always allow reselection */
331 ahd_outb(ahd, SCSISEQ1,
332 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
333 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
336 * Clear any pending sequencer interrupt. It is no
337 * longer relevant since we're resetting the Program
340 ahd_outb(ahd, CLRINT, CLRSEQINT);
342 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
347 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo)
349 ahd_mode_state saved_modes;
352 if ((ahd_debug & AHD_SHOW_FIFOS) != 0)
353 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo);
355 saved_modes = ahd_save_modes(ahd);
356 ahd_set_modes(ahd, fifo, fifo);
357 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
358 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
359 ahd_outb(ahd, CCSGCTL, CCSGRESET);
360 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
361 ahd_outb(ahd, SG_STATE, 0);
362 ahd_restore_modes(ahd, saved_modes);
365 /************************* Input/Output Queues ********************************/
367 * Flush and completed commands that are sitting in the command
368 * complete queues down on the chip but have yet to be dma'ed back up.
371 ahd_flush_qoutfifo(struct ahd_softc *ahd)
374 ahd_mode_state saved_modes;
380 saved_modes = ahd_save_modes(ahd);
383 * Flush the good status FIFO for completed packetized commands.
385 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
386 saved_scbptr = ahd_get_scbptr(ahd);
387 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) {
391 scbid = ahd_inw(ahd, GSFIFO);
392 scb = ahd_lookup_scb(ahd, scbid);
394 printf("%s: Warning - GSFIFO SCB %d invalid\n",
395 ahd_name(ahd), scbid);
399 * Determine if this transaction is still active in
400 * any FIFO. If it is, we must flush that FIFO to
401 * the host before completing the command.
405 for (i = 0; i < 2; i++) {
406 /* Toggle to the other mode. */
408 ahd_set_modes(ahd, fifo_mode, fifo_mode);
410 if (ahd_scb_active_in_fifo(ahd, scb) == 0)
413 ahd_run_data_fifo(ahd, scb);
416 * Running this FIFO may cause a CFG4DATA for
417 * this same transaction to assert in the other
418 * FIFO or a new snapshot SAVEPTRS interrupt
419 * in this FIFO. Even running a FIFO may not
420 * clear the transaction if we are still waiting
421 * for data to drain to the host. We must loop
422 * until the transaction is not active in either
423 * FIFO just to be sure. Reset our loop counter
424 * so we will visit both FIFOs again before
425 * declaring this transaction finished. We
426 * also delay a bit so that status has a chance
427 * to change before we look at this FIFO again.
432 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
433 ahd_set_scbptr(ahd, scbid);
434 if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0
435 && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0
436 || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR)
437 & SG_LIST_NULL) != 0)) {
441 * The transfer completed with a residual.
442 * Place this SCB on the complete DMA list
443 * so that we update our in-core copy of the
444 * SCB before completing the command.
446 ahd_outb(ahd, SCB_SCSI_STATUS, 0);
447 ahd_outb(ahd, SCB_SGPTR,
448 ahd_inb_scbram(ahd, SCB_SGPTR)
450 ahd_outw(ahd, SCB_TAG, scbid);
451 ahd_outw(ahd, SCB_NEXT_COMPLETE, SCB_LIST_NULL);
452 comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
453 if (SCBID_IS_NULL(comp_head)) {
454 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, scbid);
455 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
459 tail = ahd_inw(ahd, COMPLETE_DMA_SCB_TAIL);
460 ahd_set_scbptr(ahd, tail);
461 ahd_outw(ahd, SCB_NEXT_COMPLETE, scbid);
462 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
463 ahd_set_scbptr(ahd, scbid);
466 ahd_complete_scb(ahd, scb);
468 ahd_set_scbptr(ahd, saved_scbptr);
471 * Setup for command channel portion of flush.
473 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
476 * Wait for any inprogress DMA to complete and clear DMA state
477 * if this if for an SCB in the qinfifo.
479 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) {
481 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) {
482 if ((ccscbctl & ARRDONE) != 0)
484 } else if ((ccscbctl & CCSCBDONE) != 0)
489 * We leave the sequencer to cleanup in the case of DMA's to
490 * update the qoutfifo. In all other cases (DMA's to the
491 * chip or a push of an SCB from the COMPLETE_DMA_SCB list),
492 * we disable the DMA engine so that the sequencer will not
493 * attempt to handle the DMA completion.
495 if ((ccscbctl & CCSCBDIR) != 0 || (ccscbctl & ARRDONE) != 0)
496 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN));
499 * Complete any SCBs that just finished
500 * being DMA'ed into the qoutfifo.
502 ahd_run_qoutfifo(ahd);
504 saved_scbptr = ahd_get_scbptr(ahd);
506 * Manually update/complete any completed SCBs that are waiting to be
507 * DMA'ed back up to the host.
509 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
510 while (!SCBID_IS_NULL(scbid)) {
514 ahd_set_scbptr(ahd, scbid);
515 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
516 scb = ahd_lookup_scb(ahd, scbid);
518 printf("%s: Warning - DMA-up and complete "
519 "SCB %d invalid\n", ahd_name(ahd), scbid);
522 hscb_ptr = (uint8_t *)scb->hscb;
523 for (i = 0; i < sizeof(struct hardware_scb); i++)
524 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i);
526 ahd_complete_scb(ahd, scb);
529 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
530 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
532 scbid = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
533 while (!SCBID_IS_NULL(scbid)) {
535 ahd_set_scbptr(ahd, scbid);
536 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
537 scb = ahd_lookup_scb(ahd, scbid);
539 printf("%s: Warning - Complete Qfrz SCB %d invalid\n",
540 ahd_name(ahd), scbid);
544 ahd_complete_scb(ahd, scb);
547 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
549 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD);
550 while (!SCBID_IS_NULL(scbid)) {
552 ahd_set_scbptr(ahd, scbid);
553 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
554 scb = ahd_lookup_scb(ahd, scbid);
556 printf("%s: Warning - Complete SCB %d invalid\n",
557 ahd_name(ahd), scbid);
561 ahd_complete_scb(ahd, scb);
564 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
569 ahd_set_scbptr(ahd, saved_scbptr);
570 ahd_restore_modes(ahd, saved_modes);
571 ahd->flags |= AHD_UPDATE_PEND_CMDS;
575 * Determine if an SCB for a packetized transaction
576 * is active in a FIFO.
579 ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb)
583 * The FIFO is only active for our transaction if
584 * the SCBPTR matches the SCB's ID and the firmware
585 * has installed a handler for the FIFO or we have
586 * a pending SAVEPTRS or CFG4DATA interrupt.
588 if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb)
589 || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0
590 && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0))
597 * Run a data fifo to completion for a transaction we know
598 * has completed across the SCSI bus (good status has been
599 * received). We are already set to the correct FIFO mode
600 * on entry to this routine.
602 * This function attempts to operate exactly as the firmware
603 * would when running this FIFO. Care must be taken to update
604 * this routine any time the firmware's FIFO algorithm is
608 ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
612 seqintsrc = ahd_inb(ahd, SEQINTSRC);
613 if ((seqintsrc & CFG4DATA) != 0) {
618 * Clear full residual flag.
620 sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID;
621 ahd_outb(ahd, SCB_SGPTR, sgptr);
624 * Load datacnt and address.
626 datacnt = ahd_inl_scbram(ahd, SCB_DATACNT);
627 if ((datacnt & AHD_DMA_LAST_SEG) != 0) {
629 ahd_outb(ahd, SG_STATE, 0);
631 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
632 ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR));
633 ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK);
634 ahd_outb(ahd, SG_CACHE_PRE, sgptr);
635 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
638 * Initialize Residual Fields.
640 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24);
641 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK);
644 * Mark the SCB as having a FIFO in use.
646 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
647 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1);
650 * Install a "fake" handler for this FIFO.
652 ahd_outw(ahd, LONGJMP_ADDR, 0);
655 * Notify the hardware that we have satisfied
656 * this sequencer interrupt.
658 ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA);
659 } else if ((seqintsrc & SAVEPTRS) != 0) {
663 if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) {
665 * Snapshot Save Pointers. All that
666 * is necessary to clear the snapshot
673 * Disable S/G fetch so the DMA engine
674 * is available to future users.
676 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
677 ahd_outb(ahd, CCSGCTL, 0);
678 ahd_outb(ahd, SG_STATE, 0);
681 * Flush the data FIFO. Strickly only
682 * necessary for Rev A parts.
684 ahd_outb(ahd, DFCNTRL, ahd_inb(ahd, DFCNTRL) | FIFOFLUSH);
687 * Calculate residual.
689 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
690 resid = ahd_inl(ahd, SHCNT);
691 resid |= ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24;
692 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid);
693 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) {
695 * Must back up to the correct S/G element.
696 * Typically this just means resetting our
697 * low byte to the offset in the SG_CACHE,
698 * but if we wrapped, we have to correct
699 * the other bytes of the sgptr too.
701 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0
702 && (sgptr & 0x80) == 0)
705 sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW)
707 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
708 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0);
709 } else if ((resid & AHD_SG_LEN_MASK) == 0) {
710 ahd_outb(ahd, SCB_RESIDUAL_SGPTR,
711 sgptr | SG_LIST_NULL);
716 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR));
717 ahd_outl(ahd, SCB_DATACNT, resid);
718 ahd_outl(ahd, SCB_SGPTR, sgptr);
719 ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS);
720 ahd_outb(ahd, SEQIMODE,
721 ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS);
723 * If the data is to the SCSI bus, we are
724 * done, otherwise wait for FIFOEMP.
726 if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0)
728 } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) {
735 * Disable S/G fetch so the DMA engine
736 * is available to future users. We won't
737 * be using the DMA engine to load segments.
739 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) {
740 ahd_outb(ahd, CCSGCTL, 0);
741 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
745 * Wait for the DMA engine to notice that the
746 * host transfer is enabled and that there is
747 * space in the S/G FIFO for new segments before
748 * loading more segments.
750 if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) != 0
751 && (ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) {
754 * Determine the offset of the next S/G
757 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
758 sgptr &= SG_PTR_MASK;
759 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
760 struct ahd_dma64_seg *sg;
762 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
763 data_addr = sg->addr;
765 sgptr += sizeof(*sg);
767 struct ahd_dma_seg *sg;
769 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
770 data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK;
772 data_addr |= sg->addr;
774 sgptr += sizeof(*sg);
778 * Update residual information.
780 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24);
781 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
786 if (data_len & AHD_DMA_LAST_SEG) {
788 ahd_outb(ahd, SG_STATE, 0);
790 ahd_outq(ahd, HADDR, data_addr);
791 ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK);
792 ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF);
795 * Advertise the segment to the hardware.
797 dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN;
798 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
800 * Use SCSIENWRDIS so that SCSIEN
801 * is never modified by this
804 dfcntrl |= SCSIENWRDIS;
806 ahd_outb(ahd, DFCNTRL, dfcntrl);
808 } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG_DONE) != 0) {
811 * Transfer completed to the end of SG list
812 * and has flushed to the host.
814 ahd_outb(ahd, SCB_SGPTR,
815 ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL);
817 } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) {
820 * Clear any handler for this FIFO, decrement
821 * the FIFO use count for the SCB, and release
824 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
825 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
826 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1);
827 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
832 * Look for entries in the QoutFIFO that have completed.
833 * The valid_tag completion field indicates the validity
834 * of the entry - the valid value toggles each time through
835 * the queue. We use the sg_status field in the completion
836 * entry to avoid referencing the hscb if the completion
837 * occurred with no errors and no residual. sg_status is
838 * a copy of the first byte (little endian) of the sgptr
842 ahd_run_qoutfifo(struct ahd_softc *ahd)
844 struct ahd_completion *completion;
848 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0)
849 panic("ahd_run_qoutfifo recursion");
850 ahd->flags |= AHD_RUNNING_QOUTFIFO;
851 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD);
853 completion = &ahd->qoutfifo[ahd->qoutfifonext];
855 if (completion->valid_tag != ahd->qoutfifonext_valid_tag)
858 scb_index = ahd_le16toh(completion->tag);
859 scb = ahd_lookup_scb(ahd, scb_index);
861 printf("%s: WARNING no command for scb %d "
862 "(cmdcmplt)\nQOUTPOS = %d\n",
863 ahd_name(ahd), scb_index,
865 ahd_dump_card_state(ahd);
866 } else if ((completion->sg_status & SG_STATUS_VALID) != 0) {
867 ahd_handle_scb_status(ahd, scb);
872 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1);
873 if (ahd->qoutfifonext == 0)
874 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID;
876 ahd->flags &= ~AHD_RUNNING_QOUTFIFO;
879 /************************* Interrupt Handling *********************************/
881 ahd_handle_hwerrint(struct ahd_softc *ahd)
884 * Some catastrophic hardware error has occurred.
885 * Print it for the user and disable the controller.
890 error = ahd_inb(ahd, ERROR);
891 for (i = 0; i < num_errors; i++) {
892 if ((error & ahd_hard_errors[i].errno) != 0)
893 printf("%s: hwerrint, %s\n",
894 ahd_name(ahd), ahd_hard_errors[i].errmesg);
897 ahd_dump_card_state(ahd);
900 /* Tell everyone that this HBA is no longer available */
901 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
902 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
905 /* Tell the system that this controller has gone away. */
910 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat)
915 * Save the sequencer interrupt code and clear the SEQINT
916 * bit. We will unpause the sequencer, if appropriate,
917 * after servicing the request.
919 seqintcode = ahd_inb(ahd, SEQINTCODE);
920 ahd_outb(ahd, CLRINT, CLRSEQINT);
921 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
923 * Unpause the sequencer and let it clear
924 * SEQINT by writing NO_SEQINT to it. This
925 * will cause the sequencer to be paused again,
926 * which is the expected state of this routine.
929 while (!ahd_is_paused(ahd))
931 ahd_outb(ahd, CLRINT, CLRSEQINT);
933 ahd_update_modes(ahd);
935 if ((ahd_debug & AHD_SHOW_MISC) != 0)
936 printf("%s: Handle Seqint Called for code %d\n",
937 ahd_name(ahd), seqintcode);
939 switch (seqintcode) {
940 case ENTERING_NONPACK:
945 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
946 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
947 scbid = ahd_get_scbptr(ahd);
948 scb = ahd_lookup_scb(ahd, scbid);
951 * Somehow need to know if this
952 * is from a selection or reselection.
953 * From that, we can determine target
954 * ID so we at least have an I_T nexus.
957 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
958 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun);
959 ahd_outb(ahd, SEQ_FLAGS, 0x0);
961 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0
962 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
964 * Phase change after read stream with
965 * CRC error with P0 asserted on last
969 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
970 printf("%s: Assuming LQIPHASE_NLQ with "
971 "P0 assertion\n", ahd_name(ahd));
975 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
976 printf("%s: Entering NONPACK\n", ahd_name(ahd));
981 printf("%s: Invalid Sequencer interrupt occurred.\n",
983 ahd_dump_card_state(ahd);
984 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
991 scbid = ahd_get_scbptr(ahd);
992 scb = ahd_lookup_scb(ahd, scbid);
994 ahd_print_path(ahd, scb);
996 printf("%s: ", ahd_name(ahd));
997 printf("SCB %d Packetized Status Overrun", scbid);
998 ahd_dump_card_state(ahd);
999 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1002 case CFG4ISTAT_INTR:
1007 scbid = ahd_get_scbptr(ahd);
1008 scb = ahd_lookup_scb(ahd, scbid);
1010 ahd_dump_card_state(ahd);
1011 printf("CFG4ISTAT: Free SCB %d referenced", scbid);
1012 panic("For safety");
1014 ahd_outq(ahd, HADDR, scb->sense_busaddr);
1015 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE);
1016 ahd_outb(ahd, HCNT + 2, 0);
1017 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG);
1018 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
1025 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1026 printf("%s: ILLEGAL_PHASE 0x%x\n",
1027 ahd_name(ahd), bus_phase);
1029 switch (bus_phase) {
1037 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1038 printf("%s: Issued Bus Reset.\n", ahd_name(ahd));
1042 struct ahd_devinfo devinfo;
1044 struct ahd_initiator_tinfo *targ_info;
1045 struct ahd_tmode_tstate *tstate;
1046 struct ahd_transinfo *tinfo;
1050 * If a target takes us into the command phase
1051 * assume that it has been externally reset and
1052 * has thus lost our previous packetized negotiation
1053 * agreement. Since we have not sent an identify
1054 * message and may not have fully qualified the
1055 * connection, we change our command to TUR, assert
1056 * ATN and ABORT the task when we go to message in
1057 * phase. The OSM will see the REQUEUE_REQUEST
1058 * status and retry the command.
1060 scbid = ahd_get_scbptr(ahd);
1061 scb = ahd_lookup_scb(ahd, scbid);
1063 printf("Invalid phase with no valid SCB. "
1064 "Resetting bus.\n");
1065 ahd_reset_channel(ahd, 'A',
1066 /*Initiate Reset*/TRUE);
1069 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
1070 SCB_GET_TARGET(ahd, scb),
1072 SCB_GET_CHANNEL(ahd, scb),
1074 targ_info = ahd_fetch_transinfo(ahd,
1079 tinfo = &targ_info->curr;
1080 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
1081 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1082 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
1083 /*offset*/0, /*ppr_options*/0,
1084 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1085 ahd_outb(ahd, SCB_CDB_STORE, 0);
1086 ahd_outb(ahd, SCB_CDB_STORE+1, 0);
1087 ahd_outb(ahd, SCB_CDB_STORE+2, 0);
1088 ahd_outb(ahd, SCB_CDB_STORE+3, 0);
1089 ahd_outb(ahd, SCB_CDB_STORE+4, 0);
1090 ahd_outb(ahd, SCB_CDB_STORE+5, 0);
1091 ahd_outb(ahd, SCB_CDB_LEN, 6);
1092 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE);
1093 scb->hscb->control |= MK_MESSAGE;
1094 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control);
1095 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1096 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
1098 * The lun is 0, regardless of the SCB's lun
1099 * as we have not sent an identify message.
1101 ahd_outb(ahd, SAVED_LUN, 0);
1102 ahd_outb(ahd, SEQ_FLAGS, 0);
1103 ahd_assert_atn(ahd);
1104 scb->flags &= ~SCB_PACKETIZED;
1105 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT;
1106 ahd_freeze_devq(ahd, scb);
1107 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ);
1108 ahd_freeze_scb(scb);
1111 * Allow the sequencer to continue with
1112 * non-pack processing.
1114 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1115 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT);
1116 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
1117 ahd_outb(ahd, CLRLQOINT1, 0);
1120 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1121 ahd_print_path(ahd, scb);
1122 printf("Unexpected command phase from "
1123 "packetized target\n");
1137 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1138 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd),
1139 ahd_inb(ahd, MODE_PTR));
1142 scb_index = ahd_get_scbptr(ahd);
1143 scb = ahd_lookup_scb(ahd, scb_index);
1146 * Attempt to transfer to an SCB that is
1149 ahd_assert_atn(ahd);
1150 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1151 ahd->msgout_buf[0] = MSG_ABORT_TASK;
1152 ahd->msgout_len = 1;
1153 ahd->msgout_index = 0;
1154 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1156 * Clear status received flag to prevent any
1157 * attempt to complete this bogus SCB.
1159 ahd_outb(ahd, SCB_CONTROL,
1160 ahd_inb_scbram(ahd, SCB_CONTROL)
1165 case DUMP_CARD_STATE:
1167 ahd_dump_card_state(ahd);
1173 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1174 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x "
1175 "SG_CACHE_SHADOW = 0x%x\n",
1176 ahd_name(ahd), ahd_inb(ahd, DFCNTRL),
1177 ahd_inb(ahd, SG_CACHE_SHADOW));
1180 ahd_reinitialize_dataptrs(ahd);
1185 struct ahd_devinfo devinfo;
1188 * The sequencer has encountered a message phase
1189 * that requires host assistance for completion.
1190 * While handling the message phase(s), we will be
1191 * notified by the sequencer after each byte is
1192 * transfered so we can track bus phase changes.
1194 * If this is the first time we've seen a HOST_MSG_LOOP
1195 * interrupt, initialize the state of the host message
1198 ahd_fetch_devinfo(ahd, &devinfo);
1199 if (ahd->msg_type == MSG_TYPE_NONE) {
1204 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1205 if (bus_phase != P_MESGIN
1206 && bus_phase != P_MESGOUT) {
1207 printf("ahd_intr: HOST_MSG_LOOP bad "
1208 "phase 0x%x\n", bus_phase);
1210 * Probably transitioned to bus free before
1211 * we got here. Just punt the message.
1213 ahd_dump_card_state(ahd);
1214 ahd_clear_intstat(ahd);
1219 scb_index = ahd_get_scbptr(ahd);
1220 scb = ahd_lookup_scb(ahd, scb_index);
1221 if (devinfo.role == ROLE_INITIATOR) {
1222 if (bus_phase == P_MESGOUT)
1223 ahd_setup_initiator_msgout(ahd,
1228 MSG_TYPE_INITIATOR_MSGIN;
1229 ahd->msgin_index = 0;
1232 #ifdef AHD_TARGET_MODE
1234 if (bus_phase == P_MESGOUT) {
1236 MSG_TYPE_TARGET_MSGOUT;
1237 ahd->msgin_index = 0;
1240 ahd_setup_target_msgin(ahd,
1247 ahd_handle_message_phase(ahd);
1252 /* Ensure we don't leave the selection hardware on */
1253 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
1254 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
1256 printf("%s:%c:%d: no active SCB for reconnecting "
1257 "target - issuing BUS DEVICE RESET\n",
1258 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4);
1259 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1260 "REG0 == 0x%x ACCUM = 0x%x\n",
1261 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN),
1262 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM));
1263 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1265 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd),
1266 ahd_find_busy_tcl(ahd,
1267 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID),
1268 ahd_inb(ahd, SAVED_LUN))),
1269 ahd_inw(ahd, SINDEX));
1270 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1271 "SCB_CONTROL == 0x%x\n",
1272 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID),
1273 ahd_inb_scbram(ahd, SCB_LUN),
1274 ahd_inb_scbram(ahd, SCB_CONTROL));
1275 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n",
1276 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI));
1277 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0));
1278 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0));
1279 ahd_dump_card_state(ahd);
1280 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET;
1281 ahd->msgout_len = 1;
1282 ahd->msgout_index = 0;
1283 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1284 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1285 ahd_assert_atn(ahd);
1288 case PROTO_VIOLATION:
1290 ahd_handle_proto_violation(ahd);
1295 struct ahd_devinfo devinfo;
1297 ahd_fetch_devinfo(ahd, &devinfo);
1298 ahd_handle_ign_wide_residue(ahd, &devinfo);
1305 lastphase = ahd_inb(ahd, LASTPHASE);
1306 printf("%s:%c:%d: unknown scsi bus phase %x, "
1307 "lastphase = 0x%x. Attempting to continue\n",
1309 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1310 lastphase, ahd_inb(ahd, SCSISIGI));
1313 case MISSED_BUSFREE:
1317 lastphase = ahd_inb(ahd, LASTPHASE);
1318 printf("%s:%c:%d: Missed busfree. "
1319 "Lastphase = 0x%x, Curphase = 0x%x\n",
1321 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1322 lastphase, ahd_inb(ahd, SCSISIGI));
1329 * When the sequencer detects an overrun, it
1330 * places the controller in "BITBUCKET" mode
1331 * and allows the target to complete its transfer.
1332 * Unfortunately, none of the counters get updated
1333 * when the controller is in this mode, so we have
1334 * no way of knowing how large the overrun was.
1342 scbindex = ahd_get_scbptr(ahd);
1343 scb = ahd_lookup_scb(ahd, scbindex);
1345 lastphase = ahd_inb(ahd, LASTPHASE);
1346 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1347 ahd_print_path(ahd, scb);
1348 printf("data overrun detected %s. Tag == 0x%x.\n",
1349 ahd_lookup_phase_entry(lastphase)->phasemsg,
1351 ahd_print_path(ahd, scb);
1352 printf("%s seen Data Phase. Length = %ld. "
1354 ahd_inb(ahd, SEQ_FLAGS) & DPHASE
1355 ? "Have" : "Haven't",
1356 ahd_get_transfer_length(scb), scb->sg_count);
1357 ahd_dump_sglist(scb);
1362 * Set this and it will take effect when the
1363 * target does a command complete.
1365 ahd_freeze_devq(ahd, scb);
1366 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR);
1367 ahd_freeze_scb(scb);
1372 struct ahd_devinfo devinfo;
1376 ahd_fetch_devinfo(ahd, &devinfo);
1377 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
1378 ahd_name(ahd), devinfo.channel, devinfo.target,
1380 scbid = ahd_get_scbptr(ahd);
1381 scb = ahd_lookup_scb(ahd, scbid);
1383 && (scb->flags & SCB_RECOVERY_SCB) != 0)
1385 * Ensure that we didn't put a second instance of this
1386 * SCB into the QINFIFO.
1388 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1389 SCB_GET_CHANNEL(ahd, scb),
1390 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1391 ROLE_INITIATOR, /*status*/0,
1393 ahd_outb(ahd, SCB_CONTROL,
1394 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
1397 case TASKMGMT_FUNC_COMPLETE:
1402 scbid = ahd_get_scbptr(ahd);
1403 scb = ahd_lookup_scb(ahd, scbid);
1409 ahd_print_path(ahd, scb);
1410 printf("Task Management Func 0x%x Complete\n",
1411 scb->hscb->task_management);
1412 lun = CAM_LUN_WILDCARD;
1413 tag = SCB_LIST_NULL;
1415 switch (scb->hscb->task_management) {
1416 case SIU_TASKMGMT_ABORT_TASK:
1417 tag = SCB_GET_TAG(scb);
1418 case SIU_TASKMGMT_ABORT_TASK_SET:
1419 case SIU_TASKMGMT_CLEAR_TASK_SET:
1420 lun = scb->hscb->lun;
1421 error = CAM_REQ_ABORTED;
1422 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
1423 'A', lun, tag, ROLE_INITIATOR,
1426 case SIU_TASKMGMT_LUN_RESET:
1427 lun = scb->hscb->lun;
1428 case SIU_TASKMGMT_TARGET_RESET:
1430 struct ahd_devinfo devinfo;
1432 ahd_scb_devinfo(ahd, &devinfo, scb);
1433 error = CAM_BDR_SENT;
1434 ahd_handle_devreset(ahd, &devinfo, lun,
1436 lun != CAM_LUN_WILDCARD
1439 /*verbose_level*/0);
1443 panic("Unexpected TaskMgmt Func\n");
1449 case TASKMGMT_CMD_CMPLT_OKAY:
1455 * An ABORT TASK TMF failed to be delivered before
1456 * the targeted command completed normally.
1458 scbid = ahd_get_scbptr(ahd);
1459 scb = ahd_lookup_scb(ahd, scbid);
1462 * Remove the second instance of this SCB from
1463 * the QINFIFO if it is still there.
1465 ahd_print_path(ahd, scb);
1466 printf("SCB completes before TMF\n");
1468 * Handle losing the race. Wait until any
1469 * current selection completes. We will then
1470 * set the TMF back to zero in this SCB so that
1471 * the sequencer doesn't bother to issue another
1472 * sequencer interrupt for its completion.
1474 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
1475 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0
1476 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0)
1478 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0);
1479 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1480 SCB_GET_CHANNEL(ahd, scb),
1481 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1482 ROLE_INITIATOR, /*status*/0,
1491 printf("%s: Tracepoint %d\n", ahd_name(ahd),
1492 seqintcode - TRACEPOINT0);
1497 ahd_handle_hwerrint(ahd);
1500 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd),
1505 * The sequencer is paused immediately on
1506 * a SEQINT, so we should restart it when
1513 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
1524 ahd_update_modes(ahd);
1525 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1527 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR);
1528 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO);
1529 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1530 lqistat1 = ahd_inb(ahd, LQISTAT1);
1531 lqostat0 = ahd_inb(ahd, LQOSTAT0);
1532 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1533 if ((status0 & (SELDI|SELDO)) != 0) {
1536 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1537 simode0 = ahd_inb(ahd, SIMODE0);
1538 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO);
1539 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1541 scbid = ahd_get_scbptr(ahd);
1542 scb = ahd_lookup_scb(ahd, scbid);
1544 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1547 if ((status0 & IOERR) != 0) {
1550 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40;
1551 printf("%s: Transceiver State Has Changed to %s mode\n",
1552 ahd_name(ahd), now_lvd ? "LVD" : "SE");
1553 ahd_outb(ahd, CLRSINT0, CLRIOERR);
1555 * A change in I/O mode is equivalent to a bus reset.
1557 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1559 ahd_setup_iocell_workaround(ahd);
1561 } else if ((status0 & OVERRUN) != 0) {
1563 printf("%s: SCSI offset overrun detected. Resetting bus.\n",
1565 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1566 } else if ((status & SCSIRSTI) != 0) {
1568 printf("%s: Someone reset channel A\n", ahd_name(ahd));
1569 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE);
1570 } else if ((status & SCSIPERR) != 0) {
1572 /* Make sure the sequencer is in a safe location. */
1573 ahd_clear_critical_section(ahd);
1575 ahd_handle_transmission_error(ahd);
1576 } else if (lqostat0 != 0) {
1578 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0);
1579 ahd_outb(ahd, CLRLQOINT0, lqostat0);
1580 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
1581 ahd_outb(ahd, CLRLQOINT1, 0);
1582 } else if ((status & SELTO) != 0) {
1585 /* Stop the selection */
1586 ahd_outb(ahd, SCSISEQ0, 0);
1588 /* Make sure the sequencer is in a safe location. */
1589 ahd_clear_critical_section(ahd);
1591 /* No more pending messages */
1592 ahd_clear_msg_state(ahd);
1594 /* Clear interrupt state */
1595 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1598 * Although the driver does not care about the
1599 * 'Selection in Progress' status bit, the busy
1600 * LED does. SELINGO is only cleared by a sucessfull
1601 * selection, so we must manually clear it to insure
1602 * the LED turns off just incase no future successful
1603 * selections occur (e.g. no devices on the bus).
1605 ahd_outb(ahd, CLRSINT0, CLRSELINGO);
1607 scbid = ahd_inw(ahd, WAITING_TID_HEAD);
1608 scb = ahd_lookup_scb(ahd, scbid);
1610 printf("%s: ahd_intr - referenced scb not "
1611 "valid during SELTO scb(0x%x)\n",
1612 ahd_name(ahd), scbid);
1613 ahd_dump_card_state(ahd);
1615 struct ahd_devinfo devinfo;
1617 if ((ahd_debug & AHD_SHOW_SELTO) != 0) {
1618 ahd_print_path(ahd, scb);
1619 printf("Saw Selection Timeout for SCB 0x%x\n",
1623 ahd_scb_devinfo(ahd, &devinfo, scb);
1624 ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1625 ahd_freeze_devq(ahd, scb);
1628 * Cancel any pending transactions on the device
1629 * now that it seems to be missing. This will
1630 * also revert us to async/narrow transfers until
1631 * we can renegotiate with the device.
1633 ahd_handle_devreset(ahd, &devinfo,
1636 "Selection Timeout",
1637 /*verbose_level*/1);
1639 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1640 ahd_iocell_first_selection(ahd);
1642 } else if ((status0 & (SELDI|SELDO)) != 0) {
1644 ahd_iocell_first_selection(ahd);
1646 } else if (status3 != 0) {
1647 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n",
1648 ahd_name(ahd), status3);
1649 ahd_outb(ahd, CLRSINT3, status3);
1650 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) {
1652 /* Make sure the sequencer is in a safe location. */
1653 ahd_clear_critical_section(ahd);
1655 ahd_handle_lqiphase_error(ahd, lqistat1);
1656 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1658 * This status can be delayed during some
1659 * streaming operations. The SCSIPHASE
1660 * handler has already dealt with this case
1661 * so just clear the error.
1663 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ);
1664 } else if ((status & BUSFREE) != 0
1665 || (lqistat1 & LQOBUSFREE) != 0) {
1673 * Clear our selection hardware as soon as possible.
1674 * We may have an entry in the waiting Q for this target,
1675 * that is affected by this busfree and we don't want to
1676 * go about selecting the target while we handle the event.
1678 ahd_outb(ahd, SCSISEQ0, 0);
1680 /* Make sure the sequencer is in a safe location. */
1681 ahd_clear_critical_section(ahd);
1684 * Determine what we were up to at the time of
1687 mode = AHD_MODE_SCSI;
1688 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1689 lqostat1 = ahd_inb(ahd, LQOSTAT1);
1690 switch (busfreetime) {
1697 mode = busfreetime == BUSFREE_DFF0
1698 ? AHD_MODE_DFF0 : AHD_MODE_DFF1;
1699 ahd_set_modes(ahd, mode, mode);
1700 scbid = ahd_get_scbptr(ahd);
1701 scb = ahd_lookup_scb(ahd, scbid);
1703 printf("%s: Invalid SCB %d in DFF%d "
1704 "during unexpected busfree\n",
1705 ahd_name(ahd), scbid, mode);
1708 packetized = (scb->flags & SCB_PACKETIZED) != 0;
1718 packetized = (lqostat1 & LQOBUSFREE) != 0;
1720 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE
1721 && (ahd_inb(ahd, SSTAT0) & SELDI) == 0
1722 && ((ahd_inb(ahd, SSTAT0) & SELDO) == 0
1723 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) == 0))
1725 * Assume packetized if we are not
1726 * on the bus in a non-packetized
1727 * capacity and any pending selection
1728 * was a packetized selection.
1735 if ((ahd_debug & AHD_SHOW_MISC) != 0)
1736 printf("Saw Busfree. Busfreetime = 0x%x.\n",
1740 * Busfrees that occur in non-packetized phases are
1741 * handled by the nonpkt_busfree handler.
1743 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) {
1744 restart = ahd_handle_pkt_busfree(ahd, busfreetime);
1747 restart = ahd_handle_nonpkt_busfree(ahd);
1750 * Clear the busfree interrupt status. The setting of
1751 * the interrupt is a pulse, so in a perfect world, we
1752 * would not need to muck with the ENBUSFREE logic. This
1753 * would ensure that if the bus moves on to another
1754 * connection, busfree protection is still in force. If
1755 * BUSFREEREV is broken, however, we must manually clear
1756 * the ENBUSFREE if the busfree occurred during a non-pack
1757 * connection so that we don't get false positives during
1758 * future, packetized, connections.
1760 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
1762 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0)
1763 ahd_outb(ahd, SIMODE1,
1764 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE);
1767 ahd_clear_fifo(ahd, mode);
1769 ahd_clear_msg_state(ahd);
1770 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1777 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n",
1778 ahd_name(ahd), status);
1779 ahd_dump_card_state(ahd);
1780 ahd_clear_intstat(ahd);
1786 ahd_handle_transmission_error(struct ahd_softc *ahd)
1800 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1801 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ);
1802 lqistat2 = ahd_inb(ahd, LQISTAT2);
1803 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0
1804 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) {
1807 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1808 lqistate = ahd_inb(ahd, LQISTATE);
1809 if ((lqistate >= 0x1E && lqistate <= 0x24)
1810 || (lqistate == 0x29)) {
1812 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1813 printf("%s: NLQCRC found via LQISTATE\n",
1817 lqistat1 |= LQICRCI_NLQ;
1819 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1822 ahd_outb(ahd, CLRLQIINT1, lqistat1);
1823 lastphase = ahd_inb(ahd, LASTPHASE);
1824 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1825 perrdiag = ahd_inb(ahd, PERRDIAG);
1826 msg_out = MSG_INITIATOR_DET_ERR;
1827 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR);
1830 * Try to find the SCB associated with this error.
1834 || (lqistat1 & LQICRCI_NLQ) != 0) {
1835 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0)
1836 ahd_set_active_fifo(ahd);
1837 scbid = ahd_get_scbptr(ahd);
1838 scb = ahd_lookup_scb(ahd, scbid);
1839 if (scb != NULL && SCB_IS_SILENT(scb))
1844 if (silent == FALSE) {
1845 printf("%s: Transmission error detected\n", ahd_name(ahd));
1846 ahd_lqistat1_print(lqistat1, &cur_col, 50);
1847 ahd_lastphase_print(lastphase, &cur_col, 50);
1848 ahd_scsisigi_print(curphase, &cur_col, 50);
1849 ahd_perrdiag_print(perrdiag, &cur_col, 50);
1851 ahd_dump_card_state(ahd);
1854 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) {
1855 if (silent == FALSE) {
1856 printf("%s: Gross protocol error during incoming "
1857 "packet. lqistat1 == 0x%x. Resetting bus.\n",
1858 ahd_name(ahd), lqistat1);
1860 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1862 } else if ((lqistat1 & LQICRCI_LQ) != 0) {
1864 * A CRC error has been detected on an incoming LQ.
1865 * The bus is currently hung on the last ACK.
1866 * Hit LQIRETRY to release the last ack, and
1867 * wait for the sequencer to determine that ATNO
1868 * is asserted while in message out to take us
1869 * to our host message loop. No NONPACKREQ or
1870 * LQIPHASE type errors will occur in this
1871 * scenario. After this first LQIRETRY, the LQI
1872 * manager will be in ISELO where it will
1873 * happily sit until another packet phase begins.
1874 * Unexpected bus free detection is enabled
1875 * through any phases that occur after we release
1876 * this last ack until the LQI manager sees a
1877 * packet phase. This implies we may have to
1878 * ignore a perfectly valid "unexected busfree"
1879 * after our "initiator detected error" message is
1880 * sent. A busfree is the expected response after
1881 * we tell the target that it's L_Q was corrupted.
1882 * (SPI4R09 10.7.3.3.3)
1884 ahd_outb(ahd, LQCTL2, LQIRETRY);
1885 printf("LQIRetry for LQICRCI_LQ to release ACK\n");
1886 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1888 * We detected a CRC error in a NON-LQ packet.
1889 * The hardware has varying behavior in this situation
1890 * depending on whether this packet was part of a
1894 * The hardware has already acked the complete packet.
1895 * If the target honors our outstanding ATN condition,
1896 * we should be (or soon will be) in MSGOUT phase.
1897 * This will trigger the LQIPHASE_LQ status bit as the
1898 * hardware was expecting another LQ. Unexpected
1899 * busfree detection is enabled. Once LQIPHASE_LQ is
1900 * true (first entry into host message loop is much
1901 * the same), we must clear LQIPHASE_LQ and hit
1902 * LQIRETRY so the hardware is ready to handle
1903 * a future LQ. NONPACKREQ will not be asserted again
1904 * once we hit LQIRETRY until another packet is
1905 * processed. The target may either go busfree
1906 * or start another packet in response to our message.
1908 * Read Streaming P0 asserted:
1909 * If we raise ATN and the target completes the entire
1910 * stream (P0 asserted during the last packet), the
1911 * hardware will ack all data and return to the ISTART
1912 * state. When the target reponds to our ATN condition,
1913 * LQIPHASE_LQ will be asserted. We should respond to
1914 * this with an LQIRETRY to prepare for any future
1915 * packets. NONPACKREQ will not be asserted again
1916 * once we hit LQIRETRY until another packet is
1917 * processed. The target may either go busfree or
1918 * start another packet in response to our message.
1919 * Busfree detection is enabled.
1921 * Read Streaming P0 not asserted:
1922 * If we raise ATN and the target transitions to
1923 * MSGOUT in or after a packet where P0 is not
1924 * asserted, the hardware will assert LQIPHASE_NLQ.
1925 * We should respond to the LQIPHASE_NLQ with an
1926 * LQIRETRY. Should the target stay in a non-pkt
1927 * phase after we send our message, the hardware
1928 * will assert LQIPHASE_LQ. Recovery is then just as
1929 * listed above for the read streaming with P0 asserted.
1930 * Busfree detection is enabled.
1932 if (silent == FALSE)
1933 printf("LQICRC_NLQ\n");
1935 printf("%s: No SCB valid for LQICRC_NLQ. "
1936 "Resetting bus\n", ahd_name(ahd));
1937 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1940 } else if ((lqistat1 & LQIBADLQI) != 0) {
1941 printf("Need to handle BADLQI!\n");
1942 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1944 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) {
1945 if ((curphase & ~P_DATAIN_DT) != 0) {
1946 /* Ack the byte. So we can continue. */
1947 if (silent == FALSE)
1948 printf("Acking %s to clear perror\n",
1949 ahd_lookup_phase_entry(curphase)->phasemsg);
1950 ahd_inb(ahd, SCSIDAT);
1953 if (curphase == P_MESGIN)
1954 msg_out = MSG_PARITY_ERROR;
1958 * We've set the hardware to assert ATN if we
1959 * get a parity error on "in" phases, so all we
1960 * need to do is stuff the message buffer with
1961 * the appropriate message. "In" phases have set
1962 * mesg_out to something other than MSG_NOP.
1964 ahd->send_msg_perror = msg_out;
1965 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR)
1966 scb->flags |= SCB_TRANSMISSION_ERROR;
1967 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1968 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1973 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1)
1976 * Clear the sources of the interrupts.
1978 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1979 ahd_outb(ahd, CLRLQIINT1, lqistat1);
1982 * If the "illegal" phase changes were in response
1983 * to our ATN to flag a CRC error, AND we ended up
1984 * on packet boundaries, clear the error, restart the
1985 * LQI manager as appropriate, and go on our merry
1986 * way toward sending the message. Otherwise, reset
1987 * the bus to clear the error.
1989 ahd_set_active_fifo(ahd);
1990 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0
1991 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) {
1992 if ((lqistat1 & LQIPHASE_LQ) != 0) {
1993 printf("LQIRETRY for LQIPHASE_LQ\n");
1994 ahd_outb(ahd, LQCTL2, LQIRETRY);
1995 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) {
1996 printf("LQIRETRY for LQIPHASE_NLQ\n");
1997 ahd_outb(ahd, LQCTL2, LQIRETRY);
1999 panic("ahd_handle_lqiphase_error: No phase errors\n");
2000 ahd_dump_card_state(ahd);
2001 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2004 printf("Reseting Channel for LQI Phase error\n");
2005 ahd_dump_card_state(ahd);
2006 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
2011 * Packetized unexpected or expected busfree.
2012 * Entered in mode based on busfreetime.
2015 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime)
2019 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2020 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2021 lqostat1 = ahd_inb(ahd, LQOSTAT1);
2022 if ((lqostat1 & LQOBUSFREE) != 0) {
2031 * The LQO manager detected an unexpected busfree
2034 * 1) During an outgoing LQ.
2035 * 2) After an outgoing LQ but before the first
2036 * REQ of the command packet.
2037 * 3) During an outgoing command packet.
2039 * In all cases, CURRSCB is pointing to the
2040 * SCB that encountered the failure. Clean
2041 * up the queue, clear SELDO and LQOBUSFREE,
2042 * and allow the sequencer to restart the select
2043 * out at its lesure.
2045 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2046 scbid = ahd_inw(ahd, CURRSCB);
2047 scb = ahd_lookup_scb(ahd, scbid);
2049 panic("SCB not valid during LQOBUSFREE");
2053 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE);
2054 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
2055 ahd_outb(ahd, CLRLQOINT1, 0);
2056 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2057 ahd_flush_device_writes(ahd);
2058 ahd_outb(ahd, CLRSINT0, CLRSELDO);
2061 * Return the LQO manager to its idle loop. It will
2062 * not do this automatically if the busfree occurs
2063 * after the first REQ of either the LQ or command
2064 * packet or between the LQ and command packet.
2066 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE);
2069 * Update the waiting for selection queue so
2070 * we restart on the correct SCB.
2072 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD);
2073 saved_scbptr = ahd_get_scbptr(ahd);
2074 if (waiting_h != scbid) {
2076 ahd_outw(ahd, WAITING_TID_HEAD, scbid);
2077 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL);
2078 if (waiting_t == waiting_h) {
2079 ahd_outw(ahd, WAITING_TID_TAIL, scbid);
2080 next = SCB_LIST_NULL;
2082 ahd_set_scbptr(ahd, waiting_h);
2083 next = ahd_inw_scbram(ahd, SCB_NEXT2);
2085 ahd_set_scbptr(ahd, scbid);
2086 ahd_outw(ahd, SCB_NEXT2, next);
2088 ahd_set_scbptr(ahd, saved_scbptr);
2089 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) {
2090 if (SCB_IS_SILENT(scb) == FALSE) {
2091 ahd_print_path(ahd, scb);
2092 printf("Probable outgoing LQ CRC error. "
2093 "Retrying command\n");
2095 scb->crc_retry_count++;
2097 ahd_set_transaction_status(scb, CAM_UNCOR_PARITY);
2098 ahd_freeze_scb(scb);
2099 ahd_freeze_devq(ahd, scb);
2101 /* Return unpausing the sequencer. */
2103 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) {
2105 * Ignore what are really parity errors that
2106 * occur on the last REQ of a free running
2107 * clock prior to going busfree. Some drives
2108 * do not properly active negate just before
2109 * going busfree resulting in a parity glitch.
2111 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE);
2113 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0)
2114 printf("%s: Parity on last REQ detected "
2115 "during busfree phase.\n",
2118 /* Return unpausing the sequencer. */
2121 if (ahd->src_mode != AHD_MODE_SCSI) {
2125 scbid = ahd_get_scbptr(ahd);
2126 scb = ahd_lookup_scb(ahd, scbid);
2127 ahd_print_path(ahd, scb);
2128 printf("Unexpected PKT busfree condition\n");
2129 ahd_dump_card_state(ahd);
2130 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A',
2131 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
2132 ROLE_INITIATOR, CAM_UNEXP_BUSFREE);
2134 /* Return restarting the sequencer. */
2137 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd));
2138 ahd_dump_card_state(ahd);
2139 /* Restart the sequencer. */
2144 * Non-packetized unexpected or expected busfree.
2147 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd)
2149 struct ahd_devinfo devinfo;
2155 u_int initiator_role_id;
2161 * Look at what phase we were last in. If its message out,
2162 * chances are pretty good that the busfree was in response
2163 * to one of our abort requests.
2165 lastphase = ahd_inb(ahd, LASTPHASE);
2166 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
2167 saved_lun = ahd_inb(ahd, SAVED_LUN);
2168 target = SCSIID_TARGET(ahd, saved_scsiid);
2169 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
2170 ahd_compile_devinfo(&devinfo, initiator_role_id,
2171 target, saved_lun, 'A', ROLE_INITIATOR);
2174 scbid = ahd_get_scbptr(ahd);
2175 scb = ahd_lookup_scb(ahd, scbid);
2177 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
2180 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0;
2181 if (lastphase == P_MESGOUT) {
2184 tag = SCB_LIST_NULL;
2185 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE)
2186 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) {
2191 ahd_print_devinfo(ahd, &devinfo);
2192 printf("Abort for unidentified "
2193 "connection completed.\n");
2194 /* restart the sequencer. */
2197 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1];
2198 ahd_print_path(ahd, scb);
2199 printf("SCB %d - Abort%s Completed.\n",
2201 sent_msg == MSG_ABORT_TAG ? "" : " Tag");
2203 if (sent_msg == MSG_ABORT_TAG)
2204 tag = SCB_GET_TAG(scb);
2206 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) {
2208 * This abort is in response to an
2209 * unexpected switch to command phase
2210 * for a packetized connection. Since
2211 * the identify message was never sent,
2212 * "saved lun" is 0. We really want to
2213 * abort only the SCB that encountered
2214 * this error, which could have a different
2215 * lun. The SCB will be retried so the OS
2216 * will see the UA after renegotiating to
2219 tag = SCB_GET_TAG(scb);
2220 saved_lun = scb->hscb->lun;
2222 found = ahd_abort_scbs(ahd, target, 'A', saved_lun,
2223 tag, ROLE_INITIATOR,
2225 printf("found == 0x%x\n", found);
2227 } else if (ahd_sent_msg(ahd, AHDMSG_1B,
2228 MSG_BUS_DEV_RESET, TRUE)) {
2231 * Don't mark the user's request for this BDR
2232 * as completing with CAM_BDR_SENT. CAM3
2233 * specifies CAM_REQ_CMP.
2236 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
2237 && ahd_match_scb(ahd, scb, target, 'A',
2238 CAM_LUN_WILDCARD, SCB_LIST_NULL,
2240 ahd_set_transaction_status(scb, CAM_REQ_CMP);
2242 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD,
2243 CAM_BDR_SENT, "Bus Device Reset",
2244 /*verbose_level*/0);
2246 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE)
2247 && ppr_busfree == 0) {
2248 struct ahd_initiator_tinfo *tinfo;
2249 struct ahd_tmode_tstate *tstate;
2254 * If the previous negotiation was packetized,
2255 * this could be because the device has been
2256 * reset without our knowledge. Force our
2257 * current negotiation to async and retry the
2258 * negotiation. Otherwise retry the command
2259 * with non-ppr negotiation.
2262 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2263 printf("PPR negotiation rejected busfree.\n");
2265 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
2267 devinfo.target, &tstate);
2268 if ((tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ)!=0) {
2269 ahd_set_width(ahd, &devinfo,
2270 MSG_EXT_WDTR_BUS_8_BIT,
2273 ahd_set_syncrate(ahd, &devinfo,
2274 /*period*/0, /*offset*/0,
2279 * The expect PPR busfree handler below
2280 * will effect the retry and necessary
2284 tinfo->curr.transport_version = 2;
2285 tinfo->goal.transport_version = 2;
2286 tinfo->goal.ppr_options = 0;
2288 * Remove any SCBs in the waiting for selection
2289 * queue that may also be for this target so
2290 * that command ordering is preserved.
2292 ahd_freeze_devq(ahd, scb);
2293 ahd_qinfifo_requeue_tail(ahd, scb);
2296 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE)
2297 && ppr_busfree == 0) {
2299 * Negotiation Rejected. Go-narrow and
2303 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2304 printf("WDTR negotiation rejected busfree.\n");
2306 ahd_set_width(ahd, &devinfo,
2307 MSG_EXT_WDTR_BUS_8_BIT,
2308 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2311 * Remove any SCBs in the waiting for selection
2312 * queue that may also be for this target so that
2313 * command ordering is preserved.
2315 ahd_freeze_devq(ahd, scb);
2316 ahd_qinfifo_requeue_tail(ahd, scb);
2318 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)
2319 && ppr_busfree == 0) {
2321 * Negotiation Rejected. Go-async and
2325 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2326 printf("SDTR negotiation rejected busfree.\n");
2328 ahd_set_syncrate(ahd, &devinfo,
2329 /*period*/0, /*offset*/0,
2331 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2334 * Remove any SCBs in the waiting for selection
2335 * queue that may also be for this target so that
2336 * command ordering is preserved.
2338 ahd_freeze_devq(ahd, scb);
2339 ahd_qinfifo_requeue_tail(ahd, scb);
2341 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0
2342 && ahd_sent_msg(ahd, AHDMSG_1B,
2343 MSG_INITIATOR_DET_ERR, TRUE)) {
2346 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2347 printf("Expected IDE Busfree\n");
2350 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE)
2351 && ahd_sent_msg(ahd, AHDMSG_1B,
2352 MSG_MESSAGE_REJECT, TRUE)) {
2355 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2356 printf("Expected QAS Reject Busfree\n");
2363 * The busfree required flag is honored at the end of
2364 * the message phases. We check it last in case we
2365 * had to send some other message that caused a busfree.
2368 && (lastphase == P_MESGIN || lastphase == P_MESGOUT)
2369 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) {
2371 ahd_freeze_devq(ahd, scb);
2372 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ);
2373 ahd_freeze_scb(scb);
2374 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) {
2375 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
2376 SCB_GET_CHANNEL(ahd, scb),
2377 SCB_GET_LUN(scb), SCB_LIST_NULL,
2378 ROLE_INITIATOR, CAM_REQ_ABORTED);
2381 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2382 printf("PPR Negotiation Busfree.\n");
2388 if (printerror != 0) {
2395 if ((scb->hscb->control & TAG_ENB) != 0)
2396 tag = SCB_GET_TAG(scb);
2398 tag = SCB_LIST_NULL;
2399 ahd_print_path(ahd, scb);
2400 aborted = ahd_abort_scbs(ahd, target, 'A',
2401 SCB_GET_LUN(scb), tag,
2406 * We had not fully identified this connection,
2407 * so we cannot abort anything.
2409 printf("%s: ", ahd_name(ahd));
2411 printf("Unexpected busfree %s, %d SCBs aborted, "
2412 "PRGMCNT == 0x%x\n",
2413 ahd_lookup_phase_entry(lastphase)->phasemsg,
2415 ahd_inw(ahd, PRGMCNT));
2416 ahd_dump_card_state(ahd);
2417 if (lastphase != P_BUSFREE)
2418 ahd_force_renegotiation(ahd, &devinfo);
2420 /* Always restart the sequencer. */
2425 ahd_handle_proto_violation(struct ahd_softc *ahd)
2427 struct ahd_devinfo devinfo;
2435 ahd_fetch_devinfo(ahd, &devinfo);
2436 scbid = ahd_get_scbptr(ahd);
2437 scb = ahd_lookup_scb(ahd, scbid);
2438 seq_flags = ahd_inb(ahd, SEQ_FLAGS);
2439 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
2440 lastphase = ahd_inb(ahd, LASTPHASE);
2441 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2444 * The reconnecting target either did not send an
2445 * identify message, or did, but we didn't find an SCB
2448 ahd_print_devinfo(ahd, &devinfo);
2449 printf("Target did not send an IDENTIFY message. "
2450 "LASTPHASE = 0x%x.\n", lastphase);
2452 } else if (scb == NULL) {
2454 * We don't seem to have an SCB active for this
2455 * transaction. Print an error and reset the bus.
2457 ahd_print_devinfo(ahd, &devinfo);
2458 printf("No SCB found during protocol violation\n");
2459 goto proto_violation_reset;
2461 ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2462 if ((seq_flags & NO_CDB_SENT) != 0) {
2463 ahd_print_path(ahd, scb);
2464 printf("No or incomplete CDB sent to device.\n");
2465 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL)
2466 & STATUS_RCVD) == 0) {
2468 * The target never bothered to provide status to
2469 * us prior to completing the command. Since we don't
2470 * know the disposition of this command, we must attempt
2471 * to abort it. Assert ATN and prepare to send an abort
2474 ahd_print_path(ahd, scb);
2475 printf("Completed command without status.\n");
2477 ahd_print_path(ahd, scb);
2478 printf("Unknown protocol violation.\n");
2479 ahd_dump_card_state(ahd);
2482 if ((lastphase & ~P_DATAIN_DT) == 0
2483 || lastphase == P_COMMAND) {
2484 proto_violation_reset:
2486 * Target either went directly to data
2487 * phase or didn't respond to our ATN.
2488 * The only safe thing to do is to blow
2489 * it away with a bus reset.
2491 found = ahd_reset_channel(ahd, 'A', TRUE);
2492 printf("%s: Issued Channel %c Bus Reset. "
2493 "%d SCBs aborted\n", ahd_name(ahd), 'A', found);
2496 * Leave the selection hardware off in case
2497 * this abort attempt will affect yet to
2500 ahd_outb(ahd, SCSISEQ0,
2501 ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2502 ahd_assert_atn(ahd);
2503 ahd_outb(ahd, MSG_OUT, HOST_MSG);
2505 ahd_print_devinfo(ahd, &devinfo);
2506 ahd->msgout_buf[0] = MSG_ABORT_TASK;
2507 ahd->msgout_len = 1;
2508 ahd->msgout_index = 0;
2509 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2511 ahd_print_path(ahd, scb);
2512 scb->flags |= SCB_ABORT;
2514 printf("Protocol violation %s. Attempting to abort.\n",
2515 ahd_lookup_phase_entry(curphase)->phasemsg);
2520 * Force renegotiation to occur the next time we initiate
2521 * a command to the current device.
2524 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
2526 struct ahd_initiator_tinfo *targ_info;
2527 struct ahd_tmode_tstate *tstate;
2530 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
2531 ahd_print_devinfo(ahd, devinfo);
2532 printf("Forcing renegotiation\n");
2535 targ_info = ahd_fetch_transinfo(ahd,
2537 devinfo->our_scsiid,
2540 ahd_update_neg_request(ahd, devinfo, tstate,
2541 targ_info, AHD_NEG_IF_NON_ASYNC);
2544 #define AHD_MAX_STEPS 2000
2546 ahd_clear_critical_section(struct ahd_softc *ahd)
2548 ahd_mode_state saved_modes;
2560 if (ahd->num_critical_sections == 0)
2573 saved_modes = ahd_save_modes(ahd);
2579 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2580 seqaddr = ahd_inw(ahd, CURADDR);
2582 cs = ahd->critical_sections;
2583 for (i = 0; i < ahd->num_critical_sections; i++, cs++) {
2585 if (cs->begin < seqaddr && cs->end >= seqaddr)
2589 if (i == ahd->num_critical_sections)
2592 if (steps > AHD_MAX_STEPS) {
2593 printf("%s: Infinite loop in critical section\n"
2594 "%s: First Instruction 0x%x now 0x%x\n",
2595 ahd_name(ahd), ahd_name(ahd), first_instr,
2597 ahd_dump_card_state(ahd);
2598 panic("critical section loop");
2603 if ((ahd_debug & AHD_SHOW_MISC) != 0)
2604 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd),
2607 if (stepping == FALSE) {
2609 first_instr = seqaddr;
2610 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2611 simode0 = ahd_inb(ahd, SIMODE0);
2612 simode3 = ahd_inb(ahd, SIMODE3);
2613 lqimode0 = ahd_inb(ahd, LQIMODE0);
2614 lqimode1 = ahd_inb(ahd, LQIMODE1);
2615 lqomode0 = ahd_inb(ahd, LQOMODE0);
2616 lqomode1 = ahd_inb(ahd, LQOMODE1);
2617 ahd_outb(ahd, SIMODE0, 0);
2618 ahd_outb(ahd, SIMODE3, 0);
2619 ahd_outb(ahd, LQIMODE0, 0);
2620 ahd_outb(ahd, LQIMODE1, 0);
2621 ahd_outb(ahd, LQOMODE0, 0);
2622 ahd_outb(ahd, LQOMODE1, 0);
2623 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2624 simode1 = ahd_inb(ahd, SIMODE1);
2626 * We don't clear ENBUSFREE. Unfortunately
2627 * we cannot re-enable busfree detection within
2628 * the current connection, so we must leave it
2629 * on while single stepping.
2631 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE);
2632 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP);
2635 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
2636 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2637 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
2638 ahd_outb(ahd, HCNTRL, ahd->unpause);
2639 while (!ahd_is_paused(ahd))
2641 ahd_update_modes(ahd);
2644 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2645 ahd_outb(ahd, SIMODE0, simode0);
2646 ahd_outb(ahd, SIMODE3, simode3);
2647 ahd_outb(ahd, LQIMODE0, lqimode0);
2648 ahd_outb(ahd, LQIMODE1, lqimode1);
2649 ahd_outb(ahd, LQOMODE0, lqomode0);
2650 ahd_outb(ahd, LQOMODE1, lqomode1);
2651 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2652 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP);
2653 ahd_outb(ahd, SIMODE1, simode1);
2655 * SCSIINT seems to glitch occassionally when
2656 * the interrupt masks are restored. Clear SCSIINT
2657 * one more time so that only persistent errors
2658 * are seen as a real interrupt.
2660 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2662 ahd_restore_modes(ahd, saved_modes);
2666 * Clear any pending interrupt status.
2669 ahd_clear_intstat(struct ahd_softc *ahd)
2671 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2672 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2673 /* Clear any interrupt conditions this may have caused */
2674 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2
2675 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD);
2676 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT
2677 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI
2678 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ);
2679 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ
2680 |CLRLQOATNPKT|CLRLQOTCRC);
2681 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS
2682 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT);
2683 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
2684 ahd_outb(ahd, CLRLQOINT0, 0);
2685 ahd_outb(ahd, CLRLQOINT1, 0);
2687 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR);
2688 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
2689 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT);
2690 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO
2691 |CLRIOERR|CLROVERRUN);
2692 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2695 /**************************** Debugging Routines ******************************/
2697 uint32_t ahd_debug = AHD_DEBUG_OPTS;
2700 ahd_print_scb(struct scb *scb)
2702 struct hardware_scb *hscb;
2706 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
2712 printf("Shared Data: ");
2713 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++)
2714 printf("%#02x", hscb->shared_data.idata.cdb[i]);
2715 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n",
2716 (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF),
2717 (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF),
2718 ahd_le32toh(hscb->datacnt),
2719 ahd_le32toh(hscb->sgptr),
2721 ahd_dump_sglist(scb);
2725 ahd_dump_sglist(struct scb *scb)
2729 if (scb->sg_count > 0) {
2730 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) {
2731 struct ahd_dma64_seg *sg_list;
2733 sg_list = (struct ahd_dma64_seg*)scb->sg_list;
2734 for (i = 0; i < scb->sg_count; i++) {
2738 addr = ahd_le64toh(sg_list[i].addr);
2739 len = ahd_le32toh(sg_list[i].len);
2740 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2742 (uint32_t)((addr >> 32) & 0xFFFFFFFF),
2743 (uint32_t)(addr & 0xFFFFFFFF),
2744 sg_list[i].len & AHD_SG_LEN_MASK,
2745 (sg_list[i].len & AHD_DMA_LAST_SEG)
2749 struct ahd_dma_seg *sg_list;
2751 sg_list = (struct ahd_dma_seg*)scb->sg_list;
2752 for (i = 0; i < scb->sg_count; i++) {
2755 len = ahd_le32toh(sg_list[i].len);
2756 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2758 (len & AHD_SG_HIGH_ADDR_MASK) >> 24,
2759 ahd_le32toh(sg_list[i].addr),
2760 len & AHD_SG_LEN_MASK,
2761 len & AHD_DMA_LAST_SEG ? " Last" : "");
2767 /************************* Transfer Negotiation *******************************/
2769 * Allocate per target mode instance (ID we respond to as a target)
2770 * transfer negotiation data structures.
2772 static struct ahd_tmode_tstate *
2773 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel)
2775 struct ahd_tmode_tstate *master_tstate;
2776 struct ahd_tmode_tstate *tstate;
2779 master_tstate = ahd->enabled_targets[ahd->our_id];
2780 if (ahd->enabled_targets[scsi_id] != NULL
2781 && ahd->enabled_targets[scsi_id] != master_tstate)
2782 panic("%s: ahd_alloc_tstate - Target already allocated",
2784 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT);
2789 * If we have allocated a master tstate, copy user settings from
2790 * the master tstate (taken from SRAM or the EEPROM) for this
2791 * channel, but reset our current and goal settings to async/narrow
2792 * until an initiator talks to us.
2794 if (master_tstate != NULL) {
2795 memcpy(tstate, master_tstate, sizeof(*tstate));
2796 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
2797 for (i = 0; i < 16; i++) {
2798 memset(&tstate->transinfo[i].curr, 0,
2799 sizeof(tstate->transinfo[i].curr));
2800 memset(&tstate->transinfo[i].goal, 0,
2801 sizeof(tstate->transinfo[i].goal));
2804 memset(tstate, 0, sizeof(*tstate));
2805 ahd->enabled_targets[scsi_id] = tstate;
2809 #ifdef AHD_TARGET_MODE
2811 * Free per target mode instance (ID we respond to as a target)
2812 * transfer negotiation data structures.
2815 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force)
2817 struct ahd_tmode_tstate *tstate;
2820 * Don't clean up our "master" tstate.
2821 * It has our default user settings.
2823 if (scsi_id == ahd->our_id
2827 tstate = ahd->enabled_targets[scsi_id];
2829 free(tstate, M_DEVBUF);
2830 ahd->enabled_targets[scsi_id] = NULL;
2835 * Called when we have an active connection to a target on the bus,
2836 * this function finds the nearest period to the input period limited
2837 * by the capabilities of the bus connectivity of and sync settings for
2841 ahd_devlimited_syncrate(struct ahd_softc *ahd,
2842 struct ahd_initiator_tinfo *tinfo,
2843 u_int *period, u_int *ppr_options, role_t role)
2845 struct ahd_transinfo *transinfo;
2848 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0
2849 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) {
2850 maxsync = AHD_SYNCRATE_PACED;
2852 maxsync = AHD_SYNCRATE_ULTRA;
2853 /* Can't do DT related options on an SE bus */
2854 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2857 * Never allow a value higher than our current goal
2858 * period otherwise we may allow a target initiated
2859 * negotiation to go above the limit as set by the
2860 * user. In the case of an initiator initiated
2861 * sync negotiation, we limit based on the user
2862 * setting. This allows the system to still accept
2863 * incoming negotiations even if target initiated
2864 * negotiation is not performed.
2866 if (role == ROLE_TARGET)
2867 transinfo = &tinfo->user;
2869 transinfo = &tinfo->goal;
2870 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN);
2871 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
2872 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2);
2873 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2875 if (transinfo->period == 0) {
2879 *period = MAX(*period, transinfo->period);
2880 ahd_find_syncrate(ahd, period, ppr_options, maxsync);
2885 * Look up the valid period to SCSIRATE conversion in our table.
2886 * Return the period and offset that should be sent to the target
2887 * if this was the beginning of an SDTR.
2890 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
2891 u_int *ppr_options, u_int maxsync)
2893 if (*period < maxsync)
2896 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0
2897 && *period > AHD_SYNCRATE_MIN_DT)
2898 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2900 if (*period > AHD_SYNCRATE_MIN)
2903 /* Honor PPR option conformance rules. */
2904 if (*period > AHD_SYNCRATE_PACED)
2905 *ppr_options &= ~MSG_EXT_PPR_RTI;
2907 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
2908 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ);
2910 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0)
2911 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2913 /* Skip all PACED only entries if IU is not available */
2914 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0
2915 && *period < AHD_SYNCRATE_DT)
2916 *period = AHD_SYNCRATE_DT;
2918 /* Skip all DT only entries if DT is not available */
2919 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2920 && *period < AHD_SYNCRATE_ULTRA2)
2921 *period = AHD_SYNCRATE_ULTRA2;
2925 * Truncate the given synchronous offset to a value the
2926 * current adapter type and syncrate are capable of.
2929 ahd_validate_offset(struct ahd_softc *ahd,
2930 struct ahd_initiator_tinfo *tinfo,
2931 u_int period, u_int *offset, int wide,
2936 /* Limit offset to what we can do */
2939 else if (period <= AHD_SYNCRATE_PACED) {
2940 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0)
2941 maxoffset = MAX_OFFSET_PACED_BUG;
2943 maxoffset = MAX_OFFSET_PACED;
2945 maxoffset = MAX_OFFSET_NON_PACED;
2946 *offset = MIN(*offset, maxoffset);
2947 if (tinfo != NULL) {
2948 if (role == ROLE_TARGET)
2949 *offset = MIN(*offset, tinfo->user.offset);
2951 *offset = MIN(*offset, tinfo->goal.offset);
2956 * Truncate the given transfer width parameter to a value the
2957 * current adapter type is capable of.
2960 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo,
2961 u_int *bus_width, role_t role)
2963 switch (*bus_width) {
2965 if (ahd->features & AHD_WIDE) {
2967 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
2971 case MSG_EXT_WDTR_BUS_8_BIT:
2972 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
2975 if (tinfo != NULL) {
2976 if (role == ROLE_TARGET)
2977 *bus_width = MIN(tinfo->user.width, *bus_width);
2979 *bus_width = MIN(tinfo->goal.width, *bus_width);
2984 * Update the bitmask of targets for which the controller should
2985 * negotiate with at the next convenient oportunity. This currently
2986 * means the next time we send the initial identify messages for
2987 * a new transaction.
2990 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
2991 struct ahd_tmode_tstate *tstate,
2992 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type)
2994 u_int auto_negotiate_orig;
2996 auto_negotiate_orig = tstate->auto_negotiate;
2997 if (neg_type == AHD_NEG_ALWAYS) {
2999 * Force our "current" settings to be
3000 * unknown so that unless a bus reset
3001 * occurs the need to renegotiate is
3002 * recorded persistently.
3004 if ((ahd->features & AHD_WIDE) != 0)
3005 tinfo->curr.width = AHD_WIDTH_UNKNOWN;
3006 tinfo->curr.period = AHD_PERIOD_UNKNOWN;
3007 tinfo->curr.offset = AHD_OFFSET_UNKNOWN;
3009 if (tinfo->curr.period != tinfo->goal.period
3010 || tinfo->curr.width != tinfo->goal.width
3011 || tinfo->curr.offset != tinfo->goal.offset
3012 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
3013 || (neg_type == AHD_NEG_IF_NON_ASYNC
3014 && (tinfo->goal.offset != 0
3015 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
3016 || tinfo->goal.ppr_options != 0)))
3017 tstate->auto_negotiate |= devinfo->target_mask;
3019 tstate->auto_negotiate &= ~devinfo->target_mask;
3021 return (auto_negotiate_orig != tstate->auto_negotiate);
3025 * Update the user/goal/curr tables of synchronous negotiation
3026 * parameters as well as, in the case of a current or active update,
3027 * any data structures on the host controller. In the case of an
3028 * active update, the specified target is currently talking to us on
3029 * the bus, so the transfer parameter update must take effect
3033 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3034 u_int period, u_int offset, u_int ppr_options,
3035 u_int type, int paused)
3037 struct ahd_initiator_tinfo *tinfo;
3038 struct ahd_tmode_tstate *tstate;
3045 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3048 if (period == 0 || offset == 0) {
3053 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3054 devinfo->target, &tstate);
3056 if ((type & AHD_TRANS_USER) != 0) {
3057 tinfo->user.period = period;
3058 tinfo->user.offset = offset;
3059 tinfo->user.ppr_options = ppr_options;
3062 if ((type & AHD_TRANS_GOAL) != 0) {
3063 tinfo->goal.period = period;
3064 tinfo->goal.offset = offset;
3065 tinfo->goal.ppr_options = ppr_options;
3068 old_period = tinfo->curr.period;
3069 old_offset = tinfo->curr.offset;
3070 old_ppr = tinfo->curr.ppr_options;
3072 if ((type & AHD_TRANS_CUR) != 0
3073 && (old_period != period
3074 || old_offset != offset
3075 || old_ppr != ppr_options)) {
3079 tinfo->curr.period = period;
3080 tinfo->curr.offset = offset;
3081 tinfo->curr.ppr_options = ppr_options;
3083 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3084 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3089 printf("%s: target %d synchronous with "
3090 "period = 0x%x, offset = 0x%x",
3091 ahd_name(ahd), devinfo->target,
3094 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) {
3098 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) {
3099 printf("%s", options ? "|DT" : "(DT");
3102 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) {
3103 printf("%s", options ? "|IU" : "(IU");
3106 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) {
3107 printf("%s", options ? "|RTI" : "(RTI");
3110 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) {
3111 printf("%s", options ? "|QAS" : "(QAS");
3119 printf("%s: target %d using "
3120 "asynchronous transfers%s\n",
3121 ahd_name(ahd), devinfo->target,
3122 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0
3128 * Always refresh the neg-table to handle the case of the
3129 * sequencer setting the ENATNO bit for a MK_MESSAGE request.
3130 * We will always renegotiate in that case if this is a
3131 * packetized request. Also manage the busfree expected flag
3132 * from this common routine so that we catch changes due to
3133 * WDTR or SDTR messages.
3135 if ((type & AHD_TRANS_CUR) != 0) {
3138 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3141 if (ahd->msg_type != MSG_TYPE_NONE) {
3142 if ((old_ppr & MSG_EXT_PPR_IU_REQ)
3143 != (ppr_options & MSG_EXT_PPR_IU_REQ)) {
3145 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3146 ahd_print_devinfo(ahd, devinfo);
3147 printf("Expecting IU Change busfree\n");
3150 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
3151 | MSG_FLAG_IU_REQ_CHANGED;
3153 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) {
3155 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3156 printf("PPR with IU_REQ outstanding\n");
3158 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE;
3163 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3164 tinfo, AHD_NEG_TO_GOAL);
3166 if (update_needed && active)
3167 ahd_update_pending_scbs(ahd);
3171 * Update the user/goal/curr tables of wide negotiation
3172 * parameters as well as, in the case of a current or active update,
3173 * any data structures on the host controller. In the case of an
3174 * active update, the specified target is currently talking to us on
3175 * the bus, so the transfer parameter update must take effect
3179 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3180 u_int width, u_int type, int paused)
3182 struct ahd_initiator_tinfo *tinfo;
3183 struct ahd_tmode_tstate *tstate;
3188 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3190 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3191 devinfo->target, &tstate);
3193 if ((type & AHD_TRANS_USER) != 0)
3194 tinfo->user.width = width;
3196 if ((type & AHD_TRANS_GOAL) != 0)
3197 tinfo->goal.width = width;
3199 oldwidth = tinfo->curr.width;
3200 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) {
3204 tinfo->curr.width = width;
3205 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3206 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3208 printf("%s: target %d using %dbit transfers\n",
3209 ahd_name(ahd), devinfo->target,
3210 8 * (0x01 << width));
3214 if ((type & AHD_TRANS_CUR) != 0) {
3217 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3222 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3223 tinfo, AHD_NEG_TO_GOAL);
3224 if (update_needed && active)
3225 ahd_update_pending_scbs(ahd);
3230 * Update the current state of tagged queuing for a given target.
3233 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3236 ahd_platform_set_tags(ahd, devinfo, alg);
3237 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3238 devinfo->lun, AC_TRANSFER_NEG, &alg);
3242 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3243 struct ahd_transinfo *tinfo)
3245 ahd_mode_state saved_modes;
3250 u_int saved_negoaddr;
3251 uint8_t iocell_opts[sizeof(ahd->iocell_opts)];
3253 saved_modes = ahd_save_modes(ahd);
3254 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3256 saved_negoaddr = ahd_inb(ahd, NEGOADDR);
3257 ahd_outb(ahd, NEGOADDR, devinfo->target);
3258 period = tinfo->period;
3259 offset = tinfo->offset;
3260 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts));
3261 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ
3262 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI);
3265 period = AHD_SYNCRATE_ASYNC;
3266 if (period == AHD_SYNCRATE_160) {
3268 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3270 * When the SPI4 spec was finalized, PACE transfers
3271 * was not made a configurable option in the PPR
3272 * message. Instead it is assumed to be enabled for
3273 * any syncrate faster than 80MHz. Nevertheless,
3274 * Harpoon2A4 allows this to be configurable.
3276 * Harpoon2A4 also assumes at most 2 data bytes per
3277 * negotiated REQ/ACK offset. Paced transfers take
3278 * 4, so we must adjust our offset.
3280 ppr_opts |= PPROPT_PACE;
3284 * Harpoon2A assumed that there would be a
3285 * fallback rate between 160MHz and 80Mhz,
3286 * so 7 is used as the period factor rather
3287 * than 8 for 160MHz.
3289 period = AHD_SYNCRATE_REVA_160;
3291 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0)
3292 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3296 * Precomp should be disabled for non-paced transfers.
3298 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK;
3300 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0
3301 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0
3302 && (ppr_opts & MSG_EXT_PPR_IU_REQ) == 0) {
3304 * Slow down our CRC interval to be
3305 * compatible with non-packetized
3306 * U160 devices that can't handle a
3307 * CRC at full speed.
3309 con_opts |= ENSLOWCRC;
3312 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3314 * On H2A4, revert to a slower slewrate
3315 * on non-paced transfers.
3317 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3322 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW);
3323 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]);
3324 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE);
3325 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]);
3327 ahd_outb(ahd, NEGPERIOD, period);
3328 ahd_outb(ahd, NEGPPROPTS, ppr_opts);
3329 ahd_outb(ahd, NEGOFFSET, offset);
3331 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT)
3332 con_opts |= WIDEXFER;
3335 * During packetized transfers, the target will
3336 * give us the oportunity to send command packets
3337 * without us asserting attention.
3339 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
3340 con_opts |= ENAUTOATNO;
3341 ahd_outb(ahd, NEGCONOPTS, con_opts);
3342 ahd_outb(ahd, NEGOADDR, saved_negoaddr);
3343 ahd_restore_modes(ahd, saved_modes);
3347 * When the transfer settings for a connection change, setup for
3348 * negotiation in pending SCBs to effect the change as quickly as
3349 * possible. We also cancel any negotiations that are scheduled
3350 * for inflight SCBs that have not been started yet.
3353 ahd_update_pending_scbs(struct ahd_softc *ahd)
3355 struct scb *pending_scb;
3356 int pending_scb_count;
3359 ahd_mode_state saved_modes;
3362 * Traverse the pending SCB list and ensure that all of the
3363 * SCBs there have the proper settings. We can only safely
3364 * clear the negotiation required flag (setting requires the
3365 * execution queue to be modified) and this is only possible
3366 * if we are not already attempting to select out for this
3367 * SCB. For this reason, all callers only call this routine
3368 * if we are changing the negotiation settings for the currently
3369 * active transaction on the bus.
3371 pending_scb_count = 0;
3372 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3373 struct ahd_devinfo devinfo;
3374 struct ahd_initiator_tinfo *tinfo;
3375 struct ahd_tmode_tstate *tstate;
3377 ahd_scb_devinfo(ahd, &devinfo, pending_scb);
3378 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
3380 devinfo.target, &tstate);
3381 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
3382 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
3383 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
3384 pending_scb->hscb->control &= ~MK_MESSAGE;
3386 ahd_sync_scb(ahd, pending_scb,
3387 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3388 pending_scb_count++;
3391 if (pending_scb_count == 0)
3394 if (ahd_is_paused(ahd)) {
3402 * Force the sequencer to reinitialize the selection for
3403 * the command at the head of the execution queue if it
3404 * has already been setup. The negotiation changes may
3405 * effect whether we select-out with ATN. It is only
3406 * safe to clear ENSELO when the bus is not free and no
3407 * selection is in progres or completed.
3409 saved_modes = ahd_save_modes(ahd);
3410 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3411 if ((ahd_inb(ahd, SCSISIGI) & BSYI) != 0
3412 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0)
3413 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
3414 saved_scbptr = ahd_get_scbptr(ahd);
3415 /* Ensure that the hscbs down on the card match the new information */
3416 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3420 scb_tag = SCB_GET_TAG(pending_scb);
3421 ahd_set_scbptr(ahd, scb_tag);
3422 control = ahd_inb_scbram(ahd, SCB_CONTROL);
3423 control &= ~MK_MESSAGE;
3424 control |= pending_scb->hscb->control & MK_MESSAGE;
3425 ahd_outb(ahd, SCB_CONTROL, control);
3427 ahd_set_scbptr(ahd, saved_scbptr);
3428 ahd_restore_modes(ahd, saved_modes);
3434 /**************************** Pathing Information *****************************/
3436 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3438 ahd_mode_state saved_modes;
3443 saved_modes = ahd_save_modes(ahd);
3444 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3446 if (ahd_inb(ahd, SSTAT0) & TARGET)
3449 role = ROLE_INITIATOR;
3451 if (role == ROLE_TARGET
3452 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) {
3453 /* We were selected, so pull our id from TARGIDIN */
3454 our_id = ahd_inb(ahd, TARGIDIN) & OID;
3455 } else if (role == ROLE_TARGET)
3456 our_id = ahd_inb(ahd, TOWNID);
3458 our_id = ahd_inb(ahd, IOWNID);
3460 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
3461 ahd_compile_devinfo(devinfo,
3463 SCSIID_TARGET(ahd, saved_scsiid),
3464 ahd_inb(ahd, SAVED_LUN),
3465 SCSIID_CHANNEL(ahd, saved_scsiid),
3467 ahd_restore_modes(ahd, saved_modes);
3471 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3473 printf("%s:%c:%d:%d: ", ahd_name(ahd), 'A',
3474 devinfo->target, devinfo->lun);
3477 struct ahd_phase_table_entry*
3478 ahd_lookup_phase_entry(int phase)
3480 struct ahd_phase_table_entry *entry;
3481 struct ahd_phase_table_entry *last_entry;
3484 * num_phases doesn't include the default entry which
3485 * will be returned if the phase doesn't match.
3487 last_entry = &ahd_phase_table[num_phases];
3488 for (entry = ahd_phase_table; entry < last_entry; entry++) {
3489 if (phase == entry->phase)
3496 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target,
3497 u_int lun, char channel, role_t role)
3499 devinfo->our_scsiid = our_id;
3500 devinfo->target = target;
3502 devinfo->target_offset = target;
3503 devinfo->channel = channel;
3504 devinfo->role = role;
3506 devinfo->target_offset += 8;
3507 devinfo->target_mask = (0x01 << devinfo->target_offset);
3511 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3517 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
3518 role = ROLE_INITIATOR;
3519 if ((scb->hscb->control & TARGET_SCB) != 0)
3521 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb),
3522 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role);
3526 /************************ Message Phase Processing ****************************/
3528 * When an initiator transaction with the MK_MESSAGE flag either reconnects
3529 * or enters the initial message out phase, we are interrupted. Fill our
3530 * outgoing message buffer with the appropriate message and beging handing
3531 * the message phase(s) manually.
3534 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3538 * To facilitate adding multiple messages together,
3539 * each routine should increment the index and len
3540 * variables instead of setting them explicitly.
3542 ahd->msgout_index = 0;
3543 ahd->msgout_len = 0;
3545 if (ahd_currently_packetized(ahd))
3546 ahd->msg_flags |= MSG_FLAG_PACKETIZED;
3548 if (ahd->send_msg_perror
3549 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) {
3550 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror;
3552 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3554 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3555 printf("Setting up for Parity Error delivery\n");
3558 } else if (scb == NULL) {
3559 printf("%s: WARNING. No pending message for "
3560 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd));
3561 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP;
3563 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3567 if ((scb->flags & SCB_DEVICE_RESET) == 0
3568 && (scb->flags & SCB_PACKETIZED) == 0
3569 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) {
3572 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
3573 if ((scb->hscb->control & DISCENB) != 0)
3574 identify_msg |= MSG_IDENTIFY_DISCFLAG;
3575 ahd->msgout_buf[ahd->msgout_index++] = identify_msg;
3578 if ((scb->hscb->control & TAG_ENB) != 0) {
3579 ahd->msgout_buf[ahd->msgout_index++] =
3580 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
3581 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb);
3582 ahd->msgout_len += 2;
3586 if (scb->flags & SCB_DEVICE_RESET) {
3587 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET;
3589 ahd_print_path(ahd, scb);
3590 printf("Bus Device Reset Message Sent\n");
3592 * Clear our selection hardware in advance of
3593 * the busfree. We may have an entry in the waiting
3594 * Q for this target, and we don't want to go about
3595 * selecting while we handle the busfree and blow it
3598 ahd_outb(ahd, SCSISEQ0, 0);
3599 } else if ((scb->flags & SCB_ABORT) != 0) {
3601 if ((scb->hscb->control & TAG_ENB) != 0) {
3602 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG;
3604 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT;
3607 ahd_print_path(ahd, scb);
3608 printf("Abort%s Message Sent\n",
3609 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
3611 * Clear our selection hardware in advance of
3612 * the busfree. We may have an entry in the waiting
3613 * Q for this target, and we don't want to go about
3614 * selecting while we handle the busfree and blow it
3617 ahd_outb(ahd, SCSISEQ0, 0);
3618 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
3619 ahd_build_transfer_msg(ahd, devinfo);
3621 * Clear our selection hardware in advance of potential
3622 * PPR IU status change busfree. We may have an entry in
3623 * the waiting Q for this target, and we don't want to go
3624 * about selecting while we handle the busfree and blow
3627 ahd_outb(ahd, SCSISEQ0, 0);
3629 printf("ahd_intr: AWAITING_MSG for an SCB that "
3630 "does not have a waiting message\n");
3631 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
3632 devinfo->target_mask);
3633 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x "
3634 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control,
3635 ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT),
3640 * Clear the MK_MESSAGE flag from the SCB so we aren't
3641 * asked to send this message again.
3643 ahd_outb(ahd, SCB_CONTROL,
3644 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
3645 scb->hscb->control &= ~MK_MESSAGE;
3646 ahd->msgout_index = 0;
3647 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3651 * Build an appropriate transfer negotiation message for the
3652 * currently active target.
3655 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3658 * We need to initiate transfer negotiations.
3659 * If our current and goal settings are identical,
3660 * we want to renegotiate due to a check condition.
3662 struct ahd_initiator_tinfo *tinfo;
3663 struct ahd_tmode_tstate *tstate;
3671 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3672 devinfo->target, &tstate);
3674 * Filter our period based on the current connection.
3675 * If we can't perform DT transfers on this segment (not in LVD
3676 * mode for instance), then our decision to issue a PPR message
3679 period = tinfo->goal.period;
3680 offset = tinfo->goal.offset;
3681 ppr_options = tinfo->goal.ppr_options;
3682 /* Target initiated PPR is not allowed in the SCSI spec */
3683 if (devinfo->role == ROLE_TARGET)
3685 ahd_devlimited_syncrate(ahd, tinfo, &period,
3686 &ppr_options, devinfo->role);
3687 dowide = tinfo->curr.width != tinfo->goal.width;
3688 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
3690 * Only use PPR if we have options that need it, even if the device
3691 * claims to support it. There might be an expander in the way
3694 doppr = ppr_options != 0;
3696 if (!dowide && !dosync && !doppr) {
3697 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
3698 dosync = tinfo->goal.offset != 0;
3701 if (!dowide && !dosync && !doppr) {
3703 * Force async with a WDTR message if we have a wide bus,
3704 * or just issue an SDTR with a 0 offset.
3706 if ((ahd->features & AHD_WIDE) != 0)
3712 ahd_print_devinfo(ahd, devinfo);
3713 printf("Ensuring async\n");
3716 /* Target initiated PPR is not allowed in the SCSI spec */
3717 if (devinfo->role == ROLE_TARGET)
3721 * Both the PPR message and SDTR message require the
3722 * goal syncrate to be limited to what the target device
3723 * is capable of handling (based on whether an LVD->SE
3724 * expander is on the bus), so combine these two cases.
3725 * Regardless, guarantee that if we are using WDTR and SDTR
3726 * messages that WDTR comes first.
3728 if (doppr || (dosync && !dowide)) {
3730 offset = tinfo->goal.offset;
3731 ahd_validate_offset(ahd, tinfo, period, &offset,
3732 doppr ? tinfo->goal.width
3733 : tinfo->curr.width,
3736 ahd_construct_ppr(ahd, devinfo, period, offset,
3737 tinfo->goal.width, ppr_options);
3739 ahd_construct_sdtr(ahd, devinfo, period, offset);
3742 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width);
3747 * Build a synchronous negotiation message in our message
3748 * buffer based on the input parameters.
3751 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3752 u_int period, u_int offset)
3755 period = AHD_ASYNC_XFER_PERIOD;
3756 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3757 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN;
3758 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR;
3759 ahd->msgout_buf[ahd->msgout_index++] = period;
3760 ahd->msgout_buf[ahd->msgout_index++] = offset;
3761 ahd->msgout_len += 5;
3763 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
3764 ahd_name(ahd), devinfo->channel, devinfo->target,
3765 devinfo->lun, period, offset);
3770 * Build a wide negotiateion message in our message
3771 * buffer based on the input parameters.
3774 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3777 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3778 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN;
3779 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR;
3780 ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3781 ahd->msgout_len += 4;
3783 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
3784 ahd_name(ahd), devinfo->channel, devinfo->target,
3785 devinfo->lun, bus_width);
3790 * Build a parallel protocol request message in our message
3791 * buffer based on the input parameters.
3794 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3795 u_int period, u_int offset, u_int bus_width,
3799 * Always request precompensation from
3800 * the other target if we are running
3801 * at paced syncrates.
3803 if (period <= AHD_SYNCRATE_PACED)
3804 ppr_options |= MSG_EXT_PPR_PCOMP_EN;
3806 period = AHD_ASYNC_XFER_PERIOD;
3807 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3808 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN;
3809 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR;
3810 ahd->msgout_buf[ahd->msgout_index++] = period;
3811 ahd->msgout_buf[ahd->msgout_index++] = 0;
3812 ahd->msgout_buf[ahd->msgout_index++] = offset;
3813 ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3814 ahd->msgout_buf[ahd->msgout_index++] = ppr_options;
3815 ahd->msgout_len += 8;
3817 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
3818 "offset %x, ppr_options %x\n", ahd_name(ahd),
3819 devinfo->channel, devinfo->target, devinfo->lun,
3820 bus_width, period, offset, ppr_options);
3825 * Clear any active message state.
3828 ahd_clear_msg_state(struct ahd_softc *ahd)
3830 ahd_mode_state saved_modes;
3832 saved_modes = ahd_save_modes(ahd);
3833 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3834 ahd->send_msg_perror = 0;
3835 ahd->msg_flags = MSG_FLAG_NONE;
3836 ahd->msgout_len = 0;
3837 ahd->msgin_index = 0;
3838 ahd->msg_type = MSG_TYPE_NONE;
3839 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
3841 * The target didn't care to respond to our
3842 * message request, so clear ATN.
3844 ahd_outb(ahd, CLRSINT1, CLRATNO);
3846 ahd_outb(ahd, MSG_OUT, MSG_NOOP);
3847 ahd_outb(ahd, SEQ_FLAGS2,
3848 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
3849 ahd_restore_modes(ahd, saved_modes);
3853 * Manual message loop handler.
3856 ahd_handle_message_phase(struct ahd_softc *ahd)
3858 struct ahd_devinfo devinfo;
3862 ahd_fetch_devinfo(ahd, &devinfo);
3863 end_session = FALSE;
3864 bus_phase = ahd_inb(ahd, LASTPHASE);
3866 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) {
3867 printf("LQIRETRY for LQIPHASE_OUTPKT\n");
3868 ahd_outb(ahd, LQCTL2, LQIRETRY);
3871 switch (ahd->msg_type) {
3872 case MSG_TYPE_INITIATOR_MSGOUT:
3878 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0)
3879 panic("HOST_MSG_LOOP interrupt with no active message");
3882 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3883 ahd_print_devinfo(ahd, &devinfo);
3884 printf("INITIATOR_MSG_OUT");
3887 phasemis = bus_phase != P_MESGOUT;
3890 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3891 printf(" PHASEMIS %s\n",
3892 ahd_lookup_phase_entry(bus_phase)
3896 if (bus_phase == P_MESGIN) {
3898 * Change gears and see if
3899 * this messages is of interest to
3900 * us or should be passed back to
3903 ahd_outb(ahd, CLRSINT1, CLRATNO);
3904 ahd->send_msg_perror = 0;
3905 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN;
3906 ahd->msgin_index = 0;
3913 if (ahd->send_msg_perror) {
3914 ahd_outb(ahd, CLRSINT1, CLRATNO);
3915 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3917 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3918 printf(" byte 0x%x\n", ahd->send_msg_perror);
3921 * If we are notifying the target of a CRC error
3922 * during packetized operations, the target is
3923 * within its rights to acknowledge our message
3926 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0
3927 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR)
3928 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE;
3930 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror);
3931 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3935 msgdone = ahd->msgout_index == ahd->msgout_len;
3938 * The target has requested a retry.
3939 * Re-assert ATN, reset our message index to
3942 ahd->msgout_index = 0;
3943 ahd_assert_atn(ahd);
3946 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1);
3948 /* Last byte is signified by dropping ATN */
3949 ahd_outb(ahd, CLRSINT1, CLRATNO);
3953 * Clear our interrupt status and present
3954 * the next byte on the bus.
3956 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3958 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3959 printf(" byte 0x%x\n",
3960 ahd->msgout_buf[ahd->msgout_index]);
3962 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]);
3963 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3966 case MSG_TYPE_INITIATOR_MSGIN:
3972 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3973 ahd_print_devinfo(ahd, &devinfo);
3974 printf("INITIATOR_MSG_IN");
3977 phasemis = bus_phase != P_MESGIN;
3980 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3981 printf(" PHASEMIS %s\n",
3982 ahd_lookup_phase_entry(bus_phase)
3986 ahd->msgin_index = 0;
3987 if (bus_phase == P_MESGOUT
3988 && (ahd->send_msg_perror != 0
3989 || (ahd->msgout_len != 0
3990 && ahd->msgout_index == 0))) {
3991 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3998 /* Pull the byte in without acking it */
3999 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS);
4001 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4002 printf(" byte 0x%x\n",
4003 ahd->msgin_buf[ahd->msgin_index]);
4006 message_done = ahd_parse_msg(ahd, &devinfo);
4010 * Clear our incoming message buffer in case there
4011 * is another message following this one.
4013 ahd->msgin_index = 0;
4016 * If this message illicited a response,
4017 * assert ATN so the target takes us to the
4018 * message out phase.
4020 if (ahd->msgout_len != 0) {
4022 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
4023 ahd_print_devinfo(ahd, &devinfo);
4024 printf("Asserting ATN for response\n");
4027 ahd_assert_atn(ahd);
4032 if (message_done == MSGLOOP_TERMINATED) {
4036 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
4037 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ);
4041 case MSG_TYPE_TARGET_MSGIN:
4047 * By default, the message loop will continue.
4049 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
4051 if (ahd->msgout_len == 0)
4052 panic("Target MSGIN with no active message");
4055 * If we interrupted a mesgout session, the initiator
4056 * will not know this until our first REQ. So, we
4057 * only honor mesgout requests after we've sent our
4060 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0
4061 && ahd->msgout_index > 0)
4062 msgout_request = TRUE;
4064 msgout_request = FALSE;
4066 if (msgout_request) {
4069 * Change gears and see if
4070 * this messages is of interest to
4071 * us or should be passed back to
4074 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT;
4075 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO);
4076 ahd->msgin_index = 0;
4077 /* Dummy read to REQ for first byte */
4078 ahd_inb(ahd, SCSIDAT);
4079 ahd_outb(ahd, SXFRCTL0,
4080 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4084 msgdone = ahd->msgout_index == ahd->msgout_len;
4086 ahd_outb(ahd, SXFRCTL0,
4087 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4093 * Present the next byte on the bus.
4095 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4096 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]);
4099 case MSG_TYPE_TARGET_MSGOUT:
4105 * By default, the message loop will continue.
4107 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
4110 * The initiator signals that this is
4111 * the last byte by dropping ATN.
4113 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0;
4116 * Read the latched byte, but turn off SPIOEN first
4117 * so that we don't inadvertently cause a REQ for the
4120 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4121 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT);
4122 msgdone = ahd_parse_msg(ahd, &devinfo);
4123 if (msgdone == MSGLOOP_TERMINATED) {
4125 * The message is *really* done in that it caused
4126 * us to go to bus free. The sequencer has already
4127 * been reset at this point, so pull the ejection
4136 * XXX Read spec about initiator dropping ATN too soon
4137 * and use msgdone to detect it.
4139 if (msgdone == MSGLOOP_MSGCOMPLETE) {
4140 ahd->msgin_index = 0;
4143 * If this message illicited a response, transition
4144 * to the Message in phase and send it.
4146 if (ahd->msgout_len != 0) {
4147 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO);
4148 ahd_outb(ahd, SXFRCTL0,
4149 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4150 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
4151 ahd->msgin_index = 0;
4159 /* Ask for the next byte. */
4160 ahd_outb(ahd, SXFRCTL0,
4161 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4167 panic("Unknown REQINIT message type");
4171 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) {
4172 printf("%s: Returning to Idle Loop\n",
4174 ahd_clear_msg_state(ahd);
4177 * Perform the equivalent of a clear_target_state.
4179 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
4180 ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT);
4181 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
4183 ahd_clear_msg_state(ahd);
4184 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP);
4190 * See if we sent a particular extended message to the target.
4191 * If "full" is true, return true only if the target saw the full
4192 * message. If "full" is false, return true if the target saw at
4193 * least the first byte of the message.
4196 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full)
4204 while (index < ahd->msgout_len) {
4205 if (ahd->msgout_buf[index] == MSG_EXTENDED) {
4208 end_index = index + 1 + ahd->msgout_buf[index + 1];
4209 if (ahd->msgout_buf[index+2] == msgval
4210 && type == AHDMSG_EXT) {
4213 if (ahd->msgout_index > end_index)
4215 } else if (ahd->msgout_index > index)
4219 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK
4220 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
4222 /* Skip tag type and tag id or residue param*/
4225 /* Single byte message */
4226 if (type == AHDMSG_1B
4227 && ahd->msgout_index > index
4228 && (ahd->msgout_buf[index] == msgval
4229 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0
4230 && msgval == MSG_IDENTIFYFLAG)))
4242 * Wait for a complete incoming message, parse it, and respond accordingly.
4245 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4247 struct ahd_initiator_tinfo *tinfo;
4248 struct ahd_tmode_tstate *tstate;
4253 done = MSGLOOP_IN_PROG;
4256 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
4257 devinfo->target, &tstate);
4260 * Parse as much of the message as is available,
4261 * rejecting it if we don't support it. When
4262 * the entire message is available and has been
4263 * handled, return MSGLOOP_MSGCOMPLETE, indicating
4264 * that we have parsed an entire message.
4266 * In the case of extended messages, we accept the length
4267 * byte outright and perform more checking once we know the
4268 * extended message type.
4270 switch (ahd->msgin_buf[0]) {
4271 case MSG_DISCONNECT:
4272 case MSG_SAVEDATAPOINTER:
4273 case MSG_CMDCOMPLETE:
4274 case MSG_RESTOREPOINTERS:
4275 case MSG_IGN_WIDE_RESIDUE:
4277 * End our message loop as these are messages
4278 * the sequencer handles on its own.
4280 done = MSGLOOP_TERMINATED;
4282 case MSG_MESSAGE_REJECT:
4283 response = ahd_handle_msg_reject(ahd, devinfo);
4286 done = MSGLOOP_MSGCOMPLETE;
4290 /* Wait for enough of the message to begin validation */
4291 if (ahd->msgin_index < 2)
4293 switch (ahd->msgin_buf[2]) {
4301 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
4307 * Wait until we have both args before validating
4308 * and acting on this message.
4310 * Add one to MSG_EXT_SDTR_LEN to account for
4311 * the extended message preamble.
4313 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1))
4316 period = ahd->msgin_buf[3];
4318 saved_offset = offset = ahd->msgin_buf[4];
4319 ahd_devlimited_syncrate(ahd, tinfo, &period,
4320 &ppr_options, devinfo->role);
4321 ahd_validate_offset(ahd, tinfo, period, &offset,
4322 tinfo->curr.width, devinfo->role);
4324 printf("(%s:%c:%d:%d): Received "
4325 "SDTR period %x, offset %x\n\t"
4326 "Filtered to period %x, offset %x\n",
4327 ahd_name(ahd), devinfo->channel,
4328 devinfo->target, devinfo->lun,
4329 ahd->msgin_buf[3], saved_offset,
4332 ahd_set_syncrate(ahd, devinfo, period,
4333 offset, ppr_options,
4334 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4338 * See if we initiated Sync Negotiation
4339 * and didn't have to fall down to async
4342 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) {
4344 if (saved_offset != offset) {
4345 /* Went too low - force async */
4350 * Send our own SDTR in reply
4353 && devinfo->role == ROLE_INITIATOR) {
4354 printf("(%s:%c:%d:%d): Target "
4356 ahd_name(ahd), devinfo->channel,
4357 devinfo->target, devinfo->lun);
4359 ahd->msgout_index = 0;
4360 ahd->msgout_len = 0;
4361 ahd_construct_sdtr(ahd, devinfo,
4363 ahd->msgout_index = 0;
4366 done = MSGLOOP_MSGCOMPLETE;
4373 u_int sending_reply;
4375 sending_reply = FALSE;
4376 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
4382 * Wait until we have our arg before validating
4383 * and acting on this message.
4385 * Add one to MSG_EXT_WDTR_LEN to account for
4386 * the extended message preamble.
4388 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1))
4391 bus_width = ahd->msgin_buf[3];
4392 saved_width = bus_width;
4393 ahd_validate_width(ahd, tinfo, &bus_width,
4396 printf("(%s:%c:%d:%d): Received WDTR "
4397 "%x filtered to %x\n",
4398 ahd_name(ahd), devinfo->channel,
4399 devinfo->target, devinfo->lun,
4400 saved_width, bus_width);
4403 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) {
4405 * Don't send a WDTR back to the
4406 * target, since we asked first.
4407 * If the width went higher than our
4408 * request, reject it.
4410 if (saved_width > bus_width) {
4412 printf("(%s:%c:%d:%d): requested %dBit "
4413 "transfers. Rejecting...\n",
4414 ahd_name(ahd), devinfo->channel,
4415 devinfo->target, devinfo->lun,
4416 8 * (0x01 << bus_width));
4421 * Send our own WDTR in reply
4424 && devinfo->role == ROLE_INITIATOR) {
4425 printf("(%s:%c:%d:%d): Target "
4427 ahd_name(ahd), devinfo->channel,
4428 devinfo->target, devinfo->lun);
4430 ahd->msgout_index = 0;
4431 ahd->msgout_len = 0;
4432 ahd_construct_wdtr(ahd, devinfo, bus_width);
4433 ahd->msgout_index = 0;
4435 sending_reply = TRUE;
4438 * After a wide message, we are async, but
4439 * some devices don't seem to honor this portion
4440 * of the spec. Force a renegotiation of the
4441 * sync component of our transfer agreement even
4442 * if our goal is async. By updating our width
4443 * after forcing the negotiation, we avoid
4444 * renegotiating for width.
4446 ahd_update_neg_request(ahd, devinfo, tstate,
4447 tinfo, AHD_NEG_ALWAYS);
4448 ahd_set_width(ahd, devinfo, bus_width,
4449 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4451 if (sending_reply == FALSE && reject == FALSE) {
4454 * We will always have an SDTR to send.
4456 ahd->msgout_index = 0;
4457 ahd->msgout_len = 0;
4458 ahd_build_transfer_msg(ahd, devinfo);
4459 ahd->msgout_index = 0;
4462 done = MSGLOOP_MSGCOMPLETE;
4473 u_int saved_ppr_options;
4475 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) {
4481 * Wait until we have all args before validating
4482 * and acting on this message.
4484 * Add one to MSG_EXT_PPR_LEN to account for
4485 * the extended message preamble.
4487 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1))
4490 period = ahd->msgin_buf[3];
4491 offset = ahd->msgin_buf[5];
4492 bus_width = ahd->msgin_buf[6];
4493 saved_width = bus_width;
4494 ppr_options = ahd->msgin_buf[7];
4496 * According to the spec, a DT only
4497 * period factor with no DT option
4498 * set implies async.
4500 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
4503 saved_ppr_options = ppr_options;
4504 saved_offset = offset;
4507 * Transfer options are only available if we
4508 * are negotiating wide.
4511 ppr_options &= MSG_EXT_PPR_QAS_REQ;
4513 ahd_validate_width(ahd, tinfo, &bus_width,
4515 ahd_devlimited_syncrate(ahd, tinfo, &period,
4516 &ppr_options, devinfo->role);
4517 ahd_validate_offset(ahd, tinfo, period, &offset,
4518 bus_width, devinfo->role);
4520 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) {
4522 * If we are unable to do any of the
4523 * requested options (we went too low),
4524 * then we'll have to reject the message.
4526 if (saved_width > bus_width
4527 || saved_offset != offset
4528 || saved_ppr_options != ppr_options) {
4536 if (devinfo->role != ROLE_TARGET)
4537 printf("(%s:%c:%d:%d): Target "
4539 ahd_name(ahd), devinfo->channel,
4540 devinfo->target, devinfo->lun);
4542 printf("(%s:%c:%d:%d): Initiator "
4544 ahd_name(ahd), devinfo->channel,
4545 devinfo->target, devinfo->lun);
4546 ahd->msgout_index = 0;
4547 ahd->msgout_len = 0;
4548 ahd_construct_ppr(ahd, devinfo, period, offset,
4549 bus_width, ppr_options);
4550 ahd->msgout_index = 0;
4554 printf("(%s:%c:%d:%d): Received PPR width %x, "
4555 "period %x, offset %x,options %x\n"
4556 "\tFiltered to width %x, period %x, "
4557 "offset %x, options %x\n",
4558 ahd_name(ahd), devinfo->channel,
4559 devinfo->target, devinfo->lun,
4560 saved_width, ahd->msgin_buf[3],
4561 saved_offset, saved_ppr_options,
4562 bus_width, period, offset, ppr_options);
4564 ahd_set_width(ahd, devinfo, bus_width,
4565 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4567 ahd_set_syncrate(ahd, devinfo, period,
4568 offset, ppr_options,
4569 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4572 done = MSGLOOP_MSGCOMPLETE;
4576 /* Unknown extended message. Reject it. */
4582 #ifdef AHD_TARGET_MODE
4583 case MSG_BUS_DEV_RESET:
4584 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD,
4586 "Bus Device Reset Received",
4587 /*verbose_level*/0);
4589 done = MSGLOOP_TERMINATED;
4593 case MSG_CLEAR_QUEUE:
4597 /* Target mode messages */
4598 if (devinfo->role != ROLE_TARGET) {
4602 tag = SCB_LIST_NULL;
4603 if (ahd->msgin_buf[0] == MSG_ABORT_TAG)
4604 tag = ahd_inb(ahd, INITIATOR_TAG);
4605 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
4606 devinfo->lun, tag, ROLE_TARGET,
4609 tstate = ahd->enabled_targets[devinfo->our_scsiid];
4610 if (tstate != NULL) {
4611 struct ahd_tmode_lstate* lstate;
4613 lstate = tstate->enabled_luns[devinfo->lun];
4614 if (lstate != NULL) {
4615 ahd_queue_lstate_event(ahd, lstate,
4616 devinfo->our_scsiid,
4619 ahd_send_lstate_events(ahd, lstate);
4623 done = MSGLOOP_TERMINATED;
4627 case MSG_QAS_REQUEST:
4629 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4630 printf("%s: QAS request. SCSISIGI == 0x%x\n",
4631 ahd_name(ahd), ahd_inb(ahd, SCSISIGI));
4633 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE;
4635 case MSG_TERM_IO_PROC:
4643 * Setup to reject the message.
4645 ahd->msgout_index = 0;
4646 ahd->msgout_len = 1;
4647 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT;
4648 done = MSGLOOP_MSGCOMPLETE;
4652 if (done != MSGLOOP_IN_PROG && !response)
4653 /* Clear the outgoing message buffer */
4654 ahd->msgout_len = 0;
4660 * Process a message reject message.
4663 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4666 * What we care about here is if we had an
4667 * outstanding SDTR or WDTR message for this
4668 * target. If we did, this is a signal that
4669 * the target is refusing negotiation.
4672 struct ahd_initiator_tinfo *tinfo;
4673 struct ahd_tmode_tstate *tstate;
4678 scb_index = ahd_get_scbptr(ahd);
4679 scb = ahd_lookup_scb(ahd, scb_index);
4680 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel,
4681 devinfo->our_scsiid,
4682 devinfo->target, &tstate);
4683 /* Might be necessary */
4684 last_msg = ahd_inb(ahd, LAST_MSG);
4686 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
4687 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE)
4688 && tinfo->goal.period <= AHD_SYNCRATE_PACED) {
4690 * Target may not like our SPI-4 PPR Options.
4691 * Attempt to negotiate 80MHz which will turn
4692 * off these options.
4695 printf("(%s:%c:%d:%d): PPR Rejected. "
4696 "Trying simple U160 PPR\n",
4697 ahd_name(ahd), devinfo->channel,
4698 devinfo->target, devinfo->lun);
4700 tinfo->goal.period = AHD_SYNCRATE_DT;
4701 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ
4702 | MSG_EXT_PPR_QAS_REQ
4703 | MSG_EXT_PPR_DT_REQ;
4706 * Target does not support the PPR message.
4707 * Attempt to negotiate SPI-2 style.
4710 printf("(%s:%c:%d:%d): PPR Rejected. "
4711 "Trying WDTR/SDTR\n",
4712 ahd_name(ahd), devinfo->channel,
4713 devinfo->target, devinfo->lun);
4715 tinfo->goal.ppr_options = 0;
4716 tinfo->curr.transport_version = 2;
4717 tinfo->goal.transport_version = 2;
4719 ahd->msgout_index = 0;
4720 ahd->msgout_len = 0;
4721 ahd_build_transfer_msg(ahd, devinfo);
4722 ahd->msgout_index = 0;
4724 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
4726 /* note 8bit xfers */
4727 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
4728 "8bit transfers\n", ahd_name(ahd),
4729 devinfo->channel, devinfo->target, devinfo->lun);
4730 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4731 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4734 * No need to clear the sync rate. If the target
4735 * did not accept the command, our syncrate is
4736 * unaffected. If the target started the negotiation,
4737 * but rejected our response, we already cleared the
4738 * sync rate before sending our WDTR.
4740 if (tinfo->goal.offset != tinfo->curr.offset) {
4742 /* Start the sync negotiation */
4743 ahd->msgout_index = 0;
4744 ahd->msgout_len = 0;
4745 ahd_build_transfer_msg(ahd, devinfo);
4746 ahd->msgout_index = 0;
4749 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
4750 /* note asynch xfers and clear flag */
4751 ahd_set_syncrate(ahd, devinfo, /*period*/0,
4752 /*offset*/0, /*ppr_options*/0,
4753 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4755 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
4756 "Using asynchronous transfers\n",
4757 ahd_name(ahd), devinfo->channel,
4758 devinfo->target, devinfo->lun);
4759 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
4763 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
4765 if (tag_type == MSG_SIMPLE_TASK) {
4766 printf("(%s:%c:%d:%d): refuses tagged commands. "
4767 "Performing non-tagged I/O\n", ahd_name(ahd),
4768 devinfo->channel, devinfo->target, devinfo->lun);
4769 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE);
4772 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
4773 "Performing simple queue tagged I/O only\n",
4774 ahd_name(ahd), devinfo->channel, devinfo->target,
4775 devinfo->lun, tag_type == MSG_ORDERED_TASK
4776 ? "ordered" : "head of queue");
4777 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC);
4782 * Resend the identify for this CCB as the target
4783 * may believe that the selection is invalid otherwise.
4785 ahd_outb(ahd, SCB_CONTROL,
4786 ahd_inb_scbram(ahd, SCB_CONTROL) & mask);
4787 scb->hscb->control &= mask;
4788 ahd_set_transaction_tag(scb, /*enabled*/FALSE,
4789 /*type*/MSG_SIMPLE_TASK);
4790 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG);
4791 ahd_assert_atn(ahd);
4792 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
4796 * Requeue all tagged commands for this target
4797 * currently in our posession so they can be
4798 * converted to untagged commands.
4800 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
4801 SCB_GET_CHANNEL(ahd, scb),
4802 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
4803 ROLE_INITIATOR, CAM_REQUEUE_REQ,
4805 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) {
4807 * Most likely the device believes that we had
4808 * previously negotiated packetized.
4810 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
4811 | MSG_FLAG_IU_REQ_CHANGED;
4813 ahd_force_renegotiation(ahd, devinfo);
4814 ahd->msgout_index = 0;
4815 ahd->msgout_len = 0;
4816 ahd_build_transfer_msg(ahd, devinfo);
4817 ahd->msgout_index = 0;
4821 * Otherwise, we ignore it.
4823 printf("%s:%c:%d: Message reject for %x -- ignored\n",
4824 ahd_name(ahd), devinfo->channel, devinfo->target,
4831 * Process an ingnore wide residue message.
4834 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4839 scb_index = ahd_get_scbptr(ahd);
4840 scb = ahd_lookup_scb(ahd, scb_index);
4842 * XXX Actually check data direction in the sequencer?
4843 * Perhaps add datadir to some spare bits in the hscb?
4845 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0
4846 || ahd_get_transfer_dir(scb) != CAM_DIR_IN) {
4848 * Ignore the message if we haven't
4849 * seen an appropriate data phase yet.
4853 * If the residual occurred on the last
4854 * transfer and the transfer request was
4855 * expected to end on an odd count, do
4856 * nothing. Otherwise, subtract a byte
4857 * and update the residual count accordingly.
4861 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR);
4862 if ((sgptr & SG_LIST_NULL) != 0
4863 && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4864 & SCB_XFERLEN_ODD) != 0) {
4866 * If the residual occurred on the last
4867 * transfer and the transfer request was
4868 * expected to end on an odd count, do
4876 /* Pull in the rest of the sgptr */
4877 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
4878 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT);
4879 if ((sgptr & SG_LIST_NULL) != 0) {
4881 * The residual data count is not updated
4882 * for the command run to completion case.
4883 * Explicitly zero the count.
4885 data_cnt &= ~AHD_SG_LEN_MASK;
4887 data_addr = ahd_inq(ahd, SHADDR);
4890 sgptr &= SG_PTR_MASK;
4891 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
4892 struct ahd_dma64_seg *sg;
4894 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4897 * The residual sg ptr points to the next S/G
4898 * to load so we must go back one.
4901 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
4902 if (sg != scb->sg_list
4903 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4906 sglen = ahd_le32toh(sg->len);
4908 * Preserve High Address and SG_LIST
4909 * bits while setting the count to 1.
4911 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4912 data_addr = ahd_le64toh(sg->addr)
4913 + (sglen & AHD_SG_LEN_MASK)
4917 * Increment sg so it points to the
4921 sgptr = ahd_sg_virt_to_bus(ahd, scb,
4925 struct ahd_dma_seg *sg;
4927 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4930 * The residual sg ptr points to the next S/G
4931 * to load so we must go back one.
4934 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
4935 if (sg != scb->sg_list
4936 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4939 sglen = ahd_le32toh(sg->len);
4941 * Preserve High Address and SG_LIST
4942 * bits while setting the count to 1.
4944 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4945 data_addr = ahd_le32toh(sg->addr)
4946 + (sglen & AHD_SG_LEN_MASK)
4950 * Increment sg so it points to the
4954 sgptr = ahd_sg_virt_to_bus(ahd, scb,
4959 * Toggle the "oddness" of the transfer length
4960 * to handle this mid-transfer ignore wide
4961 * residue. This ensures that the oddness is
4962 * correct for subsequent data transfers.
4964 ahd_outb(ahd, SCB_TASK_ATTRIBUTE,
4965 ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4968 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
4969 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt);
4971 * The FIFO's pointers will be updated if/when the
4972 * sequencer re-enters a data phase.
4980 * Reinitialize the data pointers for the active transfer
4981 * based on its current residual.
4984 ahd_reinitialize_dataptrs(struct ahd_softc *ahd)
4987 ahd_mode_state saved_modes;
4994 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK,
4995 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK);
4997 scb_index = ahd_get_scbptr(ahd);
4998 scb = ahd_lookup_scb(ahd, scb_index);
5001 * Release and reacquire the FIFO so we
5002 * have a clean slate.
5004 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
5006 while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE))
5009 ahd_print_path(ahd, scb);
5010 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n");
5011 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
5013 saved_modes = ahd_save_modes(ahd);
5014 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5015 ahd_outb(ahd, DFFSTAT,
5016 ahd_inb(ahd, DFFSTAT)
5017 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0));
5020 * Determine initial values for data_addr and data_cnt
5021 * for resuming the data phase.
5023 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
5024 sgptr &= SG_PTR_MASK;
5026 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16)
5027 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8)
5028 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT);
5030 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
5031 struct ahd_dma64_seg *sg;
5033 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5035 /* The residual sg_ptr always points to the next sg */
5038 dataptr = ahd_le64toh(sg->addr)
5039 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK)
5041 ahd_outl(ahd, HADDR + 4, dataptr >> 32);
5043 struct ahd_dma_seg *sg;
5045 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5047 /* The residual sg_ptr always points to the next sg */
5050 dataptr = ahd_le32toh(sg->addr)
5051 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK)
5053 ahd_outb(ahd, HADDR + 4,
5054 (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24);
5056 ahd_outl(ahd, HADDR, dataptr);
5057 ahd_outb(ahd, HCNT + 2, resid >> 16);
5058 ahd_outb(ahd, HCNT + 1, resid >> 8);
5059 ahd_outb(ahd, HCNT, resid);
5063 * Handle the effects of issuing a bus device reset message.
5066 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5067 u_int lun, cam_status status, char *message,
5070 #ifdef AHD_TARGET_MODE
5071 struct ahd_tmode_tstate* tstate;
5075 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
5076 lun, SCB_LIST_NULL, devinfo->role,
5079 #ifdef AHD_TARGET_MODE
5081 * Send an immediate notify ccb to all target mord peripheral
5082 * drivers affected by this action.
5084 tstate = ahd->enabled_targets[devinfo->our_scsiid];
5085 if (tstate != NULL) {
5089 if (lun != CAM_LUN_WILDCARD) {
5091 max_lun = AHD_NUM_LUNS - 1;
5096 for (cur_lun <= max_lun; cur_lun++) {
5097 struct ahd_tmode_lstate* lstate;
5099 lstate = tstate->enabled_luns[cur_lun];
5103 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid,
5104 MSG_BUS_DEV_RESET, /*arg*/0);
5105 ahd_send_lstate_events(ahd, lstate);
5111 * Go back to async/narrow transfers and renegotiate.
5113 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
5114 AHD_TRANS_CUR, /*paused*/TRUE);
5115 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0,
5116 /*ppr_options*/0, AHD_TRANS_CUR,
5119 if (status != CAM_SEL_TIMEOUT)
5120 ahd_send_async(ahd, devinfo->channel, devinfo->target,
5121 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
5123 if (message != NULL && bootverbose)
5124 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd),
5125 message, devinfo->channel, devinfo->target, found);
5128 #ifdef AHD_TARGET_MODE
5130 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5135 * To facilitate adding multiple messages together,
5136 * each routine should increment the index and len
5137 * variables instead of setting them explicitly.
5139 ahd->msgout_index = 0;
5140 ahd->msgout_len = 0;
5142 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
5143 ahd_build_transfer_msg(ahd, devinfo);
5145 panic("ahd_intr: AWAITING target message with no message");
5147 ahd->msgout_index = 0;
5148 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
5151 /**************************** Initialization **********************************/
5153 ahd_sglist_size(struct ahd_softc *ahd)
5155 bus_size_t list_size;
5157 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG;
5158 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
5159 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG;
5164 * Calculate the optimum S/G List allocation size. S/G elements used
5165 * for a given transaction must be physically contiguous. Assume the
5166 * OS will allocate full pages to us, so it doesn't make sense to request
5170 ahd_sglist_allocsize(struct ahd_softc *ahd)
5172 bus_size_t sg_list_increment;
5173 bus_size_t sg_list_size;
5174 bus_size_t max_list_size;
5175 bus_size_t best_list_size;
5177 /* Start out with the minimum required for AHD_NSEG. */
5178 sg_list_increment = ahd_sglist_size(ahd);
5179 sg_list_size = sg_list_increment;
5181 /* Get us as close as possible to a page in size. */
5182 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE)
5183 sg_list_size += sg_list_increment;
5186 * Try to reduce the amount of wastage by allocating
5189 best_list_size = sg_list_size;
5190 max_list_size = roundup(sg_list_increment, PAGE_SIZE);
5191 if (max_list_size < 4 * PAGE_SIZE)
5192 max_list_size = 4 * PAGE_SIZE;
5193 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment))
5194 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment);
5195 while ((sg_list_size + sg_list_increment) <= max_list_size
5196 && (sg_list_size % PAGE_SIZE) != 0) {
5198 bus_size_t best_mod;
5200 sg_list_size += sg_list_increment;
5201 new_mod = sg_list_size % PAGE_SIZE;
5202 best_mod = best_list_size % PAGE_SIZE;
5203 if (new_mod > best_mod || new_mod == 0) {
5204 best_list_size = sg_list_size;
5207 return (best_list_size);
5211 * Allocate a controller structure for a new device
5212 * and perform initial initializion.
5215 ahd_alloc(void *platform_arg, char *name)
5217 struct ahd_softc *ahd;
5220 ahd = malloc(sizeof(*ahd), M_DEVBUF, M_NOWAIT);
5222 printf("aic7xxx: cannot malloc softc!\n");
5223 free(name, M_DEVBUF);
5227 ahd = device_get_softc((device_t)platform_arg);
5229 memset(ahd, 0, sizeof(*ahd));
5230 ahd->seep_config = malloc(sizeof(*ahd->seep_config),
5231 M_DEVBUF, M_NOWAIT);
5232 if (ahd->seep_config == NULL) {
5234 free(ahd, M_DEVBUF);
5236 free(name, M_DEVBUF);
5239 LIST_INIT(&ahd->pending_scbs);
5240 /* We don't know our unit number until the OSM sets it */
5243 ahd->description = NULL;
5244 ahd->bus_description = NULL;
5246 ahd->chip = AHD_NONE;
5247 ahd->features = AHD_FENONE;
5248 ahd->bugs = AHD_BUGNONE;
5249 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A
5250 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A;
5251 ahd_timer_init(&ahd->reset_timer);
5252 ahd_timer_init(&ahd->stat_timer);
5253 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT;
5254 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT;
5255 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT;
5256 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT;
5257 ahd->int_coalescing_stop_threshold =
5258 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT;
5260 if (ahd_platform_alloc(ahd, platform_arg) != 0) {
5265 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) {
5266 printf("%s: scb size = 0x%x, hscb size = 0x%x\n",
5267 ahd_name(ahd), (u_int)sizeof(struct scb),
5268 (u_int)sizeof(struct hardware_scb));
5275 ahd_softc_init(struct ahd_softc *ahd)
5284 ahd_set_unit(struct ahd_softc *ahd, int unit)
5290 ahd_set_name(struct ahd_softc *ahd, char *name)
5292 if (ahd->name != NULL)
5293 free(ahd->name, M_DEVBUF);
5298 ahd_free(struct ahd_softc *ahd)
5302 switch (ahd->init_level) {
5308 ahd_dmamap_unload(ahd, ahd->shared_data_dmat,
5309 ahd->shared_data_map.dmamap);
5312 ahd_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo,
5313 ahd->shared_data_map.dmamap);
5314 ahd_dmamap_destroy(ahd, ahd->shared_data_dmat,
5315 ahd->shared_data_map.dmamap);
5318 ahd_dma_tag_destroy(ahd, ahd->shared_data_dmat);
5321 ahd_dma_tag_destroy(ahd, ahd->buffer_dmat);
5329 ahd_dma_tag_destroy(ahd, ahd->parent_dmat);
5331 ahd_platform_free(ahd);
5332 ahd_fini_scbdata(ahd);
5333 for (i = 0; i < AHD_NUM_TARGETS; i++) {
5334 struct ahd_tmode_tstate *tstate;
5336 tstate = ahd->enabled_targets[i];
5337 if (tstate != NULL) {
5338 #ifdef AHD_TARGET_MODE
5341 for (j = 0; j < AHD_NUM_LUNS; j++) {
5342 struct ahd_tmode_lstate *lstate;
5344 lstate = tstate->enabled_luns[j];
5345 if (lstate != NULL) {
5346 xpt_free_path(lstate->path);
5347 free(lstate, M_DEVBUF);
5351 free(tstate, M_DEVBUF);
5354 #ifdef AHD_TARGET_MODE
5355 if (ahd->black_hole != NULL) {
5356 xpt_free_path(ahd->black_hole->path);
5357 free(ahd->black_hole, M_DEVBUF);
5360 if (ahd->name != NULL)
5361 free(ahd->name, M_DEVBUF);
5362 if (ahd->seep_config != NULL)
5363 free(ahd->seep_config, M_DEVBUF);
5364 if (ahd->saved_stack != NULL)
5365 free(ahd->saved_stack, M_DEVBUF);
5367 free(ahd, M_DEVBUF);
5373 ahd_shutdown(void *arg)
5375 struct ahd_softc *ahd;
5377 ahd = (struct ahd_softc *)arg;
5380 * Stop periodic timer callbacks.
5382 ahd_timer_stop(&ahd->reset_timer);
5383 ahd_timer_stop(&ahd->stat_timer);
5385 /* This will reset most registers to 0, but not all */
5386 ahd_reset(ahd, /*reinit*/FALSE);
5390 * Reset the controller and record some information about it
5391 * that is only available just after a reset. If "reinit" is
5392 * non-zero, this reset occured after initial configuration
5393 * and the caller requests that the chip be fully reinitialized
5394 * to a runable state. Chip interrupts are *not* enabled after
5395 * a reinitialization. The caller must enable interrupts via
5396 * ahd_intr_enable().
5399 ahd_reset(struct ahd_softc *ahd, int reinit)
5406 * Preserve the value of the SXFRCTL1 register for all channels.
5407 * It contains settings that affect termination and we don't want
5408 * to disturb the integrity of the bus.
5411 ahd_update_modes(ahd);
5412 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5413 sxfrctl1 = ahd_inb(ahd, SXFRCTL1);
5415 cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
5416 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5421 * During the assertion of CHIPRST, the chip
5422 * does not disable its parity logic prior to
5423 * the start of the reset. This may cause a
5424 * parity error to be detected and thus a
5425 * spurious SERR or PERR assertion. Disble
5426 * PERR and SERR responses during the CHIPRST.
5428 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN);
5429 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5430 mod_cmd, /*bytes*/2);
5432 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause);
5435 * Ensure that the reset has finished. We delay 1000us
5436 * prior to reading the register to make sure the chip
5437 * has sufficiently completed its reset to handle register
5443 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK));
5446 printf("%s: WARNING - Failed chip reset! "
5447 "Trying to initialize anyway.\n", ahd_name(ahd));
5449 ahd_outb(ahd, HCNTRL, ahd->pause);
5451 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5453 * Clear any latched PCI error status and restore
5454 * previous SERR and PERR response enables.
5456 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
5458 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5463 * Mode should be SCSI after a chip reset, but lets
5464 * set it just to be safe. We touch the MODE_PTR
5465 * register directly so as to bypass the lazy update
5466 * code in ahd_set_modes().
5468 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5469 ahd_outb(ahd, MODE_PTR,
5470 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI));
5475 * We must always initialize STPWEN to 1 before we
5476 * restore the saved values. STPWEN is initialized
5477 * to a tri-state condition which can only be cleared
5480 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
5481 ahd_outb(ahd, SXFRCTL1, sxfrctl1);
5483 /* Determine chip configuration */
5484 ahd->features &= ~AHD_WIDE;
5485 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0)
5486 ahd->features |= AHD_WIDE;
5489 * If a recovery action has forced a chip reset,
5490 * re-initialize the chip to our liking.
5499 * Determine the number of SCBs available on the controller
5502 ahd_probe_scbs(struct ahd_softc *ahd) {
5505 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
5506 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
5507 for (i = 0; i < AHD_SCB_MAX; i++) {
5510 ahd_set_scbptr(ahd, i);
5511 ahd_outw(ahd, SCB_BASE, i);
5512 for (j = 2; j < 64; j++)
5513 ahd_outb(ahd, SCB_BASE+j, 0);
5514 /* Start out life as unallocated (needing an abort) */
5515 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE);
5516 if (ahd_inw_scbram(ahd, SCB_BASE) != i)
5518 ahd_set_scbptr(ahd, 0);
5519 if (ahd_inw_scbram(ahd, SCB_BASE) != 0)
5526 ahd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
5530 baddr = (dma_addr_t *)arg;
5531 *baddr = segs->ds_addr;
5535 ahd_initialize_hscbs(struct ahd_softc *ahd)
5539 for (i = 0; i < ahd->scb_data.maxhscbs; i++) {
5540 ahd_set_scbptr(ahd, i);
5542 /* Clear the control byte. */
5543 ahd_outb(ahd, SCB_CONTROL, 0);
5545 /* Set the next pointer */
5546 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL);
5551 ahd_init_scbdata(struct ahd_softc *ahd)
5553 struct scb_data *scb_data;
5556 scb_data = &ahd->scb_data;
5557 TAILQ_INIT(&scb_data->free_scbs);
5558 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++)
5559 LIST_INIT(&scb_data->free_scb_lists[i]);
5560 LIST_INIT(&scb_data->any_dev_free_scb_list);
5561 SLIST_INIT(&scb_data->hscb_maps);
5562 SLIST_INIT(&scb_data->sg_maps);
5563 SLIST_INIT(&scb_data->sense_maps);
5565 /* Determine the number of hardware SCBs and initialize them */
5566 scb_data->maxhscbs = ahd_probe_scbs(ahd);
5567 if (scb_data->maxhscbs == 0) {
5568 printf("%s: No SCB space found\n", ahd_name(ahd));
5572 ahd_initialize_hscbs(ahd);
5575 * Create our DMA tags. These tags define the kinds of device
5576 * accessible memory allocations and memory mappings we will
5577 * need to perform during normal operation.
5579 * Unless we need to further restrict the allocation, we rely
5580 * on the restrictions of the parent dmat, hence the common
5581 * use of MAXADDR and MAXSIZE.
5584 /* DMA tag for our hardware scb structures */
5585 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5586 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5587 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5588 /*highaddr*/BUS_SPACE_MAXADDR,
5589 /*filter*/NULL, /*filterarg*/NULL,
5590 PAGE_SIZE, /*nsegments*/1,
5591 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5592 /*flags*/0, &scb_data->hscb_dmat) != 0) {
5596 scb_data->init_level++;
5598 /* DMA tag for our S/G structures. */
5599 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/8,
5600 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5601 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5602 /*highaddr*/BUS_SPACE_MAXADDR,
5603 /*filter*/NULL, /*filterarg*/NULL,
5604 ahd_sglist_allocsize(ahd), /*nsegments*/1,
5605 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5606 /*flags*/0, &scb_data->sg_dmat) != 0) {
5610 if ((ahd_debug & AHD_SHOW_MEMORY) != 0)
5611 printf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd),
5612 ahd_sglist_allocsize(ahd));
5615 scb_data->init_level++;
5617 /* DMA tag for our sense buffers. We allocate in page sized chunks */
5618 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5619 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5620 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5621 /*highaddr*/BUS_SPACE_MAXADDR,
5622 /*filter*/NULL, /*filterarg*/NULL,
5623 PAGE_SIZE, /*nsegments*/1,
5624 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5625 /*flags*/0, &scb_data->sense_dmat) != 0) {
5629 scb_data->init_level++;
5631 /* Perform initial CCB allocation */
5632 ahd_alloc_scbs(ahd);
5634 if (scb_data->numscbs == 0) {
5635 printf("%s: ahd_init_scbdata - "
5636 "Unable to allocate initial scbs\n",
5642 * Note that we were successfull
5652 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag)
5657 * Look on the pending list.
5659 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
5660 if (SCB_GET_TAG(scb) == tag)
5665 * Then on all of the collision free lists.
5667 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5668 struct scb *list_scb;
5672 if (SCB_GET_TAG(list_scb) == tag)
5674 list_scb = LIST_NEXT(list_scb, collision_links);
5679 * And finally on the generic free list.
5681 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
5682 if (SCB_GET_TAG(scb) == tag)
5690 ahd_fini_scbdata(struct ahd_softc *ahd)
5692 struct scb_data *scb_data;
5694 scb_data = &ahd->scb_data;
5695 if (scb_data == NULL)
5698 switch (scb_data->init_level) {
5702 struct map_node *sns_map;
5704 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) {
5705 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links);
5706 ahd_dmamap_unload(ahd, scb_data->sense_dmat,
5708 ahd_dmamem_free(ahd, scb_data->sense_dmat,
5709 sns_map->vaddr, sns_map->dmamap);
5710 free(sns_map, M_DEVBUF);
5712 ahd_dma_tag_destroy(ahd, scb_data->sense_dmat);
5717 struct map_node *sg_map;
5719 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) {
5720 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
5721 ahd_dmamap_unload(ahd, scb_data->sg_dmat,
5723 ahd_dmamem_free(ahd, scb_data->sg_dmat,
5724 sg_map->vaddr, sg_map->dmamap);
5725 free(sg_map, M_DEVBUF);
5727 ahd_dma_tag_destroy(ahd, scb_data->sg_dmat);
5732 struct map_node *hscb_map;
5734 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) {
5735 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links);
5736 ahd_dmamap_unload(ahd, scb_data->hscb_dmat,
5738 ahd_dmamem_free(ahd, scb_data->hscb_dmat,
5739 hscb_map->vaddr, hscb_map->dmamap);
5740 free(hscb_map, M_DEVBUF);
5742 ahd_dma_tag_destroy(ahd, scb_data->hscb_dmat);
5755 * DSP filter Bypass must be enabled until the first selection
5756 * after a change in bus mode (Razor #491 and #493).
5759 ahd_setup_iocell_workaround(struct ahd_softc *ahd)
5761 ahd_mode_state saved_modes;
5763 saved_modes = ahd_save_modes(ahd);
5764 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5765 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL)
5766 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS);
5767 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI));
5769 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5770 printf("%s: Setting up iocell workaround\n", ahd_name(ahd));
5772 ahd_restore_modes(ahd, saved_modes);
5773 ahd->flags &= ~AHD_HAD_FIRST_SEL;
5777 ahd_iocell_first_selection(struct ahd_softc *ahd)
5779 ahd_mode_state saved_modes;
5782 if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0)
5784 saved_modes = ahd_save_modes(ahd);
5785 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5786 sblkctl = ahd_inb(ahd, SBLKCTL);
5787 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5789 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5790 printf("%s: iocell first selection\n", ahd_name(ahd));
5792 if ((sblkctl & ENAB40) != 0) {
5793 ahd_outb(ahd, DSPDATACTL,
5794 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB);
5796 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5797 printf("%s: BYPASS now disabled\n", ahd_name(ahd));
5800 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI));
5801 ahd_outb(ahd, CLRINT, CLRSCSIINT);
5802 ahd_restore_modes(ahd, saved_modes);
5803 ahd->flags |= AHD_HAD_FIRST_SEL;
5806 /*************************** SCB Management ***********************************/
5808 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx)
5810 struct scb_list *free_list;
5811 struct scb_tailq *free_tailq;
5812 struct scb *first_scb;
5814 scb->flags |= SCB_ON_COL_LIST;
5815 AHD_SET_SCB_COL_IDX(scb, col_idx);
5816 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5817 free_tailq = &ahd->scb_data.free_scbs;
5818 first_scb = LIST_FIRST(free_list);
5819 if (first_scb != NULL) {
5820 LIST_INSERT_AFTER(first_scb, scb, collision_links);
5822 LIST_INSERT_HEAD(free_list, scb, collision_links);
5823 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe);
5828 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb)
5830 struct scb_list *free_list;
5831 struct scb_tailq *free_tailq;
5832 struct scb *first_scb;
5835 scb->flags &= ~SCB_ON_COL_LIST;
5836 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb);
5837 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5838 free_tailq = &ahd->scb_data.free_scbs;
5839 first_scb = LIST_FIRST(free_list);
5840 if (first_scb == scb) {
5841 struct scb *next_scb;
5844 * Maintain order in the collision free
5845 * lists for fairness if this device has
5846 * other colliding tags active.
5848 next_scb = LIST_NEXT(scb, collision_links);
5849 if (next_scb != NULL) {
5850 TAILQ_INSERT_AFTER(free_tailq, scb,
5851 next_scb, links.tqe);
5853 TAILQ_REMOVE(free_tailq, scb, links.tqe);
5855 LIST_REMOVE(scb, collision_links);
5859 * Get a free scb. If there are none, see if we can allocate a new SCB.
5862 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx)
5869 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5870 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) {
5871 ahd_rem_col_list(ahd, scb);
5875 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) {
5879 ahd_alloc_scbs(ahd);
5882 LIST_REMOVE(scb, links.le);
5883 if (col_idx != AHD_NEVER_COL_IDX
5884 && (scb->col_scb != NULL)
5885 && (scb->col_scb->flags & SCB_ACTIVE) == 0) {
5886 LIST_REMOVE(scb->col_scb, links.le);
5887 ahd_add_col_list(ahd, scb->col_scb, col_idx);
5890 scb->flags |= SCB_ACTIVE;
5895 * Return an SCB resource to the free list.
5898 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb)
5901 /* Clean up for the next user */
5902 scb->flags = SCB_FLAG_NONE;
5903 scb->hscb->control = 0;
5904 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL;
5906 if (scb->col_scb == NULL) {
5909 * No collision possible. Just free normally.
5911 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5913 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) {
5916 * The SCB we might have collided with is on
5917 * a free collision list. Put both SCBs on
5920 ahd_rem_col_list(ahd, scb->col_scb);
5921 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5923 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5924 scb->col_scb, links.le);
5925 } else if ((scb->col_scb->flags
5926 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE
5927 && (scb->col_scb->hscb->control & TAG_ENB) != 0) {
5930 * The SCB we might collide with on the next allocation
5931 * is still active in a non-packetized, tagged, context.
5932 * Put us on the SCB collision list.
5934 ahd_add_col_list(ahd, scb,
5935 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb));
5938 * The SCB we might collide with on the next allocation
5939 * is either active in a packetized context, or free.
5940 * Since we can't collide, put this SCB on the generic
5943 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5947 ahd_platform_scb_free(ahd, scb);
5951 ahd_alloc_scbs(struct ahd_softc *ahd)
5953 struct scb_data *scb_data;
5954 struct scb *next_scb;
5955 struct hardware_scb *hscb;
5956 struct map_node *hscb_map;
5957 struct map_node *sg_map;
5958 struct map_node *sense_map;
5960 uint8_t *sense_data;
5961 dma_addr_t hscb_busaddr;
5962 dma_addr_t sg_busaddr;
5963 dma_addr_t sense_busaddr;
5967 scb_data = &ahd->scb_data;
5968 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC)
5969 /* Can't allocate any more */
5972 if (scb_data->scbs_left != 0) {
5975 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left;
5976 hscb_map = SLIST_FIRST(&scb_data->hscb_maps);
5977 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset];
5978 hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb));
5980 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT);
5982 if (hscb_map == NULL)
5985 /* Allocate the next batch of hardware SCBs */
5986 if (ahd_dmamem_alloc(ahd, scb_data->hscb_dmat,
5987 (void **)&hscb_map->vaddr,
5988 BUS_DMA_NOWAIT, &hscb_map->dmamap) != 0) {
5989 free(hscb_map, M_DEVBUF);
5993 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links);
5995 ahd_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap,
5996 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
5997 &hscb_map->physaddr, /*flags*/0);
5999 hscb = (struct hardware_scb *)hscb_map->vaddr;
6000 hscb_busaddr = hscb_map->physaddr;
6001 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb);
6004 if (scb_data->sgs_left != 0) {
6007 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd))
6008 - scb_data->sgs_left) * ahd_sglist_size(ahd);
6009 sg_map = SLIST_FIRST(&scb_data->sg_maps);
6010 segs = sg_map->vaddr + offset;
6011 sg_busaddr = sg_map->physaddr + offset;
6013 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
6018 /* Allocate the next batch of S/G lists */
6019 if (ahd_dmamem_alloc(ahd, scb_data->sg_dmat,
6020 (void **)&sg_map->vaddr,
6021 BUS_DMA_NOWAIT, &sg_map->dmamap) != 0) {
6022 free(sg_map, M_DEVBUF);
6026 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
6028 ahd_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap,
6029 sg_map->vaddr, ahd_sglist_allocsize(ahd),
6030 ahd_dmamap_cb, &sg_map->physaddr, /*flags*/0);
6032 segs = sg_map->vaddr;
6033 sg_busaddr = sg_map->physaddr;
6034 scb_data->sgs_left =
6035 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd);
6037 if (ahd_debug & AHD_SHOW_MEMORY)
6038 printf("Mapped SG data\n");
6042 if (scb_data->sense_left != 0) {
6045 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left);
6046 sense_map = SLIST_FIRST(&scb_data->sense_maps);
6047 sense_data = sense_map->vaddr + offset;
6048 sense_busaddr = sense_map->physaddr + offset;
6050 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT);
6052 if (sense_map == NULL)
6055 /* Allocate the next batch of sense buffers */
6056 if (ahd_dmamem_alloc(ahd, scb_data->sense_dmat,
6057 (void **)&sense_map->vaddr,
6058 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) {
6059 free(sense_map, M_DEVBUF);
6063 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links);
6065 ahd_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap,
6066 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
6067 &sense_map->physaddr, /*flags*/0);
6069 sense_data = sense_map->vaddr;
6070 sense_busaddr = sense_map->physaddr;
6071 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE;
6073 if (ahd_debug & AHD_SHOW_MEMORY)
6074 printf("Mapped sense data\n");
6078 newcount = MIN(scb_data->sense_left, scb_data->scbs_left);
6079 newcount = MIN(newcount, scb_data->sgs_left);
6080 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs));
6081 for (i = 0; i < newcount; i++) {
6082 struct scb_platform_data *pdata;
6088 next_scb = (struct scb *)malloc(sizeof(*next_scb),
6089 M_DEVBUF, M_NOWAIT);
6090 if (next_scb == NULL)
6093 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
6094 M_DEVBUF, M_NOWAIT);
6095 if (pdata == NULL) {
6096 free(next_scb, M_DEVBUF);
6099 next_scb->platform_data = pdata;
6100 next_scb->hscb_map = hscb_map;
6101 next_scb->sg_map = sg_map;
6102 next_scb->sense_map = sense_map;
6103 next_scb->sg_list = segs;
6104 next_scb->sense_data = sense_data;
6105 next_scb->sense_busaddr = sense_busaddr;
6106 memset(hscb, 0, sizeof(*hscb));
6107 next_scb->hscb = hscb;
6108 hscb->hscb_busaddr = ahd_htole32(hscb_busaddr);
6111 * The sequencer always starts with the second entry.
6112 * The first entry is embedded in the scb.
6114 next_scb->sg_list_busaddr = sg_busaddr;
6115 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
6116 next_scb->sg_list_busaddr
6117 += sizeof(struct ahd_dma64_seg);
6119 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg);
6120 next_scb->ahd_softc = ahd;
6121 next_scb->flags = SCB_FLAG_NONE;
6123 error = ahd_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0,
6126 free(next_scb, M_DEVBUF);
6127 free(pdata, M_DEVBUF);
6131 next_scb->hscb->tag = ahd_htole16(scb_data->numscbs);
6132 col_tag = scb_data->numscbs ^ 0x100;
6133 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag);
6134 if (next_scb->col_scb != NULL)
6135 next_scb->col_scb->col_scb = next_scb;
6136 ahd_free_scb(ahd, next_scb);
6138 hscb_busaddr += sizeof(*hscb);
6139 segs += ahd_sglist_size(ahd);
6140 sg_busaddr += ahd_sglist_size(ahd);
6141 sense_data += AHD_SENSE_BUFSIZE;
6142 sense_busaddr += AHD_SENSE_BUFSIZE;
6143 scb_data->numscbs++;
6144 scb_data->sense_left--;
6145 scb_data->scbs_left--;
6146 scb_data->sgs_left--;
6151 ahd_controller_info(struct ahd_softc *ahd, char *buf)
6157 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]);
6160 speed = "Ultra320 ";
6161 if ((ahd->features & AHD_WIDE) != 0) {
6166 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ",
6167 speed, type, ahd->channel, ahd->our_id);
6170 sprintf(buf, "%s, %d SCBs", ahd->bus_description,
6171 ahd->scb_data.maxhscbs);
6174 static const char *channel_strings[] = {
6181 static const char *termstat_strings[] = {
6182 "Terminated Correctly",
6189 * Start the board, ready for normal operation
6192 ahd_init(struct ahd_softc *ahd)
6194 uint8_t *next_vaddr;
6195 dma_addr_t next_baddr;
6196 size_t driver_data_size;
6200 uint8_t current_sensing;
6203 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6205 ahd->stack_size = ahd_probe_stack_size(ahd);
6206 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t),
6207 M_DEVBUF, M_NOWAIT);
6208 if (ahd->saved_stack == NULL)
6212 * Verify that the compiler hasn't over-agressively
6213 * padded important structures.
6215 if (sizeof(struct hardware_scb) != 64)
6216 panic("Hardware SCB size is incorrect");
6219 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0)
6220 ahd->flags |= AHD_SEQUENCER_DEBUG;
6224 * Default to allowing initiator operations.
6226 ahd->flags |= AHD_INITIATORROLE;
6229 * Only allow target mode features if this unit has them enabled.
6231 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0)
6232 ahd->features &= ~AHD_TARGETMODE;
6235 /* DMA tag for mapping buffers into device visible space. */
6236 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6237 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6238 /*lowaddr*/ahd->flags & AHD_39BIT_ADDRESSING
6239 ? (dma_addr_t)0x7FFFFFFFFFULL
6240 : BUS_SPACE_MAXADDR_32BIT,
6241 /*highaddr*/BUS_SPACE_MAXADDR,
6242 /*filter*/NULL, /*filterarg*/NULL,
6243 /*maxsize*/(AHD_NSEG - 1) * PAGE_SIZE,
6244 /*nsegments*/AHD_NSEG,
6245 /*maxsegsz*/AHD_MAXTRANSFER_SIZE,
6246 /*flags*/BUS_DMA_ALLOCNOW,
6247 &ahd->buffer_dmat) != 0) {
6255 * DMA tag for our command fifos and other data in system memory
6256 * the card's sequencer must be able to access. For initiator
6257 * roles, we need to allocate space for the qoutfifo. When providing
6258 * for the target mode role, we must additionally provide space for
6259 * the incoming target command fifo.
6261 driver_data_size = AHD_SCB_MAX * sizeof(*ahd->qoutfifo)
6262 + sizeof(struct hardware_scb);
6263 if ((ahd->features & AHD_TARGETMODE) != 0)
6264 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6265 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0)
6266 driver_data_size += PKT_OVERRUN_BUFSIZE;
6267 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6268 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6269 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
6270 /*highaddr*/BUS_SPACE_MAXADDR,
6271 /*filter*/NULL, /*filterarg*/NULL,
6274 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
6275 /*flags*/0, &ahd->shared_data_dmat) != 0) {
6281 /* Allocation of driver data */
6282 if (ahd_dmamem_alloc(ahd, ahd->shared_data_dmat,
6283 (void **)&ahd->shared_data_map.vaddr,
6285 &ahd->shared_data_map.dmamap) != 0) {
6291 /* And permanently map it in */
6292 ahd_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
6293 ahd->shared_data_map.vaddr, driver_data_size,
6294 ahd_dmamap_cb, &ahd->shared_data_map.physaddr,
6296 ahd->qoutfifo = (struct ahd_completion *)ahd->shared_data_map.vaddr;
6297 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE];
6298 next_baddr = ahd->shared_data_map.physaddr
6299 + AHD_QOUT_SIZE*sizeof(struct ahd_completion);
6300 if ((ahd->features & AHD_TARGETMODE) != 0) {
6301 ahd->targetcmds = (struct target_cmd *)next_vaddr;
6302 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6303 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6306 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
6307 ahd->overrun_buf = next_vaddr;
6308 next_vaddr += PKT_OVERRUN_BUFSIZE;
6309 next_baddr += PKT_OVERRUN_BUFSIZE;
6313 * We need one SCB to serve as the "next SCB". Since the
6314 * tag identifier in this SCB will never be used, there is
6315 * no point in using a valid HSCB tag from an SCB pulled from
6316 * the standard free pool. So, we allocate this "sentinel"
6317 * specially from the DMA safe memory chunk used for the QOUTFIFO.
6319 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr;
6320 ahd->next_queued_hscb_map = &ahd->shared_data_map;
6321 ahd->next_queued_hscb->hscb_busaddr = ahd_htole32(next_baddr);
6325 /* Allocate SCB data now that buffer_dmat is initialized */
6326 if (ahd_init_scbdata(ahd) != 0)
6329 if ((ahd->flags & AHD_INITIATORROLE) == 0)
6330 ahd->flags &= ~AHD_RESET_BUS_A;
6333 * Before committing these settings to the chip, give
6334 * the OSM one last chance to modify our configuration.
6336 ahd_platform_init(ahd);
6338 /* Bring up the chip. */
6341 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6343 if ((ahd->flags & AHD_CURRENT_SENSING) == 0)
6347 * Verify termination based on current draw and
6348 * warn user if the bus is over/under terminated.
6350 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL,
6353 printf("%s: current sensing timeout 1\n", ahd_name(ahd));
6356 for (i = 20, fstat = FLX_FSTAT_BUSY;
6357 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) {
6358 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat);
6360 printf("%s: current sensing timeout 2\n",
6366 printf("%s: Timedout during current-sensing test\n",
6371 /* Latch Current Sensing status. */
6372 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing);
6374 printf("%s: current sensing timeout 3\n", ahd_name(ahd));
6378 /* Diable current sensing. */
6379 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
6382 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) {
6383 printf("%s: current_sensing == 0x%x\n",
6384 ahd_name(ahd), current_sensing);
6388 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) {
6391 term_stat = (current_sensing & FLX_CSTAT_MASK);
6392 switch (term_stat) {
6393 case FLX_CSTAT_OVER:
6394 case FLX_CSTAT_UNDER:
6396 case FLX_CSTAT_INVALID:
6397 case FLX_CSTAT_OKAY:
6398 if (warn_user == 0 && bootverbose == 0)
6400 printf("%s: %s Channel %s\n", ahd_name(ahd),
6401 channel_strings[i], termstat_strings[term_stat]);
6406 printf("%s: WARNING. Termination is not configured correctly.\n"
6407 "%s: WARNING. SCSI bus operations may FAIL.\n",
6408 ahd_name(ahd), ahd_name(ahd));
6412 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US,
6413 ahd_stat_timer, ahd);
6418 * (Re)initialize chip state after a chip reset.
6421 ahd_chip_init(struct ahd_softc *ahd)
6425 u_int scsiseq_template;
6430 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6432 * Take the LED out of diagnostic mode
6434 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON));
6437 * Return HS_MAILBOX to its default value.
6439 ahd->hs_mailbox = 0;
6440 ahd_outb(ahd, HS_MAILBOX, 0);
6442 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */
6443 ahd_outb(ahd, IOWNID, ahd->our_id);
6444 ahd_outb(ahd, TOWNID, ahd->our_id);
6445 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0;
6446 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0;
6447 if ((ahd->bugs & AHD_LONG_SETIMO_BUG)
6448 && (ahd->seltime != STIMESEL_MIN)) {
6450 * The selection timer duration is twice as long
6451 * as it should be. Halve it by adding "1" to
6452 * the user specified setting.
6454 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ;
6456 sxfrctl1 |= ahd->seltime;
6459 ahd_outb(ahd, SXFRCTL0, DFON);
6460 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN);
6461 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
6464 * Now that termination is set, wait for up
6465 * to 500ms for our transceivers to settle. If
6466 * the adapter does not have a cable attached,
6467 * the transceivers may never settle, so don't
6468 * complain if we fail here.
6471 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
6475 /* Clear any false bus resets due to the transceivers settling */
6476 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
6477 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6479 /* Initialize mode specific S/G state. */
6480 for (i = 0; i < 2; i++) {
6481 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
6482 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
6483 ahd_outb(ahd, SG_STATE, 0);
6484 ahd_outb(ahd, CLRSEQINTSRC, 0xFF);
6485 ahd_outb(ahd, SEQIMODE,
6486 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT
6487 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD);
6490 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
6491 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN);
6492 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75);
6493 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN);
6494 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR);
6495 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
6496 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE);
6498 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE);
6500 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS);
6501 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX)
6503 * Do not issue a target abort when a split completion
6504 * error occurs. Let our PCIX interrupt handler deal
6505 * with it instead. H2A4 Razor #625
6507 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS);
6509 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0)
6510 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER);
6513 * Tweak IOCELL settings.
6515 if ((ahd->flags & AHD_HP_BOARD) != 0) {
6516 for (i = 0; i < NUMDSPS; i++) {
6517 ahd_outb(ahd, DSPSELECT, i);
6518 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT);
6521 if ((ahd_debug & AHD_SHOW_MISC) != 0)
6522 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd),
6523 WRTBIASCTL_HP_DEFAULT);
6526 ahd_setup_iocell_workaround(ahd);
6529 * Enable LQI Manager interrupts.
6531 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT
6532 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI
6533 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ);
6534 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC);
6536 * We choose to have the sequencer catch LQOPHCHGINPKT errors
6537 * manually for the command phase at the start of a packetized
6538 * selection case. ENLQOBUSFREE should be made redundant by
6539 * the BUSFREE interrupt, but it seems that some LQOBUSFREE
6540 * events fail to assert the BUSFREE interrupt so we must
6541 * also enable LQOBUSFREE interrupts.
6543 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE);
6546 * Setup sequencer interrupt handlers.
6548 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr));
6549 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr));
6552 * Setup SCB Offset registers.
6554 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6555 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb,
6558 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun));
6560 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len));
6561 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute));
6562 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management));
6563 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb,
6564 shared_data.idata.cdb));
6565 ahd_outb(ahd, QNEXTPTR,
6566 offsetof(struct hardware_scb, next_hscb_busaddr));
6567 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET);
6568 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control));
6569 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6570 ahd_outb(ahd, LUNLEN,
6571 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1);
6573 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN);
6575 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1);
6576 ahd_outb(ahd, MAXCMD, 0xFF);
6577 ahd_outb(ahd, SCBAUTOPTR,
6578 AUSCBPTR_EN | offsetof(struct hardware_scb, tag));
6580 /* We haven't been enabled for target mode yet. */
6581 ahd_outb(ahd, MULTARGID, 0);
6582 ahd_outb(ahd, MULTARGID + 1, 0);
6584 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6585 /* Initialize the negotiation table. */
6586 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) {
6588 * Clear the spare bytes in the neg table to avoid
6589 * spurious parity errors.
6591 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6592 ahd_outb(ahd, NEGOADDR, target);
6593 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0);
6594 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++)
6595 ahd_outb(ahd, ANNEXDAT, 0);
6598 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6599 struct ahd_devinfo devinfo;
6600 struct ahd_initiator_tinfo *tinfo;
6601 struct ahd_tmode_tstate *tstate;
6603 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6605 ahd_compile_devinfo(&devinfo, ahd->our_id,
6606 target, CAM_LUN_WILDCARD,
6607 'A', ROLE_INITIATOR);
6608 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr);
6611 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR);
6612 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6614 #ifdef NEEDS_MORE_TESTING
6616 * Always enable abort on incoming L_Qs if this feature is
6617 * supported. We use this to catch invalid SCB references.
6619 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0)
6620 ahd_outb(ahd, LQCTL1, ABORTPENDING);
6623 ahd_outb(ahd, LQCTL1, 0);
6625 /* All of our queues are empty */
6626 ahd->qoutfifonext = 0;
6627 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID;
6628 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID);
6629 for (i = 0; i < AHD_QOUT_SIZE; i++)
6630 ahd->qoutfifo[i].valid_tag = 0;
6631 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD);
6633 ahd->qinfifonext = 0;
6634 for (i = 0; i < AHD_QIN_SIZE; i++)
6635 ahd->qinfifo[i] = SCB_LIST_NULL;
6637 if ((ahd->features & AHD_TARGETMODE) != 0) {
6638 /* All target command blocks start out invalid. */
6639 for (i = 0; i < AHD_TMODE_CMDS; i++)
6640 ahd->targetcmds[i].cmd_valid = 0;
6641 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD);
6642 ahd->tqinfifonext = 1;
6643 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1);
6644 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
6647 /* Initialize Scratch Ram. */
6648 ahd_outb(ahd, SEQ_FLAGS, 0);
6649 ahd_outb(ahd, SEQ_FLAGS2, 0);
6651 /* We don't have any waiting selections */
6652 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL);
6653 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL);
6654 ahd_outw(ahd, MK_MESSAGE_SCB, SCB_LIST_NULL);
6655 ahd_outw(ahd, MK_MESSAGE_SCSIID, 0xFF);
6656 for (i = 0; i < AHD_NUM_TARGETS; i++)
6657 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL);
6660 * Nobody is waiting to be DMAed into the QOUTFIFO.
6662 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
6663 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL);
6664 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
6665 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
6666 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
6669 * The Freeze Count is 0.
6671 ahd->qfreeze_cnt = 0;
6672 ahd_outw(ahd, QFREEZE_COUNT, 0);
6673 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, 0);
6676 * Tell the sequencer where it can find our arrays in memory.
6678 busaddr = ahd->shared_data_map.physaddr;
6679 ahd_outl(ahd, SHARED_DATA_ADDR, busaddr);
6680 ahd_outl(ahd, QOUTFIFO_NEXT_ADDR, busaddr);
6683 * Setup the allowed SCSI Sequences based on operational mode.
6684 * If we are a target, we'll enable select in operations once
6685 * we've had a lun enabled.
6687 scsiseq_template = ENAUTOATNP;
6688 if ((ahd->flags & AHD_INITIATORROLE) != 0)
6689 scsiseq_template |= ENRSELI;
6690 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template);
6692 /* There are no busy SCBs yet. */
6693 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6696 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++)
6697 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun));
6701 * Initialize the group code to command length table.
6702 * Vendor Unique codes are set to 0 so we only capture
6703 * the first byte of the cdb. These can be overridden
6704 * when target mode is enabled.
6706 ahd_outb(ahd, CMDSIZE_TABLE, 5);
6707 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9);
6708 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9);
6709 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0);
6710 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15);
6711 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11);
6712 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0);
6713 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0);
6715 /* Tell the sequencer of our initial queue positions */
6716 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
6717 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512);
6718 ahd->qinfifonext = 0;
6719 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
6720 ahd_set_hescb_qoff(ahd, 0);
6721 ahd_set_snscb_qoff(ahd, 0);
6722 ahd_set_sescb_qoff(ahd, 0);
6723 ahd_set_sdscb_qoff(ahd, 0);
6726 * Tell the sequencer which SCB will be the next one it receives.
6728 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr);
6729 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
6732 * Default to coalescing disabled.
6734 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0);
6735 ahd_outw(ahd, CMDS_PENDING, 0);
6736 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer,
6737 ahd->int_coalescing_maxcmds,
6738 ahd->int_coalescing_mincmds);
6739 ahd_enable_coalescing(ahd, FALSE);
6742 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6746 * Setup default device and controller settings.
6747 * This should only be called if our probe has
6748 * determined that no configuration data is available.
6751 ahd_default_config(struct ahd_softc *ahd)
6758 * Allocate a tstate to house information for our
6759 * initiator presence on the bus as well as the user
6760 * data for any target mode initiator.
6762 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6763 printf("%s: unable to allocate ahd_tmode_tstate. "
6764 "Failing attach\n", ahd_name(ahd));
6768 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) {
6769 struct ahd_devinfo devinfo;
6770 struct ahd_initiator_tinfo *tinfo;
6771 struct ahd_tmode_tstate *tstate;
6772 uint16_t target_mask;
6774 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6777 * We support SPC2 and SPI4.
6779 tinfo->user.protocol_version = 4;
6780 tinfo->user.transport_version = 4;
6782 target_mask = 0x01 << targ;
6783 ahd->user_discenable |= target_mask;
6784 tstate->discenable |= target_mask;
6785 ahd->user_tagenable |= target_mask;
6786 #ifdef AHD_FORCE_160
6787 tinfo->user.period = AHD_SYNCRATE_DT;
6789 tinfo->user.period = AHD_SYNCRATE_160;
6791 tinfo->user.offset = MAX_OFFSET;
6792 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM
6793 | MSG_EXT_PPR_WR_FLOW
6794 | MSG_EXT_PPR_HOLD_MCS
6795 | MSG_EXT_PPR_IU_REQ
6796 | MSG_EXT_PPR_QAS_REQ
6797 | MSG_EXT_PPR_DT_REQ;
6798 if ((ahd->features & AHD_RTI) != 0)
6799 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI;
6801 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
6804 * Start out Async/Narrow/Untagged and with
6805 * conservative protocol support.
6807 tinfo->goal.protocol_version = 2;
6808 tinfo->goal.transport_version = 2;
6809 tinfo->curr.protocol_version = 2;
6810 tinfo->curr.transport_version = 2;
6811 ahd_compile_devinfo(&devinfo, ahd->our_id,
6812 targ, CAM_LUN_WILDCARD,
6813 'A', ROLE_INITIATOR);
6814 tstate->tagenable &= ~target_mask;
6815 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6816 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6817 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6818 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
6825 * Parse device configuration information.
6828 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc)
6833 max_targ = sc->max_targets & CFMAXTARG;
6834 ahd->our_id = sc->brtime_id & CFSCSIID;
6837 * Allocate a tstate to house information for our
6838 * initiator presence on the bus as well as the user
6839 * data for any target mode initiator.
6841 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6842 printf("%s: unable to allocate ahd_tmode_tstate. "
6843 "Failing attach\n", ahd_name(ahd));
6847 for (targ = 0; targ < max_targ; targ++) {
6848 struct ahd_devinfo devinfo;
6849 struct ahd_initiator_tinfo *tinfo;
6850 struct ahd_transinfo *user_tinfo;
6851 struct ahd_tmode_tstate *tstate;
6852 uint16_t target_mask;
6854 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6856 user_tinfo = &tinfo->user;
6859 * We support SPC2 and SPI4.
6861 tinfo->user.protocol_version = 4;
6862 tinfo->user.transport_version = 4;
6864 target_mask = 0x01 << targ;
6865 ahd->user_discenable &= ~target_mask;
6866 tstate->discenable &= ~target_mask;
6867 ahd->user_tagenable &= ~target_mask;
6868 if (sc->device_flags[targ] & CFDISC) {
6869 tstate->discenable |= target_mask;
6870 ahd->user_discenable |= target_mask;
6871 ahd->user_tagenable |= target_mask;
6874 * Cannot be packetized without disconnection.
6876 sc->device_flags[targ] &= ~CFPACKETIZED;
6879 user_tinfo->ppr_options = 0;
6880 user_tinfo->period = (sc->device_flags[targ] & CFXFER);
6881 if (user_tinfo->period < CFXFER_ASYNC) {
6882 if (user_tinfo->period <= AHD_PERIOD_10MHz)
6883 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ;
6884 user_tinfo->offset = MAX_OFFSET;
6886 user_tinfo->offset = 0;
6887 user_tinfo->period = AHD_ASYNC_XFER_PERIOD;
6889 #ifdef AHD_FORCE_160
6890 if (user_tinfo->period <= AHD_SYNCRATE_160)
6891 user_tinfo->period = AHD_SYNCRATE_DT;
6894 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) {
6895 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM
6896 | MSG_EXT_PPR_WR_FLOW
6897 | MSG_EXT_PPR_HOLD_MCS
6898 | MSG_EXT_PPR_IU_REQ;
6899 if ((ahd->features & AHD_RTI) != 0)
6900 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI;
6903 if ((sc->device_flags[targ] & CFQAS) != 0)
6904 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ;
6906 if ((sc->device_flags[targ] & CFWIDEB) != 0)
6907 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT;
6909 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT;
6911 if ((ahd_debug & AHD_SHOW_MISC) != 0)
6912 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width,
6913 user_tinfo->period, user_tinfo->offset,
6914 user_tinfo->ppr_options);
6917 * Start out Async/Narrow/Untagged and with
6918 * conservative protocol support.
6920 tstate->tagenable &= ~target_mask;
6921 tinfo->goal.protocol_version = 2;
6922 tinfo->goal.transport_version = 2;
6923 tinfo->curr.protocol_version = 2;
6924 tinfo->curr.transport_version = 2;
6925 ahd_compile_devinfo(&devinfo, ahd->our_id,
6926 targ, CAM_LUN_WILDCARD,
6927 'A', ROLE_INITIATOR);
6928 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6929 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6930 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6931 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
6935 ahd->flags &= ~AHD_SPCHK_ENB_A;
6936 if (sc->bios_control & CFSPARITY)
6937 ahd->flags |= AHD_SPCHK_ENB_A;
6939 ahd->flags &= ~AHD_RESET_BUS_A;
6940 if (sc->bios_control & CFRESETB)
6941 ahd->flags |= AHD_RESET_BUS_A;
6943 ahd->flags &= ~AHD_EXTENDED_TRANS_A;
6944 if (sc->bios_control & CFEXTEND)
6945 ahd->flags |= AHD_EXTENDED_TRANS_A;
6947 ahd->flags &= ~AHD_BIOS_ENABLED;
6948 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED)
6949 ahd->flags |= AHD_BIOS_ENABLED;
6951 ahd->flags &= ~AHD_STPWLEVEL_A;
6952 if ((sc->adapter_control & CFSTPWLEVEL) != 0)
6953 ahd->flags |= AHD_STPWLEVEL_A;
6959 * Parse device configuration information.
6962 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd)
6966 error = ahd_verify_vpd_cksum(vpd);
6969 if ((vpd->bios_flags & VPDBOOTHOST) != 0)
6970 ahd->flags |= AHD_BOOT_CHANNEL;
6975 ahd_intr_enable(struct ahd_softc *ahd, int enable)
6979 hcntrl = ahd_inb(ahd, HCNTRL);
6981 ahd->pause &= ~INTEN;
6982 ahd->unpause &= ~INTEN;
6985 ahd->pause |= INTEN;
6986 ahd->unpause |= INTEN;
6988 ahd_outb(ahd, HCNTRL, hcntrl);
6992 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds,
6995 if (timer > AHD_TIMER_MAX_US)
6996 timer = AHD_TIMER_MAX_US;
6997 ahd->int_coalescing_timer = timer;
6999 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX)
7000 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX;
7001 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX)
7002 mincmds = AHD_INT_COALESCING_MINCMDS_MAX;
7003 ahd->int_coalescing_maxcmds = maxcmds;
7004 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK);
7005 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds);
7006 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds);
7010 ahd_enable_coalescing(struct ahd_softc *ahd, int enable)
7013 ahd->hs_mailbox &= ~ENINT_COALESCE;
7015 ahd->hs_mailbox |= ENINT_COALESCE;
7016 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox);
7017 ahd_flush_device_writes(ahd);
7018 ahd_run_qoutfifo(ahd);
7022 * Ensure that the card is paused in a location
7023 * outside of all critical sections and that all
7024 * pending work is completed prior to returning.
7025 * This routine should only be called from outside
7026 * an interrupt context.
7029 ahd_pause_and_flushwork(struct ahd_softc *ahd)
7035 ahd->flags |= AHD_ALL_INTERRUPTS;
7038 * Freeze the outgoing selections. We do this only
7039 * until we are safely paused without further selections
7043 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7044 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN);
7049 * Give the sequencer some time to service
7050 * any active selections.
7056 intstat = ahd_inb(ahd, INTSTAT);
7057 if ((intstat & INT_PEND) == 0) {
7058 ahd_clear_critical_section(ahd);
7059 intstat = ahd_inb(ahd, INTSTAT);
7062 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0)
7063 && ((intstat & INT_PEND) != 0
7064 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
7065 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0));
7067 if (maxloops == 0) {
7068 printf("Infinite interrupt loop, INTSTAT = %x",
7069 ahd_inb(ahd, INTSTAT));
7072 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7074 ahd_flush_qoutfifo(ahd);
7076 ahd_platform_flushwork(ahd);
7077 ahd->flags &= ~AHD_ALL_INTERRUPTS;
7081 ahd_suspend(struct ahd_softc *ahd)
7084 ahd_pause_and_flushwork(ahd);
7086 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
7095 ahd_resume(struct ahd_softc *ahd)
7098 ahd_reset(ahd, /*reinit*/TRUE);
7099 ahd_intr_enable(ahd, TRUE);
7104 /************************** Busy Target Table *********************************/
7106 * Set SCBPTR to the SCB that contains the busy
7107 * table entry for TCL. Return the offset into
7108 * the SCB that contains the entry for TCL.
7109 * saved_scbid is dereferenced and set to the
7110 * scbid that should be restored once manipualtion
7111 * of the TCL entry is complete.
7113 static __inline u_int
7114 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl)
7117 * Index to the SCB that contains the busy entry.
7119 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7120 *saved_scbid = ahd_get_scbptr(ahd);
7121 ahd_set_scbptr(ahd, TCL_LUN(tcl)
7122 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4));
7125 * And now calculate the SCB offset to the entry.
7126 * Each entry is 2 bytes wide, hence the
7127 * multiplication by 2.
7129 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS);
7133 * Return the untagged transaction id for a given target/channel lun.
7136 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl)
7142 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7143 scbid = ahd_inw_scbram(ahd, scb_offset);
7144 ahd_set_scbptr(ahd, saved_scbptr);
7149 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid)
7154 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7155 ahd_outw(ahd, scb_offset, scbid);
7156 ahd_set_scbptr(ahd, saved_scbptr);
7159 /************************** SCB and SCB queue management **********************/
7161 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target,
7162 char channel, int lun, u_int tag, role_t role)
7164 int targ = SCB_GET_TARGET(ahd, scb);
7165 char chan = SCB_GET_CHANNEL(ahd, scb);
7166 int slun = SCB_GET_LUN(scb);
7169 match = ((chan == channel) || (channel == ALL_CHANNELS));
7171 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
7173 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
7175 #ifdef AHD_TARGET_MODE
7178 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
7179 if (role == ROLE_INITIATOR) {
7180 match = (group != XPT_FC_GROUP_TMODE)
7181 && ((tag == SCB_GET_TAG(scb))
7182 || (tag == SCB_LIST_NULL));
7183 } else if (role == ROLE_TARGET) {
7184 match = (group == XPT_FC_GROUP_TMODE)
7185 && ((tag == scb->io_ctx->csio.tag_id)
7186 || (tag == SCB_LIST_NULL));
7188 #else /* !AHD_TARGET_MODE */
7189 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL));
7190 #endif /* AHD_TARGET_MODE */
7197 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb)
7203 target = SCB_GET_TARGET(ahd, scb);
7204 lun = SCB_GET_LUN(scb);
7205 channel = SCB_GET_CHANNEL(ahd, scb);
7207 ahd_search_qinfifo(ahd, target, channel, lun,
7208 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
7209 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7211 ahd_platform_freeze_devq(ahd, scb);
7215 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb)
7217 struct scb *prev_scb;
7218 ahd_mode_state saved_modes;
7220 saved_modes = ahd_save_modes(ahd);
7221 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7223 if (ahd_qinfifo_count(ahd) != 0) {
7227 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1);
7228 prev_tag = ahd->qinfifo[prev_pos];
7229 prev_scb = ahd_lookup_scb(ahd, prev_tag);
7231 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7232 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7233 ahd_restore_modes(ahd, saved_modes);
7237 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb,
7240 if (prev_scb == NULL) {
7243 busaddr = ahd_le32toh(scb->hscb->hscb_busaddr);
7244 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
7246 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
7247 ahd_sync_scb(ahd, prev_scb,
7248 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7250 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
7252 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr;
7253 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7257 ahd_qinfifo_count(struct ahd_softc *ahd)
7261 u_int wrap_qinfifonext;
7263 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7264 qinpos = ahd_get_snscb_qoff(ahd);
7265 wrap_qinpos = AHD_QIN_WRAP(qinpos);
7266 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext);
7267 if (wrap_qinfifonext >= wrap_qinpos)
7268 return (wrap_qinfifonext - wrap_qinpos);
7270 return (wrap_qinfifonext
7271 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos);
7275 ahd_reset_cmds_pending(struct ahd_softc *ahd)
7278 ahd_mode_state saved_modes;
7281 saved_modes = ahd_save_modes(ahd);
7282 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7285 * Don't count any commands as outstanding that the
7286 * sequencer has already marked for completion.
7288 ahd_flush_qoutfifo(ahd);
7291 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
7294 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd));
7295 ahd_restore_modes(ahd, saved_modes);
7296 ahd->flags &= ~AHD_UPDATE_PEND_CMDS;
7300 ahd_done_with_status(struct ahd_softc *ahd, struct scb *scb, uint32_t status)
7305 ostat = ahd_get_transaction_status(scb);
7306 if (ostat == CAM_REQ_INPROG)
7307 ahd_set_transaction_status(scb, status);
7308 cstat = ahd_get_transaction_status(scb);
7309 if (cstat != CAM_REQ_CMP)
7310 ahd_freeze_scb(scb);
7315 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel,
7316 int lun, u_int tag, role_t role, uint32_t status,
7317 ahd_search_action action)
7320 struct scb *mk_msg_scb;
7321 struct scb *prev_scb;
7322 ahd_mode_state saved_modes;
7335 /* Must be in CCHAN mode */
7336 saved_modes = ahd_save_modes(ahd);
7337 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7340 * Halt any pending SCB DMA. The sequencer will reinitiate
7341 * this dma if the qinfifo is not empty once we unpause.
7343 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR))
7344 == (CCARREN|CCSCBEN|CCSCBDIR)) {
7345 ahd_outb(ahd, CCSCBCTL,
7346 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN));
7347 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0)
7350 /* Determine sequencer's position in the qinfifo. */
7351 qintail = AHD_QIN_WRAP(ahd->qinfifonext);
7352 qinstart = ahd_get_snscb_qoff(ahd);
7353 qinpos = AHD_QIN_WRAP(qinstart);
7357 if (action == SEARCH_PRINT) {
7358 printf("qinstart = %d qinfifonext = %d\nQINFIFO:",
7359 qinstart, ahd->qinfifonext);
7363 * Start with an empty queue. Entries that are not chosen
7364 * for removal will be re-added to the queue as we go.
7366 ahd->qinfifonext = qinstart;
7367 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr);
7368 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
7370 while (qinpos != qintail) {
7371 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]);
7373 printf("qinpos = %d, SCB index = %d\n",
7374 qinpos, ahd->qinfifo[qinpos]);
7378 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) {
7380 * We found an scb that needs to be acted on.
7384 case SEARCH_COMPLETE:
7385 if ((scb->flags & SCB_ACTIVE) == 0)
7386 printf("Inactive SCB in qinfifo\n");
7387 ahd_done_with_status(ahd, scb, status);
7392 printf(" 0x%x", ahd->qinfifo[qinpos]);
7395 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7400 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7403 qinpos = AHD_QIN_WRAP(qinpos+1);
7406 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7408 if (action == SEARCH_PRINT)
7409 printf("\nWAITING_TID_QUEUES:\n");
7412 * Search waiting for selection lists. We traverse the
7413 * list of "their ids" waiting for selection and, if
7414 * appropriate, traverse the SCBs of each "their id"
7415 * looking for matches.
7417 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7418 seq_flags2 = ahd_inb(ahd, SEQ_FLAGS2);
7419 if ((seq_flags2 & PENDING_MK_MESSAGE) != 0) {
7420 scbid = ahd_inw(ahd, MK_MESSAGE_SCB);
7421 mk_msg_scb = ahd_lookup_scb(ahd, scbid);
7424 savedscbptr = ahd_get_scbptr(ahd);
7425 tid_next = ahd_inw(ahd, WAITING_TID_HEAD);
7426 tid_prev = SCB_LIST_NULL;
7428 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) {
7433 if (targets > AHD_NUM_TARGETS)
7434 panic("TID LIST LOOP");
7436 if (scbid >= ahd->scb_data.numscbs) {
7437 printf("%s: Waiting TID List inconsistency. "
7438 "SCB index == 0x%x, yet numscbs == 0x%x.",
7439 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7440 ahd_dump_card_state(ahd);
7441 panic("for safety");
7443 scb = ahd_lookup_scb(ahd, scbid);
7445 printf("%s: SCB = 0x%x Not Active!\n",
7446 ahd_name(ahd), scbid);
7447 panic("Waiting TID List traversal\n");
7449 ahd_set_scbptr(ahd, scbid);
7450 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2);
7451 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7452 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) {
7458 * We found a list of scbs that needs to be searched.
7460 if (action == SEARCH_PRINT)
7461 printf(" %d ( ", SCB_GET_TARGET(ahd, scb));
7463 found += ahd_search_scb_list(ahd, target, channel,
7464 lun, tag, role, status,
7465 action, &tid_head, &tid_tail,
7466 SCB_GET_TARGET(ahd, scb));
7468 * Check any MK_MESSAGE SCB that is still waiting to
7469 * enter this target's waiting for selection queue.
7471 if (mk_msg_scb != NULL
7472 && ahd_match_scb(ahd, mk_msg_scb, target, channel,
7476 * We found an scb that needs to be acted on.
7480 case SEARCH_COMPLETE:
7481 if ((mk_msg_scb->flags & SCB_ACTIVE) == 0)
7482 printf("Inactive SCB pending MK_MSG\n");
7483 ahd_done_with_status(ahd, mk_msg_scb, status);
7489 printf("Removing MK_MSG scb\n");
7492 * Reset our tail to the tail of the
7493 * main per-target list.
7495 tail_offset = WAITING_SCB_TAILS
7496 + (2 * SCB_GET_TARGET(ahd, mk_msg_scb));
7497 ahd_outw(ahd, tail_offset, tid_tail);
7499 seq_flags2 &= ~PENDING_MK_MESSAGE;
7500 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7501 ahd_outw(ahd, CMDS_PENDING,
7502 ahd_inw(ahd, CMDS_PENDING)-1);
7507 printf(" 0x%x", SCB_GET_TAG(scb));
7514 if (mk_msg_scb != NULL
7515 && SCBID_IS_NULL(tid_head)
7516 && ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7517 SCB_LIST_NULL, ROLE_UNKNOWN)) {
7520 * When removing the last SCB for a target
7521 * queue with a pending MK_MESSAGE scb, we
7522 * must queue the MK_MESSAGE scb.
7524 printf("Queueing mk_msg_scb\n");
7525 tid_head = ahd_inw(ahd, MK_MESSAGE_SCB);
7526 seq_flags2 &= ~PENDING_MK_MESSAGE;
7527 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7530 if (tid_head != scbid)
7531 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next);
7532 if (!SCBID_IS_NULL(tid_head))
7533 tid_prev = tid_head;
7534 if (action == SEARCH_PRINT)
7538 /* Restore saved state. */
7539 ahd_set_scbptr(ahd, savedscbptr);
7540 ahd_restore_modes(ahd, saved_modes);
7545 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel,
7546 int lun, u_int tag, role_t role, uint32_t status,
7547 ahd_search_action action, u_int *list_head,
7548 u_int *list_tail, u_int tid)
7556 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7558 prev = SCB_LIST_NULL;
7560 *list_tail = SCB_LIST_NULL;
7561 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) {
7562 if (scbid >= ahd->scb_data.numscbs) {
7563 printf("%s:SCB List inconsistency. "
7564 "SCB == 0x%x, yet numscbs == 0x%x.",
7565 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7566 ahd_dump_card_state(ahd);
7567 panic("for safety");
7569 scb = ahd_lookup_scb(ahd, scbid);
7571 printf("%s: SCB = %d Not Active!\n",
7572 ahd_name(ahd), scbid);
7573 panic("Waiting List traversal\n");
7575 ahd_set_scbptr(ahd, scbid);
7577 next = ahd_inw_scbram(ahd, SCB_NEXT);
7578 if (ahd_match_scb(ahd, scb, target, channel,
7579 lun, SCB_LIST_NULL, role) == 0) {
7585 case SEARCH_COMPLETE:
7586 if ((scb->flags & SCB_ACTIVE) == 0)
7587 printf("Inactive SCB in Waiting List\n");
7588 ahd_done_with_status(ahd, scb, status);
7591 ahd_rem_wscb(ahd, scbid, prev, next, tid);
7593 if (SCBID_IS_NULL(prev))
7597 printf("0x%x ", scbid);
7602 if (found > AHD_SCB_MAX)
7603 panic("SCB LIST LOOP");
7605 if (action == SEARCH_COMPLETE
7606 || action == SEARCH_REMOVE)
7607 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found);
7612 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev,
7613 u_int tid_cur, u_int tid_next)
7615 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7617 if (SCBID_IS_NULL(tid_cur)) {
7619 /* Bypass current TID list */
7620 if (SCBID_IS_NULL(tid_prev)) {
7621 ahd_outw(ahd, WAITING_TID_HEAD, tid_next);
7623 ahd_set_scbptr(ahd, tid_prev);
7624 ahd_outw(ahd, SCB_NEXT2, tid_next);
7626 if (SCBID_IS_NULL(tid_next))
7627 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev);
7630 /* Stitch through tid_cur */
7631 if (SCBID_IS_NULL(tid_prev)) {
7632 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur);
7634 ahd_set_scbptr(ahd, tid_prev);
7635 ahd_outw(ahd, SCB_NEXT2, tid_cur);
7637 ahd_set_scbptr(ahd, tid_cur);
7638 ahd_outw(ahd, SCB_NEXT2, tid_next);
7640 if (SCBID_IS_NULL(tid_next))
7641 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur);
7646 * Manipulate the waiting for selection list and return the
7647 * scb that follows the one that we remove.
7650 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
7651 u_int prev, u_int next, u_int tid)
7655 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7656 if (!SCBID_IS_NULL(prev)) {
7657 ahd_set_scbptr(ahd, prev);
7658 ahd_outw(ahd, SCB_NEXT, next);
7662 * SCBs that have MK_MESSAGE set in them may
7663 * cause the tail pointer to be updated without
7664 * setting the next pointer of the previous tail.
7665 * Only clear the tail if the removed SCB was
7668 tail_offset = WAITING_SCB_TAILS + (2 * tid);
7669 if (SCBID_IS_NULL(next)
7670 && ahd_inw(ahd, tail_offset) == scbid)
7671 ahd_outw(ahd, tail_offset, prev);
7673 ahd_add_scb_to_free_list(ahd, scbid);
7678 * Add the SCB as selected by SCBPTR onto the on chip list of
7679 * free hardware SCBs. This list is empty/unused if we are not
7680 * performing SCB paging.
7683 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid)
7685 /* XXX Need some other mechanism to designate "free". */
7687 * Invalidate the tag so that our abort
7688 * routines don't think it's active.
7689 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL);
7693 /******************************** Error Handling ******************************/
7695 * Abort all SCBs that match the given description (target/channel/lun/tag),
7696 * setting their status to the passed in status if the status has not already
7697 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
7698 * is paused before it is called.
7701 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel,
7702 int lun, u_int tag, role_t role, uint32_t status)
7705 struct scb *scbp_next;
7711 ahd_mode_state saved_modes;
7713 /* restore this when we're done */
7714 saved_modes = ahd_save_modes(ahd);
7715 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7717 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL,
7718 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7721 * Clean out the busy target table for any untagged commands.
7725 if (target != CAM_TARGET_WILDCARD) {
7732 if (lun == CAM_LUN_WILDCARD) {
7734 maxlun = AHD_NUM_LUNS_NONPKT;
7735 } else if (lun >= AHD_NUM_LUNS_NONPKT) {
7736 minlun = maxlun = 0;
7742 if (role != ROLE_TARGET) {
7743 for (;i < maxtarget; i++) {
7744 for (j = minlun;j < maxlun; j++) {
7748 tcl = BUILD_TCL_RAW(i, 'A', j);
7749 scbid = ahd_find_busy_tcl(ahd, tcl);
7750 scbp = ahd_lookup_scb(ahd, scbid);
7752 || ahd_match_scb(ahd, scbp, target, channel,
7753 lun, tag, role) == 0)
7755 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j));
7761 * Don't abort commands that have already completed,
7762 * but haven't quite made it up to the host yet.
7764 ahd_flush_qoutfifo(ahd);
7767 * Go through the pending CCB list and look for
7768 * commands for this target that are still active.
7769 * These are other tagged commands that were
7770 * disconnected when the reset occurred.
7772 scbp_next = LIST_FIRST(&ahd->pending_scbs);
7773 while (scbp_next != NULL) {
7775 scbp_next = LIST_NEXT(scbp, pending_links);
7776 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) {
7779 ostat = ahd_get_transaction_status(scbp);
7780 if (ostat == CAM_REQ_INPROG)
7781 ahd_set_transaction_status(scbp, status);
7782 if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP)
7783 ahd_freeze_scb(scbp);
7784 if ((scbp->flags & SCB_ACTIVE) == 0)
7785 printf("Inactive SCB on pending list\n");
7786 ahd_done(ahd, scbp);
7790 ahd_restore_modes(ahd, saved_modes);
7791 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status);
7792 ahd->flags |= AHD_UPDATE_PEND_CMDS;
7797 ahd_reset_current_bus(struct ahd_softc *ahd)
7801 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7802 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST);
7803 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO);
7804 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO);
7805 ahd_flush_device_writes(ahd);
7806 ahd_delay(AHD_BUSRESET_DELAY);
7807 /* Turn off the bus reset */
7808 ahd_outb(ahd, SCSISEQ0, scsiseq);
7809 ahd_flush_device_writes(ahd);
7810 ahd_delay(AHD_BUSRESET_DELAY);
7811 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) {
7814 * Certain chip state is not cleared for
7815 * SCSI bus resets that we initiate, so
7816 * we must reset the chip.
7818 ahd_reset(ahd, /*reinit*/TRUE);
7819 ahd_intr_enable(ahd, /*enable*/TRUE);
7820 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7823 ahd_clear_intstat(ahd);
7827 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
7829 struct ahd_devinfo devinfo;
7837 ahd->pending_device = NULL;
7839 ahd_compile_devinfo(&devinfo,
7840 CAM_TARGET_WILDCARD,
7841 CAM_TARGET_WILDCARD,
7843 channel, ROLE_UNKNOWN);
7846 /* Make sure the sequencer is in a safe location. */
7847 ahd_clear_critical_section(ahd);
7849 #ifdef AHD_TARGET_MODE
7850 if ((ahd->flags & AHD_TARGETROLE) != 0) {
7851 ahd_run_tqinfifo(ahd, /*paused*/TRUE);
7854 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7857 * Disable selections so no automatic hardware
7858 * functions will modify chip state.
7860 ahd_outb(ahd, SCSISEQ0, 0);
7861 ahd_outb(ahd, SCSISEQ1, 0);
7864 * Safely shut down our DMA engines. Always start with
7865 * the FIFO that is not currently active (if any are
7866 * actively connected).
7868 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
7869 if (next_fifo > CURRFIFO_1)
7870 /* If disconneced, arbitrarily start with FIFO1. */
7871 next_fifo = fifo = 0;
7873 next_fifo ^= CURRFIFO_1;
7874 ahd_set_modes(ahd, next_fifo, next_fifo);
7875 ahd_outb(ahd, DFCNTRL,
7876 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN));
7877 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0)
7880 * Set CURRFIFO to the now inactive channel.
7882 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7883 ahd_outb(ahd, DFFSTAT, next_fifo);
7884 } while (next_fifo != fifo);
7887 * Reset the bus if we are initiating this reset
7889 ahd_clear_msg_state(ahd);
7890 ahd_outb(ahd, SIMODE1,
7891 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST));
7894 ahd_reset_current_bus(ahd);
7896 ahd_clear_intstat(ahd);
7899 * Clean up all the state information for the
7900 * pending transactions on this bus.
7902 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel,
7903 CAM_LUN_WILDCARD, SCB_LIST_NULL,
7904 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
7907 * Cleanup anything left in the FIFOs.
7909 ahd_clear_fifo(ahd, 0);
7910 ahd_clear_fifo(ahd, 1);
7913 * Revert to async/narrow transfers until we renegotiate.
7915 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
7916 for (target = 0; target <= max_scsiid; target++) {
7918 if (ahd->enabled_targets[target] == NULL)
7920 for (initiator = 0; initiator <= max_scsiid; initiator++) {
7921 struct ahd_devinfo devinfo;
7923 ahd_compile_devinfo(&devinfo, target, initiator,
7926 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
7927 AHD_TRANS_CUR, /*paused*/TRUE);
7928 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
7929 /*offset*/0, /*ppr_options*/0,
7930 AHD_TRANS_CUR, /*paused*/TRUE);
7934 #ifdef AHD_TARGET_MODE
7935 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
7938 * Send an immediate notify ccb to all target more peripheral
7939 * drivers affected by this action.
7941 for (target = 0; target <= max_scsiid; target++) {
7942 struct ahd_tmode_tstate* tstate;
7945 tstate = ahd->enabled_targets[target];
7948 for (lun = 0; lun < AHD_NUM_LUNS; lun++) {
7949 struct ahd_tmode_lstate* lstate;
7951 lstate = tstate->enabled_luns[lun];
7955 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD,
7956 EVENT_TYPE_BUS_RESET, /*arg*/0);
7957 ahd_send_lstate_events(ahd, lstate);
7961 /* Notify the XPT that a bus reset occurred */
7962 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD,
7963 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
7966 * Freeze the SIMQ until our poller can determine that
7967 * the bus reset has really gone away. We set the initial
7968 * timer to 0 to have the check performed as soon as possible
7969 * from the timer context.
7971 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) {
7972 ahd->flags |= AHD_RESET_POLL_ACTIVE;
7973 ahd_freeze_simq(ahd);
7974 ahd_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd);
7980 #define AHD_RESET_POLL_US 1000
7982 ahd_reset_poll(void *arg)
7984 struct ahd_softc *ahd = arg;
7990 ahd_update_modes(ahd);
7991 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7992 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
7993 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) {
7994 ahd_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US,
7995 ahd_reset_poll, ahd);
7997 ahd_unlock(ahd, &s);
8001 /* Reset is now low. Complete chip reinitialization. */
8002 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST);
8003 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
8004 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP));
8006 ahd->flags &= ~AHD_RESET_POLL_ACTIVE;
8007 ahd_unlock(ahd, &s);
8008 ahd_release_simq(ahd);
8011 /**************************** Statistics Processing ***************************/
8013 ahd_stat_timer(void *arg)
8015 struct ahd_softc *ahd = arg;
8021 enint_coal = ahd->hs_mailbox & ENINT_COALESCE;
8022 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold)
8023 enint_coal |= ENINT_COALESCE;
8024 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold)
8025 enint_coal &= ~ENINT_COALESCE;
8027 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) {
8028 ahd_enable_coalescing(ahd, enint_coal);
8030 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0)
8031 printf("%s: Interrupt coalescing "
8032 "now %sabled. Cmds %d\n",
8034 (enint_coal & ENINT_COALESCE) ? "en" : "dis",
8035 ahd->cmdcmplt_total);
8039 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1);
8040 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket];
8041 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0;
8042 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US,
8043 ahd_stat_timer, ahd);
8044 ahd_unlock(ahd, &s);
8047 /****************************** Status Processing *****************************/
8049 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb)
8051 if (scb->hscb->shared_data.istatus.scsi_status != 0) {
8052 ahd_handle_scsi_status(ahd, scb);
8054 ahd_calc_residual(ahd, scb);
8060 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb)
8062 struct hardware_scb *hscb;
8066 * The sequencer freezes its select-out queue
8067 * anytime a SCSI status error occurs. We must
8068 * handle the error and increment our qfreeze count
8069 * to allow the sequencer to continue. We don't
8070 * bother clearing critical sections here since all
8071 * operations are on data structures that the sequencer
8072 * is not touching once the queue is frozen.
8076 if (ahd_is_paused(ahd)) {
8083 /* Freeze the queue until the client sees the error. */
8084 ahd_freeze_devq(ahd, scb);
8085 ahd_freeze_scb(scb);
8087 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
8092 /* Don't want to clobber the original sense code */
8093 if ((scb->flags & SCB_SENSE) != 0) {
8095 * Clear the SCB_SENSE Flag and perform
8096 * a normal command completion.
8098 scb->flags &= ~SCB_SENSE;
8099 ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
8103 ahd_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
8104 ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status);
8105 switch (hscb->shared_data.istatus.scsi_status) {
8106 case STATUS_PKT_SENSE:
8108 struct scsi_status_iu_header *siu;
8110 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD);
8111 siu = (struct scsi_status_iu_header *)scb->sense_data;
8112 ahd_set_scsi_status(scb, siu->status);
8114 if ((ahd_debug & AHD_SHOW_SENSE) != 0) {
8115 ahd_print_path(ahd, scb);
8116 printf("SCB 0x%x Received PKT Status of 0x%x\n",
8117 SCB_GET_TAG(scb), siu->status);
8118 printf("\tflags = 0x%x, sense len = 0x%x, "
8120 siu->flags, scsi_4btoul(siu->sense_length),
8121 scsi_4btoul(siu->pkt_failures_length));
8124 if ((siu->flags & SIU_RSPVALID) != 0) {
8125 ahd_print_path(ahd, scb);
8126 if (scsi_4btoul(siu->pkt_failures_length) < 4) {
8127 printf("Unable to parse pkt_failures\n");
8130 switch (SIU_PKTFAIL_CODE(siu)) {
8132 printf("No packet failure found\n");
8134 case SIU_PFC_CIU_FIELDS_INVALID:
8135 printf("Invalid Command IU Field\n");
8137 case SIU_PFC_TMF_NOT_SUPPORTED:
8138 printf("TMF not supportd\n");
8140 case SIU_PFC_TMF_FAILED:
8141 printf("TMF failed\n");
8143 case SIU_PFC_INVALID_TYPE_CODE:
8144 printf("Invalid L_Q Type code\n");
8146 case SIU_PFC_ILLEGAL_REQUEST:
8147 printf("Illegal request\n");
8152 if (siu->status == SCSI_STATUS_OK)
8153 ahd_set_transaction_status(scb,
8156 if ((siu->flags & SIU_SNSVALID) != 0) {
8157 scb->flags |= SCB_PKT_SENSE;
8159 if ((ahd_debug & AHD_SHOW_SENSE) != 0)
8160 printf("Sense data available\n");
8166 case SCSI_STATUS_CMD_TERMINATED:
8167 case SCSI_STATUS_CHECK_COND:
8169 struct ahd_devinfo devinfo;
8170 struct ahd_dma_seg *sg;
8171 struct scsi_sense *sc;
8172 struct ahd_initiator_tinfo *targ_info;
8173 struct ahd_tmode_tstate *tstate;
8174 struct ahd_transinfo *tinfo;
8176 if (ahd_debug & AHD_SHOW_SENSE) {
8177 ahd_print_path(ahd, scb);
8178 printf("SCB %d: requests Check Status\n",
8183 if (ahd_perform_autosense(scb) == 0)
8186 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
8187 SCB_GET_TARGET(ahd, scb),
8189 SCB_GET_CHANNEL(ahd, scb),
8191 targ_info = ahd_fetch_transinfo(ahd,
8196 tinfo = &targ_info->curr;
8198 sc = (struct scsi_sense *)hscb->shared_data.idata.cdb;
8200 * Save off the residual if there is one.
8202 ahd_update_residual(ahd, scb);
8204 if (ahd_debug & AHD_SHOW_SENSE) {
8205 ahd_print_path(ahd, scb);
8206 printf("Sending Sense\n");
8210 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb),
8211 ahd_get_sense_bufsize(ahd, scb),
8213 sc->opcode = REQUEST_SENSE;
8215 if (tinfo->protocol_version <= SCSI_REV_2
8216 && SCB_GET_LUN(scb) < 8)
8217 sc->byte2 = SCB_GET_LUN(scb) << 5;
8220 sc->length = ahd_get_sense_bufsize(ahd, scb);
8224 * We can't allow the target to disconnect.
8225 * This will be an untagged transaction and
8226 * having the target disconnect will make this
8227 * transaction indestinguishable from outstanding
8228 * tagged transactions.
8233 * This request sense could be because the
8234 * the device lost power or in some other
8235 * way has lost our transfer negotiations.
8236 * Renegotiate if appropriate. Unit attention
8237 * errors will be reported before any data
8240 if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) {
8241 ahd_update_neg_request(ahd, &devinfo,
8243 AHD_NEG_IF_NON_ASYNC);
8245 if (tstate->auto_negotiate & devinfo.target_mask) {
8246 hscb->control |= MK_MESSAGE;
8248 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET);
8249 scb->flags |= SCB_AUTO_NEGOTIATE;
8251 hscb->cdb_len = sizeof(*sc);
8252 ahd_setup_data_scb(ahd, scb);
8253 scb->flags |= SCB_SENSE;
8254 ahd_queue_scb(ahd, scb);
8256 * Ensure we have enough time to actually
8257 * retrieve the sense.
8259 ahd_scb_timer_reset(scb, 5 * 1000000);
8262 case SCSI_STATUS_OK:
8263 printf("%s: Interrupted for staus of 0???\n",
8273 * Calculate the residual for a just completed SCB.
8276 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb)
8278 struct hardware_scb *hscb;
8279 struct initiator_status *spkt;
8281 uint32_t resid_sgptr;
8287 * SG_STATUS_VALID clear in sgptr.
8288 * 2) Transferless command
8289 * 3) Never performed any transfers.
8290 * sgptr has SG_FULL_RESID set.
8291 * 4) No residual but target did not
8292 * save data pointers after the
8293 * last transfer, so sgptr was
8295 * 5) We have a partial residual.
8296 * Use residual_sgptr to determine
8301 sgptr = ahd_le32toh(hscb->sgptr);
8302 if ((sgptr & SG_STATUS_VALID) == 0)
8305 sgptr &= ~SG_STATUS_VALID;
8307 if ((sgptr & SG_LIST_NULL) != 0)
8312 * Residual fields are the same in both
8313 * target and initiator status packets,
8314 * so we can always use the initiator fields
8315 * regardless of the role for this SCB.
8317 spkt = &hscb->shared_data.istatus;
8318 resid_sgptr = ahd_le32toh(spkt->residual_sgptr);
8319 if ((sgptr & SG_FULL_RESID) != 0) {
8321 resid = ahd_get_transfer_length(scb);
8322 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
8325 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) {
8326 ahd_print_path(ahd, scb);
8327 printf("data overrun detected Tag == 0x%x.\n",
8329 ahd_freeze_devq(ahd, scb);
8330 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR);
8331 ahd_freeze_scb(scb);
8333 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
8334 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
8337 struct ahd_dma_seg *sg;
8340 * Remainder of the SG where the transfer
8343 resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK;
8344 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK);
8346 /* The residual sg_ptr always points to the next sg */
8350 * Add up the contents of all residual
8351 * SG segments that are after the SG where
8352 * the transfer stopped.
8354 while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) {
8356 resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
8359 if ((scb->flags & SCB_SENSE) == 0)
8360 ahd_set_residual(scb, resid);
8362 ahd_set_sense_residual(scb, resid);
8365 if ((ahd_debug & AHD_SHOW_MISC) != 0) {
8366 ahd_print_path(ahd, scb);
8367 printf("Handled %sResidual of %d bytes\n",
8368 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
8373 /******************************* Target Mode **********************************/
8374 #ifdef AHD_TARGET_MODE
8376 * Add a target mode event to this lun's queue
8379 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate,
8380 u_int initiator_id, u_int event_type, u_int event_arg)
8382 struct ahd_tmode_event *event;
8385 xpt_freeze_devq(lstate->path, /*count*/1);
8386 if (lstate->event_w_idx >= lstate->event_r_idx)
8387 pending = lstate->event_w_idx - lstate->event_r_idx;
8389 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1
8390 - (lstate->event_r_idx - lstate->event_w_idx);
8392 if (event_type == EVENT_TYPE_BUS_RESET
8393 || event_type == MSG_BUS_DEV_RESET) {
8395 * Any earlier events are irrelevant, so reset our buffer.
8396 * This has the effect of allowing us to deal with reset
8397 * floods (an external device holding down the reset line)
8398 * without losing the event that is really interesting.
8400 lstate->event_r_idx = 0;
8401 lstate->event_w_idx = 0;
8402 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
8405 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) {
8406 xpt_print_path(lstate->path);
8407 printf("immediate event %x:%x lost\n",
8408 lstate->event_buffer[lstate->event_r_idx].event_type,
8409 lstate->event_buffer[lstate->event_r_idx].event_arg);
8410 lstate->event_r_idx++;
8411 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8412 lstate->event_r_idx = 0;
8413 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
8416 event = &lstate->event_buffer[lstate->event_w_idx];
8417 event->initiator_id = initiator_id;
8418 event->event_type = event_type;
8419 event->event_arg = event_arg;
8420 lstate->event_w_idx++;
8421 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8422 lstate->event_w_idx = 0;
8426 * Send any target mode events queued up waiting
8427 * for immediate notify resources.
8430 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate)
8432 struct ccb_hdr *ccbh;
8433 struct ccb_immed_notify *inot;
8435 while (lstate->event_r_idx != lstate->event_w_idx
8436 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
8437 struct ahd_tmode_event *event;
8439 event = &lstate->event_buffer[lstate->event_r_idx];
8440 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
8441 inot = (struct ccb_immed_notify *)ccbh;
8442 switch (event->event_type) {
8443 case EVENT_TYPE_BUS_RESET:
8444 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
8447 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
8448 inot->message_args[0] = event->event_type;
8449 inot->message_args[1] = event->event_arg;
8452 inot->initiator_id = event->initiator_id;
8453 inot->sense_len = 0;
8454 xpt_done((union ccb *)inot);
8455 lstate->event_r_idx++;
8456 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8457 lstate->event_r_idx = 0;
8462 /******************** Sequencer Program Patching/Download *********************/
8466 ahd_dumpseq(struct ahd_softc* ahd)
8473 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8474 ahd_outw(ahd, PRGMCNT, 0);
8475 for (i = 0; i < max_prog; i++) {
8476 uint8_t ins_bytes[4];
8478 ahd_insb(ahd, SEQRAM, ins_bytes, 4);
8479 printf("0x%08x\n", ins_bytes[0] << 24
8480 | ins_bytes[1] << 16
8488 ahd_loadseq(struct ahd_softc *ahd)
8490 struct cs cs_table[num_critical_sections];
8491 u_int begin_set[num_critical_sections];
8492 u_int end_set[num_critical_sections];
8493 struct patch *cur_patch;
8499 u_int sg_prefetch_cnt;
8500 u_int sg_prefetch_cnt_limit;
8501 u_int sg_prefetch_align;
8503 u_int cacheline_mask;
8504 uint8_t download_consts[DOWNLOAD_CONST_COUNT];
8507 printf("%s: Downloading Sequencer Program...",
8510 #if DOWNLOAD_CONST_COUNT != 8
8511 #error "Download Const Mismatch"
8514 * Start out with 0 critical sections
8515 * that apply to this firmware load.
8519 memset(begin_set, 0, sizeof(begin_set));
8520 memset(end_set, 0, sizeof(end_set));
8523 * Setup downloadable constant table.
8525 * The computation for the S/G prefetch variables is
8526 * a bit complicated. We would like to always fetch
8527 * in terms of cachelined sized increments. However,
8528 * if the cacheline is not an even multiple of the
8529 * SG element size or is larger than our SG RAM, using
8530 * just the cache size might leave us with only a portion
8531 * of an SG element at the tail of a prefetch. If the
8532 * cacheline is larger than our S/G prefetch buffer less
8533 * the size of an SG element, we may round down to a cacheline
8534 * that doesn't contain any or all of the S/G of interest
8535 * within the bounds of our S/G ram. Provide variables to
8536 * the sequencer that will allow it to handle these edge
8539 /* Start by aligning to the nearest cacheline. */
8540 sg_prefetch_align = ahd->pci_cachesize;
8541 if (sg_prefetch_align == 0)
8542 sg_prefetch_align = 8;
8543 /* Round down to the nearest power of 2. */
8544 while (powerof2(sg_prefetch_align) == 0)
8545 sg_prefetch_align--;
8547 cacheline_mask = sg_prefetch_align - 1;
8550 * If the cacheline boundary is greater than half our prefetch RAM
8551 * we risk not being able to fetch even a single complete S/G
8552 * segment if we align to that boundary.
8554 if (sg_prefetch_align > CCSGADDR_MAX/2)
8555 sg_prefetch_align = CCSGADDR_MAX/2;
8556 /* Start by fetching a single cacheline. */
8557 sg_prefetch_cnt = sg_prefetch_align;
8559 * Increment the prefetch count by cachelines until
8560 * at least one S/G element will fit.
8562 sg_size = sizeof(struct ahd_dma_seg);
8563 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
8564 sg_size = sizeof(struct ahd_dma64_seg);
8565 while (sg_prefetch_cnt < sg_size)
8566 sg_prefetch_cnt += sg_prefetch_align;
8568 * If the cacheline is not an even multiple of
8569 * the S/G size, we may only get a partial S/G when
8570 * we align. Add a cacheline if this is the case.
8572 if ((sg_prefetch_align % sg_size) != 0
8573 && (sg_prefetch_cnt < CCSGADDR_MAX))
8574 sg_prefetch_cnt += sg_prefetch_align;
8576 * Lastly, compute a value that the sequencer can use
8577 * to determine if the remainder of the CCSGRAM buffer
8578 * has a full S/G element in it.
8580 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1);
8581 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
8582 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit;
8583 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1);
8584 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1);
8585 download_consts[SG_SIZEOF] = sg_size;
8586 download_consts[PKT_OVERRUN_BUFOFFSET] =
8587 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256;
8588 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN;
8589 download_consts[CACHELINE_MASK] = cacheline_mask;
8590 cur_patch = patches;
8593 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8594 ahd_outw(ahd, PRGMCNT, 0);
8596 for (i = 0; i < sizeof(seqprog)/4; i++) {
8597 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) {
8599 * Don't download this instruction as it
8600 * is in a patch that was removed.
8605 * Move through the CS table until we find a CS
8606 * that might apply to this instruction.
8608 for (; cur_cs < num_critical_sections; cur_cs++) {
8609 if (critical_sections[cur_cs].end <= i) {
8610 if (begin_set[cs_count] == TRUE
8611 && end_set[cs_count] == FALSE) {
8612 cs_table[cs_count].end = downloaded;
8613 end_set[cs_count] = TRUE;
8618 if (critical_sections[cur_cs].begin <= i
8619 && begin_set[cs_count] == FALSE) {
8620 cs_table[cs_count].begin = downloaded;
8621 begin_set[cs_count] = TRUE;
8625 ahd_download_instr(ahd, i, download_consts);
8629 ahd->num_critical_sections = cs_count;
8630 if (cs_count != 0) {
8632 cs_count *= sizeof(struct cs);
8633 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
8634 if (ahd->critical_sections == NULL)
8635 panic("ahd_loadseq: Could not malloc");
8636 memcpy(ahd->critical_sections, cs_table, cs_count);
8638 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE);
8641 printf(" %d instructions downloaded\n", downloaded);
8642 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
8643 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags);
8648 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch,
8649 u_int start_instr, u_int *skip_addr)
8651 struct patch *cur_patch;
8652 struct patch *last_patch;
8655 num_patches = sizeof(patches)/sizeof(struct patch);
8656 last_patch = &patches[num_patches];
8657 cur_patch = *start_patch;
8659 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
8661 if (cur_patch->patch_func(ahd) == 0) {
8663 /* Start rejecting code */
8664 *skip_addr = start_instr + cur_patch->skip_instr;
8665 cur_patch += cur_patch->skip_patch;
8667 /* Accepted this patch. Advance to the next
8668 * one and wait for our intruction pointer to
8675 *start_patch = cur_patch;
8676 if (start_instr < *skip_addr)
8677 /* Still skipping */
8684 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address)
8686 struct patch *cur_patch;
8692 cur_patch = patches;
8695 for (i = 0; i < address;) {
8697 ahd_check_patch(ahd, &cur_patch, i, &skip_addr);
8699 if (skip_addr > i) {
8702 end_addr = MIN(address, skip_addr);
8703 address_offset += end_addr - i;
8709 return (address - address_offset);
8713 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts)
8715 union ins_formats instr;
8716 struct ins_format1 *fmt1_ins;
8717 struct ins_format3 *fmt3_ins;
8721 * The firmware is always compiled into a little endian format.
8723 instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
8725 fmt1_ins = &instr.format1;
8728 /* Pull the opcode */
8729 opcode = instr.format1.opcode;
8740 fmt3_ins = &instr.format3;
8741 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address);
8750 if (fmt1_ins->parity != 0) {
8751 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
8753 fmt1_ins->parity = 0;
8759 /* Calculate odd parity for the instruction */
8760 for (i = 0, count = 0; i < 31; i++) {
8764 if ((instr.integer & mask) != 0)
8767 if ((count & 0x01) == 0)
8768 instr.format1.parity = 1;
8770 /* The sequencer is a little endian cpu */
8771 instr.integer = ahd_htole32(instr.integer);
8772 ahd_outsb(ahd, SEQRAM, instr.bytes, 4);
8776 panic("Unknown opcode encountered in seq program");
8782 ahd_probe_stack_size(struct ahd_softc *ahd)
8791 * We avoid using 0 as a pattern to avoid
8792 * confusion if the stack implementation
8793 * "back-fills" with zeros when "poping'
8796 for (i = 1; i <= last_probe+1; i++) {
8797 ahd_outb(ahd, STACK, i & 0xFF);
8798 ahd_outb(ahd, STACK, (i >> 8) & 0xFF);
8802 for (i = last_probe+1; i > 0; i--) {
8805 stack_entry = ahd_inb(ahd, STACK)
8806 |(ahd_inb(ahd, STACK) << 8);
8807 if (stack_entry != i)
8813 return (last_probe);
8817 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries,
8818 const char *name, u_int address, u_int value,
8819 u_int *cur_column, u_int wrap_point)
8824 if (cur_column != NULL && *cur_column >= wrap_point) {
8828 printed = printf("%s[0x%x]", name, value);
8829 if (table == NULL) {
8830 printed += printf(" ");
8831 *cur_column += printed;
8835 while (printed_mask != 0xFF) {
8838 for (entry = 0; entry < num_entries; entry++) {
8839 if (((value & table[entry].mask)
8840 != table[entry].value)
8841 || ((printed_mask & table[entry].mask)
8842 == table[entry].mask))
8845 printed += printf("%s%s",
8846 printed_mask == 0 ? ":(" : "|",
8848 printed_mask |= table[entry].mask;
8852 if (entry >= num_entries)
8855 if (printed_mask != 0)
8856 printed += printf(") ");
8858 printed += printf(" ");
8859 if (cur_column != NULL)
8860 *cur_column += printed;
8865 ahd_dump_card_state(struct ahd_softc *ahd)
8868 ahd_mode_state saved_modes;
8872 u_int saved_scb_index;
8876 if (ahd_is_paused(ahd)) {
8882 saved_modes = ahd_save_modes(ahd);
8883 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8884 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
8885 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n",
8887 ahd_inw(ahd, CURADDR),
8888 ahd_build_mode_state(ahd, ahd->saved_src_mode,
8889 ahd->saved_dst_mode));
8891 printf("Card was paused\n");
8893 if (ahd_check_cmdcmpltqueues(ahd))
8894 printf("Completions are pending\n");
8897 * Mode independent registers.
8900 ahd_intstat_print(ahd_inb(ahd, INTSTAT), &cur_col, 50);
8901 ahd_seloid_print(ahd_inb(ahd, SELOID), &cur_col, 50);
8902 ahd_selid_print(ahd_inb(ahd, SELID), &cur_col, 50);
8903 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50);
8904 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50);
8905 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50);
8906 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50);
8907 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50);
8908 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50);
8909 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50);
8910 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50);
8911 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50);
8912 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50);
8913 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50);
8914 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50);
8915 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50);
8916 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50);
8917 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50);
8918 ahd_qfreeze_count_print(ahd_inw(ahd, QFREEZE_COUNT), &cur_col, 50);
8919 ahd_kernel_qfreeze_count_print(ahd_inw(ahd, KERNEL_QFREEZE_COUNT),
8921 ahd_mk_message_scb_print(ahd_inw(ahd, MK_MESSAGE_SCB), &cur_col, 50);
8922 ahd_mk_message_scsiid_print(ahd_inb(ahd, MK_MESSAGE_SCSIID),
8924 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50);
8925 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50);
8926 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50);
8927 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50);
8928 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50);
8929 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50);
8930 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50);
8931 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50);
8932 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50);
8933 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50);
8934 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50);
8935 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50);
8937 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x "
8938 "CURRSCB 0x%x NEXTSCB 0x%x\n",
8939 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING),
8940 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB),
8941 ahd_inw(ahd, NEXTSCB));
8944 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
8945 CAM_LUN_WILDCARD, SCB_LIST_NULL,
8946 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT);
8947 saved_scb_index = ahd_get_scbptr(ahd);
8948 printf("Pending list:");
8950 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
8951 if (i++ > AHD_SCB_MAX)
8953 cur_col = printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb),
8954 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT));
8955 ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
8956 ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL),
8958 ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID),
8961 printf("\nTotal %d\n", i);
8963 printf("Kernel Free SCB list: ");
8965 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
8966 struct scb *list_scb;
8970 printf("%d ", SCB_GET_TAG(list_scb));
8971 list_scb = LIST_NEXT(list_scb, collision_links);
8972 } while (list_scb && i++ < AHD_SCB_MAX);
8975 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
8976 if (i++ > AHD_SCB_MAX)
8978 printf("%d ", SCB_GET_TAG(scb));
8982 printf("Sequencer Complete DMA-inprog list: ");
8983 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD);
8985 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
8986 ahd_set_scbptr(ahd, scb_index);
8987 printf("%d ", scb_index);
8988 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
8992 printf("Sequencer Complete list: ");
8993 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD);
8995 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
8996 ahd_set_scbptr(ahd, scb_index);
8997 printf("%d ", scb_index);
8998 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9003 printf("Sequencer DMA-Up and Complete list: ");
9004 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
9006 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9007 ahd_set_scbptr(ahd, scb_index);
9008 printf("%d ", scb_index);
9009 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9012 printf("Sequencer On QFreeze and Complete list: ");
9013 scb_index = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
9015 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9016 ahd_set_scbptr(ahd, scb_index);
9017 printf("%d ", scb_index);
9018 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9021 ahd_set_scbptr(ahd, saved_scb_index);
9022 dffstat = ahd_inb(ahd, DFFSTAT);
9023 for (i = 0; i < 2; i++) {
9025 struct scb *fifo_scb;
9029 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
9030 fifo_scbptr = ahd_get_scbptr(ahd);
9031 printf("\n\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n",
9033 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active",
9034 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr);
9036 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50);
9037 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50);
9038 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50);
9039 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50);
9040 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW),
9042 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50);
9043 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50);
9044 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50);
9045 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50);
9050 cur_col += printf("SHADDR = 0x%x%x, SHCNT = 0x%x ",
9051 ahd_inl(ahd, SHADDR+4),
9052 ahd_inl(ahd, SHADDR),
9053 (ahd_inb(ahd, SHCNT)
9054 | (ahd_inb(ahd, SHCNT + 1) << 8)
9055 | (ahd_inb(ahd, SHCNT + 2) << 16)));
9060 cur_col += printf("HADDR = 0x%x%x, HCNT = 0x%x ",
9061 ahd_inl(ahd, HADDR+4),
9062 ahd_inl(ahd, HADDR),
9064 | (ahd_inb(ahd, HCNT + 1) << 8)
9065 | (ahd_inb(ahd, HCNT + 2) << 16)));
9066 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50);
9068 if ((ahd_debug & AHD_SHOW_SG) != 0) {
9069 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr);
9070 if (fifo_scb != NULL)
9071 ahd_dump_sglist(fifo_scb);
9076 for (i = 0; i < 20; i++)
9077 printf("0x%x ", ahd_inb(ahd, LQIN + i));
9079 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
9080 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n",
9081 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE),
9082 ahd_inb(ahd, OPTIONMODE));
9083 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n",
9084 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT),
9085 ahd_inb(ahd, MAXCMDCNT));
9086 printf("%s: SAVED_SCSIID = 0x%x SAVED_LUN = 0x%x\n",
9087 ahd_name(ahd), ahd_inb(ahd, SAVED_SCSIID),
9088 ahd_inb(ahd, SAVED_LUN));
9089 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50);
9091 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
9093 ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50);
9095 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
9096 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n",
9097 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX),
9098 ahd_inw(ahd, DINDEX));
9099 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n",
9100 ahd_name(ahd), ahd_get_scbptr(ahd),
9101 ahd_inw_scbram(ahd, SCB_NEXT),
9102 ahd_inw_scbram(ahd, SCB_NEXT2));
9103 printf("CDB %x %x %x %x %x %x\n",
9104 ahd_inb_scbram(ahd, SCB_CDB_STORE),
9105 ahd_inb_scbram(ahd, SCB_CDB_STORE+1),
9106 ahd_inb_scbram(ahd, SCB_CDB_STORE+2),
9107 ahd_inb_scbram(ahd, SCB_CDB_STORE+3),
9108 ahd_inb_scbram(ahd, SCB_CDB_STORE+4),
9109 ahd_inb_scbram(ahd, SCB_CDB_STORE+5));
9111 for (i = 0; i < ahd->stack_size; i++) {
9112 ahd->saved_stack[i] =
9113 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8);
9114 printf(" 0x%x", ahd->saved_stack[i]);
9116 for (i = ahd->stack_size-1; i >= 0; i--) {
9117 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF);
9118 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF);
9120 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
9121 ahd_restore_modes(ahd, saved_modes);
9127 ahd_dump_scbs(struct ahd_softc *ahd)
9129 ahd_mode_state saved_modes;
9130 u_int saved_scb_index;
9133 saved_modes = ahd_save_modes(ahd);
9134 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9135 saved_scb_index = ahd_get_scbptr(ahd);
9136 for (i = 0; i < AHD_SCB_MAX; i++) {
9137 ahd_set_scbptr(ahd, i);
9139 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n",
9140 ahd_inb_scbram(ahd, SCB_CONTROL),
9141 ahd_inb_scbram(ahd, SCB_SCSIID),
9142 ahd_inw_scbram(ahd, SCB_NEXT),
9143 ahd_inw_scbram(ahd, SCB_NEXT2),
9144 ahd_inl_scbram(ahd, SCB_SGPTR),
9145 ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR));
9148 ahd_set_scbptr(ahd, saved_scb_index);
9149 ahd_restore_modes(ahd, saved_modes);
9152 /**************************** Flexport Logic **********************************/
9154 * Read count 16bit words from 16bit word address start_addr from the
9155 * SEEPROM attached to the controller, into buf, using the controller's
9156 * SEEPROM reading state machine. Optionally treat the data as a byte
9157 * stream in terms of byte order.
9160 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9161 u_int start_addr, u_int count, int bytestream)
9168 * If we never make it through the loop even once,
9169 * we were passed invalid arguments.
9172 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9173 end_addr = start_addr + count;
9174 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9176 ahd_outb(ahd, SEEADR, cur_addr);
9177 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART);
9179 error = ahd_wait_seeprom(ahd);
9182 if (bytestream != 0) {
9183 uint8_t *bytestream_ptr;
9185 bytestream_ptr = (uint8_t *)buf;
9186 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT);
9187 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1);
9190 * ahd_inw() already handles machine byte order.
9192 *buf = ahd_inw(ahd, SEEDAT);
9200 * Write count 16bit words from buf, into SEEPROM attache to the
9201 * controller starting at 16bit word address start_addr, using the
9202 * controller's SEEPROM writing state machine.
9205 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9206 u_int start_addr, u_int count)
9213 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9216 /* Place the chip into write-enable mode */
9217 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR);
9218 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART);
9219 error = ahd_wait_seeprom(ahd);
9224 * Write the data. If we don't get throught the loop at
9225 * least once, the arguments were invalid.
9228 end_addr = start_addr + count;
9229 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9230 ahd_outw(ahd, SEEDAT, *buf++);
9231 ahd_outb(ahd, SEEADR, cur_addr);
9232 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART);
9234 retval = ahd_wait_seeprom(ahd);
9242 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR);
9243 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART);
9244 error = ahd_wait_seeprom(ahd);
9251 * Wait ~100us for the serial eeprom to satisfy our request.
9254 ahd_wait_seeprom(struct ahd_softc *ahd)
9259 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt)
9268 * Validate the two checksums in the per_channel
9269 * vital product data struct.
9272 ahd_verify_vpd_cksum(struct vpd_config *vpd)
9279 vpdarray = (uint8_t *)vpd;
9280 maxaddr = offsetof(struct vpd_config, vpd_checksum);
9282 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++)
9283 checksum = checksum + vpdarray[i];
9285 || (-checksum & 0xFF) != vpd->vpd_checksum)
9289 maxaddr = offsetof(struct vpd_config, checksum);
9290 for (i = offsetof(struct vpd_config, default_target_flags);
9292 checksum = checksum + vpdarray[i];
9294 || (-checksum & 0xFF) != vpd->checksum)
9300 ahd_verify_cksum(struct seeprom_config *sc)
9307 maxaddr = (sizeof(*sc)/2) - 1;
9309 scarray = (uint16_t *)sc;
9311 for (i = 0; i < maxaddr; i++)
9312 checksum = checksum + scarray[i];
9314 || (checksum & 0xFFFF) != sc->checksum) {
9322 ahd_acquire_seeprom(struct ahd_softc *ahd)
9325 * We should be able to determine the SEEPROM type
9326 * from the flexport logic, but unfortunately not
9327 * all implementations have this logic and there is
9328 * no programatic method for determining if the logic
9336 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype);
9338 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE))
9345 ahd_release_seeprom(struct ahd_softc *ahd)
9347 /* Currently a no-op */
9351 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value)
9355 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9357 panic("ahd_write_flexport: address out of range");
9358 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9359 error = ahd_wait_flexport(ahd);
9362 ahd_outb(ahd, BRDDAT, value);
9363 ahd_flush_device_writes(ahd);
9364 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3));
9365 ahd_flush_device_writes(ahd);
9366 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9367 ahd_flush_device_writes(ahd);
9368 ahd_outb(ahd, BRDCTL, 0);
9369 ahd_flush_device_writes(ahd);
9374 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value)
9378 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9380 panic("ahd_read_flexport: address out of range");
9381 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3));
9382 error = ahd_wait_flexport(ahd);
9385 *value = ahd_inb(ahd, BRDDAT);
9386 ahd_outb(ahd, BRDCTL, 0);
9387 ahd_flush_device_writes(ahd);
9392 * Wait at most 2 seconds for flexport arbitration to succeed.
9395 ahd_wait_flexport(struct ahd_softc *ahd)
9399 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9400 cnt = 1000000 * 2 / 5;
9401 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt)
9409 /************************* Target Mode ****************************************/
9410 #ifdef AHD_TARGET_MODE
9412 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb,
9413 struct ahd_tmode_tstate **tstate,
9414 struct ahd_tmode_lstate **lstate,
9415 int notfound_failure)
9418 if ((ahd->features & AHD_TARGETMODE) == 0)
9419 return (CAM_REQ_INVALID);
9422 * Handle the 'black hole' device that sucks up
9423 * requests to unattached luns on enabled targets.
9425 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
9426 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
9428 *lstate = ahd->black_hole;
9432 max_id = (ahd->features & AHD_WIDE) ? 15 : 7;
9433 if (ccb->ccb_h.target_id > max_id)
9434 return (CAM_TID_INVALID);
9436 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS)
9437 return (CAM_LUN_INVALID);
9439 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id];
9441 if (*tstate != NULL)
9443 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
9446 if (notfound_failure != 0 && *lstate == NULL)
9447 return (CAM_PATH_INVALID);
9449 return (CAM_REQ_CMP);
9453 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb)
9456 struct ahd_tmode_tstate *tstate;
9457 struct ahd_tmode_lstate *lstate;
9458 struct ccb_en_lun *cel;
9466 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate,
9467 /*notfound_failure*/FALSE);
9469 if (status != CAM_REQ_CMP) {
9470 ccb->ccb_h.status = status;
9474 if ((ahd->features & AHD_MULTIROLE) != 0) {
9477 our_id = ahd->our_id;
9478 if (ccb->ccb_h.target_id != our_id) {
9479 if ((ahd->features & AHD_MULTI_TID) != 0
9480 && (ahd->flags & AHD_INITIATORROLE) != 0) {
9482 * Only allow additional targets if
9483 * the initiator role is disabled.
9484 * The hardware cannot handle a re-select-in
9485 * on the initiator id during a re-select-out
9486 * on a different target id.
9488 status = CAM_TID_INVALID;
9489 } else if ((ahd->flags & AHD_INITIATORROLE) != 0
9490 || ahd->enabled_luns > 0) {
9492 * Only allow our target id to change
9493 * if the initiator role is not configured
9494 * and there are no enabled luns which
9495 * are attached to the currently registered
9498 status = CAM_TID_INVALID;
9503 if (status != CAM_REQ_CMP) {
9504 ccb->ccb_h.status = status;
9509 * We now have an id that is valid.
9510 * If we aren't in target mode, switch modes.
9512 if ((ahd->flags & AHD_TARGETROLE) == 0
9513 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
9516 printf("Configuring Target Mode\n");
9518 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
9519 ccb->ccb_h.status = CAM_BUSY;
9520 ahd_unlock(ahd, &s);
9523 ahd->flags |= AHD_TARGETROLE;
9524 if ((ahd->features & AHD_MULTIROLE) == 0)
9525 ahd->flags &= ~AHD_INITIATORROLE;
9529 ahd_unlock(ahd, &s);
9532 target = ccb->ccb_h.target_id;
9533 lun = ccb->ccb_h.target_lun;
9534 channel = SIM_CHANNEL(ahd, sim);
9535 target_mask = 0x01 << target;
9539 if (cel->enable != 0) {
9542 /* Are we already enabled?? */
9543 if (lstate != NULL) {
9544 xpt_print_path(ccb->ccb_h.path);
9545 printf("Lun already enabled\n");
9546 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
9550 if (cel->grp6_len != 0
9551 || cel->grp7_len != 0) {
9553 * Don't (yet?) support vendor
9554 * specific commands.
9556 ccb->ccb_h.status = CAM_REQ_INVALID;
9557 printf("Non-zero Group Codes\n");
9563 * Setup our data structures.
9565 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
9566 tstate = ahd_alloc_tstate(ahd, target, channel);
9567 if (tstate == NULL) {
9568 xpt_print_path(ccb->ccb_h.path);
9569 printf("Couldn't allocate tstate\n");
9570 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9574 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
9575 if (lstate == NULL) {
9576 xpt_print_path(ccb->ccb_h.path);
9577 printf("Couldn't allocate lstate\n");
9578 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9581 memset(lstate, 0, sizeof(*lstate));
9582 status = xpt_create_path(&lstate->path, /*periph*/NULL,
9583 xpt_path_path_id(ccb->ccb_h.path),
9584 xpt_path_target_id(ccb->ccb_h.path),
9585 xpt_path_lun_id(ccb->ccb_h.path));
9586 if (status != CAM_REQ_CMP) {
9587 free(lstate, M_DEVBUF);
9588 xpt_print_path(ccb->ccb_h.path);
9589 printf("Couldn't allocate path\n");
9590 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9593 SLIST_INIT(&lstate->accept_tios);
9594 SLIST_INIT(&lstate->immed_notifies);
9597 if (target != CAM_TARGET_WILDCARD) {
9598 tstate->enabled_luns[lun] = lstate;
9599 ahd->enabled_luns++;
9601 if ((ahd->features & AHD_MULTI_TID) != 0) {
9604 targid_mask = ahd_inw(ahd, TARGID);
9605 targid_mask |= target_mask;
9606 ahd_outw(ahd, TARGID, targid_mask);
9607 ahd_update_scsiid(ahd, targid_mask);
9612 channel = SIM_CHANNEL(ahd, sim);
9613 our_id = SIM_SCSI_ID(ahd, sim);
9616 * This can only happen if selections
9619 if (target != our_id) {
9624 sblkctl = ahd_inb(ahd, SBLKCTL);
9625 cur_channel = (sblkctl & SELBUSB)
9627 if ((ahd->features & AHD_TWIN) == 0)
9629 swap = cur_channel != channel;
9630 ahd->our_id = target;
9633 ahd_outb(ahd, SBLKCTL,
9636 ahd_outb(ahd, SCSIID, target);
9639 ahd_outb(ahd, SBLKCTL, sblkctl);
9643 ahd->black_hole = lstate;
9644 /* Allow select-in operations */
9645 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) {
9646 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
9648 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
9649 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
9651 ahd_outb(ahd, SCSISEQ1, scsiseq1);
9654 ahd_unlock(ahd, &s);
9655 ccb->ccb_h.status = CAM_REQ_CMP;
9656 xpt_print_path(ccb->ccb_h.path);
9657 printf("Lun now enabled for target mode\n");
9662 if (lstate == NULL) {
9663 ccb->ccb_h.status = CAM_LUN_INVALID;
9669 ccb->ccb_h.status = CAM_REQ_CMP;
9670 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
9671 struct ccb_hdr *ccbh;
9673 ccbh = &scb->io_ctx->ccb_h;
9674 if (ccbh->func_code == XPT_CONT_TARGET_IO
9675 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
9676 printf("CTIO pending\n");
9677 ccb->ccb_h.status = CAM_REQ_INVALID;
9678 ahd_unlock(ahd, &s);
9683 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
9684 printf("ATIOs pending\n");
9685 ccb->ccb_h.status = CAM_REQ_INVALID;
9688 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
9689 printf("INOTs pending\n");
9690 ccb->ccb_h.status = CAM_REQ_INVALID;
9693 if (ccb->ccb_h.status != CAM_REQ_CMP) {
9694 ahd_unlock(ahd, &s);
9698 xpt_print_path(ccb->ccb_h.path);
9699 printf("Target mode disabled\n");
9700 xpt_free_path(lstate->path);
9701 free(lstate, M_DEVBUF);
9704 /* Can we clean up the target too? */
9705 if (target != CAM_TARGET_WILDCARD) {
9706 tstate->enabled_luns[lun] = NULL;
9707 ahd->enabled_luns--;
9708 for (empty = 1, i = 0; i < 8; i++)
9709 if (tstate->enabled_luns[i] != NULL) {
9715 ahd_free_tstate(ahd, target, channel,
9717 if (ahd->features & AHD_MULTI_TID) {
9720 targid_mask = ahd_inw(ahd, TARGID);
9721 targid_mask &= ~target_mask;
9722 ahd_outw(ahd, TARGID, targid_mask);
9723 ahd_update_scsiid(ahd, targid_mask);
9728 ahd->black_hole = NULL;
9731 * We can't allow selections without
9732 * our black hole device.
9736 if (ahd->enabled_luns == 0) {
9737 /* Disallow select-in */
9740 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
9741 scsiseq1 &= ~ENSELI;
9742 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
9743 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
9744 scsiseq1 &= ~ENSELI;
9745 ahd_outb(ahd, SCSISEQ1, scsiseq1);
9747 if ((ahd->features & AHD_MULTIROLE) == 0) {
9748 printf("Configuring Initiator Mode\n");
9749 ahd->flags &= ~AHD_TARGETROLE;
9750 ahd->flags |= AHD_INITIATORROLE;
9755 * Unpaused. The extra unpause
9756 * that follows is harmless.
9761 ahd_unlock(ahd, &s);
9767 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask)
9773 if ((ahd->features & AHD_MULTI_TID) == 0)
9774 panic("ahd_update_scsiid called on non-multitid unit\n");
9777 * Since we will rely on the TARGID mask
9778 * for selection enables, ensure that OID
9779 * in SCSIID is not set to some other ID
9780 * that we don't want to allow selections on.
9782 if ((ahd->features & AHD_ULTRA2) != 0)
9783 scsiid = ahd_inb(ahd, SCSIID_ULTRA2);
9785 scsiid = ahd_inb(ahd, SCSIID);
9786 scsiid_mask = 0x1 << (scsiid & OID);
9787 if ((targid_mask & scsiid_mask) == 0) {
9790 /* ffs counts from 1 */
9791 our_id = ffs(targid_mask);
9793 our_id = ahd->our_id;
9799 if ((ahd->features & AHD_ULTRA2) != 0)
9800 ahd_outb(ahd, SCSIID_ULTRA2, scsiid);
9802 ahd_outb(ahd, SCSIID, scsiid);
9807 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused)
9809 struct target_cmd *cmd;
9811 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD);
9812 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) {
9815 * Only advance through the queue if we
9816 * have the resources to process the command.
9818 if (ahd_handle_target_cmd(ahd, cmd) != 0)
9822 ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
9823 ahd->shared_data_map.dmamap,
9824 ahd_targetcmd_offset(ahd, ahd->tqinfifonext),
9825 sizeof(struct target_cmd),
9826 BUS_DMASYNC_PREREAD);
9827 ahd->tqinfifonext++;
9830 * Lazily update our position in the target mode incoming
9831 * command queue as seen by the sequencer.
9833 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
9836 hs_mailbox = ahd_inb(ahd, HS_MAILBOX);
9837 hs_mailbox &= ~HOST_TQINPOS;
9838 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS;
9839 ahd_outb(ahd, HS_MAILBOX, hs_mailbox);
9845 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd)
9847 struct ahd_tmode_tstate *tstate;
9848 struct ahd_tmode_lstate *lstate;
9849 struct ccb_accept_tio *atio;
9855 initiator = SCSIID_TARGET(ahd, cmd->scsiid);
9856 target = SCSIID_OUR_ID(cmd->scsiid);
9857 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
9860 tstate = ahd->enabled_targets[target];
9863 lstate = tstate->enabled_luns[lun];
9866 * Commands for disabled luns go to the black hole driver.
9869 lstate = ahd->black_hole;
9871 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
9873 ahd->flags |= AHD_TQINFIFO_BLOCKED;
9875 * Wait for more ATIOs from the peripheral driver for this lun.
9879 ahd->flags &= ~AHD_TQINFIFO_BLOCKED;
9881 if ((ahd_debug & AHD_SHOW_TQIN) != 0)
9882 printf("Incoming command from %d for %d:%d%s\n",
9883 initiator, target, lun,
9884 lstate == ahd->black_hole ? "(Black Holed)" : "");
9886 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
9888 if (lstate == ahd->black_hole) {
9889 /* Fill in the wildcards */
9890 atio->ccb_h.target_id = target;
9891 atio->ccb_h.target_lun = lun;
9895 * Package it up and send it off to
9896 * whomever has this lun enabled.
9898 atio->sense_len = 0;
9899 atio->init_id = initiator;
9900 if (byte[0] != 0xFF) {
9901 /* Tag was included */
9902 atio->tag_action = *byte++;
9903 atio->tag_id = *byte++;
9904 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
9906 atio->ccb_h.flags = 0;
9910 /* Okay. Now determine the cdb size based on the command code */
9911 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
9927 /* Only copy the opcode. */
9929 printf("Reserved or VU command code type encountered\n");
9933 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
9935 atio->ccb_h.status |= CAM_CDB_RECVD;
9937 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
9939 * We weren't allowed to disconnect.
9940 * We're hanging on the bus until a
9941 * continue target I/O comes in response
9942 * to this accept tio.
9945 if ((ahd_debug & AHD_SHOW_TQIN) != 0)
9946 printf("Received Immediate Command %d:%d:%d - %p\n",
9947 initiator, target, lun, ahd->pending_device);
9949 ahd->pending_device = lstate;
9950 ahd_freeze_ccb((union ccb *)atio);
9951 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
9953 xpt_done((union ccb*)atio);