drivers/scsi/a100u2w.c

   1 /*
   2  * Initio A100 device driver for Linux.
   3  *
   4  * Copyright (c) 1994-1998 Initio Corporation
   5  * Copyright (c) 2003-2004 Christoph Hellwig
   6  * All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; see the file COPYING.  If not, write to
  20  * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  * --------------------------------------------------------------------------
  23  *
  24  * Redistribution and use in source and binary forms, with or without
  25  * modification, are permitted provided that the following conditions
  26  * are met:
  27  * 1. Redistributions of source code must retain the above copyright
  28  *    notice, this list of conditions, and the following disclaimer,
  29  *    without modification, immediately at the beginning of the file.
  30  * 2. Redistributions in binary form must reproduce the above copyright
  31  *    notice, this list of conditions and the following disclaimer in the
  32  *    documentation and/or other materials provided with the distribution.
  33  * 3. The name of the author may not be used to endorse or promote products
  34  *    derived from this software without specific prior written permission.
  35  *
  36  * Where this Software is combined with software released under the terms of
  37  * the GNU General Public License ("GPL") and the terms of the GPL would require the
  38  * combined work to also be released under the terms of the GPL, the terms
  39  * and conditions of this License will apply in addition to those of the
  40  * GPL with the exception of any terms or conditions of this License that
  41  * conflict with, or are expressly prohibited by, the GPL.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  44  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  45  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  46  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  47  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  48  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  49  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  50  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  51  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  52  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  53  * SUCH DAMAGE.
  54  */
  55
  56 /*
  57  * Revision History:
  58  * 07/02/98 hl  - v.91n Initial drivers.
  59  * 09/14/98 hl - v1.01 Support new Kernel.
  60  * 09/22/98 hl - v1.01a Support reset.
  61  * 09/24/98 hl - v1.01b Fixed reset.
  62  * 10/05/98 hl - v1.02 split the source code and release.
  63  * 12/19/98 bv - v1.02a Use spinlocks for 2.1.95 and up
  64  * 01/31/99 bv - v1.02b Use mdelay instead of waitForPause
  65  * 08/08/99 bv - v1.02c Use waitForPause again.
  66  * 06/25/02 Doug Ledford <dledford@redhat.com> - v1.02d
  67  *          - Remove limit on number of controllers
  68  *          - Port to DMA mapping API
  69  *          - Clean up interrupt handler registration
  70  *          - Fix memory leaks
  71  *          - Fix allocation of scsi host structs and private data
  72  * 11/18/03 Christoph Hellwig <hch@lst.de>
  73  *          - Port to new probing API
  74  *          - Fix some more leaks in init failure cases
  75  * 9/28/04 Christoph Hellwig <hch@lst.de>
  76  *          - merge the two source files
  77  *          - remove internal queueing code
  78  */
  79
  80 #include <linux/module.h>
  81 #include <linux/errno.h>
  82 #include <linux/delay.h>
  83 #include <linux/interrupt.h>
  84 #include <linux/pci.h>
  85 #include <linux/init.h>
  86 #include <linux/blkdev.h>
  87 #include <linux/spinlock.h>
  88 #include <linux/kernel.h>
  89 #include <linux/string.h>
  90 #include <linux/ioport.h>
  91 #include <linux/slab.h>
  92 #include <linux/dma-mapping.h>
  93
  94 #include <asm/io.h>
  95 #include <asm/irq.h>
  96
  97 #include <scsi/scsi.h>
  98 #include <scsi/scsi_cmnd.h>
  99 #include <scsi/scsi_device.h>
 100 #include <scsi/scsi_host.h>
 101
 102 #include "a100u2w.h"
 103
 104
 105 #define JIFFIES_TO_MS(t) ((t) * 1000 / HZ)
 106 #define MS_TO_JIFFIES(j) ((j * HZ) / 1000)
 107
 108 static ORC_SCB *orc_alloc_scb(ORC_HCS * hcsp);
 109 static void inia100SCBPost(BYTE * pHcb, BYTE * pScb);
 110
 111 static NVRAM nvram, *nvramp = &nvram;
 112 static UCHAR dftNvRam[64] =
 113 {
 114 /*----------header -------------*/
 115         0x01,                   /* 0x00: Sub System Vendor ID 0 */
 116         0x11,                   /* 0x01: Sub System Vendor ID 1 */
 117         0x60,                   /* 0x02: Sub System ID 0        */
 118         0x10,                   /* 0x03: Sub System ID 1        */
 119         0x00,                   /* 0x04: SubClass               */
 120         0x01,                   /* 0x05: Vendor ID 0            */
 121         0x11,                   /* 0x06: Vendor ID 1            */
 122         0x60,                   /* 0x07: Device ID 0            */
 123         0x10,                   /* 0x08: Device ID 1            */
 124         0x00,                   /* 0x09: Reserved               */
 125         0x00,                   /* 0x0A: Reserved               */
 126         0x01,                   /* 0x0B: Revision of Data Structure     */
 127                                 /* -- Host Adapter Structure --- */
 128         0x01,                   /* 0x0C: Number Of SCSI Channel */
 129         0x01,                   /* 0x0D: BIOS Configuration 1   */
 130         0x00,                   /* 0x0E: BIOS Configuration 2   */
 131         0x00,                   /* 0x0F: BIOS Configuration 3   */
 132                                 /* --- SCSI Channel 0 Configuration --- */
 133         0x07,                   /* 0x10: H/A ID                 */
 134         0x83,                   /* 0x11: Channel Configuration  */
 135         0x20,                   /* 0x12: MAX TAG per target     */
 136         0x0A,                   /* 0x13: SCSI Reset Recovering time     */
 137         0x00,                   /* 0x14: Channel Configuration4 */
 138         0x00,                   /* 0x15: Channel Configuration5 */
 139                                 /* SCSI Channel 0 Target Configuration  */
 140                                 /* 0x16-0x25                    */
 141         0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
 142         0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
 143                                 /* --- SCSI Channel 1 Configuration --- */
 144         0x07,                   /* 0x26: H/A ID                 */
 145         0x83,                   /* 0x27: Channel Configuration  */
 146         0x20,                   /* 0x28: MAX TAG per target     */
 147         0x0A,                   /* 0x29: SCSI Reset Recovering time     */
 148         0x00,                   /* 0x2A: Channel Configuration4 */
 149         0x00,                   /* 0x2B: Channel Configuration5 */
 150                                 /* SCSI Channel 1 Target Configuration  */
 151                                 /* 0x2C-0x3B                    */
 152         0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
 153         0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
 154         0x00,                   /* 0x3C: Reserved               */
 155         0x00,                   /* 0x3D: Reserved               */
 156         0x00,                   /* 0x3E: Reserved               */
 157         0x00                    /* 0x3F: Checksum               */
 158 };
 159
 160
 161 /***************************************************************************/
 162 static void waitForPause(unsigned amount)
 163 {
 164         ULONG the_time = jiffies + MS_TO_JIFFIES(amount);
 165         while (time_before_eq(jiffies, the_time))
 166                 cpu_relax();
 167 }
 168
 169 /***************************************************************************/
 170 static UCHAR waitChipReady(ORC_HCS * hcsp)
 171 {
 172         int i;
 173
 174         for (i = 0; i < 10; i++) {      /* Wait 1 second for report timeout     */
 175                 if (ORC_RD(hcsp->HCS_Base, ORC_HCTRL) & HOSTSTOP)       /* Wait HOSTSTOP set */
 176                         return 1;
 177                 waitForPause(100);      /* wait 100ms before try again  */
 178         }
 179         return 0;
 180 }
 181
 182 /***************************************************************************/
 183 static UCHAR waitFWReady(ORC_HCS * hcsp)
 184 {
 185         int i;
 186
 187         for (i = 0; i < 10; i++) {      /* Wait 1 second for report timeout     */
 188                 if (ORC_RD(hcsp->HCS_Base, ORC_HSTUS) & RREADY)         /* Wait READY set */
 189                         return 1;
 190                 waitForPause(100);      /* wait 100ms before try again  */
 191         }
 192         return 0;
 193 }
 194
 195 /***************************************************************************/
 196 static UCHAR waitSCSIRSTdone(ORC_HCS * hcsp)
 197 {
 198         int i;
 199
 200         for (i = 0; i < 10; i++) {      /* Wait 1 second for report timeout     */
 201                 if (!(ORC_RD(hcsp->HCS_Base, ORC_HCTRL) & SCSIRST))     /* Wait SCSIRST done */
 202                         return 1;
 203                 waitForPause(100);      /* wait 100ms before try again  */
 204         }
 205         return 0;
 206 }
 207
 208 /***************************************************************************/
 209 static UCHAR waitHDOoff(ORC_HCS * hcsp)
 210 {
 211         int i;
 212
 213         for (i = 0; i < 10; i++) {      /* Wait 1 second for report timeout     */
 214                 if (!(ORC_RD(hcsp->HCS_Base, ORC_HCTRL) & HDO))         /* Wait HDO off */
 215                         return 1;
 216                 waitForPause(100);      /* wait 100ms before try again  */
 217         }
 218         return 0;
 219 }
 220
 221 /***************************************************************************/
 222 static UCHAR waitHDIset(ORC_HCS * hcsp, UCHAR * pData)
 223 {
 224         int i;
 225
 226         for (i = 0; i < 10; i++) {      /* Wait 1 second for report timeout     */
 227                 if ((*pData = ORC_RD(hcsp->HCS_Base, ORC_HSTUS)) & HDI)
 228                         return 1;       /* Wait HDI set */
 229                 waitForPause(100);      /* wait 100ms before try again  */
 230         }
 231         return 0;
 232 }
 233
 234 /***************************************************************************/
 235 static unsigned short get_FW_version(ORC_HCS * hcsp)
 236 {
 237         UCHAR bData;
 238         union {
 239                 unsigned short sVersion;
 240                 unsigned char cVersion[2];
 241         } Version;
 242
 243         ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_VERSION);
 244         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 245         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 246                 return 0;
 247
 248         if (waitHDIset(hcsp, &bData) == 0)      /* Wait HDI set   */
 249                 return 0;
 250         Version.cVersion[0] = ORC_RD(hcsp->HCS_Base, ORC_HDATA);
 251         ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData);      /* Clear HDI            */
 252
 253         if (waitHDIset(hcsp, &bData) == 0)      /* Wait HDI set   */
 254                 return 0;
 255         Version.cVersion[1] = ORC_RD(hcsp->HCS_Base, ORC_HDATA);
 256         ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData);      /* Clear HDI            */
 257
 258         return (Version.sVersion);
 259 }
 260
 261 /***************************************************************************/
 262 static UCHAR set_NVRAM(ORC_HCS * hcsp, unsigned char address, unsigned char value)
 263 {
 264         ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_SET_NVM);    /* Write command */
 265         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 266         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 267                 return 0;
 268
 269         ORC_WR(hcsp->HCS_Base + ORC_HDATA, address);    /* Write address */
 270         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 271         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 272                 return 0;
 273
 274         ORC_WR(hcsp->HCS_Base + ORC_HDATA, value);      /* Write value  */
 275         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 276         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 277                 return 0;
 278
 279         return 1;
 280 }
 281
 282 /***************************************************************************/
 283 static UCHAR get_NVRAM(ORC_HCS * hcsp, unsigned char address, unsigned char *pDataIn)
 284 {
 285         unsigned char bData;
 286
 287         ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_GET_NVM);    /* Write command */
 288         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 289         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 290                 return 0;
 291
 292         ORC_WR(hcsp->HCS_Base + ORC_HDATA, address);    /* Write address */
 293         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 294         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 295                 return 0;
 296
 297         if (waitHDIset(hcsp, &bData) == 0)      /* Wait HDI set   */
 298                 return 0;
 299         *pDataIn = ORC_RD(hcsp->HCS_Base, ORC_HDATA);
 300         ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData);      /* Clear HDI    */
 301
 302         return 1;
 303 }
 304
 305 /***************************************************************************/
 306 static void orc_exec_scb(ORC_HCS * hcsp, ORC_SCB * scbp)
 307 {
 308         scbp->SCB_Status = ORCSCB_POST;
 309         ORC_WR(hcsp->HCS_Base + ORC_PQUEUE, scbp->SCB_ScbIdx);
 310         return;
 311 }
 312
 313
 314 /***********************************************************************
 315  Read SCSI H/A configuration parameters from serial EEPROM
 316 ************************************************************************/
 317 static int se2_rd_all(ORC_HCS * hcsp)
 318 {
 319         int i;
 320         UCHAR *np, chksum = 0;
 321
 322         np = (UCHAR *) nvramp;
 323         for (i = 0; i < 64; i++, np++) {        /* <01> */
 324                 if (get_NVRAM(hcsp, (unsigned char) i, np) == 0)
 325                         return -1;
 326 //      *np++ = get_NVRAM(hcsp, (unsigned char ) i);
 327         }
 328
 329 /*------ Is ckecksum ok ? ------*/
 330         np = (UCHAR *) nvramp;
 331         for (i = 0; i < 63; i++)
 332                 chksum += *np++;
 333
 334         if (nvramp->CheckSum != (UCHAR) chksum)
 335                 return -1;
 336         return 1;
 337 }
 338
 339 /************************************************************************
 340  Update SCSI H/A configuration parameters from serial EEPROM
 341 *************************************************************************/
 342 static void se2_update_all(ORC_HCS * hcsp)
 343 {                               /* setup default pattern  */
 344         int i;
 345         UCHAR *np, *np1, chksum = 0;
 346
 347         /* Calculate checksum first   */
 348         np = (UCHAR *) dftNvRam;
 349         for (i = 0; i < 63; i++)
 350                 chksum += *np++;
 351         *np = chksum;
 352
 353         np = (UCHAR *) dftNvRam;
 354         np1 = (UCHAR *) nvramp;
 355         for (i = 0; i < 64; i++, np++, np1++) {
 356                 if (*np != *np1) {
 357                         set_NVRAM(hcsp, (unsigned char) i, *np);
 358                 }
 359         }
 360         return;
 361 }
 362
 363 /*************************************************************************
 364  Function name  : read_eeprom
 365 **************************************************************************/
 366 static void read_eeprom(ORC_HCS * hcsp)
 367 {
 368         if (se2_rd_all(hcsp) != 1) {
 369                 se2_update_all(hcsp);   /* setup default pattern        */
 370                 se2_rd_all(hcsp);       /* load again                   */
 371         }
 372 }
 373
 374
 375 /***************************************************************************/
 376 static UCHAR load_FW(ORC_HCS * hcsp)
 377 {
 378         U32 dData;
 379         USHORT wBIOSAddress;
 380         USHORT i;
 381         UCHAR *pData, bData;
 382
 383
 384         bData = ORC_RD(hcsp->HCS_Base, ORC_GCFG);
 385         ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData | EEPRG);       /* Enable EEPROM programming */
 386         ORC_WR(hcsp->HCS_Base + ORC_EBIOSADR2, 0x00);
 387         ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x00);
 388         if (ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA) != 0x55) {
 389                 ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData);       /* Disable EEPROM programming */
 390                 return 0;
 391         }
 392         ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x01);
 393         if (ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA) != 0xAA) {
 394                 ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData);       /* Disable EEPROM programming */
 395                 return 0;
 396         }
 397         ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST | DOWNLOAD);       /* Enable SRAM programming */
 398         pData = (UCHAR *) & dData;
 399         dData = 0;              /* Initial FW address to 0 */
 400         ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x10);
 401         *pData = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA);         /* Read from BIOS */
 402         ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x11);
 403         *(pData + 1) = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA);   /* Read from BIOS */
 404         ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, 0x12);
 405         *(pData + 2) = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA);   /* Read from BIOS */
 406         ORC_WR(hcsp->HCS_Base + ORC_EBIOSADR2, *(pData + 2));
 407         ORC_WRLONG(hcsp->HCS_Base + ORC_FWBASEADR, dData);      /* Write FW address */
 408
 409         wBIOSAddress = (USHORT) dData;  /* FW code locate at BIOS address + ? */
 410         for (i = 0, pData = (UCHAR *) & dData;  /* Download the code    */
 411              i < 0x1000;        /* Firmware code size = 4K      */
 412              i++, wBIOSAddress++) {
 413                 ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, wBIOSAddress);
 414                 *pData++ = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA);       /* Read from BIOS */
 415                 if ((i % 4) == 3) {
 416                         ORC_WRLONG(hcsp->HCS_Base + ORC_RISCRAM, dData);        /* Write every 4 bytes */
 417                         pData = (UCHAR *) & dData;
 418                 }
 419         }
 420
 421         ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST | DOWNLOAD);       /* Reset program count 0 */
 422         wBIOSAddress -= 0x1000; /* Reset the BIOS adddress      */
 423         for (i = 0, pData = (UCHAR *) & dData;  /* Check the code       */
 424              i < 0x1000;        /* Firmware code size = 4K      */
 425              i++, wBIOSAddress++) {
 426                 ORC_WRSHORT(hcsp->HCS_Base + ORC_EBIOSADR0, wBIOSAddress);
 427                 *pData++ = ORC_RD(hcsp->HCS_Base, ORC_EBIOSDATA);       /* Read from BIOS */
 428                 if ((i % 4) == 3) {
 429                         if (ORC_RDLONG(hcsp->HCS_Base, ORC_RISCRAM) != dData) {
 430                                 ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST);  /* Reset program to 0 */
 431                                 ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData);       /*Disable EEPROM programming */
 432                                 return 0;
 433                         }
 434                         pData = (UCHAR *) & dData;
 435                 }
 436         }
 437         ORC_WR(hcsp->HCS_Base + ORC_RISCCTL, PRGMRST);  /* Reset program to 0   */
 438         ORC_WR(hcsp->HCS_Base + ORC_GCFG, bData);       /* Disable EEPROM programming */
 439         return 1;
 440 }
 441
 442 /***************************************************************************/
 443 static void setup_SCBs(ORC_HCS * hcsp)
 444 {
 445         ORC_SCB *pVirScb;
 446         int i;
 447         ESCB *pVirEscb;
 448         dma_addr_t pPhysEscb;
 449
 450         /* Setup SCB HCS_Base and SCB Size registers */
 451         ORC_WR(hcsp->HCS_Base + ORC_SCBSIZE, ORC_MAXQUEUE);     /* Total number of SCBs */
 452         /* SCB HCS_Base address 0      */
 453         ORC_WRLONG(hcsp->HCS_Base + ORC_SCBBASE0, hcsp->HCS_physScbArray);
 454         /* SCB HCS_Base address 1      */
 455         ORC_WRLONG(hcsp->HCS_Base + ORC_SCBBASE1, hcsp->HCS_physScbArray);
 456
 457         /* setup scatter list address with one buffer */
 458         pVirScb = hcsp->HCS_virScbArray;
 459         pVirEscb = hcsp->HCS_virEscbArray;
 460
 461         for (i = 0; i < ORC_MAXQUEUE; i++) {
 462                 pPhysEscb = (hcsp->HCS_physEscbArray + (sizeof(ESCB) * i));
 463                 pVirScb->SCB_SGPAddr = (U32) pPhysEscb;
 464                 pVirScb->SCB_SensePAddr = (U32) pPhysEscb;
 465                 pVirScb->SCB_EScb = pVirEscb;
 466                 pVirScb->SCB_ScbIdx = i;
 467                 pVirScb++;
 468                 pVirEscb++;
 469         }
 470
 471         return;
 472 }
 473
 474 /***************************************************************************/
 475 static void initAFlag(ORC_HCS * hcsp)
 476 {
 477         UCHAR i, j;
 478
 479         for (i = 0; i < MAX_CHANNELS; i++) {
 480                 for (j = 0; j < 8; j++) {
 481                         hcsp->BitAllocFlag[i][j] = 0xffffffff;
 482                 }
 483         }
 484 }
 485
 486 /***************************************************************************/
 487 static int init_orchid(ORC_HCS * hcsp)
 488 {
 489         UBYTE *readBytep;
 490         USHORT revision;
 491         UCHAR i;
 492
 493         initAFlag(hcsp);
 494         ORC_WR(hcsp->HCS_Base + ORC_GIMSK, 0xFF);       /* Disable all interrupt        */
 495         if (ORC_RD(hcsp->HCS_Base, ORC_HSTUS) & RREADY) {       /* Orchid is ready              */
 496                 revision = get_FW_version(hcsp);
 497                 if (revision == 0xFFFF) {
 498                         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, DEVRST);     /* Reset Host Adapter   */
 499                         if (waitChipReady(hcsp) == 0)
 500                                 return (-1);
 501                         load_FW(hcsp);  /* Download FW                  */
 502                         setup_SCBs(hcsp);       /* Setup SCB HCS_Base and SCB Size registers */
 503                         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, 0);  /* clear HOSTSTOP       */
 504                         if (waitFWReady(hcsp) == 0)
 505                                 return (-1);
 506                         /* Wait for firmware ready     */
 507                 } else {
 508                         setup_SCBs(hcsp);       /* Setup SCB HCS_Base and SCB Size registers */
 509                 }
 510         } else {                /* Orchid is not Ready          */
 511                 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, DEVRST);     /* Reset Host Adapter   */
 512                 if (waitChipReady(hcsp) == 0)
 513                         return (-1);
 514                 load_FW(hcsp);  /* Download FW                  */
 515                 setup_SCBs(hcsp);       /* Setup SCB HCS_Base and SCB Size registers */
 516                 ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);        /* Do Hardware Reset &  */
 517
 518                 /*     clear HOSTSTOP  */
 519                 if (waitFWReady(hcsp) == 0)             /* Wait for firmware ready      */
 520                         return (-1);
 521         }
 522
 523 /*------------- get serial EEProm settting -------*/
 524
 525         read_eeprom(hcsp);
 526
 527         if (nvramp->Revision != 1)
 528                 return (-1);
 529
 530         hcsp->HCS_SCSI_ID = nvramp->SCSI0Id;
 531         hcsp->HCS_BIOS = nvramp->BIOSConfig1;
 532         hcsp->HCS_MaxTar = MAX_TARGETS;
 533         readBytep = (UCHAR *) & (nvramp->Target00Config);
 534         for (i = 0; i < 16; readBytep++, i++) {
 535                 hcsp->TargetFlag[i] = *readBytep;
 536                 hcsp->MaximumTags[i] = ORC_MAXTAGS;
 537         }                       /* for                          */
 538
 539         if (nvramp->SCSI0Config & NCC_BUSRESET) {       /* Reset SCSI bus               */
 540                 hcsp->HCS_Flags |= HCF_SCSI_RESET;
 541         }
 542         ORC_WR(hcsp->HCS_Base + ORC_GIMSK, 0xFB);       /* enable RP FIFO interrupt     */
 543         return (0);
 544 }
 545
 546 /*****************************************************************************
 547  Function name  : orc_reset_scsi_bus
 548  Description    : Reset registers, reset a hanging bus and
 549                   kill active and disconnected commands for target w/o soft reset
 550  Input          : pHCB  -       Pointer to host adapter structure
 551  Output         : None.
 552  Return         : pSRB  -       Pointer to SCSI request block.
 553 *****************************************************************************/
 554 static int orc_reset_scsi_bus(ORC_HCS * pHCB)
 555 {                               /* I need Host Control Block Information */
 556         ULONG flags;
 557
 558         spin_lock_irqsave(&(pHCB->BitAllocFlagLock), flags);
 559
 560         initAFlag(pHCB);
 561         /* reset scsi bus */
 562         ORC_WR(pHCB->HCS_Base + ORC_HCTRL, SCSIRST);
 563         if (waitSCSIRSTdone(pHCB) == 0) {
 564                 spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags);
 565                 return FAILED;
 566         } else {
 567                 spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags);
 568                 return SUCCESS;
 569         }
 570 }
 571
 572 /*****************************************************************************
 573  Function name  : orc_device_reset
 574  Description    : Reset registers, reset a hanging bus and
 575                   kill active and disconnected commands for target w/o soft reset
 576  Input          : pHCB  -       Pointer to host adapter structure
 577  Output         : None.
 578  Return         : pSRB  -       Pointer to SCSI request block.
 579 *****************************************************************************/
 580 static int orc_device_reset(ORC_HCS * pHCB, struct scsi_cmnd *SCpnt, unsigned int target)
 581 {                               /* I need Host Control Block Information */
 582         ORC_SCB *pScb;
 583         ESCB *pVirEscb;
 584         ORC_SCB *pVirScb;
 585         UCHAR i;
 586         ULONG flags;
 587
 588         spin_lock_irqsave(&(pHCB->BitAllocFlagLock), flags);
 589         pScb = (ORC_SCB *) NULL;
 590         pVirEscb = (ESCB *) NULL;
 591
 592         /* setup scatter list address with one buffer */
 593         pVirScb = pHCB->HCS_virScbArray;
 594
 595         initAFlag(pHCB);
 596         /* device reset */
 597         for (i = 0; i < ORC_MAXQUEUE; i++) {
 598                 pVirEscb = pVirScb->SCB_EScb;
 599                 if ((pVirScb->SCB_Status) && (pVirEscb->SCB_Srb == SCpnt))
 600                         break;
 601                 pVirScb++;
 602         }
 603
 604         if (i == ORC_MAXQUEUE) {
 605                 printk("Unable to Reset - No SCB Found\n");
 606                 spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags);
 607                 return FAILED;
 608         }
 609         if ((pScb = orc_alloc_scb(pHCB)) == NULL) {
 610                 spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags);
 611                 return FAILED;
 612         }
 613         pScb->SCB_Opcode = ORC_BUSDEVRST;
 614         pScb->SCB_Target = target;
 615         pScb->SCB_HaStat = 0;
 616         pScb->SCB_TaStat = 0;
 617         pScb->SCB_Status = 0x0;
 618         pScb->SCB_Link = 0xFF;
 619         pScb->SCB_Reserved0 = 0;
 620         pScb->SCB_Reserved1 = 0;
 621         pScb->SCB_XferLen = 0;
 622         pScb->SCB_SGLen = 0;
 623
 624         pVirEscb->SCB_Srb = NULL;
 625         pVirEscb->SCB_Srb = SCpnt;
 626         orc_exec_scb(pHCB, pScb);       /* Start execute SCB            */
 627         spin_unlock_irqrestore(&(pHCB->BitAllocFlagLock), flags);
 628         return SUCCESS;
 629 }
 630
 631
 632 /***************************************************************************/
 633 static ORC_SCB *__orc_alloc_scb(ORC_HCS * hcsp)
 634 {
 635         ORC_SCB *pTmpScb;
 636         UCHAR Ch;
 637         ULONG idx;
 638         UCHAR index;
 639         UCHAR i;
 640
 641         Ch = hcsp->HCS_Index;
 642         for (i = 0; i < 8; i++) {
 643                 for (index = 0; index < 32; index++) {
 644                         if ((hcsp->BitAllocFlag[Ch][i] >> index) & 0x01) {
 645                                 hcsp->BitAllocFlag[Ch][i] &= ~(1 << index);
 646                                 break;
 647                         }
 648                 }
 649                 idx = index + 32 * i;
 650                 pTmpScb = (ORC_SCB *) ((ULONG) hcsp->HCS_virScbArray + (idx * sizeof(ORC_SCB)));
 651                 return (pTmpScb);
 652         }
 653         return (NULL);
 654 }
 655
 656 static ORC_SCB *orc_alloc_scb(ORC_HCS * hcsp)
 657 {
 658         ORC_SCB *pTmpScb;
 659         ULONG flags;
 660
 661         spin_lock_irqsave(&(hcsp->BitAllocFlagLock), flags);
 662         pTmpScb = __orc_alloc_scb(hcsp);
 663         spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags);
 664         return (pTmpScb);
 665 }
 666
 667
 668 /***************************************************************************/
 669 static void orc_release_scb(ORC_HCS * hcsp, ORC_SCB * scbp)
 670 {
 671         ULONG flags;
 672         UCHAR Index;
 673         UCHAR i;
 674         UCHAR Ch;
 675
 676         spin_lock_irqsave(&(hcsp->BitAllocFlagLock), flags);
 677         Ch = hcsp->HCS_Index;
 678         Index = scbp->SCB_ScbIdx;
 679         i = Index / 32;
 680         Index %= 32;
 681         hcsp->BitAllocFlag[Ch][i] |= (1 << Index);
 682         spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags);
 683 }
 684
 685 /*****************************************************************************
 686  Function name  : abort_SCB
 687  Description    : Abort a queued command.
 688                          (commands that are on the bus can't be aborted easily)
 689  Input          : pHCB  -       Pointer to host adapter structure
 690  Output         : None.
 691  Return         : pSRB  -       Pointer to SCSI request block.
 692 *****************************************************************************/
 693 static int abort_SCB(ORC_HCS * hcsp, ORC_SCB * pScb)
 694 {
 695         unsigned char bData, bStatus;
 696
 697         ORC_WR(hcsp->HCS_Base + ORC_HDATA, ORC_CMD_ABORT_SCB);  /* Write command */
 698         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 699         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 700                 return 0;
 701
 702         ORC_WR(hcsp->HCS_Base + ORC_HDATA, pScb->SCB_ScbIdx);   /* Write address */
 703         ORC_WR(hcsp->HCS_Base + ORC_HCTRL, HDO);
 704         if (waitHDOoff(hcsp) == 0)      /* Wait HDO off   */
 705                 return 0;
 706
 707         if (waitHDIset(hcsp, &bData) == 0)      /* Wait HDI set   */
 708                 return 0;
 709         bStatus = ORC_RD(hcsp->HCS_Base, ORC_HDATA);
 710         ORC_WR(hcsp->HCS_Base + ORC_HSTUS, bData);      /* Clear HDI    */
 711
 712         if (bStatus == 1)       /* 0 - Successfully               */
 713                 return 0;       /* 1 - Fail                     */
 714         return 1;
 715 }
 716
 717 /*****************************************************************************
 718  Function name  : inia100_abort
 719  Description    : Abort a queued command.
 720                          (commands that are on the bus can't be aborted easily)
 721  Input          : pHCB  -       Pointer to host adapter structure
 722  Output         : None.
 723  Return         : pSRB  -       Pointer to SCSI request block.
 724 *****************************************************************************/
 725 static int orc_abort_srb(ORC_HCS * hcsp, struct scsi_cmnd *SCpnt)
 726 {
 727         ESCB *pVirEscb;
 728         ORC_SCB *pVirScb;
 729         UCHAR i;
 730         ULONG flags;
 731
 732         spin_lock_irqsave(&(hcsp->BitAllocFlagLock), flags);
 733
 734         pVirScb = hcsp->HCS_virScbArray;
 735
 736         for (i = 0; i < ORC_MAXQUEUE; i++, pVirScb++) {
 737                 pVirEscb = pVirScb->SCB_EScb;
 738                 if ((pVirScb->SCB_Status) && (pVirEscb->SCB_Srb == SCpnt)) {
 739                         if (pVirScb->SCB_TagMsg == 0) {
 740                                 spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags);
 741                                 return FAILED;
 742                         } else {
 743                                 if (abort_SCB(hcsp, pVirScb)) {
 744                                         pVirEscb->SCB_Srb = NULL;
 745                                         spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags);
 746                                         return SUCCESS;
 747                                 } else {
 748                                         spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags);
 749                                         return FAILED;
 750                                 }
 751                         }
 752                 }
 753         }
 754         spin_unlock_irqrestore(&(hcsp->BitAllocFlagLock), flags);
 755         return FAILED;
 756 }
 757
 758 /***********************************************************************
 759  Routine Description:
 760           This is the interrupt service routine for the Orchid SCSI adapter.
 761           It reads the interrupt register to determine if the adapter is indeed
 762           the source of the interrupt and clears the interrupt at the device.
 763  Arguments:
 764           HwDeviceExtension - HBA miniport driver's adapter data storage
 765  Return Value:
 766 ***********************************************************************/
 767 static void orc_interrupt(
 768                           ORC_HCS * hcsp
 769 )
 770 {
 771         BYTE bScbIdx;
 772         ORC_SCB *pScb;
 773
 774         if (ORC_RD(hcsp->HCS_Base, ORC_RQUEUECNT) == 0) {
 775                 return;         // 0;
 776
 777         }
 778         do {
 779                 bScbIdx = ORC_RD(hcsp->HCS_Base, ORC_RQUEUE);
 780
 781                 pScb = (ORC_SCB *) ((ULONG) hcsp->HCS_virScbArray + (ULONG) (sizeof(ORC_SCB) * bScbIdx));
 782                 pScb->SCB_Status = 0x0;
 783
 784                 inia100SCBPost((BYTE *) hcsp, (BYTE *) pScb);
 785         } while (ORC_RD(hcsp->HCS_Base, ORC_RQUEUECNT));
 786         return;                 //1;
 787
 788 }                               /* End of I1060Interrupt() */
 789
 790 /*****************************************************************************
 791  Function name  : inia100BuildSCB
 792  Description    :
 793  Input          : pHCB  -       Pointer to host adapter structure
 794  Output         : None.
 795  Return         : pSRB  -       Pointer to SCSI request block.
 796 *****************************************************************************/
 797 static void inia100BuildSCB(ORC_HCS * pHCB, ORC_SCB * pSCB, struct scsi_cmnd * SCpnt)
 798 {                               /* Create corresponding SCB     */
 799         struct scatterlist *sg;
 800         ORC_SG *pSG;            /* Pointer to SG list           */
 801         int i, count_sg;
 802         ESCB *pEScb;
 803
 804         pEScb = pSCB->SCB_EScb;
 805         pEScb->SCB_Srb = SCpnt;
 806         pSG = NULL;
 807
 808         pSCB->SCB_Opcode = ORC_EXECSCSI;
 809         pSCB->SCB_Flags = SCF_NO_DCHK;  /* Clear done bit               */
 810         pSCB->SCB_Target = SCpnt->device->id;
 811         pSCB->SCB_Lun = SCpnt->device->lun;
 812         pSCB->SCB_Reserved0 = 0;
 813         pSCB->SCB_Reserved1 = 0;
 814         pSCB->SCB_SGLen = 0;
 815
 816         pSCB->SCB_XferLen = (U32) scsi_bufflen(SCpnt);
 817         pSG = (ORC_SG *) & pEScb->ESCB_SGList[0];
 818
 819         count_sg = scsi_dma_map(SCpnt);
 820         BUG_ON(count_sg < 0);
 821         if (count_sg) {
 822                 pSCB->SCB_SGLen = (U32) (count_sg * 8);
 823                 scsi_for_each_sg(SCpnt, sg, count_sg, i) {
 824                         pSG->SG_Ptr = (U32) sg_dma_address(sg);
 825                         pSG->SG_Len = (U32) sg_dma_len(sg);
 826                         pSG++;
 827                 }
 828         } else {
 829                 pSCB->SCB_SGLen = 0;
 830                 pSG->SG_Ptr = 0;
 831                 pSG->SG_Len = 0;
 832         }
 833         pSCB->SCB_SGPAddr = (U32) pSCB->SCB_SensePAddr;
 834         pSCB->SCB_HaStat = 0;
 835         pSCB->SCB_TaStat = 0;
 836         pSCB->SCB_Link = 0xFF;
 837         pSCB->SCB_SenseLen = SENSE_SIZE;
 838         pSCB->SCB_CDBLen = SCpnt->cmd_len;
 839         if (pSCB->SCB_CDBLen >= IMAX_CDB) {
 840                 printk("max cdb length= %x\b", SCpnt->cmd_len);
 841                 pSCB->SCB_CDBLen = IMAX_CDB;
 842         }
 843         pSCB->SCB_Ident = SCpnt->device->lun | DISC_ALLOW;
 844         if (SCpnt->device->tagged_supported) {  /* Tag Support                  */
 845                 pSCB->SCB_TagMsg = SIMPLE_QUEUE_TAG;    /* Do simple tag only   */
 846         } else {
 847                 pSCB->SCB_TagMsg = 0;   /* No tag support               */
 848         }
 849         memcpy(&pSCB->SCB_CDB[0], &SCpnt->cmnd, pSCB->SCB_CDBLen);
 850         return;
 851 }
 852
 853 /*****************************************************************************
 854  Function name  : inia100_queue
 855  Description    : Queue a command and setup interrupts for a free bus.
 856  Input          : pHCB  -       Pointer to host adapter structure
 857  Output         : None.
 858  Return         : pSRB  -       Pointer to SCSI request block.
 859 *****************************************************************************/
 860 static int inia100_queue(struct scsi_cmnd * SCpnt, void (*done) (struct scsi_cmnd *))
 861 {
 862         register ORC_SCB *pSCB;
 863         ORC_HCS *pHCB;          /* Point to Host adapter control block */
 864
 865         pHCB = (ORC_HCS *) SCpnt->device->host->hostdata;
 866         SCpnt->scsi_done = done;
 867         /* Get free SCSI control block  */
 868         if ((pSCB = orc_alloc_scb(pHCB)) == NULL)
 869                 return SCSI_MLQUEUE_HOST_BUSY;
 870
 871         inia100BuildSCB(pHCB, pSCB, SCpnt);
 872         orc_exec_scb(pHCB, pSCB);       /* Start execute SCB            */
 873
 874         return (0);
 875 }
 876
 877 /*****************************************************************************
 878  Function name  : inia100_abort
 879  Description    : Abort a queued command.
 880                          (commands that are on the bus can't be aborted easily)
 881  Input          : pHCB  -       Pointer to host adapter structure
 882  Output         : None.
 883  Return         : pSRB  -       Pointer to SCSI request block.
 884 *****************************************************************************/
 885 static int inia100_abort(struct scsi_cmnd * SCpnt)
 886 {
 887         ORC_HCS *hcsp;
 888
 889         hcsp = (ORC_HCS *) SCpnt->device->host->hostdata;
 890         return orc_abort_srb(hcsp, SCpnt);
 891 }
 892
 893 /*****************************************************************************
 894  Function name  : inia100_reset
 895  Description    : Reset registers, reset a hanging bus and
 896                   kill active and disconnected commands for target w/o soft reset
 897  Input          : pHCB  -       Pointer to host adapter structure
 898  Output         : None.
 899  Return         : pSRB  -       Pointer to SCSI request block.
 900 *****************************************************************************/
 901 static int inia100_bus_reset(struct scsi_cmnd * SCpnt)
 902 {                               /* I need Host Control Block Information */
 903         ORC_HCS *pHCB;
 904         pHCB = (ORC_HCS *) SCpnt->device->host->hostdata;
 905         return orc_reset_scsi_bus(pHCB);
 906 }
 907
 908 /*****************************************************************************
 909  Function name  : inia100_device_reset
 910  Description    : Reset the device
 911  Input          : pHCB  -       Pointer to host adapter structure
 912  Output         : None.
 913  Return         : pSRB  -       Pointer to SCSI request block.
 914 *****************************************************************************/
 915 static int inia100_device_reset(struct scsi_cmnd * SCpnt)
 916 {                               /* I need Host Control Block Information */
 917         ORC_HCS *pHCB;
 918         pHCB = (ORC_HCS *) SCpnt->device->host->hostdata;
 919         return orc_device_reset(pHCB, SCpnt, scmd_id(SCpnt));
 920
 921 }
 922
 923 /*****************************************************************************
 924  Function name  : inia100SCBPost
 925  Description    : This is callback routine be called when orc finish one
 926                         SCSI command.
 927  Input          : pHCB  -       Pointer to host adapter control block.
 928                   pSCB  -       Pointer to SCSI control block.
 929  Output         : None.
 930  Return         : None.
 931 *****************************************************************************/
 932 static void inia100SCBPost(BYTE * pHcb, BYTE * pScb)
 933 {
 934         struct scsi_cmnd *pSRB; /* Pointer to SCSI request block */
 935         ORC_HCS *pHCB;
 936         ORC_SCB *pSCB;
 937         ESCB *pEScb;
 938
 939         pHCB = (ORC_HCS *) pHcb;
 940         pSCB = (ORC_SCB *) pScb;
 941         pEScb = pSCB->SCB_EScb;
 942         if ((pSRB = (struct scsi_cmnd *) pEScb->SCB_Srb) == 0) {
 943                 printk("inia100SCBPost: SRB pointer is empty\n");
 944                 orc_release_scb(pHCB, pSCB);    /* Release SCB for current channel */
 945                 return;
 946         }
 947         pEScb->SCB_Srb = NULL;
 948
 949         switch (pSCB->SCB_HaStat) {
 950         case 0x0:
 951         case 0xa:               /* Linked command complete without error and linked normally */
 952         case 0xb:               /* Linked command complete without error interrupt generated */
 953                 pSCB->SCB_HaStat = 0;
 954                 break;
 955
 956         case 0x11:              /* Selection time out-The initiator selection or target
 957                                    reselection was not complete within the SCSI Time out period */
 958                 pSCB->SCB_HaStat = DID_TIME_OUT;
 959                 break;
 960
 961         case 0x14:              /* Target bus phase sequence failure-An invalid bus phase or bus
 962                                    phase sequence was requested by the target. The host adapter
 963                                    will generate a SCSI Reset Condition, notifying the host with
 964                                    a SCRD interrupt */
 965                 pSCB->SCB_HaStat = DID_RESET;
 966                 break;
 967
 968         case 0x1a:              /* SCB Aborted. 07/21/98 */
 969                 pSCB->SCB_HaStat = DID_ABORT;
 970                 break;
 971
 972         case 0x12:              /* Data overrun/underrun-The target attempted to transfer more data
 973                                    than was allocated by the Data Length field or the sum of the
 974                                    Scatter / Gather Data Length fields. */
 975         case 0x13:              /* Unexpected bus free-The target dropped the SCSI BSY at an unexpected time. */
 976         case 0x16:              /* Invalid CCB Operation Code-The first byte of the CCB was invalid. */
 977
 978         default:
 979                 printk("inia100: %x %x\n", pSCB->SCB_HaStat, pSCB->SCB_TaStat);
 980                 pSCB->SCB_HaStat = DID_ERROR;   /* Couldn't find any better */
 981                 break;
 982         }
 983
 984         if (pSCB->SCB_TaStat == 2) {    /* Check condition              */
 985                 memcpy((unsigned char *) &pSRB->sense_buffer[0],
 986                    (unsigned char *) &pEScb->ESCB_SGList[0], SENSE_SIZE);
 987         }
 988         pSRB->result = pSCB->SCB_TaStat | (pSCB->SCB_HaStat << 16);
 989
 990         scsi_dma_unmap(pSRB);
 991
 992         pSRB->scsi_done(pSRB);  /* Notify system DONE           */
 993
 994         orc_release_scb(pHCB, pSCB);    /* Release SCB for current channel */
 995 }
 996
 997 /*
 998  * Interrupt handler (main routine of the driver)
 999  */
1000 static irqreturn_t inia100_intr(int irqno, void *devid)
1001 {
1002         struct Scsi_Host *host = (struct Scsi_Host *)devid;
1003         ORC_HCS *pHcb = (ORC_HCS *)host->hostdata;
1004         unsigned long flags;
1005
1006         spin_lock_irqsave(host->host_lock, flags);
1007         orc_interrupt(pHcb);
1008         spin_unlock_irqrestore(host->host_lock, flags);
1009
1010         return IRQ_HANDLED;
1011 }
1012
1013 static struct scsi_host_template inia100_template = {
1014         .proc_name              = "inia100",
1015         .name                   = inia100_REVID,
1016         .queuecommand           = inia100_queue,
1017         .eh_abort_handler       = inia100_abort,
1018         .eh_bus_reset_handler   = inia100_bus_reset,
1019         .eh_device_reset_handler = inia100_device_reset,
1020         .can_queue              = 1,
1021         .this_id                = 1,
1022         .sg_tablesize           = SG_ALL,
1023         .cmd_per_lun            = 1,
1024         .use_clustering         = ENABLE_CLUSTERING,
1025 };
1026
1027 static int __devinit inia100_probe_one(struct pci_dev *pdev,
1028                 const struct pci_device_id *id)
1029 {
1030         struct Scsi_Host *shost;
1031         ORC_HCS *pHCB;
1032         unsigned long port, bios;
1033         int error = -ENODEV;
1034         u32 sz;
1035         unsigned long dBiosAdr;
1036         char *pbBiosAdr;
1037
1038         if (pci_enable_device(pdev))
1039                 goto out;
1040         if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1041                 printk(KERN_WARNING "Unable to set 32bit DMA "
1042                                     "on inia100 adapter, ignoring.\n");
1043                 goto out_disable_device;
1044         }
1045
1046         pci_set_master(pdev);
1047
1048         port = pci_resource_start(pdev, 0);
1049         if (!request_region(port, 256, "inia100")) {
1050                 printk(KERN_WARNING "inia100: io port 0x%lx, is busy.\n", port);
1051                 goto out_disable_device;
1052         }
1053
1054         /* <02> read from base address + 0x50 offset to get the bios value. */
1055         bios = ORC_RDWORD(port, 0x50);
1056
1057
1058         shost = scsi_host_alloc(&inia100_template, sizeof(ORC_HCS));
1059         if (!shost)
1060                 goto out_release_region;
1061
1062         pHCB = (ORC_HCS *)shost->hostdata;
1063         pHCB->pdev = pdev;
1064         pHCB->HCS_Base = port;
1065         pHCB->HCS_BIOS = bios;
1066         spin_lock_init(&pHCB->BitAllocFlagLock);
1067
1068         /* Get total memory needed for SCB */
1069         sz = ORC_MAXQUEUE * sizeof(ORC_SCB);
1070         pHCB->HCS_virScbArray = pci_alloc_consistent(pdev, sz,
1071                         &pHCB->HCS_physScbArray);
1072         if (!pHCB->HCS_virScbArray) {
1073                 printk("inia100: SCB memory allocation error\n");
1074                 goto out_host_put;
1075         }
1076         memset(pHCB->HCS_virScbArray, 0, sz);
1077
1078         /* Get total memory needed for ESCB */
1079         sz = ORC_MAXQUEUE * sizeof(ESCB);
1080         pHCB->HCS_virEscbArray = pci_alloc_consistent(pdev, sz,
1081                         &pHCB->HCS_physEscbArray);
1082         if (!pHCB->HCS_virEscbArray) {
1083                 printk("inia100: ESCB memory allocation error\n");
1084                 goto out_free_scb_array;
1085         }
1086         memset(pHCB->HCS_virEscbArray, 0, sz);
1087
1088         dBiosAdr = pHCB->HCS_BIOS;
1089         dBiosAdr = (dBiosAdr << 4);
1090         pbBiosAdr = phys_to_virt(dBiosAdr);
1091         if (init_orchid(pHCB)) {        /* Initialize orchid chip */
1092                 printk("inia100: initial orchid fail!!\n");
1093                 goto out_free_escb_array;
1094         }
1095
1096         shost->io_port = pHCB->HCS_Base;
1097         shost->n_io_port = 0xff;
1098         shost->can_queue = ORC_MAXQUEUE;
1099         shost->unique_id = shost->io_port;
1100         shost->max_id = pHCB->HCS_MaxTar;
1101         shost->max_lun = 16;
1102         shost->irq = pHCB->HCS_Intr = pdev->irq;
1103         shost->this_id = pHCB->HCS_SCSI_ID;     /* Assign HCS index */
1104         shost->sg_tablesize = TOTAL_SG_ENTRY;
1105
1106         /* Initial orc chip           */
1107         error = request_irq(pdev->irq, inia100_intr, IRQF_SHARED,
1108                         "inia100", shost);
1109         if (error < 0) {
1110                 printk(KERN_WARNING "inia100: unable to get irq %d\n",
1111                                 pdev->irq);
1112                 goto out_free_escb_array;
1113         }
1114
1115         pci_set_drvdata(pdev, shost);
1116
1117         error = scsi_add_host(shost, &pdev->dev);
1118         if (error)
1119                 goto out_free_irq;
1120
1121         scsi_scan_host(shost);
1122         return 0;
1123
1124  out_free_irq:
1125         free_irq(shost->irq, shost);
1126  out_free_escb_array:
1127         pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(ESCB),
1128                         pHCB->HCS_virEscbArray, pHCB->HCS_physEscbArray);
1129  out_free_scb_array:
1130         pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(ORC_SCB),
1131                         pHCB->HCS_virScbArray, pHCB->HCS_physScbArray);
1132  out_host_put:
1133         scsi_host_put(shost);
1134  out_release_region:
1135         release_region(port, 256);
1136  out_disable_device:
1137         pci_disable_device(pdev);
1138  out:
1139         return error;
1140 }
1141
1142 static void __devexit inia100_remove_one(struct pci_dev *pdev)
1143 {
1144         struct Scsi_Host *shost = pci_get_drvdata(pdev);
1145         ORC_HCS *pHCB = (ORC_HCS *)shost->hostdata;
1146
1147         scsi_remove_host(shost);
1148
1149         free_irq(shost->irq, shost);
1150         pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(ESCB),
1151                         pHCB->HCS_virEscbArray, pHCB->HCS_physEscbArray);
1152         pci_free_consistent(pdev, ORC_MAXQUEUE * sizeof(ORC_SCB),
1153                         pHCB->HCS_virScbArray, pHCB->HCS_physScbArray);
1154         release_region(shost->io_port, 256);
1155
1156         scsi_host_put(shost);
1157 }
1158
1159 static struct pci_device_id inia100_pci_tbl[] = {
1160         {PCI_VENDOR_ID_INIT, 0x1060, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1161         {0,}
1162 };
1163 MODULE_DEVICE_TABLE(pci, inia100_pci_tbl);
1164
1165 static struct pci_driver inia100_pci_driver = {
1166         .name           = "inia100",
1167         .id_table       = inia100_pci_tbl,
1168         .probe          = inia100_probe_one,
1169         .remove         = __devexit_p(inia100_remove_one),
1170 };
1171
1172 static int __init inia100_init(void)
1173 {
1174         return pci_register_driver(&inia100_pci_driver);
1175 }
1176
1177 static void __exit inia100_exit(void)
1178 {
1179         pci_unregister_driver(&inia100_pci_driver);
1180 }
1181
1182 MODULE_DESCRIPTION("Initio A100U2W SCSI driver");
1183 MODULE_AUTHOR("Initio Corporation");
1184 MODULE_LICENSE("Dual BSD/GPL");
1185
1186 module_init(inia100_init);
1187 module_exit(inia100_exit);