2 * Tsi721 PCIExpress-to-SRIO bridge definitions
4 * Copyright 2011, Integrated Device Technology, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc., 59
18 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 #define DRV_NAME "tsi721"
26 #define DEFAULT_HOPCOUNT 0xff
27 #define DEFAULT_DESTID 0xff
30 #define PCI_DEVICE_ID_TSI721 0x80ab
37 #define TSI721_PC2SR_BARS 2
38 #define TSI721_PC2SR_WINS 8
39 #define TSI721_PC2SR_ZONES 8
40 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
41 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
42 #define IDB_QSIZE 512 /* Inbound Doorbell Queue size */
44 /* Memory space sizes */
45 #define TSI721_REG_SPACE_SIZE (512 * 1024) /* 512K */
46 #define TSI721_DB_WIN_SIZE (16 * 1024 * 1024) /* 16MB */
48 #define RIO_TT_CODE_8 0x00000000
49 #define RIO_TT_CODE_16 0x00000001
51 #define TSI721_DMA_MAXCH 8
52 #define TSI721_DMA_MINSTSSZ 32
53 #define TSI721_DMA_STSBLKSZ 8
55 #define TSI721_SRIO_MAXCH 8
57 #define DBELL_SID(buf) (((u8)buf[2] << 8) | (u8)buf[3])
58 #define DBELL_TID(buf) (((u8)buf[4] << 8) | (u8)buf[5])
59 #define DBELL_INF(buf) (((u8)buf[0] << 8) | (u8)buf[1])
61 #define TSI721_RIO_PW_MSG_SIZE 16 /* Tsi721 saves only 16 bytes of PW msg */
63 /* Register definitions */
66 * Registers in PCIe configuration space
69 #define TSI721_PCIECFG_MSIXTBL 0x0a4
70 #define TSI721_MSIXTBL_OFFSET 0x2c000
71 #define TSI721_PCIECFG_MSIXPBA 0x0a8
72 #define TSI721_MSIXPBA_OFFSET 0x2a000
73 #define TSI721_PCIECFG_EPCTL 0x400
76 * Event Management Registers
79 #define TSI721_RIO_EM_INT_STAT 0x10910
80 #define TSI721_RIO_EM_INT_STAT_PW_RX 0x00010000
82 #define TSI721_RIO_EM_INT_ENABLE 0x10914
83 #define TSI721_RIO_EM_INT_ENABLE_PW_RX 0x00010000
85 #define TSI721_RIO_EM_DEV_INT_EN 0x10930
86 #define TSI721_RIO_EM_DEV_INT_EN_INT 0x00000001
89 * Port-Write Block Registers
92 #define TSI721_RIO_PW_CTL 0x10a04
93 #define TSI721_RIO_PW_CTL_PW_TIMER 0xf0000000
94 #define TSI721_RIO_PW_CTL_PWT_DIS (0 << 28)
95 #define TSI721_RIO_PW_CTL_PWT_103 (1 << 28)
96 #define TSI721_RIO_PW_CTL_PWT_205 (1 << 29)
97 #define TSI721_RIO_PW_CTL_PWT_410 (1 << 30)
98 #define TSI721_RIO_PW_CTL_PWT_820 (1 << 31)
99 #define TSI721_RIO_PW_CTL_PWC_MODE 0x01000000
100 #define TSI721_RIO_PW_CTL_PWC_CONT 0x00000000
101 #define TSI721_RIO_PW_CTL_PWC_REL 0x01000000
103 #define TSI721_RIO_PW_RX_STAT 0x10a10
104 #define TSI721_RIO_PW_RX_STAT_WR_SIZE 0x0000f000
105 #define TSI_RIO_PW_RX_STAT_WDPTR 0x00000100
106 #define TSI721_RIO_PW_RX_STAT_PW_SHORT 0x00000008
107 #define TSI721_RIO_PW_RX_STAT_PW_TRUNC 0x00000004
108 #define TSI721_RIO_PW_RX_STAT_PW_DISC 0x00000002
109 #define TSI721_RIO_PW_RX_STAT_PW_VAL 0x00000001
111 #define TSI721_RIO_PW_RX_CAPT(x) (0x10a20 + (x)*4)
117 #define TSI721_IDB_ENTRY_SIZE 64
119 #define TSI721_IDQ_CTL(x) (0x20000 + (x) * 1000)
120 #define TSI721_IDQ_SUSPEND 0x00000002
121 #define TSI721_IDQ_INIT 0x00000001
123 #define TSI721_IDQ_STS(x) (0x20004 + (x) * 1000)
124 #define TSI721_IDQ_RUN 0x00200000
126 #define TSI721_IDQ_MASK(x) (0x20008 + (x) * 1000)
127 #define TSI721_IDQ_MASK_MASK 0xffff0000
128 #define TSI721_IDQ_MASK_PATT 0x0000ffff
130 #define TSI721_IDQ_RP(x) (0x2000c + (x) * 1000)
131 #define TSI721_IDQ_RP_PTR 0x0007ffff
133 #define TSI721_IDQ_WP(x) (0x20010 + (x) * 1000)
134 #define TSI721_IDQ_WP_PTR 0x0007ffff
136 #define TSI721_IDQ_BASEL(x) (0x20014 + (x) * 1000)
137 #define TSI721_IDQ_BASEL_ADDR 0xffffffc0
138 #define TSI721_IDQ_BASEU(x) (0x20018 + (x) * 1000)
139 #define TSI721_IDQ_SIZE(x) (0x2001c + (x) * 1000)
140 #define TSI721_IDQ_SIZE_VAL(size) (__fls(size) - 4)
141 #define TSI721_IDQ_SIZE_MIN 512
142 #define TSI721_IDQ_SIZE_MAX (512 * 1024)
144 #define TSI721_SR_CHINT(x) (0x20040 + (x) * 1000)
145 #define TSI721_SR_CHINTE(x) (0x20044 + (x) * 1000)
146 #define TSI721_SR_CHINTSET(x) (0x20048 + (x) * 1000)
147 #define TSI721_SR_CHINT_ODBOK 0x00000020
148 #define TSI721_SR_CHINT_IDBQRCV 0x00000010
149 #define TSI721_SR_CHINT_SUSP 0x00000008
150 #define TSI721_SR_CHINT_ODBTO 0x00000004
151 #define TSI721_SR_CHINT_ODBRTRY 0x00000002
152 #define TSI721_SR_CHINT_ODBERR 0x00000001
153 #define TSI721_SR_CHINT_ALL 0x0000003f
155 #define TSI721_IBWIN_NUM 8
157 #define TSI721_IBWINLB(x) (0x29000 + (x) * 20)
158 #define TSI721_IBWINLB_BA 0xfffff000
159 #define TSI721_IBWINLB_WEN 0x00000001
161 #define TSI721_SR2PC_GEN_INTE 0x29800
162 #define TSI721_SR2PC_PWE 0x29804
163 #define TSI721_SR2PC_GEN_INT 0x29808
165 #define TSI721_DEV_INTE 0x29840
166 #define TSI721_DEV_INT 0x29844
167 #define TSI721_DEV_INTSET 0x29848
168 #define TSI721_DEV_INT_SMSG_CH 0x00000800
169 #define TSI721_DEV_INT_SMSG_NCH 0x00000400
170 #define TSI721_DEV_INT_SR2PC_CH 0x00000200
171 #define TSI721_DEV_INT_SRIO 0x00000020
173 #define TSI721_DEV_CHAN_INTE 0x2984c
174 #define TSI721_DEV_CHAN_INT 0x29850
176 #define TSI721_INT_SR2PC_CHAN_M 0xff000000
177 #define TSI721_INT_SR2PC_CHAN(x) (1 << (24 + (x)))
178 #define TSI721_INT_IMSG_CHAN_M 0x00ff0000
179 #define TSI721_INT_IMSG_CHAN(x) (1 << (16 + (x)))
180 #define TSI721_INT_OMSG_CHAN_M 0x0000ff00
181 #define TSI721_INT_OMSG_CHAN(x) (1 << (8 + (x)))
184 * PC2SR block registers
186 #define TSI721_OBWIN_NUM TSI721_PC2SR_WINS
188 #define TSI721_OBWINLB(x) (0x40000 + (x) * 20)
189 #define TSI721_OBWINLB_BA 0xffff8000
190 #define TSI721_OBWINLB_WEN 0x00000001
192 #define TSI721_OBWINUB(x) (0x40004 + (x) * 20)
194 #define TSI721_OBWINSZ(x) (0x40008 + (x) * 20)
195 #define TSI721_OBWINSZ_SIZE 0x00001f00
196 #define TSI721_OBWIN_SIZE(size) (__fls(size) - 15)
198 #define TSI721_ZONE_SEL 0x41300
199 #define TSI721_ZONE_SEL_RD_WRB 0x00020000
200 #define TSI721_ZONE_SEL_GO 0x00010000
201 #define TSI721_ZONE_SEL_WIN 0x00000038
202 #define TSI721_ZONE_SEL_ZONE 0x00000007
204 #define TSI721_LUT_DATA0 0x41304
205 #define TSI721_LUT_DATA0_ADD 0xfffff000
206 #define TSI721_LUT_DATA0_RDTYPE 0x00000f00
207 #define TSI721_LUT_DATA0_NREAD 0x00000100
208 #define TSI721_LUT_DATA0_MNTRD 0x00000200
209 #define TSI721_LUT_DATA0_RDCRF 0x00000020
210 #define TSI721_LUT_DATA0_WRCRF 0x00000010
211 #define TSI721_LUT_DATA0_WRTYPE 0x0000000f
212 #define TSI721_LUT_DATA0_NWR 0x00000001
213 #define TSI721_LUT_DATA0_MNTWR 0x00000002
214 #define TSI721_LUT_DATA0_NWR_R 0x00000004
216 #define TSI721_LUT_DATA1 0x41308
218 #define TSI721_LUT_DATA2 0x4130c
219 #define TSI721_LUT_DATA2_HC 0xff000000
220 #define TSI721_LUT_DATA2_ADD65 0x000c0000
221 #define TSI721_LUT_DATA2_TT 0x00030000
222 #define TSI721_LUT_DATA2_DSTID 0x0000ffff
224 #define TSI721_PC2SR_INTE 0x41310
226 #define TSI721_DEVCTL 0x48004
227 #define TSI721_DEVCTL_SRBOOT_CMPL 0x00000004
229 #define TSI721_I2C_INT_ENABLE 0x49120
232 * Block DMA Engine Registers
236 #define TSI721_DMAC_DWRCNT(x) (0x51000 + (x) * 0x1000)
237 #define TSI721_DMAC_DRDCNT(x) (0x51004 + (x) * 0x1000)
239 #define TSI721_DMAC_CTL(x) (0x51008 + (x) * 0x1000)
240 #define TSI721_DMAC_CTL_SUSP 0x00000002
241 #define TSI721_DMAC_CTL_INIT 0x00000001
243 #define TSI721_DMAC_INT(x) (0x5100c + (x) * 0x1000)
244 #define TSI721_DMAC_INT_STFULL 0x00000010
245 #define TSI721_DMAC_INT_DONE 0x00000008
246 #define TSI721_DMAC_INT_SUSP 0x00000004
247 #define TSI721_DMAC_INT_ERR 0x00000002
248 #define TSI721_DMAC_INT_IOFDONE 0x00000001
249 #define TSI721_DMAC_INT_ALL 0x0000001f
251 #define TSI721_DMAC_INTSET(x) (0x51010 + (x) * 0x1000)
253 #define TSI721_DMAC_STS(x) (0x51014 + (x) * 0x1000)
254 #define TSI721_DMAC_STS_ABORT 0x00400000
255 #define TSI721_DMAC_STS_RUN 0x00200000
256 #define TSI721_DMAC_STS_CS 0x001f0000
258 #define TSI721_DMAC_INTE(x) (0x51018 + (x) * 0x1000)
260 #define TSI721_DMAC_DPTRL(x) (0x51024 + (x) * 0x1000)
261 #define TSI721_DMAC_DPTRL_MASK 0xffffffe0
263 #define TSI721_DMAC_DPTRH(x) (0x51028 + (x) * 0x1000)
265 #define TSI721_DMAC_DSBL(x) (0x5102c + (x) * 0x1000)
266 #define TSI721_DMAC_DSBL_MASK 0xffffffc0
268 #define TSI721_DMAC_DSBH(x) (0x51030 + (x) * 0x1000)
270 #define TSI721_DMAC_DSSZ(x) (0x51034 + (x) * 0x1000)
271 #define TSI721_DMAC_DSSZ_SIZE_M 0x0000000f
272 #define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4)
275 #define TSI721_DMAC_DSRP(x) (0x51038 + (x) * 0x1000)
276 #define TSI721_DMAC_DSRP_MASK 0x0007ffff
278 #define TSI721_DMAC_DSWP(x) (0x5103c + (x) * 0x1000)
279 #define TSI721_DMAC_DSWP_MASK 0x0007ffff
281 #define TSI721_BDMA_INTE 0x5f000
284 * Messaging definitions
286 #define TSI721_MSG_BUFFER_SIZE RIO_MAX_MSG_SIZE
287 #define TSI721_MSG_MAX_SIZE RIO_MAX_MSG_SIZE
288 #define TSI721_IMSG_MAXCH 8
289 #define TSI721_IMSG_CHNUM TSI721_IMSG_MAXCH
290 #define TSI721_IMSGD_MIN_RING_SIZE 32
291 #define TSI721_IMSGD_RING_SIZE 512
293 #define TSI721_OMSG_CHNUM 4 /* One channel per MBOX */
294 #define TSI721_OMSGD_MIN_RING_SIZE 32
295 #define TSI721_OMSGD_RING_SIZE 512
298 * Outbound Messaging Engine Registers
302 #define TSI721_OBDMAC_DWRCNT(x) (0x61000 + (x) * 0x1000)
304 #define TSI721_OBDMAC_DRDCNT(x) (0x61004 + (x) * 0x1000)
306 #define TSI721_OBDMAC_CTL(x) (0x61008 + (x) * 0x1000)
307 #define TSI721_OBDMAC_CTL_MASK 0x00000007
308 #define TSI721_OBDMAC_CTL_RETRY_THR 0x00000004
309 #define TSI721_OBDMAC_CTL_SUSPEND 0x00000002
310 #define TSI721_OBDMAC_CTL_INIT 0x00000001
312 #define TSI721_OBDMAC_INT(x) (0x6100c + (x) * 0x1000)
313 #define TSI721_OBDMAC_INTSET(x) (0x61010 + (x) * 0x1000)
314 #define TSI721_OBDMAC_INTE(x) (0x61018 + (x) * 0x1000)
315 #define TSI721_OBDMAC_INT_MASK 0x0000001F
316 #define TSI721_OBDMAC_INT_ST_FULL 0x00000010
317 #define TSI721_OBDMAC_INT_DONE 0x00000008
318 #define TSI721_OBDMAC_INT_SUSPENDED 0x00000004
319 #define TSI721_OBDMAC_INT_ERROR 0x00000002
320 #define TSI721_OBDMAC_INT_IOF_DONE 0x00000001
321 #define TSI721_OBDMAC_INT_ALL TSI721_OBDMAC_INT_MASK
323 #define TSI721_OBDMAC_STS(x) (0x61014 + (x) * 0x1000)
324 #define TSI721_OBDMAC_STS_MASK 0x007f0000
325 #define TSI721_OBDMAC_STS_ABORT 0x00400000
326 #define TSI721_OBDMAC_STS_RUN 0x00200000
327 #define TSI721_OBDMAC_STS_CS 0x001f0000
329 #define TSI721_OBDMAC_PWE(x) (0x6101c + (x) * 0x1000)
330 #define TSI721_OBDMAC_PWE_MASK 0x00000002
331 #define TSI721_OBDMAC_PWE_ERROR_EN 0x00000002
333 #define TSI721_OBDMAC_DPTRL(x) (0x61020 + (x) * 0x1000)
334 #define TSI721_OBDMAC_DPTRL_MASK 0xfffffff0
336 #define TSI721_OBDMAC_DPTRH(x) (0x61024 + (x) * 0x1000)
337 #define TSI721_OBDMAC_DPTRH_MASK 0xffffffff
339 #define TSI721_OBDMAC_DSBL(x) (0x61040 + (x) * 0x1000)
340 #define TSI721_OBDMAC_DSBL_MASK 0xffffffc0
342 #define TSI721_OBDMAC_DSBH(x) (0x61044 + (x) * 0x1000)
343 #define TSI721_OBDMAC_DSBH_MASK 0xffffffff
345 #define TSI721_OBDMAC_DSSZ(x) (0x61048 + (x) * 0x1000)
346 #define TSI721_OBDMAC_DSSZ_MASK 0x0000000f
348 #define TSI721_OBDMAC_DSRP(x) (0x6104c + (x) * 0x1000)
349 #define TSI721_OBDMAC_DSRP_MASK 0x0007ffff
351 #define TSI721_OBDMAC_DSWP(x) (0x61050 + (x) * 0x1000)
352 #define TSI721_OBDMAC_DSWP_MASK 0x0007ffff
354 #define TSI721_RQRPTO 0x60010
355 #define TSI721_RQRPTO_MASK 0x00ffffff
356 #define TSI721_RQRPTO_VAL 400 /* Response TO value */
359 * Inbound Messaging Engine Registers
363 #define TSI721_IB_DEVID_GLOBAL 0xffff
364 #define TSI721_IBDMAC_FQBL(x) (0x61200 + (x) * 0x1000)
365 #define TSI721_IBDMAC_FQBL_MASK 0xffffffc0
367 #define TSI721_IBDMAC_FQBH(x) (0x61204 + (x) * 0x1000)
368 #define TSI721_IBDMAC_FQBH_MASK 0xffffffff
370 #define TSI721_IBDMAC_FQSZ_ENTRY_INX TSI721_IMSGD_RING_SIZE
371 #define TSI721_IBDMAC_FQSZ(x) (0x61208 + (x) * 0x1000)
372 #define TSI721_IBDMAC_FQSZ_MASK 0x0000000f
374 #define TSI721_IBDMAC_FQRP(x) (0x6120c + (x) * 0x1000)
375 #define TSI721_IBDMAC_FQRP_MASK 0x0007ffff
377 #define TSI721_IBDMAC_FQWP(x) (0x61210 + (x) * 0x1000)
378 #define TSI721_IBDMAC_FQWP_MASK 0x0007ffff
380 #define TSI721_IBDMAC_FQTH(x) (0x61214 + (x) * 0x1000)
381 #define TSI721_IBDMAC_FQTH_MASK 0x0007ffff
383 #define TSI721_IB_DEVID 0x60020
384 #define TSI721_IB_DEVID_MASK 0x0000ffff
386 #define TSI721_IBDMAC_CTL(x) (0x61240 + (x) * 0x1000)
387 #define TSI721_IBDMAC_CTL_MASK 0x00000003
388 #define TSI721_IBDMAC_CTL_SUSPEND 0x00000002
389 #define TSI721_IBDMAC_CTL_INIT 0x00000001
391 #define TSI721_IBDMAC_STS(x) (0x61244 + (x) * 0x1000)
392 #define TSI721_IBDMAC_STS_MASK 0x007f0000
393 #define TSI721_IBSMAC_STS_ABORT 0x00400000
394 #define TSI721_IBSMAC_STS_RUN 0x00200000
395 #define TSI721_IBSMAC_STS_CS 0x001f0000
397 #define TSI721_IBDMAC_INT(x) (0x61248 + (x) * 0x1000)
398 #define TSI721_IBDMAC_INTSET(x) (0x6124c + (x) * 0x1000)
399 #define TSI721_IBDMAC_INTE(x) (0x61250 + (x) * 0x1000)
400 #define TSI721_IBDMAC_INT_MASK 0x0000100f
401 #define TSI721_IBDMAC_INT_SRTO 0x00001000
402 #define TSI721_IBDMAC_INT_SUSPENDED 0x00000008
403 #define TSI721_IBDMAC_INT_PC_ERROR 0x00000004
404 #define TSI721_IBDMAC_INT_FQ_LOW 0x00000002
405 #define TSI721_IBDMAC_INT_DQ_RCV 0x00000001
406 #define TSI721_IBDMAC_INT_ALL TSI721_IBDMAC_INT_MASK
408 #define TSI721_IBDMAC_PWE(x) (0x61254 + (x) * 0x1000)
409 #define TSI721_IBDMAC_PWE_MASK 0x00001700
410 #define TSI721_IBDMAC_PWE_SRTO 0x00001000
411 #define TSI721_IBDMAC_PWE_ILL_FMT 0x00000400
412 #define TSI721_IBDMAC_PWE_ILL_DEC 0x00000200
413 #define TSI721_IBDMAC_PWE_IMP_SP 0x00000100
415 #define TSI721_IBDMAC_DQBL(x) (0x61300 + (x) * 0x1000)
416 #define TSI721_IBDMAC_DQBL_MASK 0xffffffc0
417 #define TSI721_IBDMAC_DQBL_ADDR 0xffffffc0
419 #define TSI721_IBDMAC_DQBH(x) (0x61304 + (x) * 0x1000)
420 #define TSI721_IBDMAC_DQBH_MASK 0xffffffff
422 #define TSI721_IBDMAC_DQRP(x) (0x61308 + (x) * 0x1000)
423 #define TSI721_IBDMAC_DQRP_MASK 0x0007ffff
425 #define TSI721_IBDMAC_DQWR(x) (0x6130c + (x) * 0x1000)
426 #define TSI721_IBDMAC_DQWR_MASK 0x0007ffff
428 #define TSI721_IBDMAC_DQSZ(x) (0x61314 + (x) * 0x1000)
429 #define TSI721_IBDMAC_DQSZ_MASK 0x0000000f
432 * Messaging Engine Interrupts
435 #define TSI721_SMSG_PWE 0x6a004
437 #define TSI721_SMSG_INTE 0x6a000
438 #define TSI721_SMSG_INT 0x6a008
439 #define TSI721_SMSG_INTSET 0x6a010
440 #define TSI721_SMSG_INT_MASK 0x0086ffff
441 #define TSI721_SMSG_INT_UNS_RSP 0x00800000
442 #define TSI721_SMSG_INT_ECC_NCOR 0x00040000
443 #define TSI721_SMSG_INT_ECC_COR 0x00020000
444 #define TSI721_SMSG_INT_ECC_NCOR_CH 0x0000ff00
445 #define TSI721_SMSG_INT_ECC_COR_CH 0x000000ff
447 #define TSI721_SMSG_ECC_LOG 0x6a014
448 #define TSI721_SMSG_ECC_LOG_MASK 0x00070007
449 #define TSI721_SMSG_ECC_LOG_ECC_NCOR_M 0x00070000
450 #define TSI721_SMSG_ECC_LOG_ECC_COR_M 0x00000007
452 #define TSI721_RETRY_GEN_CNT 0x6a100
453 #define TSI721_RETRY_GEN_CNT_MASK 0xffffffff
455 #define TSI721_RETRY_RX_CNT 0x6a104
456 #define TSI721_RETRY_RX_CNT_MASK 0xffffffff
458 #define TSI721_SMSG_ECC_COR_LOG(x) (0x6a300 + (x) * 4)
459 #define TSI721_SMSG_ECC_COR_LOG_MASK 0x000000ff
461 #define TSI721_SMSG_ECC_NCOR(x) (0x6a340 + (x) * 4)
462 #define TSI721_SMSG_ECC_NCOR_MASK 0x000000ff
465 * Block DMA Descriptors
468 struct tsi721_dma_desc {
471 #define TSI721_DMAD_DEVID 0x0000ffff
472 #define TSI721_DMAD_CRF 0x00010000
473 #define TSI721_DMAD_PRIO 0x00060000
474 #define TSI721_DMAD_RTYPE 0x00780000
475 #define TSI721_DMAD_IOF 0x08000000
476 #define TSI721_DMAD_DTYPE 0xe0000000
480 #define TSI721_DMAD_BCOUNT1 0x03ffffff /* if DTYPE == 1 */
481 #define TSI721_DMAD_BCOUNT2 0x0000000f /* if DTYPE == 2 */
482 #define TSI721_DMAD_TT 0x0c000000
483 #define TSI721_DMAD_RADDR0 0xc0000000
486 __le32 raddr_lo; /* if DTYPE == (1 || 2) */
487 __le32 next_lo; /* if DTYPE == 3 */
490 #define TSI721_DMAD_CFGOFF 0x00ffffff
491 #define TSI721_DMAD_HOPCNT 0xff000000
494 __le32 raddr_hi; /* if DTYPE == (1 || 2) */
495 __le32 next_hi; /* if DTYPE == 3 */
499 struct { /* if DTYPE == 1 */
505 __le32 data[4]; /* if DTYPE == 2 */
506 u32 reserved[4]; /* if DTYPE == 3 */
511 * Inbound Messaging Descriptor
513 struct tsi721_imsg_desc {
516 #define TSI721_IMD_DEVID 0x0000ffff
517 #define TSI721_IMD_CRF 0x00010000
518 #define TSI721_IMD_PRIO 0x00060000
519 #define TSI721_IMD_TT 0x00180000
520 #define TSI721_IMD_DTYPE 0xe0000000
524 #define TSI721_IMD_BCOUNT 0x00000ff8
525 #define TSI721_IMD_SSIZE 0x0000f000
526 #define TSI721_IMD_LETER 0x00030000
527 #define TSI721_IMD_XMBOX 0x003c0000
528 #define TSI721_IMD_MBOX 0x00c00000
529 #define TSI721_IMD_CS 0x78000000
530 #define TSI721_IMD_HO 0x80000000
539 * Outbound Messaging Descriptor
541 struct tsi721_omsg_desc {
544 #define TSI721_OMD_DEVID 0x0000ffff
545 #define TSI721_OMD_CRF 0x00010000
546 #define TSI721_OMD_PRIO 0x00060000
547 #define TSI721_OMD_IOF 0x08000000
548 #define TSI721_OMD_DTYPE 0xe0000000
549 #define TSI721_OMD_RSRVD 0x17f80000
553 #define TSI721_OMD_BCOUNT 0x00000ff8
554 #define TSI721_OMD_SSIZE 0x0000f000
555 #define TSI721_OMD_LETER 0x00030000
556 #define TSI721_OMD_XMBOX 0x003c0000
557 #define TSI721_OMD_MBOX 0x00c00000
558 #define TSI721_OMD_TT 0x0c000000
561 __le32 bufptr_lo; /* if DTYPE == 4 */
562 __le32 next_lo; /* if DTYPE == 5 */
566 __le32 bufptr_hi; /* if DTYPE == 4 */
567 __le32 next_hi; /* if DTYPE == 5 */
572 struct tsi721_dma_sts {
576 struct tsi721_desc_sts_fifo {
586 /* Descriptor types for BDMA and Messaging blocks */
588 DTYPE1 = 1, /* Data Transfer DMA Descriptor */
589 DTYPE2 = 2, /* Immediate Data Transfer DMA Descriptor */
590 DTYPE3 = 3, /* Block Pointer DMA Descriptor */
591 DTYPE4 = 4, /* Outbound Msg DMA Descriptor */
592 DTYPE5 = 5, /* OB Messaging Block Pointer Descriptor */
593 DTYPE6 = 6 /* Inbound Messaging Descriptor */
606 * mport Driver Definitions
608 #define TSI721_DMA_CHNUM TSI721_DMA_MAXCH
610 #define TSI721_DMACH_MAINT 0 /* DMA channel for maint requests */
611 #define TSI721_DMACH_MAINT_NBD 32 /* Number of BDs for maint requests */
613 #define MSG_DMA_ENTRY_INX_TO_SIZE(x) ((0x10 << (x)) & 0xFFFF0)
615 enum tsi721_smsg_int_flag {
616 SMSG_INT_NONE = 0x00000000,
617 SMSG_INT_ECC_COR_CH = 0x000000ff,
618 SMSG_INT_ECC_NCOR_CH = 0x0000ff00,
619 SMSG_INT_ECC_COR = 0x00020000,
620 SMSG_INT_ECC_NCOR = 0x00040000,
621 SMSG_INT_UNS_RSP = 0x00800000,
622 SMSG_INT_ALL = 0x0006ffff
627 struct tsi721_bdma_chan {
628 int bd_num; /* number of buffer descriptors */
629 void *bd_base; /* start of DMA descriptors */
631 void *sts_base; /* start of DMA BD status FIFO */
636 struct tsi721_imsg_ring {
638 /* VA/PA of data buffers for incoming messages */
641 /* VA/PA of circular free buffer list */
643 dma_addr_t imfq_phys;
644 /* VA/PA of Inbound message descriptors */
647 /* Inbound Queue buffer pointers */
648 void *imq_base[TSI721_IMSGD_RING_SIZE];
657 struct tsi721_omsg_ring {
659 /* VA/PA of OB Msg descriptors */
662 /* VA/PA of OB Msg data buffers */
663 void *omq_base[TSI721_OMSGD_RING_SIZE];
664 dma_addr_t omq_phys[TSI721_OMSGD_RING_SIZE];
665 /* VA/PA of OB Msg descriptor status FIFO */
668 u32 sts_size; /* # of allocated status entries */
678 TSI721_USING_MSI = (1 << 0),
679 TSI721_USING_MSIX = (1 << 1),
680 TSI721_IMSGID_SET = (1 << 2),
683 #ifdef CONFIG_PCI_MSI
685 * MSI-X Table Entries (0 ... 69)
687 #define TSI721_MSIX_DMACH_DONE(x) (0 + (x))
688 #define TSI721_MSIX_DMACH_INT(x) (8 + (x))
689 #define TSI721_MSIX_BDMA_INT 16
690 #define TSI721_MSIX_OMSG_DONE(x) (17 + (x))
691 #define TSI721_MSIX_OMSG_INT(x) (25 + (x))
692 #define TSI721_MSIX_IMSG_DQ_RCV(x) (33 + (x))
693 #define TSI721_MSIX_IMSG_INT(x) (41 + (x))
694 #define TSI721_MSIX_MSG_INT 49
695 #define TSI721_MSIX_SR2PC_IDBQ_RCV(x) (50 + (x))
696 #define TSI721_MSIX_SR2PC_CH_INT(x) (58 + (x))
697 #define TSI721_MSIX_SR2PC_INT 66
698 #define TSI721_MSIX_PC2SR_INT 67
699 #define TSI721_MSIX_SRIO_MAC_INT 68
700 #define TSI721_MSIX_I2C_INT 69
702 /* MSI-X vector and init table entry indexes */
703 enum tsi721_msix_vect {
705 TSI721_VECT_PWRX, /* PW_RX is part of SRIO MAC Interrupt reporting */
706 TSI721_VECT_OMB0_DONE,
707 TSI721_VECT_OMB1_DONE,
708 TSI721_VECT_OMB2_DONE,
709 TSI721_VECT_OMB3_DONE,
710 TSI721_VECT_OMB0_INT,
711 TSI721_VECT_OMB1_INT,
712 TSI721_VECT_OMB2_INT,
713 TSI721_VECT_OMB3_INT,
714 TSI721_VECT_IMB0_RCV,
715 TSI721_VECT_IMB1_RCV,
716 TSI721_VECT_IMB2_RCV,
717 TSI721_VECT_IMB3_RCV,
718 TSI721_VECT_IMB0_INT,
719 TSI721_VECT_IMB1_INT,
720 TSI721_VECT_IMB2_INT,
721 TSI721_VECT_IMB3_INT,
725 #define IRQ_DEVICE_NAME_MAX 64
729 char irq_name[IRQ_DEVICE_NAME_MAX];
731 #endif /* CONFIG_PCI_MSI */
733 struct tsi721_device {
734 struct pci_dev *pdev;
735 struct rio_mport *mport;
738 #ifdef CONFIG_PCI_MSI
739 struct msix_irq msix[TSI721_VECT_MAX];
742 void __iomem *odb_base;
745 struct work_struct idb_work;
746 u32 db_discard_count;
748 /* Inbound Port-Write */
749 struct work_struct pw_work;
750 struct kfifo pw_fifo;
751 spinlock_t pw_fifo_lock;
752 u32 pw_discard_count;
755 struct tsi721_bdma_chan bdma[TSI721_DMA_CHNUM];
757 /* Inbound Messaging */
758 int imsg_init[TSI721_IMSG_CHNUM];
759 struct tsi721_imsg_ring imsg_ring[TSI721_IMSG_CHNUM];
761 /* Outbound Messaging */
762 int omsg_init[TSI721_OMSG_CHNUM];
763 struct tsi721_omsg_ring omsg_ring[TSI721_OMSG_CHNUM];