drivers/ram/k3-ddrss/k3-ddrss.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Texas Instruments' K3 DDRSS driver
   4  *
   5  * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dm/device_compat.h>
  12 #include <ram.h>
  13 #include <hang.h>
  14 #include <log.h>
  15 #include <asm/io.h>
  16 #include <power-domain.h>
  17 #include <wait_bit.h>
  18
  19 #include "lpddr4_obj_if.h"
  20 #include "lpddr4_if.h"
  21 #include "lpddr4_structs_if.h"
  22 #include "lpddr4_ctl_regs.h"
  23
  24 #define SRAM_MAX 512
  25
  26 #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS       0x80
  27 #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS       0xc0
  28
  29 struct k3_ddrss_desc {
  30         struct udevice *dev;
  31         void __iomem *ddrss_ss_cfg;
  32         void __iomem *ddrss_ctrl_mmr;
  33         struct power_domain ddrcfg_pwrdmn;
  34         struct power_domain ddrdata_pwrdmn;
  35         struct clk ddr_clk;
  36         struct clk osc_clk;
  37         u32 ddr_freq1;
  38         u32 ddr_freq2;
  39         u32 ddr_fhs_cnt;
  40 };
  41
  42 static lpddr4_obj *driverdt;
  43 static lpddr4_config config;
  44 static lpddr4_privatedata pd;
  45
  46 static struct k3_ddrss_desc *ddrss;
  47
  48 struct reginitdata {
  49         u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
  50         u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
  51         u32 pi_regs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
  52         u16 pi_regs_offs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
  53         u32 phy_regs[LPDDR4_INTR_PHY_REG_COUNT];
  54         u16 phy_regs_offs[LPDDR4_INTR_PHY_REG_COUNT];
  55 };
  56
  57 #define TH_MACRO_EXP(fld, str) (fld##str)
  58
  59 #define TH_FLD_MASK(fld)  TH_MACRO_EXP(fld, _MASK)
  60 #define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)
  61 #define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)
  62 #define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)
  63 #define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)
  64
  65 #define str(s) #s
  66 #define xstr(s) str(s)
  67
  68 #define CTL_SHIFT 11
  69 #define PHY_SHIFT 11
  70 #define PI_SHIFT 10
  71
  72 #define DENALI_CTL_0_DRAM_CLASS_DDR4            0xA
  73 #define DENALI_CTL_0_DRAM_CLASS_LPDDR4          0xB
  74
  75 #define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
  76         char *i, *pstr = xstr(REG); offset = 0;\
  77         for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
  78                 offset = offset * 10 + (*i - '0'); } \
  79         } while (0)
  80
  81 static u32 k3_lpddr4_read_ddr_type(void)
  82 {
  83         u32 status = 0U;
  84         u32 offset = 0U;
  85         u32 regval = 0U;
  86         u32 dram_class = 0U;
  87
  88         TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
  89         status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
  90         if (status > 0U) {
  91                 printf("%s: Failed to read DRAM_CLASS\n", __func__);
  92                 hang();
  93         }
  94
  95         dram_class = ((regval & TH_FLD_MASK(LPDDR4__DRAM_CLASS__FLD)) >>
  96                 TH_FLD_SHIFT(LPDDR4__DRAM_CLASS__FLD));
  97         return dram_class;
  98 }
  99
 100 static void k3_lpddr4_freq_update(void)
 101 {
 102         unsigned int req_type, counter;
 103
 104         for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
 105                 if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
 106                                       CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
 107                                       true, 10000, false)) {
 108                         printf("Timeout during frequency handshake\n");
 109                         hang();
 110                 }
 111
 112                 req_type = readl(ddrss->ddrss_ctrl_mmr +
 113                                  CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
 114
 115                 debug("%s: received freq change req: req type = %d, req no. = %d\n",
 116                       __func__, req_type, counter);
 117
 118                 if (req_type == 1)
 119                         clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
 120                 else if (req_type == 2)
 121                         clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
 122                 else if (req_type == 0)
 123                         /* Put DDR pll in bypass mode */
 124                         clk_set_rate(&ddrss->ddr_clk,
 125                                      clk_get_rate(&ddrss->osc_clk));
 126                 else
 127                         printf("%s: Invalid freq request type\n", __func__);
 128
 129                 writel(0x1, ddrss->ddrss_ctrl_mmr +
 130                        CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
 131                 if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
 132                                       CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
 133                                       false, 10, false)) {
 134                         printf("Timeout during frequency handshake\n");
 135                         hang();
 136                 }
 137                 writel(0x0, ddrss->ddrss_ctrl_mmr +
 138                        CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
 139         }
 140 }
 141
 142 static void k3_lpddr4_ack_freq_upd_req(void)
 143 {
 144         u32 dram_class;
 145
 146         debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
 147
 148         dram_class = k3_lpddr4_read_ddr_type();
 149
 150         switch (dram_class) {
 151         case DENALI_CTL_0_DRAM_CLASS_DDR4:
 152                 break;
 153         case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
 154                 k3_lpddr4_freq_update();
 155                 break;
 156         default:
 157                 printf("Unrecognized dram_class cannot update frequency!\n");
 158         }
 159 }
 160
 161 static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss)
 162 {
 163         u32 dram_class;
 164         int ret;
 165
 166         dram_class = k3_lpddr4_read_ddr_type();
 167
 168         switch (dram_class) {
 169         case DENALI_CTL_0_DRAM_CLASS_DDR4:
 170                 /* Set to ddr_freq1 from DT for DDR4 */
 171                 ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
 172                 break;
 173         case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
 174                 /* Set to bypass frequency for LPDDR4*/
 175                 ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
 176                 break;
 177         default:
 178                 ret = -EINVAL;
 179                 printf("Unrecognized dram_class cannot init frequency!\n");
 180         }
 181
 182         if (ret < 0)
 183                 dev_err(ddrss->dev, "ddr clk init failed: %d\n", ret);
 184         else
 185                 ret = 0;
 186
 187         return ret;
 188 }
 189
 190 static void k3_lpddr4_info_handler(const lpddr4_privatedata *pd,
 191                                    lpddr4_infotype infotype)
 192 {
 193         if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)
 194                 k3_lpddr4_ack_freq_upd_req();
 195 }
 196
 197 static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
 198 {
 199         int ret;
 200
 201         debug("%s(ddrss=%p)\n", __func__, ddrss);
 202
 203         ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
 204         if (ret) {
 205                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 206                 return ret;
 207         }
 208
 209         ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
 210         if (ret) {
 211                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 212                 return ret;
 213         }
 214
 215         return 0;
 216 }
 217
 218 static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
 219 {
 220         struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
 221         phys_addr_t reg;
 222         int ret;
 223
 224         debug("%s(dev=%p)\n", __func__, dev);
 225
 226         reg = dev_read_addr_name(dev, "cfg");
 227         if (reg == FDT_ADDR_T_NONE) {
 228                 dev_err(dev, "No reg property for DDRSS wrapper logic\n");
 229                 return -EINVAL;
 230         }
 231         ddrss->ddrss_ss_cfg = (void *)reg;
 232
 233         reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
 234         if (reg == FDT_ADDR_T_NONE) {
 235                 dev_err(dev, "No reg property for CTRL MMR\n");
 236                 return -EINVAL;
 237         }
 238         ddrss->ddrss_ctrl_mmr = (void *)reg;
 239
 240         ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
 241         if (ret) {
 242                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 243                 return ret;
 244         }
 245
 246         ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
 247         if (ret) {
 248                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 249                 return ret;
 250         }
 251
 252         ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
 253         if (ret)
 254                 dev_err(dev, "clk get failed%d\n", ret);
 255
 256         ret = clk_get_by_index(dev, 1, &ddrss->osc_clk);
 257         if (ret)
 258                 dev_err(dev, "clk get failed for osc clk %d\n", ret);
 259
 260         ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
 261         if (ret)
 262                 dev_err(dev, "ddr freq1 not populated %d\n", ret);
 263
 264         ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2);
 265         if (ret)
 266                 dev_err(dev, "ddr freq2 not populated %d\n", ret);
 267
 268         ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt);
 269         if (ret)
 270                 dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
 271
 272         return ret;
 273 }
 274
 275 void k3_lpddr4_probe(void)
 276 {
 277         u32 status = 0U;
 278         u16 configsize = 0U;
 279
 280         status = driverdt->probe(&config, &configsize);
 281
 282         if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
 283             || (configsize > SRAM_MAX)) {
 284                 printf("%s: FAIL\n", __func__);
 285                 hang();
 286         } else {
 287                 debug("%s: PASS\n", __func__);
 288         }
 289 }
 290
 291 void k3_lpddr4_init(void)
 292 {
 293         u32 status = 0U;
 294
 295         if ((sizeof(pd) != sizeof(lpddr4_privatedata))
 296             || (sizeof(pd) > SRAM_MAX)) {
 297                 printf("%s: FAIL\n", __func__);
 298                 hang();
 299         }
 300
 301         config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
 302         config.infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
 303
 304         status = driverdt->init(&pd, &config);
 305
 306         if ((status > 0U) ||
 307             (pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
 308             (pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
 309             (pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
 310                 printf("%s: FAIL\n", __func__);
 311                 hang();
 312         } else {
 313                 debug("%s: PASS\n", __func__);
 314         }
 315 }
 316
 317 void populate_data_array_from_dt(struct reginitdata *reginit_data)
 318 {
 319         int ret, i;
 320
 321         ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
 322                                  (u32 *)reginit_data->ctl_regs,
 323                                  LPDDR4_INTR_CTL_REG_COUNT);
 324         if (ret)
 325                 printf("Error reading ctrl data %d\n", ret);
 326
 327         for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++)
 328                 reginit_data->ctl_regs_offs[i] = i;
 329
 330         ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
 331                                  (u32 *)reginit_data->pi_regs,
 332                                  LPDDR4_INTR_PHY_INDEP_REG_COUNT);
 333         if (ret)
 334                 printf("Error reading PI data\n");
 335
 336         for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
 337                 reginit_data->pi_regs_offs[i] = i;
 338
 339         ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
 340                                  (u32 *)reginit_data->phy_regs,
 341                                  LPDDR4_INTR_PHY_REG_COUNT);
 342         if (ret)
 343                 printf("Error reading PHY data %d\n", ret);
 344
 345         for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++)
 346                 reginit_data->phy_regs_offs[i] = i;
 347 }
 348
 349 void k3_lpddr4_hardware_reg_init(void)
 350 {
 351         u32 status = 0U;
 352         struct reginitdata reginitdata;
 353
 354         populate_data_array_from_dt(&reginitdata);
 355
 356         status = driverdt->writectlconfig(&pd, reginitdata.ctl_regs,
 357                                           reginitdata.ctl_regs_offs,
 358                                           LPDDR4_INTR_CTL_REG_COUNT);
 359         if (!status)
 360                 status = driverdt->writephyindepconfig(&pd, reginitdata.pi_regs,
 361                                                        reginitdata.pi_regs_offs,
 362                                                        LPDDR4_INTR_PHY_INDEP_REG_COUNT);
 363         if (!status)
 364                 status = driverdt->writephyconfig(&pd, reginitdata.phy_regs,
 365                                                   reginitdata.phy_regs_offs,
 366                                                   LPDDR4_INTR_PHY_REG_COUNT);
 367         if (status) {
 368                 printf("%s: FAIL\n", __func__);
 369                 hang();
 370         }
 371 }
 372
 373 void k3_lpddr4_start(void)
 374 {
 375         u32 status = 0U;
 376         u32 regval = 0U;
 377         u32 offset = 0U;
 378
 379         TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
 380
 381         status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
 382         if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
 383                 printf("%s: Pre start FAIL\n", __func__);
 384                 hang();
 385         }
 386
 387         status = driverdt->start(&pd);
 388         if (status > 0U) {
 389                 printf("%s: FAIL\n", __func__);
 390                 hang();
 391         }
 392
 393         status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
 394         if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
 395                 printf("%s: Post start FAIL\n", __func__);
 396                 hang();
 397         } else {
 398                 debug("%s: Post start PASS\n", __func__);
 399         }
 400 }
 401
 402 static int k3_ddrss_probe(struct udevice *dev)
 403 {
 404         int ret;
 405
 406         ddrss = dev_get_priv(dev);
 407
 408         debug("%s(dev=%p)\n", __func__, dev);
 409
 410         ret = k3_ddrss_ofdata_to_priv(dev);
 411         if (ret)
 412                 return ret;
 413
 414         ddrss->dev = dev;
 415         ret = k3_ddrss_power_on(ddrss);
 416         if (ret)
 417                 return ret;
 418
 419         driverdt = lpddr4_getinstance();
 420         k3_lpddr4_probe();
 421         k3_lpddr4_init();
 422         k3_lpddr4_hardware_reg_init();
 423
 424         ret = k3_ddrss_init_freq(ddrss);
 425         if (ret)
 426                 return ret;
 427
 428         k3_lpddr4_start();
 429
 430         return ret;
 431 }
 432
 433 static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info)
 434 {
 435         return 0;
 436 }
 437
 438 static struct ram_ops k3_ddrss_ops = {
 439         .get_info = k3_ddrss_get_info,
 440 };
 441
 442 static const struct udevice_id k3_ddrss_ids[] = {
 443         {.compatible = "ti,j721e-ddrss"},
 444         {}
 445 };
 446
 447 U_BOOT_DRIVER(k3_ddrss) = {
 448         .name                   = "k3_ddrss",
 449         .id                     = UCLASS_RAM,
 450         .of_match               = k3_ddrss_ids,
 451         .ops                    = &k3_ddrss_ops,
 452         .probe                  = k3_ddrss_probe,
 453         .priv_auto              = sizeof(struct k3_ddrss_desc),
 454 };