1 /* SPDX-License-Identifier: BSD-3-Clause */
5 * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
6 * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
9 #ifndef REG_LPDDR4_DATA_SLICE_2_MACROS_H_
10 #define REG_LPDDR4_DATA_SLICE_2_MACROS_H_
12 #define LPDDR4__DENALI_PHY_512_READ_MASK 0x000F07FFU
13 #define LPDDR4__DENALI_PHY_512_WRITE_MASK 0x000F07FFU
14 #define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU
15 #define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT 0U
16 #define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH 11U
17 #define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_512
18 #define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2
20 #define LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_MASK 0x000F0000U
21 #define LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_SHIFT 16U
22 #define LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_WIDTH 4U
23 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__REG DENALI_PHY_512
24 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__FLD LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2
26 #define LPDDR4__DENALI_PHY_513_READ_MASK 0x000703FFU
27 #define LPDDR4__DENALI_PHY_513_WRITE_MASK 0x000703FFU
28 #define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_MASK 0x000003FFU
29 #define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_SHIFT 0U
30 #define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_WIDTH 10U
31 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2__REG DENALI_PHY_513
32 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2
34 #define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_MASK 0x00070000U
35 #define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_SHIFT 16U
36 #define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_WIDTH 3U
37 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__REG DENALI_PHY_513
38 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2
40 #define LPDDR4__DENALI_PHY_514_READ_MASK 0x010303FFU
41 #define LPDDR4__DENALI_PHY_514_WRITE_MASK 0x010303FFU
42 #define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU
43 #define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_SHIFT 0U
44 #define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_WIDTH 10U
45 #define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_514
46 #define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2
48 #define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_MASK 0x00030000U
49 #define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_SHIFT 16U
50 #define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_WIDTH 2U
51 #define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_514
52 #define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2
54 #define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_MASK 0x01000000U
55 #define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_SHIFT 24U
56 #define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WIDTH 1U
57 #define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WOCLR 0U
58 #define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WOSET 0U
59 #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_514
60 #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2
62 #define LPDDR4__DENALI_PHY_515_READ_MASK 0x3F3F3F3FU
63 #define LPDDR4__DENALI_PHY_515_WRITE_MASK 0x3F3F3F3FU
64 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_MASK 0x0000003FU
65 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_SHIFT 0U
66 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_WIDTH 6U
67 #define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__REG DENALI_PHY_515
68 #define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2
70 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_MASK 0x00003F00U
71 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_SHIFT 8U
72 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_WIDTH 6U
73 #define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__REG DENALI_PHY_515
74 #define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2
76 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_MASK 0x003F0000U
77 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_SHIFT 16U
78 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_WIDTH 6U
79 #define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__REG DENALI_PHY_515
80 #define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2
82 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_MASK 0x3F000000U
83 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_SHIFT 24U
84 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_WIDTH 6U
85 #define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__REG DENALI_PHY_515
86 #define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2
88 #define LPDDR4__DENALI_PHY_516_READ_MASK 0x3F3F3F3FU
89 #define LPDDR4__DENALI_PHY_516_WRITE_MASK 0x3F3F3F3FU
90 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_MASK 0x0000003FU
91 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_SHIFT 0U
92 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_WIDTH 6U
93 #define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__REG DENALI_PHY_516
94 #define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2
96 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_MASK 0x00003F00U
97 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_SHIFT 8U
98 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_WIDTH 6U
99 #define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__REG DENALI_PHY_516
100 #define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2
102 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_MASK 0x003F0000U
103 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_SHIFT 16U
104 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_WIDTH 6U
105 #define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__REG DENALI_PHY_516
106 #define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2
108 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_MASK 0x3F000000U
109 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_SHIFT 24U
110 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_WIDTH 6U
111 #define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__REG DENALI_PHY_516
112 #define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2
114 #define LPDDR4__DENALI_PHY_517_READ_MASK 0x01030F3FU
115 #define LPDDR4__DENALI_PHY_517_WRITE_MASK 0x01030F3FU
116 #define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_MASK 0x0000003FU
117 #define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_SHIFT 0U
118 #define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_WIDTH 6U
119 #define LPDDR4__PHY_SW_WRDM_SHIFT_2__REG DENALI_PHY_517
120 #define LPDDR4__PHY_SW_WRDM_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2
122 #define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_MASK 0x00000F00U
123 #define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_SHIFT 8U
124 #define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_WIDTH 4U
125 #define LPDDR4__PHY_SW_WRDQS_SHIFT_2__REG DENALI_PHY_517
126 #define LPDDR4__PHY_SW_WRDQS_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2
128 #define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_MASK 0x00030000U
129 #define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_SHIFT 16U
130 #define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_WIDTH 2U
131 #define LPDDR4__PHY_PER_RANK_CS_MAP_2__REG DENALI_PHY_517
132 #define LPDDR4__PHY_PER_RANK_CS_MAP_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2
134 #define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_MASK 0x01000000U
135 #define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_SHIFT 24U
136 #define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WIDTH 1U
137 #define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WOCLR 0U
138 #define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WOSET 0U
139 #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__REG DENALI_PHY_517
140 #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2
142 #define LPDDR4__DENALI_PHY_518_READ_MASK 0x1F1F0301U
143 #define LPDDR4__DENALI_PHY_518_WRITE_MASK 0x1F1F0301U
144 #define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_MASK 0x00000001U
145 #define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_SHIFT 0U
146 #define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WIDTH 1U
147 #define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WOCLR 0U
148 #define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WOSET 0U
149 #define LPDDR4__PHY_PER_CS_TRAINING_INDEX_2__REG DENALI_PHY_518
150 #define LPDDR4__PHY_PER_CS_TRAINING_INDEX_2__FLD LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2
152 #define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_MASK 0x00000300U
153 #define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_SHIFT 8U
154 #define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_WIDTH 2U
155 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_518
156 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2
158 #define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_MASK 0x001F0000U
159 #define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_SHIFT 16U
160 #define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_WIDTH 5U
161 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_2__REG DENALI_PHY_518
162 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2
164 #define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_MASK 0x1F000000U
165 #define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_SHIFT 24U
166 #define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_WIDTH 5U
167 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_518
168 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2
170 #define LPDDR4__DENALI_PHY_519_READ_MASK 0x1F030F0FU
171 #define LPDDR4__DENALI_PHY_519_WRITE_MASK 0x1F030F0FU
172 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_MASK 0x0000000FU
173 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_SHIFT 0U
174 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_WIDTH 4U
175 #define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_2__REG DENALI_PHY_519
176 #define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2
178 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_MASK 0x00000F00U
179 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_SHIFT 8U
180 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_WIDTH 4U
181 #define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2__REG DENALI_PHY_519
182 #define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2
184 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_MASK 0x00030000U
185 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_SHIFT 16U
186 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_WIDTH 2U
187 #define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2__REG DENALI_PHY_519
188 #define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2
190 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_MASK 0x1F000000U
191 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_SHIFT 24U
192 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_WIDTH 5U
193 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_519
194 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2
196 #define LPDDR4__DENALI_PHY_520_READ_MASK 0x0101FF03U
197 #define LPDDR4__DENALI_PHY_520_WRITE_MASK 0x0101FF03U
198 #define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_MASK 0x00000003U
199 #define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_SHIFT 0U
200 #define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_WIDTH 2U
201 #define LPDDR4__PHY_CTRL_LPBK_EN_2__REG DENALI_PHY_520
202 #define LPDDR4__PHY_CTRL_LPBK_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2
204 #define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_MASK 0x0001FF00U
205 #define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_SHIFT 8U
206 #define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_WIDTH 9U
207 #define LPDDR4__PHY_LPBK_CONTROL_2__REG DENALI_PHY_520
208 #define LPDDR4__PHY_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2
210 #define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_MASK 0x01000000U
211 #define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_SHIFT 24U
212 #define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WIDTH 1U
213 #define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WOCLR 0U
214 #define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WOSET 0U
215 #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__REG DENALI_PHY_520
216 #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2
218 #define LPDDR4__DENALI_PHY_521_READ_MASK 0xFFFFFFFFU
219 #define LPDDR4__DENALI_PHY_521_WRITE_MASK 0xFFFFFFFFU
220 #define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_MASK 0xFFFFFFFFU
221 #define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_SHIFT 0U
222 #define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_WIDTH 32U
223 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__REG DENALI_PHY_521
224 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__FLD LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2
226 #define LPDDR4__DENALI_PHY_522_READ_MASK 0x0FFFFFFFU
227 #define LPDDR4__DENALI_PHY_522_WRITE_MASK 0x0FFFFFFFU
228 #define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_MASK 0x0FFFFFFFU
229 #define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_SHIFT 0U
230 #define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_WIDTH 28U
231 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__REG DENALI_PHY_522
232 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__FLD LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2
234 #define LPDDR4__DENALI_PHY_523_READ_MASK 0x0101FF7FU
235 #define LPDDR4__DENALI_PHY_523_WRITE_MASK 0x0101FF7FU
236 #define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_MASK 0x0000007FU
237 #define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_SHIFT 0U
238 #define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_WIDTH 7U
239 #define LPDDR4__PHY_PRBS_PATTERN_START_2__REG DENALI_PHY_523
240 #define LPDDR4__PHY_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2
242 #define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_MASK 0x0001FF00U
243 #define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_SHIFT 8U
244 #define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_WIDTH 9U
245 #define LPDDR4__PHY_PRBS_PATTERN_MASK_2__REG DENALI_PHY_523
246 #define LPDDR4__PHY_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2
248 #define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_MASK 0x01000000U
249 #define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_SHIFT 24U
250 #define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_WIDTH 1U
251 #define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_WOCLR 0U
252 #define LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2_WOSET 0U
253 #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__REG DENALI_PHY_523
254 #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__FLD LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2
256 #define LPDDR4__DENALI_PHY_524_READ_MASK 0x007F3F01U
257 #define LPDDR4__DENALI_PHY_524_WRITE_MASK 0x007F3F01U
258 #define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_MASK 0x00000001U
259 #define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_SHIFT 0U
260 #define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WIDTH 1U
261 #define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WOCLR 0U
262 #define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WOSET 0U
263 #define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2__REG DENALI_PHY_524
264 #define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2__FLD LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2
266 #define LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2_MASK 0x00003F00U
267 #define LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2_SHIFT 8U
268 #define LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2_WIDTH 6U
269 #define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__REG DENALI_PHY_524
270 #define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__FLD LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2
272 #define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_MASK 0x007F0000U
273 #define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_SHIFT 16U
274 #define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_WIDTH 7U
275 #define LPDDR4__PHY_VREF_TRAIN_OBS_2__REG DENALI_PHY_524
276 #define LPDDR4__PHY_VREF_TRAIN_OBS_2__FLD LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2
278 #define LPDDR4__DENALI_PHY_525_READ_MASK 0x000F03FFU
279 #define LPDDR4__DENALI_PHY_525_WRITE_MASK 0x000F03FFU
280 #define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU
281 #define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_SHIFT 0U
282 #define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_WIDTH 10U
283 #define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_525
284 #define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2
286 #define LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2_MASK 0x000F0000U
287 #define LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2_SHIFT 16U
288 #define LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2_WIDTH 4U
289 #define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__REG DENALI_PHY_525
290 #define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__FLD LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2
292 #define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_MASK 0x01000000U
293 #define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_SHIFT 24U
294 #define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WIDTH 1U
295 #define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOCLR 0U
296 #define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOSET 0U
297 #define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__REG DENALI_PHY_525
298 #define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2
300 #define LPDDR4__DENALI_PHY_526_READ_MASK 0x070101FFU
301 #define LPDDR4__DENALI_PHY_526_WRITE_MASK 0x070101FFU
302 #define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_MASK 0x000001FFU
303 #define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_SHIFT 0U
304 #define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_WIDTH 9U
305 #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__REG DENALI_PHY_526
306 #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2
308 #define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_MASK 0x00010000U
309 #define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_SHIFT 16U
310 #define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WIDTH 1U
311 #define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOCLR 0U
312 #define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOSET 0U
313 #define LPDDR4__PHY_LPDDR_2__REG DENALI_PHY_526
314 #define LPDDR4__PHY_LPDDR_2__FLD LPDDR4__DENALI_PHY_526__PHY_LPDDR_2
316 #define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_MASK 0x07000000U
317 #define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_SHIFT 24U
318 #define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_WIDTH 3U
319 #define LPDDR4__PHY_MEM_CLASS_2__REG DENALI_PHY_526
320 #define LPDDR4__PHY_MEM_CLASS_2__FLD LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2
322 #define LPDDR4__DENALI_PHY_527_READ_MASK 0x000301FFU
323 #define LPDDR4__DENALI_PHY_527_WRITE_MASK 0x000301FFU
324 #define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_MASK 0x000001FFU
325 #define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_SHIFT 0U
326 #define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_WIDTH 9U
327 #define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__REG DENALI_PHY_527
328 #define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2
330 #define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_MASK 0x00030000U
331 #define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_SHIFT 16U
332 #define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_WIDTH 2U
333 #define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__REG DENALI_PHY_527
334 #define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__FLD LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2
336 #define LPDDR4__DENALI_PHY_528_READ_MASK 0xFFFFFFFFU
337 #define LPDDR4__DENALI_PHY_528_WRITE_MASK 0xFFFFFFFFU
338 #define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_MASK 0xFFFFFFFFU
339 #define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_SHIFT 0U
340 #define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_WIDTH 32U
341 #define LPDDR4__PHY_GATE_TRACKING_OBS_2__REG DENALI_PHY_528
342 #define LPDDR4__PHY_GATE_TRACKING_OBS_2__FLD LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2
344 #define LPDDR4__DENALI_PHY_529_READ_MASK 0x00000301U
345 #define LPDDR4__DENALI_PHY_529_WRITE_MASK 0x00000301U
346 #define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_MASK 0x00000001U
347 #define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_SHIFT 0U
348 #define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WIDTH 1U
349 #define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOCLR 0U
350 #define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOSET 0U
351 #define LPDDR4__PHY_DFI40_POLARITY_2__REG DENALI_PHY_529
352 #define LPDDR4__PHY_DFI40_POLARITY_2__FLD LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2
354 #define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_MASK 0x00000300U
355 #define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_SHIFT 8U
356 #define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_WIDTH 2U
357 #define LPDDR4__PHY_LP4_PST_AMBLE_2__REG DENALI_PHY_529
358 #define LPDDR4__PHY_LP4_PST_AMBLE_2__FLD LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2
360 #define LPDDR4__DENALI_PHY_530_READ_MASK 0xFFFFFFFFU
361 #define LPDDR4__DENALI_PHY_530_WRITE_MASK 0xFFFFFFFFU
362 #define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_MASK 0xFFFFFFFFU
363 #define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_SHIFT 0U
364 #define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_WIDTH 32U
365 #define LPDDR4__PHY_RDLVL_PATT8_2__REG DENALI_PHY_530
366 #define LPDDR4__PHY_RDLVL_PATT8_2__FLD LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2
368 #define LPDDR4__DENALI_PHY_531_READ_MASK 0xFFFFFFFFU
369 #define LPDDR4__DENALI_PHY_531_WRITE_MASK 0xFFFFFFFFU
370 #define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_MASK 0xFFFFFFFFU
371 #define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_SHIFT 0U
372 #define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_WIDTH 32U
373 #define LPDDR4__PHY_RDLVL_PATT9_2__REG DENALI_PHY_531
374 #define LPDDR4__PHY_RDLVL_PATT9_2__FLD LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2
376 #define LPDDR4__DENALI_PHY_532_READ_MASK 0xFFFFFFFFU
377 #define LPDDR4__DENALI_PHY_532_WRITE_MASK 0xFFFFFFFFU
378 #define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_MASK 0xFFFFFFFFU
379 #define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_SHIFT 0U
380 #define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_WIDTH 32U
381 #define LPDDR4__PHY_RDLVL_PATT10_2__REG DENALI_PHY_532
382 #define LPDDR4__PHY_RDLVL_PATT10_2__FLD LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2
384 #define LPDDR4__DENALI_PHY_533_READ_MASK 0xFFFFFFFFU
385 #define LPDDR4__DENALI_PHY_533_WRITE_MASK 0xFFFFFFFFU
386 #define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_MASK 0xFFFFFFFFU
387 #define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_SHIFT 0U
388 #define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_WIDTH 32U
389 #define LPDDR4__PHY_RDLVL_PATT11_2__REG DENALI_PHY_533
390 #define LPDDR4__PHY_RDLVL_PATT11_2__FLD LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2
392 #define LPDDR4__DENALI_PHY_534_READ_MASK 0xFFFFFFFFU
393 #define LPDDR4__DENALI_PHY_534_WRITE_MASK 0xFFFFFFFFU
394 #define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_MASK 0xFFFFFFFFU
395 #define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_SHIFT 0U
396 #define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_WIDTH 32U
397 #define LPDDR4__PHY_RDLVL_PATT12_2__REG DENALI_PHY_534
398 #define LPDDR4__PHY_RDLVL_PATT12_2__FLD LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2
400 #define LPDDR4__DENALI_PHY_535_READ_MASK 0xFFFFFFFFU
401 #define LPDDR4__DENALI_PHY_535_WRITE_MASK 0xFFFFFFFFU
402 #define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_MASK 0xFFFFFFFFU
403 #define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_SHIFT 0U
404 #define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_WIDTH 32U
405 #define LPDDR4__PHY_RDLVL_PATT13_2__REG DENALI_PHY_535
406 #define LPDDR4__PHY_RDLVL_PATT13_2__FLD LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2
408 #define LPDDR4__DENALI_PHY_536_READ_MASK 0xFFFFFFFFU
409 #define LPDDR4__DENALI_PHY_536_WRITE_MASK 0xFFFFFFFFU
410 #define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_MASK 0xFFFFFFFFU
411 #define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_SHIFT 0U
412 #define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_WIDTH 32U
413 #define LPDDR4__PHY_RDLVL_PATT14_2__REG DENALI_PHY_536
414 #define LPDDR4__PHY_RDLVL_PATT14_2__FLD LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2
416 #define LPDDR4__DENALI_PHY_537_READ_MASK 0xFFFFFFFFU
417 #define LPDDR4__DENALI_PHY_537_WRITE_MASK 0xFFFFFFFFU
418 #define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_MASK 0xFFFFFFFFU
419 #define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_SHIFT 0U
420 #define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_WIDTH 32U
421 #define LPDDR4__PHY_RDLVL_PATT15_2__REG DENALI_PHY_537
422 #define LPDDR4__PHY_RDLVL_PATT15_2__FLD LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2
424 #define LPDDR4__DENALI_PHY_538_READ_MASK 0x070F0107U
425 #define LPDDR4__DENALI_PHY_538_WRITE_MASK 0x070F0107U
426 #define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U
427 #define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_SHIFT 0U
428 #define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_WIDTH 3U
429 #define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_538
430 #define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2
432 #define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_MASK 0x00000100U
433 #define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_SHIFT 8U
434 #define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_WIDTH 1U
435 #define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_WOCLR 0U
436 #define LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2_WOSET 0U
437 #define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_2__REG DENALI_PHY_538
438 #define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_2__FLD LPDDR4__DENALI_PHY_538__PHY_SW_FIFO_PTR_RST_DISABLE_2
440 #define LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x000F0000U
441 #define LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT 16U
442 #define LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH 4U
443 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_538
444 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_538__PHY_MASTER_DLY_LOCK_OBS_SELECT_2
446 #define LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2_MASK 0x07000000U
447 #define LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2_SHIFT 24U
448 #define LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2_WIDTH 3U
449 #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__REG DENALI_PHY_538
450 #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2
452 #define LPDDR4__DENALI_PHY_539_READ_MASK 0x0F0F0F0FU
453 #define LPDDR4__DENALI_PHY_539_WRITE_MASK 0x0F0F0F0FU
454 #define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_MASK 0x0000000FU
455 #define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_SHIFT 0U
456 #define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_WIDTH 4U
457 #define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__REG DENALI_PHY_539
458 #define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2
460 #define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_MASK 0x00000F00U
461 #define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_SHIFT 8U
462 #define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_WIDTH 4U
463 #define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__REG DENALI_PHY_539
464 #define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2
466 #define LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2_MASK 0x000F0000U
467 #define LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2_SHIFT 16U
468 #define LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2_WIDTH 4U
469 #define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_2__REG DENALI_PHY_539
470 #define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_WR_SHIFT_OBS_SELECT_2
472 #define LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2_MASK 0x0F000000U
473 #define LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2_SHIFT 24U
474 #define LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2_WIDTH 4U
475 #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__REG DENALI_PHY_539
476 #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2
478 #define LPDDR4__DENALI_PHY_540_READ_MASK 0xFF030001U
479 #define LPDDR4__DENALI_PHY_540_WRITE_MASK 0xFF030001U
480 #define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_MASK 0x00000001U
481 #define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_SHIFT 0U
482 #define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WIDTH 1U
483 #define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOCLR 0U
484 #define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOSET 0U
485 #define LPDDR4__PHY_LVL_DEBUG_MODE_2__REG DENALI_PHY_540
486 #define LPDDR4__PHY_LVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2
488 #define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_MASK 0x00000100U
489 #define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_SHIFT 8U
490 #define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WIDTH 1U
491 #define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOCLR 0U
492 #define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOSET 0U
493 #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__REG DENALI_PHY_540
494 #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2
496 #define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_MASK 0x00030000U
497 #define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_SHIFT 16U
498 #define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_WIDTH 2U
499 #define LPDDR4__PHY_WRLVL_ALGO_2__REG DENALI_PHY_540
500 #define LPDDR4__PHY_WRLVL_ALGO_2__FLD LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2
502 #define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_MASK 0xFF000000U
503 #define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_SHIFT 24U
504 #define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_WIDTH 8U
505 #define LPDDR4__PHY_WRLVL_PER_START_2__REG DENALI_PHY_540
506 #define LPDDR4__PHY_WRLVL_PER_START_2__FLD LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2
508 #define LPDDR4__DENALI_PHY_541_READ_MASK 0x00FF0F3FU
509 #define LPDDR4__DENALI_PHY_541_WRITE_MASK 0x00FF0F3FU
510 #define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_MASK 0x0000003FU
511 #define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_SHIFT 0U
512 #define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_WIDTH 6U
513 #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__REG DENALI_PHY_541
514 #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2
516 #define LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2_MASK 0x00000F00U
517 #define LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2_SHIFT 8U
518 #define LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2_WIDTH 4U
519 #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_541
520 #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2
522 #define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_MASK 0x00FF0000U
523 #define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_SHIFT 16U
524 #define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_WIDTH 8U
525 #define LPDDR4__PHY_DQ_MASK_2__REG DENALI_PHY_541
526 #define LPDDR4__PHY_DQ_MASK_2__FLD LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2
528 #define LPDDR4__DENALI_PHY_542_READ_MASK 0x0F3F03FFU
529 #define LPDDR4__DENALI_PHY_542_WRITE_MASK 0x0F3F03FFU
530 #define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_MASK 0x000003FFU
531 #define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_SHIFT 0U
532 #define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_WIDTH 10U
533 #define LPDDR4__PHY_GTLVL_PER_START_2__REG DENALI_PHY_542
534 #define LPDDR4__PHY_GTLVL_PER_START_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2
536 #define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_MASK 0x003F0000U
537 #define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_SHIFT 16U
538 #define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_WIDTH 6U
539 #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__REG DENALI_PHY_542
540 #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2
542 #define LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2_MASK 0x0F000000U
543 #define LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2_SHIFT 24U
544 #define LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2_WIDTH 4U
545 #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_542
546 #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2
548 #define LPDDR4__DENALI_PHY_543_READ_MASK 0x1F030F3FU
549 #define LPDDR4__DENALI_PHY_543_WRITE_MASK 0x1F030F3FU
550 #define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_MASK 0x0000003FU
551 #define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_SHIFT 0U
552 #define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_WIDTH 6U
553 #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__REG DENALI_PHY_543
554 #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2
556 #define LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2_MASK 0x00000F00U
557 #define LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2_SHIFT 8U
558 #define LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2_WIDTH 4U
559 #define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_543
560 #define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2
562 #define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_MASK 0x00030000U
563 #define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_SHIFT 16U
564 #define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_WIDTH 2U
565 #define LPDDR4__PHY_RDLVL_OP_MODE_2__REG DENALI_PHY_543
566 #define LPDDR4__PHY_RDLVL_OP_MODE_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2
568 #define LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_MASK 0x1F000000U
569 #define LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_SHIFT 24U
570 #define LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_WIDTH 5U
571 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__REG DENALI_PHY_543
572 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2
574 #define LPDDR4__DENALI_PHY_544_READ_MASK 0x3FFFFFFFU
575 #define LPDDR4__DENALI_PHY_544_WRITE_MASK 0x3FFFFFFFU
576 #define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_MASK 0x000000FFU
577 #define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_SHIFT 0U
578 #define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_WIDTH 8U
579 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_2__REG DENALI_PHY_544
580 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2
582 #define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_MASK 0x0000FF00U
583 #define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_SHIFT 8U
584 #define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_WIDTH 8U
585 #define LPDDR4__PHY_RDLVL_DATA_MASK_2__REG DENALI_PHY_544
586 #define LPDDR4__PHY_RDLVL_DATA_MASK_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2
588 #define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_MASK 0x00FF0000U
589 #define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_SHIFT 16U
590 #define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_WIDTH 8U
591 #define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__REG DENALI_PHY_544
592 #define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__FLD LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2
594 #define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_MASK 0x3F000000U
595 #define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_SHIFT 24U
596 #define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_WIDTH 6U
597 #define LPDDR4__PHY_WDQLVL_BURST_CNT_2__REG DENALI_PHY_544
598 #define LPDDR4__PHY_WDQLVL_BURST_CNT_2__FLD LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2
600 #define LPDDR4__DENALI_PHY_545_READ_MASK 0x0F07FF07U
601 #define LPDDR4__DENALI_PHY_545_WRITE_MASK 0x0F07FF07U
602 #define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_MASK 0x00000007U
603 #define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_SHIFT 0U
604 #define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_WIDTH 3U
605 #define LPDDR4__PHY_WDQLVL_PATT_2__REG DENALI_PHY_545
606 #define LPDDR4__PHY_WDQLVL_PATT_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2
608 #define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_MASK 0x0007FF00U
609 #define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_SHIFT 8U
610 #define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_WIDTH 11U
611 #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2__REG DENALI_PHY_545
612 #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2
614 #define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2_MASK 0x0F000000U
615 #define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2_SHIFT 24U
616 #define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2_WIDTH 4U
617 #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_545
618 #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2
620 #define LPDDR4__DENALI_PHY_546_READ_MASK 0x0000FF0FU
621 #define LPDDR4__DENALI_PHY_546_WRITE_MASK 0x0000FF0FU
622 #define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_MASK 0x0000000FU
623 #define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_SHIFT 0U
624 #define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_WIDTH 4U
625 #define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_2__REG DENALI_PHY_546
626 #define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2
628 #define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_MASK 0x0000FF00U
629 #define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_SHIFT 8U
630 #define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_WIDTH 8U
631 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_2__REG DENALI_PHY_546
632 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PERIODIC_OBS_SELECT_2
634 #define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_MASK 0x00010000U
635 #define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_SHIFT 16U
636 #define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WIDTH 1U
637 #define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WOCLR 0U
638 #define LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WOSET 0U
639 #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__REG DENALI_PHY_546
640 #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__FLD LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2
642 #define LPDDR4__DENALI_PHY_547_READ_MASK 0x000001FFU
643 #define LPDDR4__DENALI_PHY_547_WRITE_MASK 0x000001FFU
644 #define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_MASK 0x000001FFU
645 #define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_SHIFT 0U
646 #define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_WIDTH 9U
647 #define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__REG DENALI_PHY_547
648 #define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2
650 #define LPDDR4__DENALI_PHY_548_READ_MASK 0xFFFFFFFFU
651 #define LPDDR4__DENALI_PHY_548_WRITE_MASK 0xFFFFFFFFU
652 #define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_MASK 0xFFFFFFFFU
653 #define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_SHIFT 0U
654 #define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_WIDTH 32U
655 #define LPDDR4__PHY_USER_PATT0_2__REG DENALI_PHY_548
656 #define LPDDR4__PHY_USER_PATT0_2__FLD LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2
658 #define LPDDR4__DENALI_PHY_549_READ_MASK 0xFFFFFFFFU
659 #define LPDDR4__DENALI_PHY_549_WRITE_MASK 0xFFFFFFFFU
660 #define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_MASK 0xFFFFFFFFU
661 #define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_SHIFT 0U
662 #define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_WIDTH 32U
663 #define LPDDR4__PHY_USER_PATT1_2__REG DENALI_PHY_549
664 #define LPDDR4__PHY_USER_PATT1_2__FLD LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2
666 #define LPDDR4__DENALI_PHY_550_READ_MASK 0xFFFFFFFFU
667 #define LPDDR4__DENALI_PHY_550_WRITE_MASK 0xFFFFFFFFU
668 #define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_MASK 0xFFFFFFFFU
669 #define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_SHIFT 0U
670 #define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_WIDTH 32U
671 #define LPDDR4__PHY_USER_PATT2_2__REG DENALI_PHY_550
672 #define LPDDR4__PHY_USER_PATT2_2__FLD LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2
674 #define LPDDR4__DENALI_PHY_551_READ_MASK 0xFFFFFFFFU
675 #define LPDDR4__DENALI_PHY_551_WRITE_MASK 0xFFFFFFFFU
676 #define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_MASK 0xFFFFFFFFU
677 #define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_SHIFT 0U
678 #define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_WIDTH 32U
679 #define LPDDR4__PHY_USER_PATT3_2__REG DENALI_PHY_551
680 #define LPDDR4__PHY_USER_PATT3_2__FLD LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2
682 #define LPDDR4__DENALI_PHY_552_READ_MASK 0x0001FFFFU
683 #define LPDDR4__DENALI_PHY_552_WRITE_MASK 0x0001FFFFU
684 #define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_MASK 0x0000FFFFU
685 #define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_SHIFT 0U
686 #define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_WIDTH 16U
687 #define LPDDR4__PHY_USER_PATT4_2__REG DENALI_PHY_552
688 #define LPDDR4__PHY_USER_PATT4_2__FLD LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2
690 #define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_MASK 0x00010000U
691 #define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_SHIFT 16U
692 #define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WIDTH 1U
693 #define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOCLR 0U
694 #define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOSET 0U
695 #define LPDDR4__PHY_NTP_MULT_TRAIN_2__REG DENALI_PHY_552
696 #define LPDDR4__PHY_NTP_MULT_TRAIN_2__FLD LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2
698 #define LPDDR4__DENALI_PHY_553_READ_MASK 0x03FF03FFU
699 #define LPDDR4__DENALI_PHY_553_WRITE_MASK 0x03FF03FFU
700 #define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_MASK 0x000003FFU
701 #define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_SHIFT 0U
702 #define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_WIDTH 10U
703 #define LPDDR4__PHY_NTP_EARLY_THRESHOLD_2__REG DENALI_PHY_553
704 #define LPDDR4__PHY_NTP_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2
706 #define LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2_MASK 0x03FF0000U
707 #define LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2_SHIFT 16U
708 #define LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2_WIDTH 10U
709 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__REG DENALI_PHY_553
710 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2
712 #define LPDDR4__DENALI_PHY_554_READ_MASK 0x03FF03FFU
713 #define LPDDR4__DENALI_PHY_554_WRITE_MASK 0x03FF03FFU
714 #define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_MASK 0x000003FFU
715 #define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_SHIFT 0U
716 #define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_WIDTH 10U
717 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_2__REG DENALI_PHY_554
718 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_2__FLD LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2
720 #define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2_MASK 0x03FF0000U
721 #define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2_SHIFT 16U
722 #define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2_WIDTH 10U
723 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__REG DENALI_PHY_554
724 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__FLD LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2
726 #define LPDDR4__DENALI_PHY_555_READ_MASK 0x00FF0001U
727 #define LPDDR4__DENALI_PHY_555_WRITE_MASK 0x00FF0001U
728 #define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_MASK 0x00000001U
729 #define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_SHIFT 0U
730 #define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_WIDTH 1U
731 #define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_WOCLR 0U
732 #define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_WOSET 0U
733 #define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__REG DENALI_PHY_555
734 #define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__FLD LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2
736 #define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_MASK 0x00003F00U
737 #define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_SHIFT 8U
738 #define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_WIDTH 6U
739 #define LPDDR4__SC_PHY_MANUAL_CLEAR_2__REG DENALI_PHY_555
740 #define LPDDR4__SC_PHY_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2
742 #define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_MASK 0x00FF0000U
743 #define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_SHIFT 16U
744 #define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_WIDTH 8U
745 #define LPDDR4__PHY_FIFO_PTR_OBS_2__REG DENALI_PHY_555
746 #define LPDDR4__PHY_FIFO_PTR_OBS_2__FLD LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2
748 #define LPDDR4__DENALI_PHY_556_READ_MASK 0xFFFFFFFFU
749 #define LPDDR4__DENALI_PHY_556_WRITE_MASK 0xFFFFFFFFU
750 #define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_MASK 0xFFFFFFFFU
751 #define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_SHIFT 0U
752 #define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_WIDTH 32U
753 #define LPDDR4__PHY_LPBK_RESULT_OBS_2__REG DENALI_PHY_556
754 #define LPDDR4__PHY_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2
756 #define LPDDR4__DENALI_PHY_557_READ_MASK 0x07FFFFFFU
757 #define LPDDR4__DENALI_PHY_557_WRITE_MASK 0x07FFFFFFU
758 #define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU
759 #define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_SHIFT 0U
760 #define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_WIDTH 16U
761 #define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_557
762 #define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2
764 #define LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2_MASK 0x07FF0000U
765 #define LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2_SHIFT 16U
766 #define LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2_WIDTH 11U
767 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_557
768 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2
770 #define LPDDR4__DENALI_PHY_558_READ_MASK 0xFFFF7F7FU
771 #define LPDDR4__DENALI_PHY_558_WRITE_MASK 0xFFFF7F7FU
772 #define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_MASK 0x0000007FU
773 #define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_SHIFT 0U
774 #define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_WIDTH 7U
775 #define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_558
776 #define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2
778 #define LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_MASK 0x00007F00U
779 #define LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_SHIFT 8U
780 #define LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U
781 #define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_558
782 #define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2
784 #define LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2_MASK 0x00FF0000U
785 #define LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2_SHIFT 16U
786 #define LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2_WIDTH 8U
787 #define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_558
788 #define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_558__PHY_MEAS_DLY_STEP_VALUE_2
790 #define LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U
791 #define LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 24U
792 #define LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
793 #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_558
794 #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2
796 #define LPDDR4__DENALI_PHY_559_READ_MASK 0x7F07FFFFU
797 #define LPDDR4__DENALI_PHY_559_WRITE_MASK 0x7F07FFFFU
798 #define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU
799 #define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 0U
800 #define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
801 #define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_559
802 #define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2
804 #define LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_MASK 0x0007FF00U
805 #define LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_SHIFT 8U
806 #define LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_WIDTH 11U
807 #define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_559
808 #define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2
810 #define LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_MASK 0x7F000000U
811 #define LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_SHIFT 24U
812 #define LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U
813 #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_559
814 #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2
816 #define LPDDR4__DENALI_PHY_560_READ_MASK 0x0007FFFFU
817 #define LPDDR4__DENALI_PHY_560_WRITE_MASK 0x0007FFFFU
818 #define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU
819 #define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_SHIFT 0U
820 #define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_WIDTH 8U
821 #define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560
822 #define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2
824 #define LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0x0000FF00U
825 #define LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 8U
826 #define LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
827 #define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560
828 #define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2
830 #define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_MASK 0x00070000U
831 #define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_SHIFT 16U
832 #define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_WIDTH 3U
833 #define LPDDR4__PHY_WR_SHIFT_OBS_2__REG DENALI_PHY_560
834 #define LPDDR4__PHY_WR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2
836 #define LPDDR4__DENALI_PHY_561_READ_MASK 0x03FF03FFU
837 #define LPDDR4__DENALI_PHY_561_WRITE_MASK 0x03FF03FFU
838 #define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_MASK 0x000003FFU
839 #define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_SHIFT 0U
840 #define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_WIDTH 10U
841 #define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_561
842 #define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2
844 #define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2_MASK 0x03FF0000U
845 #define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2_SHIFT 16U
846 #define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2_WIDTH 10U
847 #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_561
848 #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2
850 #define LPDDR4__DENALI_PHY_562_READ_MASK 0x0001FFFFU
851 #define LPDDR4__DENALI_PHY_562_WRITE_MASK 0x0001FFFFU
852 #define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_MASK 0x0001FFFFU
853 #define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_SHIFT 0U
854 #define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_WIDTH 17U
855 #define LPDDR4__PHY_WRLVL_STATUS_OBS_2__REG DENALI_PHY_562
856 #define LPDDR4__PHY_WRLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2
858 #define LPDDR4__DENALI_PHY_563_READ_MASK 0x03FF03FFU
859 #define LPDDR4__DENALI_PHY_563_WRITE_MASK 0x03FF03FFU
860 #define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_MASK 0x000003FFU
861 #define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_SHIFT 0U
862 #define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_WIDTH 10U
863 #define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_563
864 #define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2
866 #define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_MASK 0x03FF0000U
867 #define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_SHIFT 16U
868 #define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_WIDTH 10U
869 #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_563
870 #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2
872 #define LPDDR4__DENALI_PHY_564_READ_MASK 0x3FFFFFFFU
873 #define LPDDR4__DENALI_PHY_564_WRITE_MASK 0x3FFFFFFFU
874 #define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_MASK 0x0000FFFFU
875 #define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_SHIFT 0U
876 #define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_WIDTH 16U
877 #define LPDDR4__PHY_WRLVL_ERROR_OBS_2__REG DENALI_PHY_564
878 #define LPDDR4__PHY_WRLVL_ERROR_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2
880 #define LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2_MASK 0x3FFF0000U
881 #define LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2_SHIFT 16U
882 #define LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2_WIDTH 14U
883 #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_564
884 #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2
886 #define LPDDR4__DENALI_PHY_565_READ_MASK 0x00003FFFU
887 #define LPDDR4__DENALI_PHY_565_WRITE_MASK 0x00003FFFU
888 #define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_MASK 0x00003FFFU
889 #define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_SHIFT 0U
890 #define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_WIDTH 14U
891 #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_565
892 #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2
894 #define LPDDR4__DENALI_PHY_566_READ_MASK 0x0003FFFFU
895 #define LPDDR4__DENALI_PHY_566_WRITE_MASK 0x0003FFFFU
896 #define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_MASK 0x0003FFFFU
897 #define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_SHIFT 0U
898 #define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_WIDTH 18U
899 #define LPDDR4__PHY_GTLVL_STATUS_OBS_2__REG DENALI_PHY_566
900 #define LPDDR4__PHY_GTLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2
902 #define LPDDR4__DENALI_PHY_567_READ_MASK 0x03FF03FFU
903 #define LPDDR4__DENALI_PHY_567_WRITE_MASK 0x03FF03FFU
904 #define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_MASK 0x000003FFU
905 #define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_SHIFT 0U
906 #define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_WIDTH 10U
907 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2__REG DENALI_PHY_567
908 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2
910 #define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_MASK 0x03FF0000U
911 #define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_SHIFT 16U
912 #define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_WIDTH 10U
913 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__REG DENALI_PHY_567
914 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2
916 #define LPDDR4__DENALI_PHY_568_READ_MASK 0x00000003U
917 #define LPDDR4__DENALI_PHY_568_WRITE_MASK 0x00000003U
918 #define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_MASK 0x00000003U
919 #define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_SHIFT 0U
920 #define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_WIDTH 2U
921 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__REG DENALI_PHY_568
922 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__FLD LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2
924 #define LPDDR4__DENALI_PHY_569_READ_MASK 0xFFFFFFFFU
925 #define LPDDR4__DENALI_PHY_569_WRITE_MASK 0xFFFFFFFFU
926 #define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_MASK 0xFFFFFFFFU
927 #define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_SHIFT 0U
928 #define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_WIDTH 32U
929 #define LPDDR4__PHY_RDLVL_STATUS_OBS_2__REG DENALI_PHY_569
930 #define LPDDR4__PHY_RDLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2
932 #define LPDDR4__DENALI_PHY_570_READ_MASK 0xFFFFFFFFU
933 #define LPDDR4__DENALI_PHY_570_WRITE_MASK 0xFFFFFFFFU
934 #define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_MASK 0xFFFFFFFFU
935 #define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_SHIFT 0U
936 #define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_WIDTH 32U
937 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_2__REG DENALI_PHY_570
938 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2
940 #define LPDDR4__DENALI_PHY_571_READ_MASK 0x07FF07FFU
941 #define LPDDR4__DENALI_PHY_571_WRITE_MASK 0x07FF07FFU
942 #define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_MASK 0x000007FFU
943 #define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_SHIFT 0U
944 #define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_WIDTH 11U
945 #define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_2__REG DENALI_PHY_571
946 #define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2
948 #define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_MASK 0x07FF0000U
949 #define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_SHIFT 16U
950 #define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_WIDTH 11U
951 #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__REG DENALI_PHY_571
952 #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2
954 #define LPDDR4__DENALI_PHY_572_READ_MASK 0xFFFFFFFFU
955 #define LPDDR4__DENALI_PHY_572_WRITE_MASK 0xFFFFFFFFU
956 #define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_MASK 0xFFFFFFFFU
957 #define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_SHIFT 0U
958 #define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_WIDTH 32U
959 #define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__REG DENALI_PHY_572
960 #define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2
962 #define LPDDR4__DENALI_PHY_573_READ_MASK 0xFFFFFFFFU
963 #define LPDDR4__DENALI_PHY_573_WRITE_MASK 0xFFFFFFFFU
964 #define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_MASK 0xFFFFFFFFU
965 #define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_SHIFT 0U
966 #define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_WIDTH 32U
967 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__REG DENALI_PHY_573
968 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2
970 #define LPDDR4__DENALI_PHY_574_READ_MASK 0x7FFFFFFFU
971 #define LPDDR4__DENALI_PHY_574_WRITE_MASK 0x7FFFFFFFU
972 #define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_MASK 0x7FFFFFFFU
973 #define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_SHIFT 0U
974 #define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_WIDTH 31U
975 #define LPDDR4__PHY_DDL_MODE_2__REG DENALI_PHY_574
976 #define LPDDR4__PHY_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2
978 #define LPDDR4__DENALI_PHY_575_READ_MASK 0x0000003FU
979 #define LPDDR4__DENALI_PHY_575_WRITE_MASK 0x0000003FU
980 #define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_MASK 0x0000003FU
981 #define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_SHIFT 0U
982 #define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_WIDTH 6U
983 #define LPDDR4__PHY_DDL_MASK_2__REG DENALI_PHY_575
984 #define LPDDR4__PHY_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2
986 #define LPDDR4__DENALI_PHY_576_READ_MASK 0xFFFFFFFFU
987 #define LPDDR4__DENALI_PHY_576_WRITE_MASK 0xFFFFFFFFU
988 #define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_MASK 0xFFFFFFFFU
989 #define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_SHIFT 0U
990 #define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_WIDTH 32U
991 #define LPDDR4__PHY_DDL_TEST_OBS_2__REG DENALI_PHY_576
992 #define LPDDR4__PHY_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2
994 #define LPDDR4__DENALI_PHY_577_READ_MASK 0xFFFFFFFFU
995 #define LPDDR4__DENALI_PHY_577_WRITE_MASK 0xFFFFFFFFU
996 #define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU
997 #define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_SHIFT 0U
998 #define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_WIDTH 32U
999 #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_577
1000 #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2
1002 #define LPDDR4__DENALI_PHY_578_READ_MASK 0x010001FFU
1003 #define LPDDR4__DENALI_PHY_578_WRITE_MASK 0x010001FFU
1004 #define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_MASK 0x000000FFU
1005 #define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_SHIFT 0U
1006 #define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_WIDTH 8U
1007 #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__REG DENALI_PHY_578
1008 #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2
1010 #define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_MASK 0x00000100U
1011 #define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_SHIFT 8U
1012 #define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WIDTH 1U
1013 #define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOCLR 0U
1014 #define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOSET 0U
1015 #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__REG DENALI_PHY_578
1016 #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__FLD LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2
1018 #define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_MASK 0x00010000U
1019 #define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_SHIFT 16U
1020 #define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WIDTH 1U
1021 #define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOCLR 0U
1022 #define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOSET 0U
1023 #define LPDDR4__SC_PHY_RX_CAL_START_2__REG DENALI_PHY_578
1024 #define LPDDR4__SC_PHY_RX_CAL_START_2__FLD LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2
1026 #define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_MASK 0x01000000U
1027 #define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_SHIFT 24U
1028 #define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WIDTH 1U
1029 #define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOCLR 0U
1030 #define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOSET 0U
1031 #define LPDDR4__PHY_RX_CAL_OVERRIDE_2__REG DENALI_PHY_578
1032 #define LPDDR4__PHY_RX_CAL_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2
1034 #define LPDDR4__DENALI_PHY_579_READ_MASK 0x01FF01FFU
1035 #define LPDDR4__DENALI_PHY_579_WRITE_MASK 0x01FF01FFU
1036 #define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_MASK 0x000000FFU
1037 #define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_SHIFT 0U
1038 #define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_WIDTH 8U
1039 #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_579
1040 #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2
1042 #define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_MASK 0x00000100U
1043 #define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_SHIFT 8U
1044 #define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_WIDTH 1U
1045 #define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_WOCLR 0U
1046 #define LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2_WOSET 0U
1047 #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2__REG DENALI_PHY_579
1048 #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2__FLD LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2
1050 #define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_MASK 0x01FF0000U
1051 #define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_SHIFT 16U
1052 #define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_WIDTH 9U
1053 #define LPDDR4__PHY_RX_CAL_DQ0_2__REG DENALI_PHY_579
1054 #define LPDDR4__PHY_RX_CAL_DQ0_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2
1056 #define LPDDR4__DENALI_PHY_580_READ_MASK 0x01FF01FFU
1057 #define LPDDR4__DENALI_PHY_580_WRITE_MASK 0x01FF01FFU
1058 #define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_MASK 0x000001FFU
1059 #define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_SHIFT 0U
1060 #define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_WIDTH 9U
1061 #define LPDDR4__PHY_RX_CAL_DQ1_2__REG DENALI_PHY_580
1062 #define LPDDR4__PHY_RX_CAL_DQ1_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2
1064 #define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_MASK 0x01FF0000U
1065 #define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_SHIFT 16U
1066 #define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_WIDTH 9U
1067 #define LPDDR4__PHY_RX_CAL_DQ2_2__REG DENALI_PHY_580
1068 #define LPDDR4__PHY_RX_CAL_DQ2_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2
1070 #define LPDDR4__DENALI_PHY_581_READ_MASK 0x01FF01FFU
1071 #define LPDDR4__DENALI_PHY_581_WRITE_MASK 0x01FF01FFU
1072 #define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_MASK 0x000001FFU
1073 #define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_SHIFT 0U
1074 #define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_WIDTH 9U
1075 #define LPDDR4__PHY_RX_CAL_DQ3_2__REG DENALI_PHY_581
1076 #define LPDDR4__PHY_RX_CAL_DQ3_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2
1078 #define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_MASK 0x01FF0000U
1079 #define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_SHIFT 16U
1080 #define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_WIDTH 9U
1081 #define LPDDR4__PHY_RX_CAL_DQ4_2__REG DENALI_PHY_581
1082 #define LPDDR4__PHY_RX_CAL_DQ4_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2
1084 #define LPDDR4__DENALI_PHY_582_READ_MASK 0x01FF01FFU
1085 #define LPDDR4__DENALI_PHY_582_WRITE_MASK 0x01FF01FFU
1086 #define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_MASK 0x000001FFU
1087 #define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_SHIFT 0U
1088 #define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_WIDTH 9U
1089 #define LPDDR4__PHY_RX_CAL_DQ5_2__REG DENALI_PHY_582
1090 #define LPDDR4__PHY_RX_CAL_DQ5_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2
1092 #define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_MASK 0x01FF0000U
1093 #define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_SHIFT 16U
1094 #define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_WIDTH 9U
1095 #define LPDDR4__PHY_RX_CAL_DQ6_2__REG DENALI_PHY_582
1096 #define LPDDR4__PHY_RX_CAL_DQ6_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2
1098 #define LPDDR4__DENALI_PHY_583_READ_MASK 0x000001FFU
1099 #define LPDDR4__DENALI_PHY_583_WRITE_MASK 0x000001FFU
1100 #define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_MASK 0x000001FFU
1101 #define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_SHIFT 0U
1102 #define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_WIDTH 9U
1103 #define LPDDR4__PHY_RX_CAL_DQ7_2__REG DENALI_PHY_583
1104 #define LPDDR4__PHY_RX_CAL_DQ7_2__FLD LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2
1106 #define LPDDR4__DENALI_PHY_584_READ_MASK 0x0003FFFFU
1107 #define LPDDR4__DENALI_PHY_584_WRITE_MASK 0x0003FFFFU
1108 #define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_MASK 0x0003FFFFU
1109 #define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_SHIFT 0U
1110 #define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_WIDTH 18U
1111 #define LPDDR4__PHY_RX_CAL_DM_2__REG DENALI_PHY_584
1112 #define LPDDR4__PHY_RX_CAL_DM_2__FLD LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2
1114 #define LPDDR4__DENALI_PHY_585_READ_MASK 0x01FF01FFU
1115 #define LPDDR4__DENALI_PHY_585_WRITE_MASK 0x01FF01FFU
1116 #define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_MASK 0x000001FFU
1117 #define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_SHIFT 0U
1118 #define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_WIDTH 9U
1119 #define LPDDR4__PHY_RX_CAL_DQS_2__REG DENALI_PHY_585
1120 #define LPDDR4__PHY_RX_CAL_DQS_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2
1122 #define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_MASK 0x01FF0000U
1123 #define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_SHIFT 16U
1124 #define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_WIDTH 9U
1125 #define LPDDR4__PHY_RX_CAL_FDBK_2__REG DENALI_PHY_585
1126 #define LPDDR4__PHY_RX_CAL_FDBK_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2
1128 #define LPDDR4__DENALI_PHY_586_READ_MASK 0x01FF07FFU
1129 #define LPDDR4__DENALI_PHY_586_WRITE_MASK 0x01FF07FFU
1130 #define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_MASK 0x000007FFU
1131 #define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_SHIFT 0U
1132 #define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_WIDTH 11U
1133 #define LPDDR4__PHY_RX_CAL_OBS_2__REG DENALI_PHY_586
1134 #define LPDDR4__PHY_RX_CAL_OBS_2__FLD LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2
1136 #define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_MASK 0x01FF0000U
1137 #define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_SHIFT 16U
1138 #define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_WIDTH 9U
1139 #define LPDDR4__PHY_RX_CAL_LOCK_OBS_2__REG DENALI_PHY_586
1140 #define LPDDR4__PHY_RX_CAL_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2
1142 #define LPDDR4__DENALI_PHY_587_READ_MASK 0x017F7F01U
1143 #define LPDDR4__DENALI_PHY_587_WRITE_MASK 0x017F7F01U
1144 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_MASK 0x00000001U
1145 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_SHIFT 0U
1146 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WIDTH 1U
1147 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOCLR 0U
1148 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOSET 0U
1149 #define LPDDR4__PHY_RX_CAL_DISABLE_2__REG DENALI_PHY_587
1150 #define LPDDR4__PHY_RX_CAL_DISABLE_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2
1152 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_MASK 0x00007F00U
1153 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_SHIFT 8U
1154 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_WIDTH 7U
1155 #define LPDDR4__PHY_RX_CAL_SE_ADJUST_2__REG DENALI_PHY_587
1156 #define LPDDR4__PHY_RX_CAL_SE_ADJUST_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2
1158 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_MASK 0x007F0000U
1159 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_SHIFT 16U
1160 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_WIDTH 7U
1161 #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_2__REG DENALI_PHY_587
1162 #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2
1164 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_MASK 0x01000000U
1165 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_SHIFT 24U
1166 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WIDTH 1U
1167 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOCLR 0U
1168 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOSET 0U
1169 #define LPDDR4__PHY_RX_CAL_COMP_VAL_2__REG DENALI_PHY_587
1170 #define LPDDR4__PHY_RX_CAL_COMP_VAL_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2
1172 #define LPDDR4__DENALI_PHY_588_READ_MASK 0x07FF0FFFU
1173 #define LPDDR4__DENALI_PHY_588_WRITE_MASK 0x07FF0FFFU
1174 #define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_MASK 0x00000FFFU
1175 #define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_SHIFT 0U
1176 #define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_WIDTH 12U
1177 #define LPDDR4__PHY_RX_CAL_INDEX_MASK_2__REG DENALI_PHY_588
1178 #define LPDDR4__PHY_RX_CAL_INDEX_MASK_2__FLD LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2
1180 #define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_MASK 0x07FF0000U
1181 #define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_SHIFT 16U
1182 #define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_WIDTH 11U
1183 #define LPDDR4__PHY_PAD_RX_BIAS_EN_2__REG DENALI_PHY_588
1184 #define LPDDR4__PHY_PAD_RX_BIAS_EN_2__FLD LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2
1186 #define LPDDR4__DENALI_PHY_589_READ_MASK 0x03FFFF1FU
1187 #define LPDDR4__DENALI_PHY_589_WRITE_MASK 0x03FFFF1FU
1188 #define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_MASK 0x0000001FU
1189 #define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_SHIFT 0U
1190 #define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_WIDTH 5U
1191 #define LPDDR4__PHY_STATIC_TOG_DISABLE_2__REG DENALI_PHY_589
1192 #define LPDDR4__PHY_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2
1194 #define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_MASK 0x0000FF00U
1195 #define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_SHIFT 8U
1196 #define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_WIDTH 8U
1197 #define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_589
1198 #define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_SAMPLE_WAIT_2
1200 #define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2_MASK 0x00FF0000U
1201 #define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2_SHIFT 16U
1202 #define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2_WIDTH 8U
1203 #define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__REG DENALI_PHY_589
1204 #define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2
1206 #define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_MASK 0x03000000U
1207 #define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_SHIFT 24U
1208 #define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_WIDTH 2U
1209 #define LPDDR4__PHY_DATA_DC_WEIGHT_2__REG DENALI_PHY_589
1210 #define LPDDR4__PHY_DATA_DC_WEIGHT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2
1212 #define LPDDR4__DENALI_PHY_590_READ_MASK 0x01FFFF3FU
1213 #define LPDDR4__DENALI_PHY_590_WRITE_MASK 0x01FFFF3FU
1214 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_MASK 0x0000003FU
1215 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_SHIFT 0U
1216 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_WIDTH 6U
1217 #define LPDDR4__PHY_DATA_DC_ADJUST_START_2__REG DENALI_PHY_590
1218 #define LPDDR4__PHY_DATA_DC_ADJUST_START_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2
1220 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_MASK 0x0000FF00U
1221 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_SHIFT 8U
1222 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_WIDTH 8U
1223 #define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2__REG DENALI_PHY_590
1224 #define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2
1226 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2_MASK 0x00FF0000U
1227 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2_SHIFT 16U
1228 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2_WIDTH 8U
1229 #define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_2__REG DENALI_PHY_590
1230 #define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_THRSHLD_2
1232 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_MASK 0x01000000U
1233 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_SHIFT 24U
1234 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_WIDTH 1U
1235 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_WOCLR 0U
1236 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2_WOSET 0U
1237 #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__REG DENALI_PHY_590
1238 #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2
1240 #define LPDDR4__DENALI_PHY_591_READ_MASK 0x07030101U
1241 #define LPDDR4__DENALI_PHY_591_WRITE_MASK 0x07030101U
1242 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_MASK 0x00000001U
1243 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_SHIFT 0U
1244 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_WIDTH 1U
1245 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_WOCLR 0U
1246 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_WOSET 0U
1247 #define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__REG DENALI_PHY_591
1248 #define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2
1250 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_MASK 0x00000100U
1251 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_SHIFT 8U
1252 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WIDTH 1U
1253 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOCLR 0U
1254 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOSET 0U
1255 #define LPDDR4__PHY_DATA_DC_CAL_START_2__REG DENALI_PHY_591
1256 #define LPDDR4__PHY_DATA_DC_CAL_START_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2
1258 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_MASK 0x00030000U
1259 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_SHIFT 16U
1260 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_WIDTH 2U
1261 #define LPDDR4__PHY_DATA_DC_SW_RANK_2__REG DENALI_PHY_591
1262 #define LPDDR4__PHY_DATA_DC_SW_RANK_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2
1264 #define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_MASK 0x07000000U
1265 #define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_SHIFT 24U
1266 #define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_WIDTH 3U
1267 #define LPDDR4__PHY_FDBK_PWR_CTRL_2__REG DENALI_PHY_591
1268 #define LPDDR4__PHY_FDBK_PWR_CTRL_2__FLD LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2
1270 #define LPDDR4__DENALI_PHY_592_READ_MASK 0x01010101U
1271 #define LPDDR4__DENALI_PHY_592_WRITE_MASK 0x01010101U
1272 #define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U
1273 #define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT 0U
1274 #define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH 1U
1275 #define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR 0U
1276 #define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET 0U
1277 #define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_592
1278 #define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2
1280 #define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_MASK 0x00000100U
1281 #define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_SHIFT 8U
1282 #define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_WIDTH 1U
1283 #define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_WOCLR 0U
1284 #define LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2_WOSET 0U
1285 #define LPDDR4__PHY_RDPATH_GATE_DISABLE_2__REG DENALI_PHY_592
1286 #define LPDDR4__PHY_RDPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_RDPATH_GATE_DISABLE_2
1288 #define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_MASK 0x00010000U
1289 #define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_SHIFT 16U
1290 #define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WIDTH 1U
1291 #define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOCLR 0U
1292 #define LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOSET 0U
1293 #define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2__REG DENALI_PHY_592
1294 #define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2
1296 #define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_MASK 0x01000000U
1297 #define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_SHIFT 24U
1298 #define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_WIDTH 1U
1299 #define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_WOCLR 0U
1300 #define LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2_WOSET 0U
1301 #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__REG DENALI_PHY_592
1302 #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2
1304 #define LPDDR4__DENALI_PHY_593_READ_MASK 0x3FFF07FFU
1305 #define LPDDR4__DENALI_PHY_593_WRITE_MASK 0x3FFF07FFU
1306 #define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_MASK 0x000007FFU
1307 #define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_SHIFT 0U
1308 #define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_WIDTH 11U
1309 #define LPDDR4__PHY_PARITY_ERROR_REGIF_2__REG DENALI_PHY_593
1310 #define LPDDR4__PHY_PARITY_ERROR_REGIF_2__FLD LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2
1312 #define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_MASK 0x3FFF0000U
1313 #define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_SHIFT 16U
1314 #define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_WIDTH 14U
1315 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_2__REG DENALI_PHY_593
1316 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_2__FLD LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2
1318 #define LPDDR4__DENALI_PHY_594_READ_MASK 0x00003FFFU
1319 #define LPDDR4__DENALI_PHY_594_WRITE_MASK 0x00003FFFU
1320 #define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_MASK 0x00003FFFU
1321 #define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_SHIFT 0U
1322 #define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_WIDTH 14U
1323 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_2__REG DENALI_PHY_594
1324 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_2__FLD LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2
1326 #define LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2_MASK 0x3FFF0000U
1327 #define LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2_SHIFT 16U
1328 #define LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2_WIDTH 14U
1329 #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2__REG DENALI_PHY_594
1330 #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2__FLD LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2
1332 #define LPDDR4__DENALI_PHY_595_READ_MASK 0x00001F1FU
1333 #define LPDDR4__DENALI_PHY_595_WRITE_MASK 0x00001F1FU
1334 #define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_MASK 0x0000001FU
1335 #define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_SHIFT 0U
1336 #define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_WIDTH 5U
1337 #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_2__REG DENALI_PHY_595
1338 #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_2__FLD LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2
1340 #define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2_MASK 0x00001F00U
1341 #define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2_SHIFT 8U
1342 #define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2_WIDTH 5U
1343 #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2__REG DENALI_PHY_595
1344 #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2__FLD LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2
1346 #define LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2_MASK 0x001F0000U
1347 #define LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2_SHIFT 16U
1348 #define LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2_WIDTH 5U
1349 #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2__REG DENALI_PHY_595
1350 #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2__FLD LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2
1352 #define LPDDR4__DENALI_PHY_596_READ_MASK 0x07FFFF07U
1353 #define LPDDR4__DENALI_PHY_596_WRITE_MASK 0x07FFFF07U
1354 #define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_MASK 0x00000007U
1355 #define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_SHIFT 0U
1356 #define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_WIDTH 3U
1357 #define LPDDR4__PHY_DQ_TSEL_ENABLE_2__REG DENALI_PHY_596
1358 #define LPDDR4__PHY_DQ_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2
1360 #define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_MASK 0x00FFFF00U
1361 #define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_SHIFT 8U
1362 #define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_WIDTH 16U
1363 #define LPDDR4__PHY_DQ_TSEL_SELECT_2__REG DENALI_PHY_596
1364 #define LPDDR4__PHY_DQ_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2
1366 #define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_MASK 0x07000000U
1367 #define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_SHIFT 24U
1368 #define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_WIDTH 3U
1369 #define LPDDR4__PHY_DQS_TSEL_ENABLE_2__REG DENALI_PHY_596
1370 #define LPDDR4__PHY_DQS_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2
1372 #define LPDDR4__DENALI_PHY_597_READ_MASK 0x7F03FFFFU
1373 #define LPDDR4__DENALI_PHY_597_WRITE_MASK 0x7F03FFFFU
1374 #define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_MASK 0x0000FFFFU
1375 #define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_SHIFT 0U
1376 #define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_WIDTH 16U
1377 #define LPDDR4__PHY_DQS_TSEL_SELECT_2__REG DENALI_PHY_597
1378 #define LPDDR4__PHY_DQS_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2
1380 #define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_MASK 0x00030000U
1381 #define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_SHIFT 16U
1382 #define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_WIDTH 2U
1383 #define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_597
1384 #define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2
1386 #define LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2_MASK 0x7F000000U
1387 #define LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2_SHIFT 24U
1388 #define LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2_WIDTH 7U
1389 #define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__REG DENALI_PHY_597
1390 #define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__FLD LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2
1392 #define LPDDR4__DENALI_PHY_598_READ_MASK 0xFF01037FU
1393 #define LPDDR4__DENALI_PHY_598_WRITE_MASK 0xFF01037FU
1394 #define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_MASK 0x0000007FU
1395 #define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_SHIFT 0U
1396 #define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_WIDTH 7U
1397 #define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__REG DENALI_PHY_598
1398 #define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__FLD LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2
1400 #define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_MASK 0x00000300U
1401 #define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_SHIFT 8U
1402 #define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_WIDTH 2U
1403 #define LPDDR4__PHY_VREF_TRAINING_CTRL_2__REG DENALI_PHY_598
1404 #define LPDDR4__PHY_VREF_TRAINING_CTRL_2__FLD LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2
1406 #define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_MASK 0x00010000U
1407 #define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_SHIFT 16U
1408 #define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WIDTH 1U
1409 #define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOCLR 0U
1410 #define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOSET 0U
1411 #define LPDDR4__PHY_NTP_TRAIN_EN_2__REG DENALI_PHY_598
1412 #define LPDDR4__PHY_NTP_TRAIN_EN_2__FLD LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2
1414 #define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_MASK 0xFF000000U
1415 #define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_SHIFT 24U
1416 #define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_WIDTH 8U
1417 #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__REG DENALI_PHY_598
1418 #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__FLD LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2
1420 #define LPDDR4__DENALI_PHY_599_READ_MASK 0x07FF07FFU
1421 #define LPDDR4__DENALI_PHY_599_WRITE_MASK 0x07FF07FFU
1422 #define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_MASK 0x000007FFU
1423 #define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_SHIFT 0U
1424 #define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_WIDTH 11U
1425 #define LPDDR4__PHY_NTP_WDQ_START_2__REG DENALI_PHY_599
1426 #define LPDDR4__PHY_NTP_WDQ_START_2__FLD LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2
1428 #define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_MASK 0x07FF0000U
1429 #define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_SHIFT 16U
1430 #define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_WIDTH 11U
1431 #define LPDDR4__PHY_NTP_WDQ_STOP_2__REG DENALI_PHY_599
1432 #define LPDDR4__PHY_NTP_WDQ_STOP_2__FLD LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2
1434 #define LPDDR4__DENALI_PHY_600_READ_MASK 0x0103FFFFU
1435 #define LPDDR4__DENALI_PHY_600_WRITE_MASK 0x0103FFFFU
1436 #define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_MASK 0x000000FFU
1437 #define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_SHIFT 0U
1438 #define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_WIDTH 8U
1439 #define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__REG DENALI_PHY_600
1440 #define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__FLD LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2
1442 #define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_MASK 0x0003FF00U
1443 #define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_SHIFT 8U
1444 #define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_WIDTH 10U
1445 #define LPDDR4__PHY_WDQLVL_DVW_MIN_2__REG DENALI_PHY_600
1446 #define LPDDR4__PHY_WDQLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2
1448 #define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_MASK 0x01000000U
1449 #define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_SHIFT 24U
1450 #define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_WIDTH 1U
1451 #define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_WOCLR 0U
1452 #define LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2_WOSET 0U
1453 #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__REG DENALI_PHY_600
1454 #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2
1456 #define LPDDR4__DENALI_PHY_601_READ_MASK 0x1F1F0F3FU
1457 #define LPDDR4__DENALI_PHY_601_WRITE_MASK 0x1F1F0F3FU
1458 #define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_MASK 0x0000003FU
1459 #define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_SHIFT 0U
1460 #define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_WIDTH 6U
1461 #define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__REG DENALI_PHY_601
1462 #define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2
1464 #define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_MASK 0x00000F00U
1465 #define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_SHIFT 8U
1466 #define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_WIDTH 4U
1467 #define LPDDR4__PHY_FAST_LVL_EN_2__REG DENALI_PHY_601
1468 #define LPDDR4__PHY_FAST_LVL_EN_2__FLD LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2
1470 #define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_MASK 0x001F0000U
1471 #define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_SHIFT 16U
1472 #define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_WIDTH 5U
1473 #define LPDDR4__PHY_PAD_TX_DCD_2__REG DENALI_PHY_601
1474 #define LPDDR4__PHY_PAD_TX_DCD_2__FLD LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2
1476 #define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_MASK 0x1F000000U
1477 #define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_SHIFT 24U
1478 #define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_WIDTH 5U
1479 #define LPDDR4__PHY_PAD_RX_DCD_0_2__REG DENALI_PHY_601
1480 #define LPDDR4__PHY_PAD_RX_DCD_0_2__FLD LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2
1482 #define LPDDR4__DENALI_PHY_602_READ_MASK 0x1F1F1F1FU
1483 #define LPDDR4__DENALI_PHY_602_WRITE_MASK 0x1F1F1F1FU
1484 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_MASK 0x0000001FU
1485 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_SHIFT 0U
1486 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_WIDTH 5U
1487 #define LPDDR4__PHY_PAD_RX_DCD_1_2__REG DENALI_PHY_602
1488 #define LPDDR4__PHY_PAD_RX_DCD_1_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2
1490 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_MASK 0x00001F00U
1491 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_SHIFT 8U
1492 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_WIDTH 5U
1493 #define LPDDR4__PHY_PAD_RX_DCD_2_2__REG DENALI_PHY_602
1494 #define LPDDR4__PHY_PAD_RX_DCD_2_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2
1496 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_MASK 0x001F0000U
1497 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_SHIFT 16U
1498 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_WIDTH 5U
1499 #define LPDDR4__PHY_PAD_RX_DCD_3_2__REG DENALI_PHY_602
1500 #define LPDDR4__PHY_PAD_RX_DCD_3_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2
1502 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_MASK 0x1F000000U
1503 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_SHIFT 24U
1504 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_WIDTH 5U
1505 #define LPDDR4__PHY_PAD_RX_DCD_4_2__REG DENALI_PHY_602
1506 #define LPDDR4__PHY_PAD_RX_DCD_4_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2
1508 #define LPDDR4__DENALI_PHY_603_READ_MASK 0x1F1F1F1FU
1509 #define LPDDR4__DENALI_PHY_603_WRITE_MASK 0x1F1F1F1FU
1510 #define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_MASK 0x0000001FU
1511 #define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_SHIFT 0U
1512 #define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_WIDTH 5U
1513 #define LPDDR4__PHY_PAD_RX_DCD_5_2__REG DENALI_PHY_603
1514 #define LPDDR4__PHY_PAD_RX_DCD_5_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2
1516 #define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_MASK 0x00001F00U
1517 #define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_SHIFT 8U
1518 #define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_WIDTH 5U
1519 #define LPDDR4__PHY_PAD_RX_DCD_6_2__REG DENALI_PHY_603
1520 #define LPDDR4__PHY_PAD_RX_DCD_6_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2
1522 #define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_MASK 0x001F0000U
1523 #define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_SHIFT 16U
1524 #define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_WIDTH 5U
1525 #define LPDDR4__PHY_PAD_RX_DCD_7_2__REG DENALI_PHY_603
1526 #define LPDDR4__PHY_PAD_RX_DCD_7_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2
1528 #define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_MASK 0x1F000000U
1529 #define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_SHIFT 24U
1530 #define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_WIDTH 5U
1531 #define LPDDR4__PHY_PAD_DM_RX_DCD_2__REG DENALI_PHY_603
1532 #define LPDDR4__PHY_PAD_DM_RX_DCD_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2
1534 #define LPDDR4__DENALI_PHY_604_READ_MASK 0x003F1F1FU
1535 #define LPDDR4__DENALI_PHY_604_WRITE_MASK 0x003F1F1FU
1536 #define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_MASK 0x0000001FU
1537 #define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_SHIFT 0U
1538 #define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_WIDTH 5U
1539 #define LPDDR4__PHY_PAD_DQS_RX_DCD_2__REG DENALI_PHY_604
1540 #define LPDDR4__PHY_PAD_DQS_RX_DCD_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2
1542 #define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_MASK 0x00001F00U
1543 #define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_SHIFT 8U
1544 #define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_WIDTH 5U
1545 #define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__REG DENALI_PHY_604
1546 #define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2
1548 #define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_MASK 0x003F0000U
1549 #define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_SHIFT 16U
1550 #define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_WIDTH 6U
1551 #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__REG DENALI_PHY_604
1552 #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2
1554 #define LPDDR4__DENALI_PHY_605_READ_MASK 0x03FF03FFU
1555 #define LPDDR4__DENALI_PHY_605_WRITE_MASK 0x03FF03FFU
1556 #define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_MASK 0x000003FFU
1557 #define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_SHIFT 0U
1558 #define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_WIDTH 10U
1559 #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__REG DENALI_PHY_605
1560 #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2
1562 #define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_MASK 0x03FF0000U
1563 #define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_SHIFT 16U
1564 #define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_WIDTH 10U
1565 #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__REG DENALI_PHY_605
1566 #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2
1568 #define LPDDR4__DENALI_PHY_606_READ_MASK 0x03FF03FFU
1569 #define LPDDR4__DENALI_PHY_606_WRITE_MASK 0x03FF03FFU
1570 #define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_MASK 0x000003FFU
1571 #define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_SHIFT 0U
1572 #define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_WIDTH 10U
1573 #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__REG DENALI_PHY_606
1574 #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2
1576 #define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_MASK 0x03FF0000U
1577 #define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_SHIFT 16U
1578 #define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_WIDTH 10U
1579 #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__REG DENALI_PHY_606
1580 #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2
1582 #define LPDDR4__DENALI_PHY_607_READ_MASK 0x03FF03FFU
1583 #define LPDDR4__DENALI_PHY_607_WRITE_MASK 0x03FF03FFU
1584 #define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_MASK 0x000003FFU
1585 #define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_SHIFT 0U
1586 #define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_WIDTH 10U
1587 #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__REG DENALI_PHY_607
1588 #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2
1590 #define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_MASK 0x03FF0000U
1591 #define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_SHIFT 16U
1592 #define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_WIDTH 10U
1593 #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__REG DENALI_PHY_607
1594 #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2
1596 #define LPDDR4__DENALI_PHY_608_READ_MASK 0x03FF03FFU
1597 #define LPDDR4__DENALI_PHY_608_WRITE_MASK 0x03FF03FFU
1598 #define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_MASK 0x000003FFU
1599 #define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_SHIFT 0U
1600 #define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_WIDTH 10U
1601 #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__REG DENALI_PHY_608
1602 #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2
1604 #define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_MASK 0x03FF0000U
1605 #define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_SHIFT 16U
1606 #define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_WIDTH 10U
1607 #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__REG DENALI_PHY_608
1608 #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2
1610 #define LPDDR4__DENALI_PHY_609_READ_MASK 0x000703FFU
1611 #define LPDDR4__DENALI_PHY_609_WRITE_MASK 0x000703FFU
1612 #define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_MASK 0x000003FFU
1613 #define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_SHIFT 0U
1614 #define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_WIDTH 10U
1615 #define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__REG DENALI_PHY_609
1616 #define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2
1618 #define LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2_MASK 0x00070000U
1619 #define LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2_SHIFT 16U
1620 #define LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2_WIDTH 3U
1621 #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__REG DENALI_PHY_609
1622 #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2
1624 #define LPDDR4__DENALI_PHY_610_READ_MASK 0xFFFFFFFFU
1625 #define LPDDR4__DENALI_PHY_610_WRITE_MASK 0xFFFFFFFFU
1626 #define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_MASK 0x000000FFU
1627 #define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_SHIFT 0U
1628 #define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_WIDTH 8U
1629 #define LPDDR4__PHY_DQ_OE_TIMING_2__REG DENALI_PHY_610
1630 #define LPDDR4__PHY_DQ_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2
1632 #define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_MASK 0x0000FF00U
1633 #define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_SHIFT 8U
1634 #define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_WIDTH 8U
1635 #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__REG DENALI_PHY_610
1636 #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2
1638 #define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_MASK 0x00FF0000U
1639 #define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_SHIFT 16U
1640 #define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_WIDTH 8U
1641 #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__REG DENALI_PHY_610
1642 #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2
1644 #define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_MASK 0xFF000000U
1645 #define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_SHIFT 24U
1646 #define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_WIDTH 8U
1647 #define LPDDR4__PHY_DQS_OE_TIMING_2__REG DENALI_PHY_610
1648 #define LPDDR4__PHY_DQS_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2
1650 #define LPDDR4__DENALI_PHY_611_READ_MASK 0xFFFFFF0FU
1651 #define LPDDR4__DENALI_PHY_611_WRITE_MASK 0xFFFFFF0FU
1652 #define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_MASK 0x0000000FU
1653 #define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_SHIFT 0U
1654 #define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_WIDTH 4U
1655 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__REG DENALI_PHY_611
1656 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2
1658 #define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_MASK 0x0000FF00U
1659 #define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_SHIFT 8U
1660 #define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_WIDTH 8U
1661 #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__REG DENALI_PHY_611
1662 #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2
1664 #define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_MASK 0x00FF0000U
1665 #define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_SHIFT 16U
1666 #define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_WIDTH 8U
1667 #define LPDDR4__PHY_DQS_OE_RD_TIMING_2__REG DENALI_PHY_611
1668 #define LPDDR4__PHY_DQS_OE_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2
1670 #define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_MASK 0xFF000000U
1671 #define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_SHIFT 24U
1672 #define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_WIDTH 8U
1673 #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__REG DENALI_PHY_611
1674 #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2
1676 #define LPDDR4__DENALI_PHY_612_READ_MASK 0x0FFFFFFFU
1677 #define LPDDR4__DENALI_PHY_612_WRITE_MASK 0x0FFFFFFFU
1678 #define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_MASK 0x0000FFFFU
1679 #define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_SHIFT 0U
1680 #define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_WIDTH 16U
1681 #define LPDDR4__PHY_VREF_SETTING_TIME_2__REG DENALI_PHY_612
1682 #define LPDDR4__PHY_VREF_SETTING_TIME_2__FLD LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2
1684 #define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_MASK 0x0FFF0000U
1685 #define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_SHIFT 16U
1686 #define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_WIDTH 12U
1687 #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__REG DENALI_PHY_612
1688 #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__FLD LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2
1690 #define LPDDR4__DENALI_PHY_613_READ_MASK 0x03FFFF01U
1691 #define LPDDR4__DENALI_PHY_613_WRITE_MASK 0x03FFFF01U
1692 #define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_MASK 0x00000001U
1693 #define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_SHIFT 0U
1694 #define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WIDTH 1U
1695 #define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOCLR 0U
1696 #define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOSET 0U
1697 #define LPDDR4__PHY_PER_CS_TRAINING_EN_2__REG DENALI_PHY_613
1698 #define LPDDR4__PHY_PER_CS_TRAINING_EN_2__FLD LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2
1700 #define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_MASK 0x0000FF00U
1701 #define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_SHIFT 8U
1702 #define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_WIDTH 8U
1703 #define LPDDR4__PHY_DQ_IE_TIMING_2__REG DENALI_PHY_613
1704 #define LPDDR4__PHY_DQ_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2
1706 #define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_MASK 0x00FF0000U
1707 #define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_SHIFT 16U
1708 #define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_WIDTH 8U
1709 #define LPDDR4__PHY_DQS_IE_TIMING_2__REG DENALI_PHY_613
1710 #define LPDDR4__PHY_DQS_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2
1712 #define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_MASK 0x03000000U
1713 #define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_SHIFT 24U
1714 #define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_WIDTH 2U
1715 #define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_613
1716 #define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2
1718 #define LPDDR4__DENALI_PHY_614_READ_MASK 0x1F1F0103U
1719 #define LPDDR4__DENALI_PHY_614_WRITE_MASK 0x1F1F0103U
1720 #define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_MASK 0x00000003U
1721 #define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_SHIFT 0U
1722 #define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_WIDTH 2U
1723 #define LPDDR4__PHY_IE_MODE_2__REG DENALI_PHY_614
1724 #define LPDDR4__PHY_IE_MODE_2__FLD LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2
1726 #define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_MASK 0x00000100U
1727 #define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_SHIFT 8U
1728 #define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WIDTH 1U
1729 #define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOCLR 0U
1730 #define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOSET 0U
1731 #define LPDDR4__PHY_DBI_MODE_2__REG DENALI_PHY_614
1732 #define LPDDR4__PHY_DBI_MODE_2__FLD LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2
1734 #define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_MASK 0x001F0000U
1735 #define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_SHIFT 16U
1736 #define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_WIDTH 5U
1737 #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_614
1738 #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2
1740 #define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_MASK 0x1F000000U
1741 #define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_SHIFT 24U
1742 #define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_WIDTH 5U
1743 #define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_614
1744 #define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2
1746 #define LPDDR4__DENALI_PHY_615_READ_MASK 0x3F07FF0FU
1747 #define LPDDR4__DENALI_PHY_615_WRITE_MASK 0x3F07FF0FU
1748 #define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_MASK 0x0000000FU
1749 #define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_SHIFT 0U
1750 #define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_WIDTH 4U
1751 #define LPDDR4__PHY_SW_MASTER_MODE_2__REG DENALI_PHY_615
1752 #define LPDDR4__PHY_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2
1754 #define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_MASK 0x0007FF00U
1755 #define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_SHIFT 8U
1756 #define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_WIDTH 11U
1757 #define LPDDR4__PHY_MASTER_DELAY_START_2__REG DENALI_PHY_615
1758 #define LPDDR4__PHY_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2
1760 #define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_MASK 0x3F000000U
1761 #define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_SHIFT 24U
1762 #define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_WIDTH 6U
1763 #define LPDDR4__PHY_MASTER_DELAY_STEP_2__REG DENALI_PHY_615
1764 #define LPDDR4__PHY_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2
1766 #define LPDDR4__DENALI_PHY_616_READ_MASK 0xFF0FFFFFU
1767 #define LPDDR4__DENALI_PHY_616_WRITE_MASK 0xFF0FFFFFU
1768 #define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_MASK 0x000000FFU
1769 #define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_SHIFT 0U
1770 #define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_WIDTH 8U
1771 #define LPDDR4__PHY_MASTER_DELAY_WAIT_2__REG DENALI_PHY_616
1772 #define LPDDR4__PHY_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2
1774 #define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2_MASK 0x0000FF00U
1775 #define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2_SHIFT 8U
1776 #define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2_WIDTH 8U
1777 #define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_616
1778 #define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2
1780 #define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_MASK 0x000F0000U
1781 #define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_SHIFT 16U
1782 #define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_WIDTH 4U
1783 #define LPDDR4__PHY_RPTR_UPDATE_2__REG DENALI_PHY_616
1784 #define LPDDR4__PHY_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2
1786 #define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_MASK 0xFF000000U
1787 #define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_SHIFT 24U
1788 #define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_WIDTH 8U
1789 #define LPDDR4__PHY_WRLVL_DLY_STEP_2__REG DENALI_PHY_616
1790 #define LPDDR4__PHY_WRLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2
1792 #define LPDDR4__DENALI_PHY_617_READ_MASK 0x1F0F3F0FU
1793 #define LPDDR4__DENALI_PHY_617_WRITE_MASK 0x1F0F3F0FU
1794 #define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_MASK 0x0000000FU
1795 #define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_SHIFT 0U
1796 #define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_WIDTH 4U
1797 #define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_2__REG DENALI_PHY_617
1798 #define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_2__FLD LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2
1800 #define LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2_MASK 0x00003F00U
1801 #define LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2_SHIFT 8U
1802 #define LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2_WIDTH 6U
1803 #define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_617
1804 #define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2
1806 #define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_MASK 0x000F0000U
1807 #define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_SHIFT 16U
1808 #define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_WIDTH 4U
1809 #define LPDDR4__PHY_GTLVL_DLY_STEP_2__REG DENALI_PHY_617
1810 #define LPDDR4__PHY_GTLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2
1812 #define LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2_MASK 0x1F000000U
1813 #define LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2_SHIFT 24U
1814 #define LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2_WIDTH 5U
1815 #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_617
1816 #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2
1818 #define LPDDR4__DENALI_PHY_618_READ_MASK 0x03FF03FFU
1819 #define LPDDR4__DENALI_PHY_618_WRITE_MASK 0x03FF03FFU
1820 #define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_MASK 0x000003FFU
1821 #define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_SHIFT 0U
1822 #define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_WIDTH 10U
1823 #define LPDDR4__PHY_GTLVL_BACK_STEP_2__REG DENALI_PHY_618
1824 #define LPDDR4__PHY_GTLVL_BACK_STEP_2__FLD LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2
1826 #define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_MASK 0x03FF0000U
1827 #define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_SHIFT 16U
1828 #define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_WIDTH 10U
1829 #define LPDDR4__PHY_GTLVL_FINAL_STEP_2__REG DENALI_PHY_618
1830 #define LPDDR4__PHY_GTLVL_FINAL_STEP_2__FLD LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2
1832 #define LPDDR4__DENALI_PHY_619_READ_MASK 0x0F010FFFU
1833 #define LPDDR4__DENALI_PHY_619_WRITE_MASK 0x0F010FFFU
1834 #define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_MASK 0x000000FFU
1835 #define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_SHIFT 0U
1836 #define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_WIDTH 8U
1837 #define LPDDR4__PHY_WDQLVL_DLY_STEP_2__REG DENALI_PHY_619
1838 #define LPDDR4__PHY_WDQLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2
1840 #define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2_MASK 0x00000F00U
1841 #define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2_SHIFT 8U
1842 #define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2_WIDTH 4U
1843 #define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_2__REG DENALI_PHY_619
1844 #define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_WDQLVL_QTR_DLY_STEP_2
1846 #define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_MASK 0x00010000U
1847 #define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_SHIFT 16U
1848 #define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WIDTH 1U
1849 #define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOCLR 0U
1850 #define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOSET 0U
1851 #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__REG DENALI_PHY_619
1852 #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__FLD LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2
1854 #define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_MASK 0x0F000000U
1855 #define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_SHIFT 24U
1856 #define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_WIDTH 4U
1857 #define LPDDR4__PHY_RDLVL_DLY_STEP_2__REG DENALI_PHY_619
1858 #define LPDDR4__PHY_RDLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2
1860 #define LPDDR4__DENALI_PHY_620_READ_MASK 0x000003FFU
1861 #define LPDDR4__DENALI_PHY_620_WRITE_MASK 0x000003FFU
1862 #define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_MASK 0x000003FFU
1863 #define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_SHIFT 0U
1864 #define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_WIDTH 10U
1865 #define LPDDR4__PHY_RDLVL_MAX_EDGE_2__REG DENALI_PHY_620
1866 #define LPDDR4__PHY_RDLVL_MAX_EDGE_2__FLD LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2
1868 #define LPDDR4__DENALI_PHY_621_READ_MASK 0x3F0103FFU
1869 #define LPDDR4__DENALI_PHY_621_WRITE_MASK 0x3F0103FFU
1870 #define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_MASK 0x000003FFU
1871 #define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_SHIFT 0U
1872 #define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_WIDTH 10U
1873 #define LPDDR4__PHY_RDLVL_DVW_MIN_2__REG DENALI_PHY_621
1874 #define LPDDR4__PHY_RDLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2
1876 #define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_MASK 0x00010000U
1877 #define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_SHIFT 16U
1878 #define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_WIDTH 1U
1879 #define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_WOCLR 0U
1880 #define LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2_WOSET 0U
1881 #define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_2__REG DENALI_PHY_621
1882 #define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_621__PHY_SW_RDLVL_DVW_MIN_EN_2
1884 #define LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2_MASK 0x3F000000U
1885 #define LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2_SHIFT 24U
1886 #define LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2_WIDTH 6U
1887 #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_2__REG DENALI_PHY_621
1888 #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2
1890 #define LPDDR4__DENALI_PHY_622_READ_MASK 0x00030703U
1891 #define LPDDR4__DENALI_PHY_622_WRITE_MASK 0x00030703U
1892 #define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_MASK 0x00000003U
1893 #define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_SHIFT 0U
1894 #define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_WIDTH 2U
1895 #define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__REG DENALI_PHY_622
1896 #define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2
1898 #define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_MASK 0x00000700U
1899 #define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_SHIFT 8U
1900 #define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_WIDTH 3U
1901 #define LPDDR4__PHY_WRPATH_GATE_TIMING_2__REG DENALI_PHY_622
1902 #define LPDDR4__PHY_WRPATH_GATE_TIMING_2__FLD LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2
1904 #define LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2_MASK 0x00030000U
1905 #define LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2_SHIFT 16U
1906 #define LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2_WIDTH 2U
1907 #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__REG DENALI_PHY_622
1908 #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2
1910 #define LPDDR4__DENALI_PHY_623_READ_MASK 0x07FF03FFU
1911 #define LPDDR4__DENALI_PHY_623_WRITE_MASK 0x07FF03FFU
1912 #define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_MASK 0x000003FFU
1913 #define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_SHIFT 0U
1914 #define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_WIDTH 10U
1915 #define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2__REG DENALI_PHY_623
1916 #define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2
1918 #define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_MASK 0x07FF0000U
1919 #define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_SHIFT 16U
1920 #define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_WIDTH 11U
1921 #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__REG DENALI_PHY_623
1922 #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2
1924 #define LPDDR4__DENALI_PHY_624_READ_MASK 0xFFFF0101U
1925 #define LPDDR4__DENALI_PHY_624_WRITE_MASK 0xFFFF0101U
1926 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_MASK 0x00000001U
1927 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_SHIFT 0U
1928 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_WIDTH 1U
1929 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_WOCLR 0U
1930 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_WOSET 0U
1931 #define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_2__REG DENALI_PHY_624
1932 #define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2
1934 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_MASK 0x00000100U
1935 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_SHIFT 8U
1936 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_WIDTH 1U
1937 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_WOCLR 0U
1938 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2_WOSET 0U
1939 #define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_2__REG DENALI_PHY_624
1940 #define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WDQLVL_ENABLE_2
1942 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_MASK 0x00FF0000U
1943 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_SHIFT 16U
1944 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_WIDTH 8U
1945 #define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2__REG DENALI_PHY_624
1946 #define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2
1948 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_MASK 0xFF000000U
1949 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_SHIFT 24U
1950 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_WIDTH 8U
1951 #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__REG DENALI_PHY_624
1952 #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2
1954 #define LPDDR4__DENALI_PHY_625_READ_MASK 0x001F3F7FU
1955 #define LPDDR4__DENALI_PHY_625_WRITE_MASK 0x001F3F7FU
1956 #define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_MASK 0x0000007FU
1957 #define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_SHIFT 0U
1958 #define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_WIDTH 7U
1959 #define LPDDR4__PHY_WDQ_OSC_DELTA_2__REG DENALI_PHY_625
1960 #define LPDDR4__PHY_WDQ_OSC_DELTA_2__FLD LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2
1962 #define LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2_MASK 0x00003F00U
1963 #define LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2_SHIFT 8U
1964 #define LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2_WIDTH 6U
1965 #define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_625
1966 #define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2
1968 #define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_MASK 0x001F0000U
1969 #define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_SHIFT 16U
1970 #define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_WIDTH 5U
1971 #define LPDDR4__PHY_RDDATA_EN_DLY_2__REG DENALI_PHY_625
1972 #define LPDDR4__PHY_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2
1974 #define LPDDR4__DENALI_PHY_626_READ_MASK 0xFFFFFFFFU
1975 #define LPDDR4__DENALI_PHY_626_WRITE_MASK 0xFFFFFFFFU
1976 #define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_MASK 0xFFFFFFFFU
1977 #define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_SHIFT 0U
1978 #define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_WIDTH 32U
1979 #define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__REG DENALI_PHY_626
1980 #define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2
1982 #define LPDDR4__DENALI_PHY_627_READ_MASK 0x0000000FU
1983 #define LPDDR4__DENALI_PHY_627_WRITE_MASK 0x0000000FU
1984 #define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_MASK 0x0000000FU
1985 #define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_SHIFT 0U
1986 #define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_WIDTH 4U
1987 #define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__REG DENALI_PHY_627
1988 #define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2
1990 #define LPDDR4__DENALI_PHY_628_READ_MASK 0x07FF07FFU
1991 #define LPDDR4__DENALI_PHY_628_WRITE_MASK 0x07FF07FFU
1992 #define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_MASK 0x000007FFU
1993 #define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_SHIFT 0U
1994 #define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_WIDTH 11U
1995 #define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_2__REG DENALI_PHY_628
1996 #define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2
1998 #define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2_MASK 0x07FF0000U
1999 #define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2_SHIFT 16U
2000 #define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2_WIDTH 11U
2001 #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__REG DENALI_PHY_628
2002 #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2
2004 #define LPDDR4__DENALI_PHY_629_READ_MASK 0x07FF07FFU
2005 #define LPDDR4__DENALI_PHY_629_WRITE_MASK 0x07FF07FFU
2006 #define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_MASK 0x000007FFU
2007 #define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_SHIFT 0U
2008 #define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_WIDTH 11U
2009 #define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_2__REG DENALI_PHY_629
2010 #define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2
2012 #define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2_MASK 0x07FF0000U
2013 #define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2_SHIFT 16U
2014 #define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2_WIDTH 11U
2015 #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__REG DENALI_PHY_629
2016 #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2
2018 #define LPDDR4__DENALI_PHY_630_READ_MASK 0x07FF07FFU
2019 #define LPDDR4__DENALI_PHY_630_WRITE_MASK 0x07FF07FFU
2020 #define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_MASK 0x000007FFU
2021 #define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_SHIFT 0U
2022 #define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_WIDTH 11U
2023 #define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_2__REG DENALI_PHY_630
2024 #define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2
2026 #define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2_MASK 0x07FF0000U
2027 #define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2_SHIFT 16U
2028 #define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2_WIDTH 11U
2029 #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__REG DENALI_PHY_630
2030 #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2
2032 #define LPDDR4__DENALI_PHY_631_READ_MASK 0x07FF07FFU
2033 #define LPDDR4__DENALI_PHY_631_WRITE_MASK 0x07FF07FFU
2034 #define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_MASK 0x000007FFU
2035 #define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_SHIFT 0U
2036 #define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_WIDTH 11U
2037 #define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_2__REG DENALI_PHY_631
2038 #define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2
2040 #define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2_MASK 0x07FF0000U
2041 #define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2_SHIFT 16U
2042 #define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2_WIDTH 11U
2043 #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__REG DENALI_PHY_631
2044 #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2
2046 #define LPDDR4__DENALI_PHY_632_READ_MASK 0x03FF07FFU
2047 #define LPDDR4__DENALI_PHY_632_WRITE_MASK 0x03FF07FFU
2048 #define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_MASK 0x000007FFU
2049 #define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_SHIFT 0U
2050 #define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_WIDTH 11U
2051 #define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_2__REG DENALI_PHY_632
2052 #define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2
2054 #define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2_MASK 0x03FF0000U
2055 #define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2_SHIFT 16U
2056 #define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2_WIDTH 10U
2057 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__REG DENALI_PHY_632
2058 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2
2060 #define LPDDR4__DENALI_PHY_633_READ_MASK 0x0003FF03U
2061 #define LPDDR4__DENALI_PHY_633_WRITE_MASK 0x0003FF03U
2062 #define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_MASK 0x00000003U
2063 #define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_SHIFT 0U
2064 #define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_WIDTH 2U
2065 #define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_2__REG DENALI_PHY_633
2066 #define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_2__FLD LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2
2068 #define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_MASK 0x0003FF00U
2069 #define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_SHIFT 8U
2070 #define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_WIDTH 10U
2071 #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__REG DENALI_PHY_633
2072 #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2
2074 #define LPDDR4__DENALI_PHY_634_READ_MASK 0x03FF03FFU
2075 #define LPDDR4__DENALI_PHY_634_WRITE_MASK 0x03FF03FFU
2076 #define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
2077 #define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_SHIFT 0U
2078 #define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_WIDTH 10U
2079 #define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2__REG DENALI_PHY_634
2080 #define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2
2082 #define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
2083 #define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_SHIFT 16U
2084 #define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_WIDTH 10U
2085 #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__REG DENALI_PHY_634
2086 #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2
2088 #define LPDDR4__DENALI_PHY_635_READ_MASK 0x03FF03FFU
2089 #define LPDDR4__DENALI_PHY_635_WRITE_MASK 0x03FF03FFU
2090 #define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
2091 #define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_SHIFT 0U
2092 #define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_WIDTH 10U
2093 #define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2__REG DENALI_PHY_635
2094 #define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2
2096 #define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
2097 #define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_SHIFT 16U
2098 #define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_WIDTH 10U
2099 #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__REG DENALI_PHY_635
2100 #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2
2102 #define LPDDR4__DENALI_PHY_636_READ_MASK 0x03FF03FFU
2103 #define LPDDR4__DENALI_PHY_636_WRITE_MASK 0x03FF03FFU
2104 #define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
2105 #define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_SHIFT 0U
2106 #define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_WIDTH 10U
2107 #define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2__REG DENALI_PHY_636
2108 #define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2
2110 #define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
2111 #define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_SHIFT 16U
2112 #define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_WIDTH 10U
2113 #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__REG DENALI_PHY_636
2114 #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2
2116 #define LPDDR4__DENALI_PHY_637_READ_MASK 0x03FF03FFU
2117 #define LPDDR4__DENALI_PHY_637_WRITE_MASK 0x03FF03FFU
2118 #define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
2119 #define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_SHIFT 0U
2120 #define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_WIDTH 10U
2121 #define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2__REG DENALI_PHY_637
2122 #define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2
2124 #define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
2125 #define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_SHIFT 16U
2126 #define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_WIDTH 10U
2127 #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__REG DENALI_PHY_637
2128 #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2
2130 #define LPDDR4__DENALI_PHY_638_READ_MASK 0x03FF03FFU
2131 #define LPDDR4__DENALI_PHY_638_WRITE_MASK 0x03FF03FFU
2132 #define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
2133 #define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_SHIFT 0U
2134 #define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_WIDTH 10U
2135 #define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2__REG DENALI_PHY_638
2136 #define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2
2138 #define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
2139 #define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_SHIFT 16U
2140 #define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_WIDTH 10U
2141 #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__REG DENALI_PHY_638
2142 #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2
2144 #define LPDDR4__DENALI_PHY_639_READ_MASK 0x03FF03FFU
2145 #define LPDDR4__DENALI_PHY_639_WRITE_MASK 0x03FF03FFU
2146 #define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
2147 #define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_SHIFT 0U
2148 #define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_WIDTH 10U
2149 #define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2__REG DENALI_PHY_639
2150 #define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2
2152 #define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
2153 #define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_SHIFT 16U
2154 #define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_WIDTH 10U
2155 #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__REG DENALI_PHY_639
2156 #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2
2158 #define LPDDR4__DENALI_PHY_640_READ_MASK 0x03FF03FFU
2159 #define LPDDR4__DENALI_PHY_640_WRITE_MASK 0x03FF03FFU
2160 #define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
2161 #define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_SHIFT 0U
2162 #define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_WIDTH 10U
2163 #define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2__REG DENALI_PHY_640
2164 #define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2
2166 #define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
2167 #define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_SHIFT 16U
2168 #define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_WIDTH 10U
2169 #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__REG DENALI_PHY_640
2170 #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2
2172 #define LPDDR4__DENALI_PHY_641_READ_MASK 0x03FF03FFU
2173 #define LPDDR4__DENALI_PHY_641_WRITE_MASK 0x03FF03FFU
2174 #define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
2175 #define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_SHIFT 0U
2176 #define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_WIDTH 10U
2177 #define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2__REG DENALI_PHY_641
2178 #define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2
2180 #define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U
2181 #define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_SHIFT 16U
2182 #define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_WIDTH 10U
2183 #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__REG DENALI_PHY_641
2184 #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2
2186 #define LPDDR4__DENALI_PHY_642_READ_MASK 0x03FF03FFU
2187 #define LPDDR4__DENALI_PHY_642_WRITE_MASK 0x03FF03FFU
2188 #define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
2189 #define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_SHIFT 0U
2190 #define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_WIDTH 10U
2191 #define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2__REG DENALI_PHY_642
2192 #define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2
2194 #define LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2_MASK 0x03FF0000U
2195 #define LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2_SHIFT 16U
2196 #define LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2_WIDTH 10U
2197 #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__REG DENALI_PHY_642
2198 #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2
2200 #define LPDDR4__DENALI_PHY_643_READ_MASK 0x03FF070FU
2201 #define LPDDR4__DENALI_PHY_643_WRITE_MASK 0x03FF070FU
2202 #define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_MASK 0x0000000FU
2203 #define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_SHIFT 0U
2204 #define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_WIDTH 4U
2205 #define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__REG DENALI_PHY_643
2206 #define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2
2208 #define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_MASK 0x00000700U
2209 #define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_SHIFT 8U
2210 #define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_WIDTH 3U
2211 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__REG DENALI_PHY_643
2212 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__FLD LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2
2214 #define LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_MASK 0x03FF0000U
2215 #define LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_SHIFT 16U
2216 #define LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_WIDTH 10U
2217 #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__REG DENALI_PHY_643
2218 #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2
2220 #define LPDDR4__DENALI_PHY_644_READ_MASK 0x000103FFU
2221 #define LPDDR4__DENALI_PHY_644_WRITE_MASK 0x000103FFU
2222 #define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_MASK 0x000003FFU
2223 #define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_SHIFT 0U
2224 #define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_WIDTH 10U
2225 #define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2__REG DENALI_PHY_644
2226 #define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2
2228 #define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_MASK 0x00010000U
2229 #define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_SHIFT 16U
2230 #define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_WIDTH 1U
2231 #define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_WOCLR 0U
2232 #define LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2_WOSET 0U
2233 #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__REG DENALI_PHY_644
2234 #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__FLD LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2
2236 #define LPDDR4__DENALI_PHY_645_READ_MASK 0x000F03FFU
2237 #define LPDDR4__DENALI_PHY_645_WRITE_MASK 0x000F03FFU
2238 #define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_MASK 0x000003FFU
2239 #define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_SHIFT 0U
2240 #define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_WIDTH 10U
2241 #define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_2__REG DENALI_PHY_645
2242 #define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2
2244 #define LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2_MASK 0x000F0000U
2245 #define LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2_SHIFT 16U
2246 #define LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2_WIDTH 4U
2247 #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__REG DENALI_PHY_645
2248 #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__FLD LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2
2250 #define LPDDR4__DENALI_PHY_646_READ_MASK 0x010F07FFU
2251 #define LPDDR4__DENALI_PHY_646_WRITE_MASK 0x010F07FFU
2252 #define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_MASK 0x000007FFU
2253 #define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_SHIFT 0U
2254 #define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_WIDTH 11U
2255 #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__REG DENALI_PHY_646
2256 #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2
2258 #define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_MASK 0x000F0000U
2259 #define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_SHIFT 16U
2260 #define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_WIDTH 4U
2261 #define LPDDR4__PHY_NTP_WRLAT_START_2__REG DENALI_PHY_646
2262 #define LPDDR4__PHY_NTP_WRLAT_START_2__FLD LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2
2264 #define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_MASK 0x01000000U
2265 #define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_SHIFT 24U
2266 #define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WIDTH 1U
2267 #define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOCLR 0U
2268 #define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOSET 0U
2269 #define LPDDR4__PHY_NTP_PASS_2__REG DENALI_PHY_646
2270 #define LPDDR4__PHY_NTP_PASS_2__FLD LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2
2272 #define LPDDR4__DENALI_PHY_647_READ_MASK 0x000003FFU
2273 #define LPDDR4__DENALI_PHY_647_WRITE_MASK 0x000003FFU
2274 #define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_MASK 0x000003FFU
2275 #define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_SHIFT 0U
2276 #define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_WIDTH 10U
2277 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__REG DENALI_PHY_647
2278 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2
2280 #define LPDDR4__DENALI_PHY_648_READ_MASK 0xFFFFFFFFU
2281 #define LPDDR4__DENALI_PHY_648_WRITE_MASK 0xFFFFFFFFU
2282 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_MASK 0x000000FFU
2283 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_SHIFT 0U
2284 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_WIDTH 8U
2285 #define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_2__REG DENALI_PHY_648
2286 #define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2
2288 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2_MASK 0x0000FF00U
2289 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2_SHIFT 8U
2290 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2_WIDTH 8U
2291 #define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_2__REG DENALI_PHY_648
2292 #define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ0_CLK_ADJUST_2
2294 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2_MASK 0x00FF0000U
2295 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2_SHIFT 16U
2296 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2_WIDTH 8U
2297 #define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_2__REG DENALI_PHY_648
2298 #define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ1_CLK_ADJUST_2
2300 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2_MASK 0xFF000000U
2301 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2_SHIFT 24U
2302 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2_WIDTH 8U
2303 #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__REG DENALI_PHY_648
2304 #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2
2306 #define LPDDR4__DENALI_PHY_649_READ_MASK 0xFFFFFFFFU
2307 #define LPDDR4__DENALI_PHY_649_WRITE_MASK 0xFFFFFFFFU
2308 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_MASK 0x000000FFU
2309 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_SHIFT 0U
2310 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_WIDTH 8U
2311 #define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_2__REG DENALI_PHY_649
2312 #define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2
2314 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2_MASK 0x0000FF00U
2315 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2_SHIFT 8U
2316 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2_WIDTH 8U
2317 #define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_2__REG DENALI_PHY_649
2318 #define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ4_CLK_ADJUST_2
2320 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2_MASK 0x00FF0000U
2321 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2_SHIFT 16U
2322 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2_WIDTH 8U
2323 #define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_2__REG DENALI_PHY_649
2324 #define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ5_CLK_ADJUST_2
2326 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2_MASK 0xFF000000U
2327 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2_SHIFT 24U
2328 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2_WIDTH 8U
2329 #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__REG DENALI_PHY_649
2330 #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2
2332 #define LPDDR4__DENALI_PHY_650_READ_MASK 0xFFFFFFFFU
2333 #define LPDDR4__DENALI_PHY_650_WRITE_MASK 0xFFFFFFFFU
2334 #define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_MASK 0x000000FFU
2335 #define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_SHIFT 0U
2336 #define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_WIDTH 8U
2337 #define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_2__REG DENALI_PHY_650
2338 #define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2
2340 #define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2_MASK 0x0000FF00U
2341 #define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2_SHIFT 8U
2342 #define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2_WIDTH 8U
2343 #define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_2__REG DENALI_PHY_650
2344 #define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DM_CLK_ADJUST_2
2346 #define LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_MASK 0xFFFF0000U
2347 #define LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_SHIFT 16U
2348 #define LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_WIDTH 16U
2349 #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__REG DENALI_PHY_650
2350 #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__FLD LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2
2352 #define LPDDR4__DENALI_PHY_651_READ_MASK 0x0003033FU
2353 #define LPDDR4__DENALI_PHY_651_WRITE_MASK 0x0003033FU
2354 #define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_MASK 0x0000003FU
2355 #define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_SHIFT 0U
2356 #define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_WIDTH 6U
2357 #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__REG DENALI_PHY_651
2358 #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__FLD LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2
2360 #define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_MASK 0x00000300U
2361 #define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_SHIFT 8U
2362 #define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_WIDTH 2U
2363 #define LPDDR4__PHY_DQ_FFE_2__REG DENALI_PHY_651
2364 #define LPDDR4__PHY_DQ_FFE_2__FLD LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2
2366 #define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_MASK 0x00030000U
2367 #define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_SHIFT 16U
2368 #define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_WIDTH 2U
2369 #define LPDDR4__PHY_DQS_FFE_2__REG DENALI_PHY_651
2370 #define LPDDR4__PHY_DQS_FFE_2__FLD LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2
2372 #endif /* REG_LPDDR4_DATA_SLICE_2_MACROS_H_ */