drivers/pinctrl/sh-pfc/pfc-r8a7791.c

   1 /*
   2  * r8a7791 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2
   8  * as published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/platform_data/gpio-rcar.h>
  13
  14 #include "core.h"
  15 #include "sh_pfc.h"
  16
  17 #define CPU_ALL_PORT(fn, sfx)                                           \
  18         PORT_GP_32(0, fn, sfx),                                         \
  19         PORT_GP_32(1, fn, sfx),                                         \
  20         PORT_GP_32(2, fn, sfx),                                         \
  21         PORT_GP_32(3, fn, sfx),                                         \
  22         PORT_GP_32(4, fn, sfx),                                         \
  23         PORT_GP_32(5, fn, sfx),                                         \
  24         PORT_GP_32(6, fn, sfx),                                         \
  25         PORT_GP_32(7, fn, sfx)
  26
  27 enum {
  28         PINMUX_RESERVED = 0,
  29
  30         PINMUX_DATA_BEGIN,
  31         GP_ALL(DATA),
  32         PINMUX_DATA_END,
  33
  34         PINMUX_FUNCTION_BEGIN,
  35         GP_ALL(FN),
  36
  37         /* GPSR0 */
  38         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  39         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  40         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
  41         FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
  42         FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
  43         FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
  44
  45         /* GPSR1 */
  46         FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
  47         FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
  48         FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
  49         FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
  50         FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
  51         FN_IP3_21_20,
  52
  53         /* GPSR2 */
  54         FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
  55         FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
  56         FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
  57         FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
  58         FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
  59         FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
  60         FN_IP6_5_3, FN_IP6_7_6,
  61
  62         /* GPSR3 */
  63         FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
  64         FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
  65         FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
  66         FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
  67         FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
  68         FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
  69         FN_IP9_18_17,
  70
  71         /* GPSR4 */
  72         FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
  73         FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
  74         FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
  75         FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
  76         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
  77         FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
  78         FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
  79         FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
  80
  81         /* GPSR5 */
  82         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
  83         FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
  84         FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
  85         FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
  86         FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
  87         FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
  88         FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
  89
  90         /* GPSR6 */
  91         FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
  92         FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
  93         FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
  94         FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
  95         FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
  96         FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
  97         FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
  98         FN_USB1_OVC, FN_DU0_DOTCLKIN,
  99
 100         /* GPSR7 */
 101         FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
 102         FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
 103         FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
 104         FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
 105         FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
 106         FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
 107
 108         /* IPSR0 */
 109         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
 110         FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
 111         FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
 112         FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
 113         FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
 114         FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
 115
 116         /* IPSR1 */
 117         FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0,
 118         FN_A9, FN_MSIOF1_SS2, FN_SDA0,
 119         FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
 120         FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
 121         FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
 122         FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
 123         FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
 124         FN_A15, FN_BPFCLK_C,
 125         FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
 126         FN_A17, FN_DACK2_B, FN_SDA0_C,
 127         FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
 128
 129         /* IPSR2 */
 130         FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
 131         FN_A20, FN_SPCLK,
 132         FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
 133         FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
 134         FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
 135         FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
 136         FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
 137         FN_CS0_N, FN_ATAG0_N_B, FN_SCL1,
 138         FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1,
 139         FN_EX_CS1_N, FN_MSIOF2_SCK,
 140         FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
 141         FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
 142
 143         /* IPSR3 */
 144         FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
 145         FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
 146         FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
 147         FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
 148         FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
 149         FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
 150         FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
 151         FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
 152         FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
 153         FN_DREQ0, FN_PWM3, FN_TPU_TO3,
 154         FN_DACK0, FN_DRACK0, FN_REMOCON,
 155         FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
 156         FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
 157         FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
 158         FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
 159
 160         /* IPSR4 */
 161         FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C,
 162         FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
 163         FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
 164         FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
 165         FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
 166         FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
 167         FN_GLO_Q1_D, FN_HCTS1_N_E,
 168         FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
 169         FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
 170         FN_SSI_SCK4, FN_GLO_SS_D,
 171         FN_SSI_WS4, FN_GLO_RFON_D,
 172         FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
 173         FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
 174         FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
 175
 176         /* IPSR5 */
 177         FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
 178         FN_MSIOF2_TXD_D, FN_VI1_R3_B,
 179         FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
 180         FN_MSIOF2_SS1_D, FN_VI1_R4_B,
 181         FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
 182         FN_MSIOF2_RXD_D, FN_VI1_R5_B,
 183         FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
 184         FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
 185         FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
 186         FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
 187         FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
 188         FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
 189         FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
 190         FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
 191         FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
 192
 193         /* IPSR6 */
 194         FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
 195         FN_SCIF_CLK, FN_BPFCLK_E,
 196         FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
 197         FN_SCIFA2_RXD, FN_FMIN_E,
 198         FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
 199         FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
 200         FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
 201         FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
 202         FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
 203         FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
 204         FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
 205         FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
 206         FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
 207         FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
 208
 209         /* IPSR7 */
 210         FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
 211         FN_SCIF_CLK_B, FN_GPS_MAG_D,
 212         FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
 213         FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
 214         FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
 215         FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
 216         FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
 217         FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
 218         FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
 219         FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
 220         FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
 221         FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
 222         FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
 223         FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
 224         FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
 225         FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
 226         FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
 227         FN_SCIFA1_SCK, FN_SSI_SCK78_B,
 228
 229         /* IPSR8 */
 230         FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
 231         FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
 232         FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
 233         FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
 234         FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
 235         FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
 236         FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
 237         FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
 238         FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
 239         FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
 240         FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
 241         FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
 242         FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
 243         FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
 244         FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
 245         FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
 246         FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
 247
 248         /* IPSR9 */
 249         FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
 250         FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
 251         FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
 252         FN_DU1_DOTCLKOUT0, FN_QCLK,
 253         FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
 254         FN_TX3_B, FN_SCL2_B, FN_PWM4,
 255         FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
 256         FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
 257         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
 258         FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
 259         FN_DU1_DISP, FN_QPOLA,
 260         FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
 261         FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
 262         FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
 263         FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
 264         FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
 265         FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
 266         FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
 267         FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
 268
 269         /* IPSR10 */
 270         FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
 271         FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
 272         FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
 273         FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
 274         FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
 275         FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
 276         FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
 277         FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
 278         FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
 279         FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
 280         FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
 281         FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
 282         FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
 283         FN_TS_SDATA0_C, FN_ATACS11_N,
 284         FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
 285         FN_TS_SCK0_C, FN_ATAG1_N,
 286         FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
 287         FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
 288         FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
 289
 290         /* IPSR11 */
 291         FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
 292         FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
 293         FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
 294         FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
 295         FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
 296         FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
 297         FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
 298         FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
 299         FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
 300         FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
 301         FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
 302         FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
 303         FN_VI1_DATA7, FN_AVB_MDC,
 304         FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
 305         FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
 306
 307         /* IPSR12 */
 308         FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
 309         FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
 310         FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
 311         FN_SCL2_D, FN_MSIOF1_RXD_E,
 312         FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
 313         FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
 314         FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
 315         FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
 316         FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
 317         FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
 318         FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
 319         FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
 320         FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
 321         FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
 322         FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
 323         FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
 324         FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
 325
 326         /* IPSR13 */
 327         FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
 328         FN_ADICLK_B, FN_MSIOF0_SS1_C,
 329         FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
 330         FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
 331         FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
 332         FN_ADICHS2_B, FN_MSIOF0_TXD_C,
 333         FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
 334         FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
 335         FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
 336         FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
 337         FN_SCIFA5_TXD_B, FN_TX3_C,
 338         FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
 339         FN_SCIFA5_RXD_B, FN_RX3_C,
 340         FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
 341         FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
 342         FN_SD1_DATA3, FN_IERX_B,
 343         FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
 344
 345         /* IPSR14 */
 346         FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
 347         FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
 348         FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
 349         FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
 350         FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
 351         FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
 352         FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
 353         FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
 354         FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
 355         FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
 356         FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
 357         FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
 358         FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
 359         FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
 360
 361         /* IPSR15 */
 362         FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
 363         FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
 364         FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
 365         FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
 366         FN_PWM5_B, FN_SCIFA3_TXD_C,
 367         FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
 368         FN_VI1_G6_B, FN_SCIFA3_RXD_C,
 369         FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
 370         FN_VI1_G7_B, FN_SCIFA3_SCK_C,
 371         FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
 372         FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
 373         FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
 374         FN_TCLK2, FN_VI1_DATA3_C,
 375         FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
 376         FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
 377
 378         /* IPSR16 */
 379         FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
 380         FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
 381         FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
 382         FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
 383         FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
 384
 385         /* MOD_SEL */
 386         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 387         FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
 388         FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
 389         FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 390         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
 391         FN_SEL_SSI9_0, FN_SEL_SSI9_1,
 392         FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 393         FN_SEL_QSP_0, FN_SEL_QSP_1,
 394         FN_SEL_SSI7_0, FN_SEL_SSI7_1,
 395         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
 396         FN_SEL_HSCIF1_4,
 397         FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
 398         FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 399         FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
 400         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 401         FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
 402
 403         /* MOD_SEL2 */
 404         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 405         FN_SEL_SCIF0_4,
 406         FN_SEL_SCIF_0, FN_SEL_SCIF_1,
 407         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 408         FN_SEL_CAN0_4, FN_SEL_CAN0_5,
 409         FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
 410         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
 411         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
 412         FN_SEL_ADG_0, FN_SEL_ADG_1,
 413         FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
 414         FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
 415         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 416         FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
 417         FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
 418         FN_SEL_SIM_0, FN_SEL_SIM_1,
 419         FN_SEL_SSI8_0, FN_SEL_SSI8_1,
 420
 421         /* MOD_SEL3 */
 422         FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
 423         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
 424         FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
 425         FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
 426         FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
 427         FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
 428         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
 429         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 430         FN_SEL_MMC_0, FN_SEL_MMC_1,
 431         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
 432         FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
 433         FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
 434         FN_SEL_IIC1_4,
 435         FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
 436
 437         /* MOD_SEL4 */
 438         FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
 439         FN_SEL_SOF1_4,
 440         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
 441         FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
 442         FN_SEL_RAD_0, FN_SEL_RAD_1,
 443         FN_SEL_RCN_0, FN_SEL_RCN_1,
 444         FN_SEL_RSP_0, FN_SEL_RSP_1,
 445         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
 446         FN_SEL_SCIF2_4,
 447         FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
 448         FN_SEL_SOF2_4,
 449         FN_SEL_SSI1_0, FN_SEL_SSI1_1,
 450         FN_SEL_SSI0_0, FN_SEL_SSI0_1,
 451         FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
 452         PINMUX_FUNCTION_END,
 453
 454         PINMUX_MARK_BEGIN,
 455
 456         EX_CS0_N_MARK, RD_N_MARK,
 457
 458         AUDIO_CLKA_MARK,
 459
 460         VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
 461         VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
 462         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
 463
 464         SD1_CLK_MARK,
 465
 466         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 467         DU0_DOTCLKIN_MARK,
 468
 469         /* IPSR0 */
 470         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
 471         D6_MARK, D7_MARK, D8_MARK,
 472         D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
 473         A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK,
 474         A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
 475         A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
 476         A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
 477
 478         /* IPSR1 */
 479         A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK,
 480         A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK,
 481         A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
 482         A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK,
 483         A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK,
 484         A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
 485         A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
 486         A15_MARK, BPFCLK_C_MARK,
 487         A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
 488         A17_MARK, DACK2_B_MARK, SDA0_C_MARK,
 489         A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
 490
 491         /* IPSR2 */
 492         A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
 493         SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
 494         A20_MARK, SPCLK_MARK,
 495         A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
 496         A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
 497         A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
 498         A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
 499         A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
 500         RX1_MARK, SCIFA1_RXD_MARK,
 501         CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK,
 502         CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK,
 503         EX_CS1_N_MARK, MSIOF2_SCK_MARK,
 504         EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
 505         EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
 506         ATAG0_N_MARK, EX_WAIT1_MARK,
 507
 508         /* IPSR3 */
 509         EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
 510         EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
 511         SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
 512         BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
 513         SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
 514         RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
 515         SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
 516         WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
 517         WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
 518         EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
 519         DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
 520         DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
 521         SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
 522         SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
 523         SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
 524         SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
 525         SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
 526         SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
 527
 528         /* IPSR4 */
 529         SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK,
 530         SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK,
 531         MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
 532         SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK,
 533         MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
 534         SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK,
 535         SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK,
 536         SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
 537         GLO_Q1_D_MARK, HCTS1_N_E_MARK,
 538         SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
 539         SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
 540         SSI_SCK4_MARK, GLO_SS_D_MARK,
 541         SSI_WS4_MARK, GLO_RFON_D_MARK,
 542         SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
 543         SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
 544         MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
 545
 546         /* IPSR5 */
 547         SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
 548         MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
 549         SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
 550         MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
 551         SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
 552         MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
 553         SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
 554         SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
 555         SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
 556         SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
 557         SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
 558         SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
 559         SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
 560         SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
 561         SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
 562
 563         /* IPSR6 */
 564         AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
 565         SCIF_CLK_MARK, BPFCLK_E_MARK,
 566         AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
 567         SCIFA2_RXD_MARK, FMIN_E_MARK,
 568         AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
 569         IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
 570         IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
 571         IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
 572         IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
 573         IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
 574         MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
 575         IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
 576         IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
 577         SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
 578         IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
 579         GPS_CLK_C_MARK, GPS_CLK_D_MARK,
 580         IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
 581         GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
 582
 583         /* IPSR7 */
 584         IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
 585         SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
 586         DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
 587         SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
 588         DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
 589         SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
 590         DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
 591         DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
 592         DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
 593         DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
 594         DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
 595         DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
 596         DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
 597         SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
 598         DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
 599         SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
 600         DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
 601         SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
 602
 603         /* IPSR8 */
 604         DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
 605         DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
 606         SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
 607         DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
 608         SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
 609         DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
 610         SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
 611         DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
 612         SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
 613         DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
 614         SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
 615         DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
 616         SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
 617         DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
 618         SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
 619         DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
 620         DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
 621         DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
 622
 623         /* IPSR9 */
 624         DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
 625         DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK,
 626         SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
 627         DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 628         DU1_DOTCLKOUT0_MARK, QCLK_MARK,
 629         DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
 630         TX3_B_MARK, SCL2_B_MARK, PWM4_MARK,
 631         DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
 632         DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
 633         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 634         CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK,
 635         DU1_DISP_MARK, QPOLA_MARK,
 636         DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
 637         VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
 638         VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
 639         VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
 640         VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
 641         VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
 642         VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK,
 643         HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
 644
 645         /* IPSR10 */
 646         VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK,
 647         HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
 648         VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK,
 649         HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
 650         VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK,
 651         HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
 652         VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
 653         HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
 654         VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
 655         CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
 656         VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
 657         VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
 658         VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
 659         TS_SDATA0_C_MARK, ATACS11_N_MARK,
 660         VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
 661         TS_SCK0_C_MARK, ATAG1_N_MARK,
 662         VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
 663         VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
 664         VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK,
 665
 666         /* IPSR11 */
 667         VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
 668         VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
 669         VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
 670         SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
 671         VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
 672         TX4_B_MARK, SCIFA4_TXD_B_MARK,
 673         VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
 674         RX4_B_MARK, SCIFA4_RXD_B_MARK,
 675         VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
 676         VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
 677         VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
 678         VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
 679         VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
 680         VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
 681         VI1_DATA7_MARK, AVB_MDC_MARK,
 682         ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
 683         ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
 684
 685         /* IPSR12 */
 686         ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
 687         ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
 688         ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
 689         SCL2_D_MARK, MSIOF1_RXD_E_MARK,
 690         ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
 691         SDA2_D_MARK, MSIOF1_SCK_E_MARK,
 692         ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
 693         CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
 694         ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
 695         CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
 696         ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
 697         ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
 698         ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
 699         ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
 700         STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
 701         ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
 702         STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
 703         ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
 704
 705         /* IPSR13 */
 706         STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
 707         ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
 708         STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
 709         STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
 710         STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
 711         ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
 712         SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
 713         SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
 714         SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
 715         SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
 716         SCIFA5_TXD_B_MARK, TX3_C_MARK,
 717         SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
 718         SCIFA5_RXD_B_MARK, RX3_C_MARK,
 719         SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
 720         SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
 721         SD1_DATA3_MARK, IERX_B_MARK,
 722         SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
 723
 724         /* IPSR14 */
 725         SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
 726         SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
 727         SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
 728         SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
 729         SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
 730         SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
 731         MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
 732         VI1_CLK_C_MARK, VI1_G0_B_MARK,
 733         MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
 734         VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
 735         MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
 736         MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
 737         MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
 738         VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
 739         MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
 740         VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
 741
 742         /* IPSR15 */
 743         SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
 744         SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
 745         SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
 746         GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
 747         PWM5_B_MARK, SCIFA3_TXD_C_MARK,
 748         GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
 749         VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
 750         GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
 751         VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
 752         HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
 753         TCLK1_MARK, VI1_DATA1_C_MARK,
 754         HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
 755         HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
 756         TCLK2_MARK, VI1_DATA3_C_MARK,
 757         HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
 758         CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
 759         HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
 760         CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
 761
 762         /* IPSR16 */
 763         HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
 764         GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
 765         HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
 766         GLO_SS_C_MARK, VI1_DATA7_C_MARK,
 767         HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK,
 768         HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
 769         HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
 770         PINMUX_MARK_END,
 771 };
 772
 773 static const u16 pinmux_data[] = {
 774         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 775
 776         PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N),
 777         PINMUX_DATA(RD_N_MARK, FN_RD_N),
 778         PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
 779         PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
 780         PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0),
 781         PINMUX_DATA(VI0_DATA1_VI0_B1_MARK, FN_VI0_DATA1_VI0_B1),
 782         PINMUX_DATA(VI0_DATA2_VI0_B2_MARK, FN_VI0_DATA2_VI0_B2),
 783         PINMUX_DATA(VI0_DATA4_VI0_B4_MARK, FN_VI0_DATA4_VI0_B4),
 784         PINMUX_DATA(VI0_DATA5_VI0_B5_MARK, FN_VI0_DATA5_VI0_B5),
 785         PINMUX_DATA(VI0_DATA6_VI0_B6_MARK, FN_VI0_DATA6_VI0_B6),
 786         PINMUX_DATA(VI0_DATA7_VI0_B7_MARK, FN_VI0_DATA7_VI0_B7),
 787         PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
 788         PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
 789         PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
 790         PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
 791         PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN),
 792         PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
 793
 794         /* IPSR0 */
 795         PINMUX_IPSR_DATA(IP0_0, D0),
 796         PINMUX_IPSR_DATA(IP0_1, D1),
 797         PINMUX_IPSR_DATA(IP0_2, D2),
 798         PINMUX_IPSR_DATA(IP0_3, D3),
 799         PINMUX_IPSR_DATA(IP0_4, D4),
 800         PINMUX_IPSR_DATA(IP0_5, D5),
 801         PINMUX_IPSR_DATA(IP0_6, D6),
 802         PINMUX_IPSR_DATA(IP0_7, D7),
 803         PINMUX_IPSR_DATA(IP0_8, D8),
 804         PINMUX_IPSR_DATA(IP0_9, D9),
 805         PINMUX_IPSR_DATA(IP0_10, D10),
 806         PINMUX_IPSR_DATA(IP0_11, D11),
 807         PINMUX_IPSR_DATA(IP0_12, D12),
 808         PINMUX_IPSR_DATA(IP0_13, D13),
 809         PINMUX_IPSR_DATA(IP0_14, D14),
 810         PINMUX_IPSR_DATA(IP0_15, D15),
 811         PINMUX_IPSR_DATA(IP0_18_16, A0),
 812         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
 813         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
 814         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SCL0_C, SEL_IIC0_2),
 815         PINMUX_IPSR_DATA(IP0_18_16, PWM2_B),
 816         PINMUX_IPSR_DATA(IP0_20_19, A1),
 817         PINMUX_IPSR_MODSEL_DATA(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
 818         PINMUX_IPSR_DATA(IP0_22_21, A2),
 819         PINMUX_IPSR_MODSEL_DATA(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
 820         PINMUX_IPSR_DATA(IP0_24_23, A3),
 821         PINMUX_IPSR_MODSEL_DATA(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
 822         PINMUX_IPSR_DATA(IP0_26_25, A4),
 823         PINMUX_IPSR_MODSEL_DATA(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
 824         PINMUX_IPSR_DATA(IP0_28_27, A5),
 825         PINMUX_IPSR_MODSEL_DATA(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
 826         PINMUX_IPSR_DATA(IP0_30_29, A6),
 827         PINMUX_IPSR_MODSEL_DATA(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
 828
 829         /* IPSR1 */
 830         PINMUX_IPSR_DATA(IP1_1_0, A7),
 831         PINMUX_IPSR_MODSEL_DATA(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
 832         PINMUX_IPSR_DATA(IP1_3_2, A8),
 833         PINMUX_IPSR_MODSEL_DATA(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
 834         PINMUX_IPSR_MODSEL_DATA(IP1_3_2, SCL0, SEL_IIC0_0),
 835         PINMUX_IPSR_DATA(IP1_5_4, A9),
 836         PINMUX_IPSR_MODSEL_DATA(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
 837         PINMUX_IPSR_MODSEL_DATA(IP1_5_4, SDA0, SEL_IIC0_0),
 838         PINMUX_IPSR_DATA(IP1_7_6, A10),
 839         PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
 840         PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
 841         PINMUX_IPSR_DATA(IP1_10_8, A11),
 842         PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
 843         PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCL3_D, SEL_IIC3_3),
 844         PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
 845         PINMUX_IPSR_DATA(IP1_13_11, A12),
 846         PINMUX_IPSR_MODSEL_DATA(IP1_13_11, FMCLK, SEL_FM_0),
 847         PINMUX_IPSR_MODSEL_DATA(IP1_13_11, SDA3_D, SEL_IIC3_3),
 848         PINMUX_IPSR_MODSEL_DATA(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
 849         PINMUX_IPSR_DATA(IP1_16_14, A13),
 850         PINMUX_IPSR_MODSEL_DATA(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
 851         PINMUX_IPSR_MODSEL_DATA(IP1_16_14, BPFCLK, SEL_FM_0),
 852         PINMUX_IPSR_MODSEL_DATA(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
 853         PINMUX_IPSR_DATA(IP1_19_17, A14),
 854         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
 855         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN, SEL_FM_0),
 856         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN_C, SEL_FM_2),
 857         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
 858         PINMUX_IPSR_DATA(IP1_22_20, A15),
 859         PINMUX_IPSR_MODSEL_DATA(IP1_22_20, BPFCLK_C, SEL_FM_2),
 860         PINMUX_IPSR_DATA(IP1_25_23, A16),
 861         PINMUX_IPSR_MODSEL_DATA(IP1_25_23, DREQ2_B, SEL_LBS_1),
 862         PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FMCLK_C, SEL_FM_2),
 863         PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
 864         PINMUX_IPSR_DATA(IP1_28_26, A17),
 865         PINMUX_IPSR_MODSEL_DATA(IP1_28_26, DACK2_B, SEL_LBS_1),
 866         PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SDA0_C, SEL_IIC0_2),
 867         PINMUX_IPSR_DATA(IP1_31_29, A18),
 868         PINMUX_IPSR_MODSEL_DATA(IP1_31_29, DREQ1, SEL_LBS_0),
 869         PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
 870         PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
 871
 872         /* IPSR2 */
 873         PINMUX_IPSR_DATA(IP2_2_0, A19),
 874         PINMUX_IPSR_DATA(IP2_2_0, DACK1),
 875         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
 876         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
 877         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_0),
 878         PINMUX_IPSR_DATA(IP2_2_0, A20),
 879         PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SPCLK, SEL_QSP_0),
 880         PINMUX_IPSR_DATA(IP2_6_5, A21),
 881         PINMUX_IPSR_MODSEL_DATA(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
 882         PINMUX_IPSR_MODSEL_DATA(IP2_6_5, MOSI_IO0, SEL_QSP_0),
 883         PINMUX_IPSR_DATA(IP2_9_7, A22),
 884         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, MISO_IO1, SEL_QSP_0),
 885         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, FMCLK_B, SEL_FM_1),
 886         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, TX0, SEL_SCIF0_0),
 887         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
 888         PINMUX_IPSR_DATA(IP2_12_10, A23),
 889         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, IO2, SEL_QSP_0),
 890         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, BPFCLK_B, SEL_FM_1),
 891         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, RX0, SEL_SCIF0_0),
 892         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
 893         PINMUX_IPSR_DATA(IP2_15_13, A24),
 894         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, DREQ2, SEL_LBS_0),
 895         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, IO3, SEL_QSP_0),
 896         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, TX1, SEL_SCIF1_0),
 897         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
 898         PINMUX_IPSR_DATA(IP2_18_16, A25),
 899         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DACK2, SEL_LBS_0),
 900         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SSL, SEL_QSP_0),
 901         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ1_C, SEL_LBS_2),
 902         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, RX1, SEL_SCIF1_0),
 903         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
 904         PINMUX_IPSR_DATA(IP2_20_19, CS0_N),
 905         PINMUX_IPSR_MODSEL_DATA(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
 906         PINMUX_IPSR_MODSEL_DATA(IP2_20_19, SCL1, SEL_IIC1_0),
 907         PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26),
 908         PINMUX_IPSR_MODSEL_DATA(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
 909         PINMUX_IPSR_MODSEL_DATA(IP2_22_21, SDA1, SEL_IIC1_0),
 910         PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N),
 911         PINMUX_IPSR_MODSEL_DATA(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
 912         PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N),
 913         PINMUX_IPSR_MODSEL_DATA(IP2_26_25, ATAWR0_N, SEL_LBS_0),
 914         PINMUX_IPSR_MODSEL_DATA(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
 915         PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N),
 916         PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATADIR0_N, SEL_LBS_0),
 917         PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
 918         PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATAG0_N, SEL_LBS_0),
 919         PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1),
 920
 921         /* IPSR3 */
 922         PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N),
 923         PINMUX_IPSR_MODSEL_DATA(IP3_2_0, ATARD0_N, SEL_LBS_0),
 924         PINMUX_IPSR_MODSEL_DATA(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
 925         PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2),
 926         PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N),
 927         PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N),
 928         PINMUX_IPSR_MODSEL_DATA(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
 929         PINMUX_IPSR_MODSEL_DATA(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
 930         PINMUX_IPSR_MODSEL_DATA(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
 931         PINMUX_IPSR_DATA(IP3_5_3, PWM1),
 932         PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1),
 933         PINMUX_IPSR_DATA(IP3_8_6, BS_N),
 934         PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N),
 935         PINMUX_IPSR_MODSEL_DATA(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
 936         PINMUX_IPSR_MODSEL_DATA(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
 937         PINMUX_IPSR_MODSEL_DATA(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
 938         PINMUX_IPSR_DATA(IP3_8_6, PWM2),
 939         PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2),
 940         PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N),
 941         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
 942         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, FMIN_B, SEL_FM_1),
 943         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
 944         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, DREQ1_D, SEL_LBS_1),
 945         PINMUX_IPSR_DATA(IP3_13_12, WE0_N),
 946         PINMUX_IPSR_MODSEL_DATA(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
 947         PINMUX_IPSR_MODSEL_DATA(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
 948         PINMUX_IPSR_DATA(IP3_15_14, WE1_N),
 949         PINMUX_IPSR_MODSEL_DATA(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
 950         PINMUX_IPSR_MODSEL_DATA(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
 951         PINMUX_IPSR_MODSEL_DATA(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
 952         PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0),
 953         PINMUX_IPSR_MODSEL_DATA(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
 954         PINMUX_IPSR_MODSEL_DATA(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
 955         PINMUX_IPSR_DATA(IP3_19_18, DREQ0),
 956         PINMUX_IPSR_DATA(IP3_19_18, PWM3),
 957         PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3),
 958         PINMUX_IPSR_DATA(IP3_21_20, DACK0),
 959         PINMUX_IPSR_DATA(IP3_21_20, DRACK0),
 960         PINMUX_IPSR_MODSEL_DATA(IP3_21_20, REMOCON, SEL_RCN_0),
 961         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SPEEDIN, SEL_RSP_0),
 962         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
 963         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
 964         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
 965         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
 966         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, DREQ2_C, SEL_LBS_2),
 967         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 968         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
 969         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
 970         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
 971         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
 972         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
 973         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
 974         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
 975         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 976         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
 977         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
 978
 979         /* IPSR4 */
 980         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
 981         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL0_B, SEL_IIC0_1),
 982         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL7_B, SEL_IIC7_1),
 983         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
 984         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
 985         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA0_B, SEL_IIC0_1),
 986         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA7_B, SEL_IIC7_1),
 987         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
 988         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, GLO_I0_D, SEL_GPS_3),
 989         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SSI_WS1, SEL_SSI1_0),
 990         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL1_B, SEL_IIC1_1),
 991         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL8_B, SEL_IIC8_1),
 992         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
 993         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, GLO_I1_D, SEL_GPS_3),
 994         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
 995         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA1_B, SEL_IIC1_1),
 996         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA8_B, SEL_IIC8_1),
 997         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
 998         PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2),
 999         PINMUX_IPSR_MODSEL_DATA(IP4_12_10, SCL2, SEL_IIC2_0),
1000         PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1001         PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1002         PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2),
1003         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, SDA2, SEL_IIC2_0),
1004         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1005         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, RX2_E, SEL_SCIF2_4),
1006         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1007         PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2),
1008         PINMUX_IPSR_MODSEL_DATA(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1009         PINMUX_IPSR_MODSEL_DATA(IP4_18_16, TX2_E, SEL_SCIF2_4),
1010         PINMUX_IPSR_DATA(IP4_19, SSI_SCK34),
1011         PINMUX_IPSR_DATA(IP4_20, SSI_WS34),
1012         PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3),
1013         PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4),
1014         PINMUX_IPSR_MODSEL_DATA(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1015         PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4),
1016         PINMUX_IPSR_MODSEL_DATA(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1017         PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4),
1018         PINMUX_IPSR_MODSEL_DATA(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1019         PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5),
1020         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1021         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1022         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, GLO_I0, SEL_GPS_0),
1023         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1024         PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B),
1025
1026         /* IPSR5 */
1027         PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5),
1028         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1029         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1030         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, GLO_I1, SEL_GPS_0),
1031         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1032         PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B),
1033         PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5),
1034         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1035         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1036         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, GLO_Q0, SEL_GPS_0),
1037         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1038         PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B),
1039         PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6),
1040         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1041         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1042         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, GLO_Q1, SEL_GPS_0),
1043         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1044         PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B),
1045         PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6),
1046         PINMUX_IPSR_MODSEL_DATA(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1047         PINMUX_IPSR_MODSEL_DATA(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1048         PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B),
1049         PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6),
1050         PINMUX_IPSR_MODSEL_DATA(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1051         PINMUX_IPSR_MODSEL_DATA(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1052         PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B),
1053         PINMUX_IPSR_MODSEL_DATA(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1054         PINMUX_IPSR_MODSEL_DATA(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1055         PINMUX_IPSR_MODSEL_DATA(IP5_16_15, GLO_SS, SEL_GPS_0),
1056         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1057         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, TX0_D, SEL_SCIF0_3),
1058         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1059         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, GLO_RFON, SEL_GPS_0),
1060         PINMUX_IPSR_MODSEL_DATA(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1061         PINMUX_IPSR_MODSEL_DATA(IP5_21_20, RX0_D, SEL_SCIF0_3),
1062         PINMUX_IPSR_MODSEL_DATA(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1063         PINMUX_IPSR_MODSEL_DATA(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1064         PINMUX_IPSR_MODSEL_DATA(IP5_23_22, TX1_D, SEL_SCIF1_3),
1065         PINMUX_IPSR_MODSEL_DATA(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1066         PINMUX_IPSR_MODSEL_DATA(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1067         PINMUX_IPSR_MODSEL_DATA(IP5_25_24, RX1_D, SEL_SCIF1_3),
1068         PINMUX_IPSR_MODSEL_DATA(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1069         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1070         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, TX3_D, SEL_SCIF3_3),
1071         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1072         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1073         PINMUX_IPSR_MODSEL_DATA(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1074         PINMUX_IPSR_MODSEL_DATA(IP5_31_29, RX3_D, SEL_SCIF3_3),
1075         PINMUX_IPSR_MODSEL_DATA(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1076
1077         /* IPSR6 */
1078         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1079         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1080         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1081         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1082         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4),
1083         PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
1084         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1085         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1086         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0),
1087         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1088         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4),
1089         PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
1090         PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1091         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0),
1092         PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1093         PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
1094         PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1095         PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
1096         PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
1097         PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1098         PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
1099         PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
1100         PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1101         PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
1102         PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
1103         PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2),
1104         PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1105         PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
1106         PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
1107         PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1108         PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2),
1109         PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1110         PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
1111         PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
1112         PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1113         PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4),
1114         PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1115         PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
1116         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1117         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1118         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4),
1119         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1120         PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
1121         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1122         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1123         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1124         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1125         PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
1126         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1127         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1128         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1129         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1130
1131         /* IPSR7 */
1132         PINMUX_IPSR_DATA(IP7_2_0, IRQ9),
1133         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1134         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1135         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1136         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1137         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1138         PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0),
1139         PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0),
1140         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1141         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TX0_B, SEL_SCIF0_1),
1142         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1143         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1144         PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1),
1145         PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1),
1146         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1147         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX0_B, SEL_SCIF0_1),
1148         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1149         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1150         PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2),
1151         PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2),
1152         PINMUX_IPSR_MODSEL_DATA(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1153         PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3),
1154         PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3),
1155         PINMUX_IPSR_MODSEL_DATA(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1156         PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4),
1157         PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4),
1158         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1159         PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5),
1160         PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5),
1161         PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1162         PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6),
1163         PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6),
1164         PINMUX_IPSR_MODSEL_DATA(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1165         PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7),
1166         PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7),
1167         PINMUX_IPSR_MODSEL_DATA(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1168         PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0),
1169         PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8),
1170         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1171         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX1_B, SEL_SCIF1_1),
1172         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1173         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1174         PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1),
1175         PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9),
1176         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1177         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX1_B, SEL_SCIF1_1),
1178         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1179         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1180         PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2),
1181         PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10),
1182         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1183         PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B),
1184         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1185         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1186
1187         /* IPSR8 */
1188         PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3),
1189         PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11),
1190         PINMUX_IPSR_MODSEL_DATA(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1191         PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1192         PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4),
1193         PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12),
1194         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1195         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1196         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1197         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1198         PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5),
1199         PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13),
1200         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1201         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1202         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1203         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1204         PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6),
1205         PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14),
1206         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1207         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1208         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1209         PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7),
1210         PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15),
1211         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1212         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1213         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1214         PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0),
1215         PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16),
1216         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1217         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, TX2_B, SEL_SCIF2_1),
1218         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1219         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1220         PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1),
1221         PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17),
1222         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1223         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, RX2_B, SEL_SCIF2_1),
1224         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1225         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1226         PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2),
1227         PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18),
1228         PINMUX_IPSR_MODSEL_DATA(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1229         PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B),
1230         PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1231         PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1232         PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3),
1233         PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19),
1234         PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1235         PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4),
1236         PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20),
1237         PINMUX_IPSR_MODSEL_DATA(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1238         PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1239         PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5),
1240         PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21),
1241         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, TX3, SEL_SCIF3_0),
1242         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1243         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1244
1245         /* IPSR9 */
1246         PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6),
1247         PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22),
1248         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCL3_C, SEL_IIC3_2),
1249         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RX3, SEL_SCIF3_0),
1250         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1251         PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7),
1252         PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23),
1253         PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SDA3_C, SEL_IIC3_2),
1254         PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1255         PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1256         PINMUX_IPSR_MODSEL_DATA(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1257         PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS),
1258         PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0),
1259         PINMUX_IPSR_DATA(IP9_7, QCLK),
1260         PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1),
1261         PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE),
1262         PINMUX_IPSR_MODSEL_DATA(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1263         PINMUX_IPSR_MODSEL_DATA(IP9_10_8, TX3_B, SEL_SCIF3_1),
1264         PINMUX_IPSR_MODSEL_DATA(IP9_10_8, SCL2_B, SEL_IIC2_1),
1265         PINMUX_IPSR_DATA(IP9_10_8, PWM4),
1266         PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1267         PINMUX_IPSR_DATA(IP9_11, QSTH_QHS),
1268         PINMUX_IPSR_DATA(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1269         PINMUX_IPSR_DATA(IP9_12, QSTB_QHE),
1270         PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1271         PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE),
1272         PINMUX_IPSR_MODSEL_DATA(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1273         PINMUX_IPSR_MODSEL_DATA(IP9_15_13, RX3_B, SEL_SCIF3_1),
1274         PINMUX_IPSR_MODSEL_DATA(IP9_15_13, SDA2_B, SEL_IIC2_1),
1275         PINMUX_IPSR_DATA(IP9_16, DU1_DISP),
1276         PINMUX_IPSR_DATA(IP9_16, QPOLA),
1277         PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE),
1278         PINMUX_IPSR_DATA(IP9_18_17, QPOLB),
1279         PINMUX_IPSR_DATA(IP9_18_17, PWM4_B),
1280         PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB),
1281         PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TX4, SEL_SCIF4_0),
1282         PINMUX_IPSR_MODSEL_DATA(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1283         PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1284         PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD),
1285         PINMUX_IPSR_MODSEL_DATA(IP9_22_21, RX4, SEL_SCIF4_0),
1286         PINMUX_IPSR_MODSEL_DATA(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1287         PINMUX_IPSR_MODSEL_DATA(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1288         PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N),
1289         PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TX5, SEL_SCIF5_0),
1290         PINMUX_IPSR_MODSEL_DATA(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1291         PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1292         PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N),
1293         PINMUX_IPSR_MODSEL_DATA(IP9_26_25, RX5, SEL_SCIF5_0),
1294         PINMUX_IPSR_MODSEL_DATA(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1295         PINMUX_IPSR_MODSEL_DATA(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1296         PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3),
1297         PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1298         PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1299         PINMUX_IPSR_DATA(IP9_31_29, VI0_G0),
1300         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL8, SEL_IIC8_0),
1301         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1302         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL4, SEL_IIC4_0),
1303         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1304         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1305         PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N),
1306
1307         /* IPSR10 */
1308         PINMUX_IPSR_DATA(IP10_2_0, VI0_G1),
1309         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA8, SEL_IIC8_0),
1310         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1311         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA4, SEL_IIC4_0),
1312         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1313         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1314         PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N),
1315         PINMUX_IPSR_DATA(IP10_5_3, VI0_G2),
1316         PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N),
1317         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1318         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCL3_B, SEL_IIC3_1),
1319         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1320         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1321         PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N),
1322         PINMUX_IPSR_DATA(IP10_8_6, VI0_G3),
1323         PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N),
1324         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1325         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SDA3_B, SEL_IIC3_1),
1326         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX2, SEL_HSCIF2_0),
1327         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1328         PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N),
1329         PINMUX_IPSR_DATA(IP10_11_9, VI0_G4),
1330         PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB),
1331         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1332         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX2, SEL_HSCIF2_0),
1333         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1334         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1335         PINMUX_IPSR_DATA(IP10_14_12, VI0_G5),
1336         PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD),
1337         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1338         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, FMCLK_D, SEL_FM_3),
1339         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1340         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1341         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1342         PINMUX_IPSR_DATA(IP10_16_15, VI0_G6),
1343         PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK),
1344         PINMUX_IPSR_MODSEL_DATA(IP10_16_15, BPFCLK_D, SEL_FM_3),
1345         PINMUX_IPSR_DATA(IP10_18_17, VI0_G7),
1346         PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0),
1347         PINMUX_IPSR_MODSEL_DATA(IP10_18_17, FMIN_D, SEL_FM_3),
1348         PINMUX_IPSR_DATA(IP10_21_19, VI0_R0),
1349         PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1),
1350         PINMUX_IPSR_MODSEL_DATA(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1351         PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1352         PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N),
1353         PINMUX_IPSR_DATA(IP10_24_22, VI0_R1),
1354         PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2),
1355         PINMUX_IPSR_MODSEL_DATA(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1356         PINMUX_IPSR_MODSEL_DATA(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1357         PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N),
1358         PINMUX_IPSR_DATA(IP10_26_25, VI0_R2),
1359         PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3),
1360         PINMUX_IPSR_MODSEL_DATA(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1361         PINMUX_IPSR_MODSEL_DATA(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1362         PINMUX_IPSR_DATA(IP10_28_27, VI0_R3),
1363         PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4),
1364         PINMUX_IPSR_MODSEL_DATA(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1365         PINMUX_IPSR_MODSEL_DATA(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1366         PINMUX_IPSR_DATA(IP10_31_29, VI0_R4),
1367         PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5),
1368         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1369         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, TX0_C, SEL_SCIF0_2),
1370         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL1_D, SEL_IIC1_3),
1371
1372         /* IPSR11 */
1373         PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
1374         PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
1375         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1376         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
1377         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
1378         PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
1379         PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
1380         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1381         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
1382         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
1383         PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
1384         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1385         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
1386         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1387         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
1388         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1389         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1390         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1391         PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
1392         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1393         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
1394         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1395         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1396         PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
1397         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1398         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
1399         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1400         PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1401         PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
1402         PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1403         PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1404         PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
1405         PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1406         PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
1407         PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
1408         PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
1409         PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
1410         PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
1411         PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
1412         PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
1413         PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
1414         PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
1415         PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
1416         PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
1417         PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
1418         PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
1419         PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
1420         PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
1421         PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
1422         PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
1423         PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
1424         PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
1425         PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
1426         PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
1427         PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
1428         PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
1429         PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
1430
1431         /* IPSR12 */
1432         PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
1433         PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
1434         PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
1435         PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
1436         PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
1437         PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
1438         PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
1439         PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
1440         PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
1441         PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
1442         PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1443         PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
1444         PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1445         PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
1446         PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
1447         PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1448         PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
1449         PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1450         PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
1451         PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
1452         PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1453         PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1454         PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1455         PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
1456         PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
1457         PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1458         PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1459         PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1460         PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
1461         PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
1462         PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1463         PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1464         PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
1465         PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
1466         PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
1467         PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
1468         PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
1469         PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
1470         PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
1471         PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
1472         PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
1473         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1474         PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
1475         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1476         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1477         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1478         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1479         PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
1480         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1481         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1482         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1483
1484         /* IPSR13 */
1485         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1486         PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
1487         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1488         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1),
1489         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1490         PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1491         PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
1492         PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1493         PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1494         PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1495         PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
1496         PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1497         PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1498         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1499         PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
1500         PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
1501         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1502         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1503         PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
1504         PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1),
1505         PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
1506         PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1507         PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
1508         PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1),
1509         PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
1510         PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1),
1511         PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
1512         PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1),
1513         PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
1514         PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1),
1515         PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
1516         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1517         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1518         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1519         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1520         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2),
1521         PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
1522         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1523         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1524         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1525         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1526         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2),
1527         PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
1528         PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1),
1529         PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
1530         PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1531         PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
1532         PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1),
1533         PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
1534         PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1),
1535         PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
1536         PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1),
1537         PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
1538         PINMUX_IPSR_DATA(IP13_30_28, PWM0),
1539         PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
1540         PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2),
1541
1542         /* IPSR14 */
1543         PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
1544         PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
1545         PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2),
1546         PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
1547         PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
1548         PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
1549         PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
1550         PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
1551         PINMUX_IPSR_DATA(IP14_4, MMC_D0),
1552         PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
1553         PINMUX_IPSR_DATA(IP14_5, MMC_D1),
1554         PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
1555         PINMUX_IPSR_DATA(IP14_6, MMC_D2),
1556         PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
1557         PINMUX_IPSR_DATA(IP14_7, MMC_D3),
1558         PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
1559         PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
1560         PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2),
1561         PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1),
1562         PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1563         PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
1564         PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
1565         PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2),
1566         PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1),
1567         PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1568         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1569         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2),
1570         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0),
1571         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1572         PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
1573         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1574         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2),
1575         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1576         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1577         PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
1578         PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1579         PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0),
1580         PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1581         PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
1582         PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1583         PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0),
1584         PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1585         PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
1586         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1587         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0),
1588         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0),
1589         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4),
1590         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1591         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2),
1592         PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
1593         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1594         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0),
1595         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0),
1596         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4),
1597         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1598         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2),
1599         PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
1600
1601         /* IPSR15 */
1602         PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0),
1603         PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0),
1604         PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1605         PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
1606         PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0),
1607         PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1608         PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0),
1609         PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0),
1610         PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1611         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0),
1612         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1613         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1614         PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
1615         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1616         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1617         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2),
1618         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1619         PINMUX_IPSR_DATA(IP15_11_9, PWM5),
1620         PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
1621         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1622         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0),
1623         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2),
1624         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1625         PINMUX_IPSR_DATA(IP15_14_12, PWM6),
1626         PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
1627         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1628         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1629         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1630         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1631         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0),
1632         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1633         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1634         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1635         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1636         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1637         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1638         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1639         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1640         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1641         PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
1642         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1643         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0),
1644         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1645         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1646         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1647         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1648         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0),
1649         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1650         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1651         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1652         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1653
1654         /* IPSR16 */
1655         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0),
1656         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1657         PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
1658         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1659         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1660         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0),
1661         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1662         PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
1663         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1664         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1665         PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1666         PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1667         PINMUX_IPSR_DATA(IP16_7_6, MLB_CK),
1668         PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1669         PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1670         PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
1671         PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
1672         PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1673         PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1674         PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
1675         PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
1676         PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1677 };
1678
1679 static const struct sh_pfc_pin pinmux_pins[] = {
1680         PINMUX_GPIO_GP_ALL(),
1681 };
1682
1683 /* - DU --------------------------------------------------------------------- */
1684 static const unsigned int du_rgb666_pins[] = {
1685         /* R[7:2], G[7:2], B[7:2] */
1686         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
1687         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
1688         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1689         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1690         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1691         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1692 };
1693 static const unsigned int du_rgb666_mux[] = {
1694         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1695         DU1_DR3_MARK, DU1_DR2_MARK,
1696         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1697         DU1_DG3_MARK, DU1_DG2_MARK,
1698         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1699         DU1_DB3_MARK, DU1_DB2_MARK,
1700 };
1701 static const unsigned int du_rgb888_pins[] = {
1702         /* R[7:0], G[7:0], B[7:0] */
1703         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
1704         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
1705         RCAR_GP_PIN(3, 1),  RCAR_GP_PIN(3, 0),
1706         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1707         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1708         RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 8),
1709         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1710         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1711         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
1712 };
1713 static const unsigned int du_rgb888_mux[] = {
1714         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1715         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1716         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1717         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1718         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1719         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1720 };
1721 static const unsigned int du_clk_out_0_pins[] = {
1722         /* CLKOUT */
1723         RCAR_GP_PIN(3, 25),
1724 };
1725 static const unsigned int du_clk_out_0_mux[] = {
1726         DU1_DOTCLKOUT0_MARK
1727 };
1728 static const unsigned int du_clk_out_1_pins[] = {
1729         /* CLKOUT */
1730         RCAR_GP_PIN(3, 26),
1731 };
1732 static const unsigned int du_clk_out_1_mux[] = {
1733         DU1_DOTCLKOUT1_MARK
1734 };
1735 static const unsigned int du_sync_pins[] = {
1736         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC, EXDISP/EXODDF/EXCDE */
1737         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1738 };
1739 static const unsigned int du_sync_mux[] = {
1740         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1741         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1742 };
1743 static const unsigned int du_cde_disp_pins[] = {
1744         /* CDE DISP */
1745         RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
1746 };
1747 static const unsigned int du_cde_disp_mux[] = {
1748         DU1_CDE_MARK, DU1_DISP_MARK
1749 };
1750 static const unsigned int du0_clk_in_pins[] = {
1751         /* CLKIN */
1752         RCAR_GP_PIN(6, 31),
1753 };
1754 static const unsigned int du0_clk_in_mux[] = {
1755         DU0_DOTCLKIN_MARK
1756 };
1757 static const unsigned int du1_clk_in_pins[] = {
1758         /* CLKIN */
1759         RCAR_GP_PIN(3, 24),
1760 };
1761 static const unsigned int du1_clk_in_mux[] = {
1762         DU1_DOTCLKIN_MARK
1763 };
1764 static const unsigned int du1_clk_in_b_pins[] = {
1765         /* CLKIN */
1766         RCAR_GP_PIN(7, 19),
1767 };
1768 static const unsigned int du1_clk_in_b_mux[] = {
1769         DU1_DOTCLKIN_B_MARK,
1770 };
1771 static const unsigned int du1_clk_in_c_pins[] = {
1772         /* CLKIN */
1773         RCAR_GP_PIN(7, 20),
1774 };
1775 static const unsigned int du1_clk_in_c_mux[] = {
1776         DU1_DOTCLKIN_C_MARK,
1777 };
1778 /* - ETH -------------------------------------------------------------------- */
1779 static const unsigned int eth_link_pins[] = {
1780         /* LINK */
1781         RCAR_GP_PIN(5, 18),
1782 };
1783 static const unsigned int eth_link_mux[] = {
1784         ETH_LINK_MARK,
1785 };
1786 static const unsigned int eth_magic_pins[] = {
1787         /* MAGIC */
1788         RCAR_GP_PIN(5, 22),
1789 };
1790 static const unsigned int eth_magic_mux[] = {
1791         ETH_MAGIC_MARK,
1792 };
1793 static const unsigned int eth_mdio_pins[] = {
1794         /* MDC, MDIO */
1795         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
1796 };
1797 static const unsigned int eth_mdio_mux[] = {
1798         ETH_MDC_MARK, ETH_MDIO_MARK,
1799 };
1800 static const unsigned int eth_rmii_pins[] = {
1801         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1802         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
1803         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
1804         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
1805 };
1806 static const unsigned int eth_rmii_mux[] = {
1807         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1808         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1809 };
1810 /* - I2C0 ------------------------------------------------------------------- */
1811 static const unsigned int i2c0_pins[] = {
1812         /* SCL, SDA */
1813         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
1814 };
1815 static const unsigned int i2c0_mux[] = {
1816         SCL0_MARK, SDA0_MARK,
1817 };
1818 static const unsigned int i2c0_b_pins[] = {
1819         /* SCL, SDA */
1820         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1821 };
1822 static const unsigned int i2c0_b_mux[] = {
1823         SCL0_B_MARK, SDA0_B_MARK,
1824 };
1825 static const unsigned int i2c0_c_pins[] = {
1826         /* SCL, SDA */
1827         RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
1828 };
1829 static const unsigned int i2c0_c_mux[] = {
1830         SCL0_C_MARK, SDA0_C_MARK,
1831 };
1832 /* - I2C1 ------------------------------------------------------------------- */
1833 static const unsigned int i2c1_pins[] = {
1834         /* SCL, SDA */
1835         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
1836 };
1837 static const unsigned int i2c1_mux[] = {
1838         SCL1_MARK, SDA1_MARK,
1839 };
1840 static const unsigned int i2c1_b_pins[] = {
1841         /* SCL, SDA */
1842         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1843 };
1844 static const unsigned int i2c1_b_mux[] = {
1845         SCL1_B_MARK, SDA1_B_MARK,
1846 };
1847 static const unsigned int i2c1_c_pins[] = {
1848         /* SCL, SDA */
1849         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1850 };
1851 static const unsigned int i2c1_c_mux[] = {
1852         SCL1_C_MARK, SDA1_C_MARK,
1853 };
1854 static const unsigned int i2c1_d_pins[] = {
1855         /* SCL, SDA */
1856         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
1857 };
1858 static const unsigned int i2c1_d_mux[] = {
1859         SCL1_D_MARK, SDA1_D_MARK,
1860 };
1861 static const unsigned int i2c1_e_pins[] = {
1862         /* SCL, SDA */
1863         RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
1864 };
1865 static const unsigned int i2c1_e_mux[] = {
1866         SCL1_E_MARK, SDA1_E_MARK,
1867 };
1868 /* - I2C2 ------------------------------------------------------------------- */
1869 static const unsigned int i2c2_pins[] = {
1870         /* SCL, SDA */
1871         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1872 };
1873 static const unsigned int i2c2_mux[] = {
1874         SCL2_MARK, SDA2_MARK,
1875 };
1876 static const unsigned int i2c2_b_pins[] = {
1877         /* SCL, SDA */
1878         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1879 };
1880 static const unsigned int i2c2_b_mux[] = {
1881         SCL2_B_MARK, SDA2_B_MARK,
1882 };
1883 static const unsigned int i2c2_c_pins[] = {
1884         /* SCL, SDA */
1885         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1886 };
1887 static const unsigned int i2c2_c_mux[] = {
1888         SCL2_C_MARK, SDA2_C_MARK,
1889 };
1890 static const unsigned int i2c2_d_pins[] = {
1891         /* SCL, SDA */
1892         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1893 };
1894 static const unsigned int i2c2_d_mux[] = {
1895         SCL2_D_MARK, SDA2_D_MARK,
1896 };
1897 /* - I2C3 ------------------------------------------------------------------- */
1898 static const unsigned int i2c3_pins[] = {
1899         /* SCL, SDA */
1900         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1901 };
1902 static const unsigned int i2c3_mux[] = {
1903         SCL3_MARK, SDA3_MARK,
1904 };
1905 static const unsigned int i2c3_b_pins[] = {
1906         /* SCL, SDA */
1907         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
1908 };
1909 static const unsigned int i2c3_b_mux[] = {
1910         SCL3_B_MARK, SDA3_B_MARK,
1911 };
1912 static const unsigned int i2c3_c_pins[] = {
1913         /* SCL, SDA */
1914         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
1915 };
1916 static const unsigned int i2c3_c_mux[] = {
1917         SCL3_C_MARK, SDA3_C_MARK,
1918 };
1919 static const unsigned int i2c3_d_pins[] = {
1920         /* SCL, SDA */
1921         RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
1922 };
1923 static const unsigned int i2c3_d_mux[] = {
1924         SCL3_D_MARK, SDA3_D_MARK,
1925 };
1926 /* - I2C4 ------------------------------------------------------------------- */
1927 static const unsigned int i2c4_pins[] = {
1928         /* SCL, SDA */
1929         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
1930 };
1931 static const unsigned int i2c4_mux[] = {
1932         SCL4_MARK, SDA4_MARK,
1933 };
1934 static const unsigned int i2c4_b_pins[] = {
1935         /* SCL, SDA */
1936         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
1937 };
1938 static const unsigned int i2c4_b_mux[] = {
1939         SCL4_B_MARK, SDA4_B_MARK,
1940 };
1941 static const unsigned int i2c4_c_pins[] = {
1942         /* SCL, SDA */
1943         RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1944 };
1945 static const unsigned int i2c4_c_mux[] = {
1946         SCL4_C_MARK, SDA4_C_MARK,
1947 };
1948 /* - I2C7 ------------------------------------------------------------------- */
1949 static const unsigned int i2c7_pins[] = {
1950         /* SCL, SDA */
1951         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1952 };
1953 static const unsigned int i2c7_mux[] = {
1954         SCL7_MARK, SDA7_MARK,
1955 };
1956 static const unsigned int i2c7_b_pins[] = {
1957         /* SCL, SDA */
1958         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1959 };
1960 static const unsigned int i2c7_b_mux[] = {
1961         SCL7_B_MARK, SDA7_B_MARK,
1962 };
1963 static const unsigned int i2c7_c_pins[] = {
1964         /* SCL, SDA */
1965         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
1966 };
1967 static const unsigned int i2c7_c_mux[] = {
1968         SCL7_C_MARK, SDA7_C_MARK,
1969 };
1970 /* - I2C8 ------------------------------------------------------------------- */
1971 static const unsigned int i2c8_pins[] = {
1972         /* SCL, SDA */
1973         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
1974 };
1975 static const unsigned int i2c8_mux[] = {
1976         SCL8_MARK, SDA8_MARK,
1977 };
1978 static const unsigned int i2c8_b_pins[] = {
1979         /* SCL, SDA */
1980         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1981 };
1982 static const unsigned int i2c8_b_mux[] = {
1983         SCL8_B_MARK, SDA8_B_MARK,
1984 };
1985 static const unsigned int i2c8_c_pins[] = {
1986         /* SCL, SDA */
1987         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
1988 };
1989 static const unsigned int i2c8_c_mux[] = {
1990         SCL8_C_MARK, SDA8_C_MARK,
1991 };
1992 /* - INTC ------------------------------------------------------------------- */
1993 static const unsigned int intc_irq0_pins[] = {
1994         /* IRQ */
1995         RCAR_GP_PIN(7, 10),
1996 };
1997 static const unsigned int intc_irq0_mux[] = {
1998         IRQ0_MARK,
1999 };
2000 static const unsigned int intc_irq1_pins[] = {
2001         /* IRQ */
2002         RCAR_GP_PIN(7, 11),
2003 };
2004 static const unsigned int intc_irq1_mux[] = {
2005         IRQ1_MARK,
2006 };
2007 static const unsigned int intc_irq2_pins[] = {
2008         /* IRQ */
2009         RCAR_GP_PIN(7, 12),
2010 };
2011 static const unsigned int intc_irq2_mux[] = {
2012         IRQ2_MARK,
2013 };
2014 static const unsigned int intc_irq3_pins[] = {
2015         /* IRQ */
2016         RCAR_GP_PIN(7, 13),
2017 };
2018 static const unsigned int intc_irq3_mux[] = {
2019         IRQ3_MARK,
2020 };
2021 /* - MMCIF ------------------------------------------------------------------ */
2022 static const unsigned int mmc_data1_pins[] = {
2023         /* D[0] */
2024         RCAR_GP_PIN(6, 18),
2025 };
2026 static const unsigned int mmc_data1_mux[] = {
2027         MMC_D0_MARK,
2028 };
2029 static const unsigned int mmc_data4_pins[] = {
2030         /* D[0:3] */
2031         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2032         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2033 };
2034 static const unsigned int mmc_data4_mux[] = {
2035         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2036 };
2037 static const unsigned int mmc_data8_pins[] = {
2038         /* D[0:7] */
2039         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2040         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2041         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2042         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2043 };
2044 static const unsigned int mmc_data8_mux[] = {
2045         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2046         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2047 };
2048 static const unsigned int mmc_ctrl_pins[] = {
2049         /* CLK, CMD */
2050         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2051 };
2052 static const unsigned int mmc_ctrl_mux[] = {
2053         MMC_CLK_MARK, MMC_CMD_MARK,
2054 };
2055 /* - MSIOF0 ----------------------------------------------------------------- */
2056 static const unsigned int msiof0_clk_pins[] = {
2057         /* SCK */
2058         RCAR_GP_PIN(6, 24),
2059 };
2060 static const unsigned int msiof0_clk_mux[] = {
2061         MSIOF0_SCK_MARK,
2062 };
2063 static const unsigned int msiof0_sync_pins[] = {
2064         /* SYNC */
2065         RCAR_GP_PIN(6, 25),
2066 };
2067 static const unsigned int msiof0_sync_mux[] = {
2068         MSIOF0_SYNC_MARK,
2069 };
2070 static const unsigned int msiof0_ss1_pins[] = {
2071         /* SS1 */
2072         RCAR_GP_PIN(6, 28),
2073 };
2074 static const unsigned int msiof0_ss1_mux[] = {
2075         MSIOF0_SS1_MARK,
2076 };
2077 static const unsigned int msiof0_ss2_pins[] = {
2078         /* SS2 */
2079         RCAR_GP_PIN(6, 29),
2080 };
2081 static const unsigned int msiof0_ss2_mux[] = {
2082         MSIOF0_SS2_MARK,
2083 };
2084 static const unsigned int msiof0_rx_pins[] = {
2085         /* RXD */
2086         RCAR_GP_PIN(6, 27),
2087 };
2088 static const unsigned int msiof0_rx_mux[] = {
2089         MSIOF0_RXD_MARK,
2090 };
2091 static const unsigned int msiof0_tx_pins[] = {
2092         /* TXD */
2093         RCAR_GP_PIN(6, 26),
2094 };
2095 static const unsigned int msiof0_tx_mux[] = {
2096         MSIOF0_TXD_MARK,
2097 };
2098
2099 static const unsigned int msiof0_clk_b_pins[] = {
2100         /* SCK */
2101         RCAR_GP_PIN(0, 16),
2102 };
2103 static const unsigned int msiof0_clk_b_mux[] = {
2104         MSIOF0_SCK_B_MARK,
2105 };
2106 static const unsigned int msiof0_sync_b_pins[] = {
2107         /* SYNC */
2108         RCAR_GP_PIN(0, 17),
2109 };
2110 static const unsigned int msiof0_sync_b_mux[] = {
2111         MSIOF0_SYNC_B_MARK,
2112 };
2113 static const unsigned int msiof0_ss1_b_pins[] = {
2114         /* SS1 */
2115         RCAR_GP_PIN(0, 18),
2116 };
2117 static const unsigned int msiof0_ss1_b_mux[] = {
2118         MSIOF0_SS1_B_MARK,
2119 };
2120 static const unsigned int msiof0_ss2_b_pins[] = {
2121         /* SS2 */
2122         RCAR_GP_PIN(0, 19),
2123 };
2124 static const unsigned int msiof0_ss2_b_mux[] = {
2125         MSIOF0_SS2_B_MARK,
2126 };
2127 static const unsigned int msiof0_rx_b_pins[] = {
2128         /* RXD */
2129         RCAR_GP_PIN(0, 21),
2130 };
2131 static const unsigned int msiof0_rx_b_mux[] = {
2132         MSIOF0_RXD_B_MARK,
2133 };
2134 static const unsigned int msiof0_tx_b_pins[] = {
2135         /* TXD */
2136         RCAR_GP_PIN(0, 20),
2137 };
2138 static const unsigned int msiof0_tx_b_mux[] = {
2139         MSIOF0_TXD_B_MARK,
2140 };
2141
2142 static const unsigned int msiof0_clk_c_pins[] = {
2143         /* SCK */
2144         RCAR_GP_PIN(5, 26),
2145 };
2146 static const unsigned int msiof0_clk_c_mux[] = {
2147         MSIOF0_SCK_C_MARK,
2148 };
2149 static const unsigned int msiof0_sync_c_pins[] = {
2150         /* SYNC */
2151         RCAR_GP_PIN(5, 25),
2152 };
2153 static const unsigned int msiof0_sync_c_mux[] = {
2154         MSIOF0_SYNC_C_MARK,
2155 };
2156 static const unsigned int msiof0_ss1_c_pins[] = {
2157         /* SS1 */
2158         RCAR_GP_PIN(5, 27),
2159 };
2160 static const unsigned int msiof0_ss1_c_mux[] = {
2161         MSIOF0_SS1_C_MARK,
2162 };
2163 static const unsigned int msiof0_ss2_c_pins[] = {
2164         /* SS2 */
2165         RCAR_GP_PIN(5, 28),
2166 };
2167 static const unsigned int msiof0_ss2_c_mux[] = {
2168         MSIOF0_SS2_C_MARK,
2169 };
2170 static const unsigned int msiof0_rx_c_pins[] = {
2171         /* RXD */
2172         RCAR_GP_PIN(5, 29),
2173 };
2174 static const unsigned int msiof0_rx_c_mux[] = {
2175         MSIOF0_RXD_C_MARK,
2176 };
2177 static const unsigned int msiof0_tx_c_pins[] = {
2178         /* TXD */
2179         RCAR_GP_PIN(5, 30),
2180 };
2181 static const unsigned int msiof0_tx_c_mux[] = {
2182         MSIOF0_TXD_C_MARK,
2183 };
2184 /* - MSIOF1 ----------------------------------------------------------------- */
2185 static const unsigned int msiof1_clk_pins[] = {
2186         /* SCK */
2187         RCAR_GP_PIN(0, 22),
2188 };
2189 static const unsigned int msiof1_clk_mux[] = {
2190         MSIOF1_SCK_MARK,
2191 };
2192 static const unsigned int msiof1_sync_pins[] = {
2193         /* SYNC */
2194         RCAR_GP_PIN(0, 23),
2195 };
2196 static const unsigned int msiof1_sync_mux[] = {
2197         MSIOF1_SYNC_MARK,
2198 };
2199 static const unsigned int msiof1_ss1_pins[] = {
2200         /* SS1 */
2201         RCAR_GP_PIN(0, 24),
2202 };
2203 static const unsigned int msiof1_ss1_mux[] = {
2204         MSIOF1_SS1_MARK,
2205 };
2206 static const unsigned int msiof1_ss2_pins[] = {
2207         /* SS2 */
2208         RCAR_GP_PIN(0, 25),
2209 };
2210 static const unsigned int msiof1_ss2_mux[] = {
2211         MSIOF1_SS2_MARK,
2212 };
2213 static const unsigned int msiof1_rx_pins[] = {
2214         /* RXD */
2215         RCAR_GP_PIN(0, 27),
2216 };
2217 static const unsigned int msiof1_rx_mux[] = {
2218         MSIOF1_RXD_MARK,
2219 };
2220 static const unsigned int msiof1_tx_pins[] = {
2221         /* TXD */
2222         RCAR_GP_PIN(0, 26),
2223 };
2224 static const unsigned int msiof1_tx_mux[] = {
2225         MSIOF1_TXD_MARK,
2226 };
2227
2228 static const unsigned int msiof1_clk_b_pins[] = {
2229         /* SCK */
2230         RCAR_GP_PIN(2, 29),
2231 };
2232 static const unsigned int msiof1_clk_b_mux[] = {
2233         MSIOF1_SCK_B_MARK,
2234 };
2235 static const unsigned int msiof1_sync_b_pins[] = {
2236         /* SYNC */
2237         RCAR_GP_PIN(2, 30),
2238 };
2239 static const unsigned int msiof1_sync_b_mux[] = {
2240         MSIOF1_SYNC_B_MARK,
2241 };
2242 static const unsigned int msiof1_ss1_b_pins[] = {
2243         /* SS1 */
2244         RCAR_GP_PIN(2, 31),
2245 };
2246 static const unsigned int msiof1_ss1_b_mux[] = {
2247         MSIOF1_SS1_B_MARK,
2248 };
2249 static const unsigned int msiof1_ss2_b_pins[] = {
2250         /* SS2 */
2251         RCAR_GP_PIN(7, 16),
2252 };
2253 static const unsigned int msiof1_ss2_b_mux[] = {
2254         MSIOF1_SS2_B_MARK,
2255 };
2256 static const unsigned int msiof1_rx_b_pins[] = {
2257         /* RXD */
2258         RCAR_GP_PIN(7, 18),
2259 };
2260 static const unsigned int msiof1_rx_b_mux[] = {
2261         MSIOF1_RXD_B_MARK,
2262 };
2263 static const unsigned int msiof1_tx_b_pins[] = {
2264         /* TXD */
2265         RCAR_GP_PIN(7, 17),
2266 };
2267 static const unsigned int msiof1_tx_b_mux[] = {
2268         MSIOF1_TXD_B_MARK,
2269 };
2270
2271 static const unsigned int msiof1_clk_c_pins[] = {
2272         /* SCK */
2273         RCAR_GP_PIN(2, 15),
2274 };
2275 static const unsigned int msiof1_clk_c_mux[] = {
2276         MSIOF1_SCK_C_MARK,
2277 };
2278 static const unsigned int msiof1_sync_c_pins[] = {
2279         /* SYNC */
2280         RCAR_GP_PIN(2, 16),
2281 };
2282 static const unsigned int msiof1_sync_c_mux[] = {
2283         MSIOF1_SYNC_C_MARK,
2284 };
2285 static const unsigned int msiof1_rx_c_pins[] = {
2286         /* RXD */
2287         RCAR_GP_PIN(2, 18),
2288 };
2289 static const unsigned int msiof1_rx_c_mux[] = {
2290         MSIOF1_RXD_C_MARK,
2291 };
2292 static const unsigned int msiof1_tx_c_pins[] = {
2293         /* TXD */
2294         RCAR_GP_PIN(2, 17),
2295 };
2296 static const unsigned int msiof1_tx_c_mux[] = {
2297         MSIOF1_TXD_C_MARK,
2298 };
2299
2300 static const unsigned int msiof1_clk_d_pins[] = {
2301         /* SCK */
2302         RCAR_GP_PIN(0, 28),
2303 };
2304 static const unsigned int msiof1_clk_d_mux[] = {
2305         MSIOF1_SCK_D_MARK,
2306 };
2307 static const unsigned int msiof1_sync_d_pins[] = {
2308         /* SYNC */
2309         RCAR_GP_PIN(0, 30),
2310 };
2311 static const unsigned int msiof1_sync_d_mux[] = {
2312         MSIOF1_SYNC_D_MARK,
2313 };
2314 static const unsigned int msiof1_ss1_d_pins[] = {
2315         /* SS1 */
2316         RCAR_GP_PIN(0, 29),
2317 };
2318 static const unsigned int msiof1_ss1_d_mux[] = {
2319         MSIOF1_SS1_D_MARK,
2320 };
2321 static const unsigned int msiof1_rx_d_pins[] = {
2322         /* RXD */
2323         RCAR_GP_PIN(0, 27),
2324 };
2325 static const unsigned int msiof1_rx_d_mux[] = {
2326         MSIOF1_RXD_D_MARK,
2327 };
2328 static const unsigned int msiof1_tx_d_pins[] = {
2329         /* TXD */
2330         RCAR_GP_PIN(0, 26),
2331 };
2332 static const unsigned int msiof1_tx_d_mux[] = {
2333         MSIOF1_TXD_D_MARK,
2334 };
2335
2336 static const unsigned int msiof1_clk_e_pins[] = {
2337         /* SCK */
2338         RCAR_GP_PIN(5, 18),
2339 };
2340 static const unsigned int msiof1_clk_e_mux[] = {
2341         MSIOF1_SCK_E_MARK,
2342 };
2343 static const unsigned int msiof1_sync_e_pins[] = {
2344         /* SYNC */
2345         RCAR_GP_PIN(5, 19),
2346 };
2347 static const unsigned int msiof1_sync_e_mux[] = {
2348         MSIOF1_SYNC_E_MARK,
2349 };
2350 static const unsigned int msiof1_rx_e_pins[] = {
2351         /* RXD */
2352         RCAR_GP_PIN(5, 17),
2353 };
2354 static const unsigned int msiof1_rx_e_mux[] = {
2355         MSIOF1_RXD_E_MARK,
2356 };
2357 static const unsigned int msiof1_tx_e_pins[] = {
2358         /* TXD */
2359         RCAR_GP_PIN(5, 20),
2360 };
2361 static const unsigned int msiof1_tx_e_mux[] = {
2362         MSIOF1_TXD_E_MARK,
2363 };
2364 /* - MSIOF2 ----------------------------------------------------------------- */
2365 static const unsigned int msiof2_clk_pins[] = {
2366         /* SCK */
2367         RCAR_GP_PIN(1, 13),
2368 };
2369 static const unsigned int msiof2_clk_mux[] = {
2370         MSIOF2_SCK_MARK,
2371 };
2372 static const unsigned int msiof2_sync_pins[] = {
2373         /* SYNC */
2374         RCAR_GP_PIN(1, 14),
2375 };
2376 static const unsigned int msiof2_sync_mux[] = {
2377         MSIOF2_SYNC_MARK,
2378 };
2379 static const unsigned int msiof2_ss1_pins[] = {
2380         /* SS1 */
2381         RCAR_GP_PIN(1, 17),
2382 };
2383 static const unsigned int msiof2_ss1_mux[] = {
2384         MSIOF2_SS1_MARK,
2385 };
2386 static const unsigned int msiof2_ss2_pins[] = {
2387         /* SS2 */
2388         RCAR_GP_PIN(1, 18),
2389 };
2390 static const unsigned int msiof2_ss2_mux[] = {
2391         MSIOF2_SS2_MARK,
2392 };
2393 static const unsigned int msiof2_rx_pins[] = {
2394         /* RXD */
2395         RCAR_GP_PIN(1, 16),
2396 };
2397 static const unsigned int msiof2_rx_mux[] = {
2398         MSIOF2_RXD_MARK,
2399 };
2400 static const unsigned int msiof2_tx_pins[] = {
2401         /* TXD */
2402         RCAR_GP_PIN(1, 15),
2403 };
2404 static const unsigned int msiof2_tx_mux[] = {
2405         MSIOF2_TXD_MARK,
2406 };
2407
2408 static const unsigned int msiof2_clk_b_pins[] = {
2409         /* SCK */
2410         RCAR_GP_PIN(3, 0),
2411 };
2412 static const unsigned int msiof2_clk_b_mux[] = {
2413         MSIOF2_SCK_B_MARK,
2414 };
2415 static const unsigned int msiof2_sync_b_pins[] = {
2416         /* SYNC */
2417         RCAR_GP_PIN(3, 1),
2418 };
2419 static const unsigned int msiof2_sync_b_mux[] = {
2420         MSIOF2_SYNC_B_MARK,
2421 };
2422 static const unsigned int msiof2_ss1_b_pins[] = {
2423         /* SS1 */
2424         RCAR_GP_PIN(3, 8),
2425 };
2426 static const unsigned int msiof2_ss1_b_mux[] = {
2427         MSIOF2_SS1_B_MARK,
2428 };
2429 static const unsigned int msiof2_ss2_b_pins[] = {
2430         /* SS2 */
2431         RCAR_GP_PIN(3, 9),
2432 };
2433 static const unsigned int msiof2_ss2_b_mux[] = {
2434         MSIOF2_SS2_B_MARK,
2435 };
2436 static const unsigned int msiof2_rx_b_pins[] = {
2437         /* RXD */
2438         RCAR_GP_PIN(3, 17),
2439 };
2440 static const unsigned int msiof2_rx_b_mux[] = {
2441         MSIOF2_RXD_B_MARK,
2442 };
2443 static const unsigned int msiof2_tx_b_pins[] = {
2444         /* TXD */
2445         RCAR_GP_PIN(3, 16),
2446 };
2447 static const unsigned int msiof2_tx_b_mux[] = {
2448         MSIOF2_TXD_B_MARK,
2449 };
2450
2451 static const unsigned int msiof2_clk_c_pins[] = {
2452         /* SCK */
2453         RCAR_GP_PIN(2, 2),
2454 };
2455 static const unsigned int msiof2_clk_c_mux[] = {
2456         MSIOF2_SCK_C_MARK,
2457 };
2458 static const unsigned int msiof2_sync_c_pins[] = {
2459         /* SYNC */
2460         RCAR_GP_PIN(2, 3),
2461 };
2462 static const unsigned int msiof2_sync_c_mux[] = {
2463         MSIOF2_SYNC_C_MARK,
2464 };
2465 static const unsigned int msiof2_rx_c_pins[] = {
2466         /* RXD */
2467         RCAR_GP_PIN(2, 5),
2468 };
2469 static const unsigned int msiof2_rx_c_mux[] = {
2470         MSIOF2_RXD_C_MARK,
2471 };
2472 static const unsigned int msiof2_tx_c_pins[] = {
2473         /* TXD */
2474         RCAR_GP_PIN(2, 4),
2475 };
2476 static const unsigned int msiof2_tx_c_mux[] = {
2477         MSIOF2_TXD_C_MARK,
2478 };
2479
2480 static const unsigned int msiof2_clk_d_pins[] = {
2481         /* SCK */
2482         RCAR_GP_PIN(2, 14),
2483 };
2484 static const unsigned int msiof2_clk_d_mux[] = {
2485         MSIOF2_SCK_D_MARK,
2486 };
2487 static const unsigned int msiof2_sync_d_pins[] = {
2488         /* SYNC */
2489         RCAR_GP_PIN(2, 15),
2490 };
2491 static const unsigned int msiof2_sync_d_mux[] = {
2492         MSIOF2_SYNC_D_MARK,
2493 };
2494 static const unsigned int msiof2_ss1_d_pins[] = {
2495         /* SS1 */
2496         RCAR_GP_PIN(2, 17),
2497 };
2498 static const unsigned int msiof2_ss1_d_mux[] = {
2499         MSIOF2_SS1_D_MARK,
2500 };
2501 static const unsigned int msiof2_ss2_d_pins[] = {
2502         /* SS2 */
2503         RCAR_GP_PIN(2, 19),
2504 };
2505 static const unsigned int msiof2_ss2_d_mux[] = {
2506         MSIOF2_SS2_D_MARK,
2507 };
2508 static const unsigned int msiof2_rx_d_pins[] = {
2509         /* RXD */
2510         RCAR_GP_PIN(2, 18),
2511 };
2512 static const unsigned int msiof2_rx_d_mux[] = {
2513         MSIOF2_RXD_D_MARK,
2514 };
2515 static const unsigned int msiof2_tx_d_pins[] = {
2516         /* TXD */
2517         RCAR_GP_PIN(2, 16),
2518 };
2519 static const unsigned int msiof2_tx_d_mux[] = {
2520         MSIOF2_TXD_D_MARK,
2521 };
2522
2523 static const unsigned int msiof2_clk_e_pins[] = {
2524         /* SCK */
2525         RCAR_GP_PIN(7, 15),
2526 };
2527 static const unsigned int msiof2_clk_e_mux[] = {
2528         MSIOF2_SCK_E_MARK,
2529 };
2530 static const unsigned int msiof2_sync_e_pins[] = {
2531         /* SYNC */
2532         RCAR_GP_PIN(7, 16),
2533 };
2534 static const unsigned int msiof2_sync_e_mux[] = {
2535         MSIOF2_SYNC_E_MARK,
2536 };
2537 static const unsigned int msiof2_rx_e_pins[] = {
2538         /* RXD */
2539         RCAR_GP_PIN(7, 14),
2540 };
2541 static const unsigned int msiof2_rx_e_mux[] = {
2542         MSIOF2_RXD_E_MARK,
2543 };
2544 static const unsigned int msiof2_tx_e_pins[] = {
2545         /* TXD */
2546         RCAR_GP_PIN(7, 13),
2547 };
2548 static const unsigned int msiof2_tx_e_mux[] = {
2549         MSIOF2_TXD_E_MARK,
2550 };
2551 /* - QSPI ------------------------------------------------------------------- */
2552 static const unsigned int qspi_ctrl_pins[] = {
2553         /* SPCLK, SSL */
2554         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2555 };
2556 static const unsigned int qspi_ctrl_mux[] = {
2557         SPCLK_MARK, SSL_MARK,
2558 };
2559 static const unsigned int qspi_data2_pins[] = {
2560         /* MOSI_IO0, MISO_IO1 */
2561         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2562 };
2563 static const unsigned int qspi_data2_mux[] = {
2564         MOSI_IO0_MARK, MISO_IO1_MARK,
2565 };
2566 static const unsigned int qspi_data4_pins[] = {
2567         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2568         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2569         RCAR_GP_PIN(1, 8),
2570 };
2571 static const unsigned int qspi_data4_mux[] = {
2572         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2573 };
2574
2575 static const unsigned int qspi_ctrl_b_pins[] = {
2576         /* SPCLK, SSL */
2577         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
2578 };
2579 static const unsigned int qspi_ctrl_b_mux[] = {
2580         SPCLK_B_MARK, SSL_B_MARK,
2581 };
2582 static const unsigned int qspi_data2_b_pins[] = {
2583         /* MOSI_IO0, MISO_IO1 */
2584         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
2585 };
2586 static const unsigned int qspi_data2_b_mux[] = {
2587         MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
2588 };
2589 static const unsigned int qspi_data4_b_pins[] = {
2590         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2591         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
2592         RCAR_GP_PIN(6, 4),
2593 };
2594 static const unsigned int qspi_data4_b_mux[] = {
2595         SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
2596         IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
2597 };
2598 /* - SCIF0 ------------------------------------------------------------------ */
2599 static const unsigned int scif0_data_pins[] = {
2600         /* RX, TX */
2601         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2602 };
2603 static const unsigned int scif0_data_mux[] = {
2604         RX0_MARK, TX0_MARK,
2605 };
2606 static const unsigned int scif0_data_b_pins[] = {
2607         /* RX, TX */
2608         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2609 };
2610 static const unsigned int scif0_data_b_mux[] = {
2611         RX0_B_MARK, TX0_B_MARK,
2612 };
2613 static const unsigned int scif0_data_c_pins[] = {
2614         /* RX, TX */
2615         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
2616 };
2617 static const unsigned int scif0_data_c_mux[] = {
2618         RX0_C_MARK, TX0_C_MARK,
2619 };
2620 static const unsigned int scif0_data_d_pins[] = {
2621         /* RX, TX */
2622         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
2623 };
2624 static const unsigned int scif0_data_d_mux[] = {
2625         RX0_D_MARK, TX0_D_MARK,
2626 };
2627 static const unsigned int scif0_data_e_pins[] = {
2628         /* RX, TX */
2629         RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
2630 };
2631 static const unsigned int scif0_data_e_mux[] = {
2632         RX0_E_MARK, TX0_E_MARK,
2633 };
2634 /* - SCIF1 ------------------------------------------------------------------ */
2635 static const unsigned int scif1_data_pins[] = {
2636         /* RX, TX */
2637         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2638 };
2639 static const unsigned int scif1_data_mux[] = {
2640         RX1_MARK, TX1_MARK,
2641 };
2642 static const unsigned int scif1_data_b_pins[] = {
2643         /* RX, TX */
2644         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2645 };
2646 static const unsigned int scif1_data_b_mux[] = {
2647         RX1_B_MARK, TX1_B_MARK,
2648 };
2649 static const unsigned int scif1_clk_b_pins[] = {
2650         /* SCK */
2651         RCAR_GP_PIN(3, 10),
2652 };
2653 static const unsigned int scif1_clk_b_mux[] = {
2654         SCIF1_SCK_B_MARK,
2655 };
2656 static const unsigned int scif1_data_c_pins[] = {
2657         /* RX, TX */
2658         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
2659 };
2660 static const unsigned int scif1_data_c_mux[] = {
2661         RX1_C_MARK, TX1_C_MARK,
2662 };
2663 static const unsigned int scif1_data_d_pins[] = {
2664         /* RX, TX */
2665         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
2666 };
2667 static const unsigned int scif1_data_d_mux[] = {
2668         RX1_D_MARK, TX1_D_MARK,
2669 };
2670 /* - SCIF2 ------------------------------------------------------------------ */
2671 static const unsigned int scif2_data_pins[] = {
2672         /* RX, TX */
2673         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
2674 };
2675 static const unsigned int scif2_data_mux[] = {
2676         RX2_MARK, TX2_MARK,
2677 };
2678 static const unsigned int scif2_data_b_pins[] = {
2679         /* RX, TX */
2680         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2681 };
2682 static const unsigned int scif2_data_b_mux[] = {
2683         RX2_B_MARK, TX2_B_MARK,
2684 };
2685 static const unsigned int scif2_clk_b_pins[] = {
2686         /* SCK */
2687         RCAR_GP_PIN(3, 18),
2688 };
2689 static const unsigned int scif2_clk_b_mux[] = {
2690         SCIF2_SCK_B_MARK,
2691 };
2692 static const unsigned int scif2_data_c_pins[] = {
2693         /* RX, TX */
2694         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2695 };
2696 static const unsigned int scif2_data_c_mux[] = {
2697         RX2_C_MARK, TX2_C_MARK,
2698 };
2699 static const unsigned int scif2_data_e_pins[] = {
2700         /* RX, TX */
2701         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2702 };
2703 static const unsigned int scif2_data_e_mux[] = {
2704         RX2_E_MARK, TX2_E_MARK,
2705 };
2706 /* - SCIF3 ------------------------------------------------------------------ */
2707 static const unsigned int scif3_data_pins[] = {
2708         /* RX, TX */
2709         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2710 };
2711 static const unsigned int scif3_data_mux[] = {
2712         RX3_MARK, TX3_MARK,
2713 };
2714 static const unsigned int scif3_clk_pins[] = {
2715         /* SCK */
2716         RCAR_GP_PIN(3, 23),
2717 };
2718 static const unsigned int scif3_clk_mux[] = {
2719         SCIF3_SCK_MARK,
2720 };
2721 static const unsigned int scif3_data_b_pins[] = {
2722         /* RX, TX */
2723         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
2724 };
2725 static const unsigned int scif3_data_b_mux[] = {
2726         RX3_B_MARK, TX3_B_MARK,
2727 };
2728 static const unsigned int scif3_clk_b_pins[] = {
2729         /* SCK */
2730         RCAR_GP_PIN(4, 8),
2731 };
2732 static const unsigned int scif3_clk_b_mux[] = {
2733         SCIF3_SCK_B_MARK,
2734 };
2735 static const unsigned int scif3_data_c_pins[] = {
2736         /* RX, TX */
2737         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2738 };
2739 static const unsigned int scif3_data_c_mux[] = {
2740         RX3_C_MARK, TX3_C_MARK,
2741 };
2742 static const unsigned int scif3_data_d_pins[] = {
2743         /* RX, TX */
2744         RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
2745 };
2746 static const unsigned int scif3_data_d_mux[] = {
2747         RX3_D_MARK, TX3_D_MARK,
2748 };
2749 /* - SCIF4 ------------------------------------------------------------------ */
2750 static const unsigned int scif4_data_pins[] = {
2751         /* RX, TX */
2752         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
2753 };
2754 static const unsigned int scif4_data_mux[] = {
2755         RX4_MARK, TX4_MARK,
2756 };
2757 static const unsigned int scif4_data_b_pins[] = {
2758         /* RX, TX */
2759         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
2760 };
2761 static const unsigned int scif4_data_b_mux[] = {
2762         RX4_B_MARK, TX4_B_MARK,
2763 };
2764 static const unsigned int scif4_data_c_pins[] = {
2765         /* RX, TX */
2766         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
2767 };
2768 static const unsigned int scif4_data_c_mux[] = {
2769         RX4_C_MARK, TX4_C_MARK,
2770 };
2771 /* - SCIF5 ------------------------------------------------------------------ */
2772 static const unsigned int scif5_data_pins[] = {
2773         /* RX, TX */
2774         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
2775 };
2776 static const unsigned int scif5_data_mux[] = {
2777         RX5_MARK, TX5_MARK,
2778 };
2779 static const unsigned int scif5_data_b_pins[] = {
2780         /* RX, TX */
2781         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
2782 };
2783 static const unsigned int scif5_data_b_mux[] = {
2784         RX5_B_MARK, TX5_B_MARK,
2785 };
2786 /* - SCIFA0 ----------------------------------------------------------------- */
2787 static const unsigned int scifa0_data_pins[] = {
2788         /* RXD, TXD */
2789         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2790 };
2791 static const unsigned int scifa0_data_mux[] = {
2792         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2793 };
2794 static const unsigned int scifa0_data_b_pins[] = {
2795         /* RXD, TXD */
2796         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2797 };
2798 static const unsigned int scifa0_data_b_mux[] = {
2799         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2800 };
2801 /* - SCIFA1 ----------------------------------------------------------------- */
2802 static const unsigned int scifa1_data_pins[] = {
2803         /* RXD, TXD */
2804         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2805 };
2806 static const unsigned int scifa1_data_mux[] = {
2807         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2808 };
2809 static const unsigned int scifa1_clk_pins[] = {
2810         /* SCK */
2811         RCAR_GP_PIN(3, 10),
2812 };
2813 static const unsigned int scifa1_clk_mux[] = {
2814         SCIFA1_SCK_MARK,
2815 };
2816 static const unsigned int scifa1_data_b_pins[] = {
2817         /* RXD, TXD */
2818         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2819 };
2820 static const unsigned int scifa1_data_b_mux[] = {
2821         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2822 };
2823 static const unsigned int scifa1_clk_b_pins[] = {
2824         /* SCK */
2825         RCAR_GP_PIN(1, 0),
2826 };
2827 static const unsigned int scifa1_clk_b_mux[] = {
2828         SCIFA1_SCK_B_MARK,
2829 };
2830 static const unsigned int scifa1_data_c_pins[] = {
2831         /* RXD, TXD */
2832         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2833 };
2834 static const unsigned int scifa1_data_c_mux[] = {
2835         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2836 };
2837 /* - SCIFA2 ----------------------------------------------------------------- */
2838 static const unsigned int scifa2_data_pins[] = {
2839         /* RXD, TXD */
2840         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
2841 };
2842 static const unsigned int scifa2_data_mux[] = {
2843         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2844 };
2845 static const unsigned int scifa2_clk_pins[] = {
2846         /* SCK */
2847         RCAR_GP_PIN(3, 18),
2848 };
2849 static const unsigned int scifa2_clk_mux[] = {
2850         SCIFA2_SCK_MARK,
2851 };
2852 static const unsigned int scifa2_data_b_pins[] = {
2853         /* RXD, TXD */
2854         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2855 };
2856 static const unsigned int scifa2_data_b_mux[] = {
2857         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2858 };
2859 /* - SCIFA3 ----------------------------------------------------------------- */
2860 static const unsigned int scifa3_data_pins[] = {
2861         /* RXD, TXD */
2862         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2863 };
2864 static const unsigned int scifa3_data_mux[] = {
2865         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2866 };
2867 static const unsigned int scifa3_clk_pins[] = {
2868         /* SCK */
2869         RCAR_GP_PIN(3, 23),
2870 };
2871 static const unsigned int scifa3_clk_mux[] = {
2872         SCIFA3_SCK_MARK,
2873 };
2874 static const unsigned int scifa3_data_b_pins[] = {
2875         /* RXD, TXD */
2876         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
2877 };
2878 static const unsigned int scifa3_data_b_mux[] = {
2879         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
2880 };
2881 static const unsigned int scifa3_clk_b_pins[] = {
2882         /* SCK */
2883         RCAR_GP_PIN(4, 8),
2884 };
2885 static const unsigned int scifa3_clk_b_mux[] = {
2886         SCIFA3_SCK_B_MARK,
2887 };
2888 static const unsigned int scifa3_data_c_pins[] = {
2889         /* RXD, TXD */
2890         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
2891 };
2892 static const unsigned int scifa3_data_c_mux[] = {
2893         SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
2894 };
2895 static const unsigned int scifa3_clk_c_pins[] = {
2896         /* SCK */
2897         RCAR_GP_PIN(7, 22),
2898 };
2899 static const unsigned int scifa3_clk_c_mux[] = {
2900         SCIFA3_SCK_C_MARK,
2901 };
2902 /* - SCIFA4 ----------------------------------------------------------------- */
2903 static const unsigned int scifa4_data_pins[] = {
2904         /* RXD, TXD */
2905         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
2906 };
2907 static const unsigned int scifa4_data_mux[] = {
2908         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2909 };
2910 static const unsigned int scifa4_data_b_pins[] = {
2911         /* RXD, TXD */
2912         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
2913 };
2914 static const unsigned int scifa4_data_b_mux[] = {
2915         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
2916 };
2917 static const unsigned int scifa4_data_c_pins[] = {
2918         /* RXD, TXD */
2919         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
2920 };
2921 static const unsigned int scifa4_data_c_mux[] = {
2922         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
2923 };
2924 /* - SCIFA5 ----------------------------------------------------------------- */
2925 static const unsigned int scifa5_data_pins[] = {
2926         /* RXD, TXD */
2927         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
2928 };
2929 static const unsigned int scifa5_data_mux[] = {
2930         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
2931 };
2932 static const unsigned int scifa5_data_b_pins[] = {
2933         /* RXD, TXD */
2934         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2935 };
2936 static const unsigned int scifa5_data_b_mux[] = {
2937         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
2938 };
2939 static const unsigned int scifa5_data_c_pins[] = {
2940         /* RXD, TXD */
2941         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
2942 };
2943 static const unsigned int scifa5_data_c_mux[] = {
2944         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
2945 };
2946 /* - SCIFB0 ----------------------------------------------------------------- */
2947 static const unsigned int scifb0_data_pins[] = {
2948         /* RXD, TXD */
2949         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2950 };
2951 static const unsigned int scifb0_data_mux[] = {
2952         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2953 };
2954 static const unsigned int scifb0_clk_pins[] = {
2955         /* SCK */
2956         RCAR_GP_PIN(7, 2),
2957 };
2958 static const unsigned int scifb0_clk_mux[] = {
2959         SCIFB0_SCK_MARK,
2960 };
2961 static const unsigned int scifb0_ctrl_pins[] = {
2962         /* RTS, CTS */
2963         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2964 };
2965 static const unsigned int scifb0_ctrl_mux[] = {
2966         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2967 };
2968 static const unsigned int scifb0_data_b_pins[] = {
2969         /* RXD, TXD */
2970         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2971 };
2972 static const unsigned int scifb0_data_b_mux[] = {
2973         SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
2974 };
2975 static const unsigned int scifb0_clk_b_pins[] = {
2976         /* SCK */
2977         RCAR_GP_PIN(5, 31),
2978 };
2979 static const unsigned int scifb0_clk_b_mux[] = {
2980         SCIFB0_SCK_B_MARK,
2981 };
2982 static const unsigned int scifb0_ctrl_b_pins[] = {
2983         /* RTS, CTS */
2984         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
2985 };
2986 static const unsigned int scifb0_ctrl_b_mux[] = {
2987         SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
2988 };
2989 static const unsigned int scifb0_data_c_pins[] = {
2990         /* RXD, TXD */
2991         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2992 };
2993 static const unsigned int scifb0_data_c_mux[] = {
2994         SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
2995 };
2996 static const unsigned int scifb0_clk_c_pins[] = {
2997         /* SCK */
2998         RCAR_GP_PIN(2, 30),
2999 };
3000 static const unsigned int scifb0_clk_c_mux[] = {
3001         SCIFB0_SCK_C_MARK,
3002 };
3003 static const unsigned int scifb0_data_d_pins[] = {
3004         /* RXD, TXD */
3005         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3006 };
3007 static const unsigned int scifb0_data_d_mux[] = {
3008         SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3009 };
3010 static const unsigned int scifb0_clk_d_pins[] = {
3011         /* SCK */
3012         RCAR_GP_PIN(4, 17),
3013 };
3014 static const unsigned int scifb0_clk_d_mux[] = {
3015         SCIFB0_SCK_D_MARK,
3016 };
3017 /* - SCIFB1 ----------------------------------------------------------------- */
3018 static const unsigned int scifb1_data_pins[] = {
3019         /* RXD, TXD */
3020         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3021 };
3022 static const unsigned int scifb1_data_mux[] = {
3023         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3024 };
3025 static const unsigned int scifb1_clk_pins[] = {
3026         /* SCK */
3027         RCAR_GP_PIN(7, 7),
3028 };
3029 static const unsigned int scifb1_clk_mux[] = {
3030         SCIFB1_SCK_MARK,
3031 };
3032 static const unsigned int scifb1_ctrl_pins[] = {
3033         /* RTS, CTS */
3034         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3035 };
3036 static const unsigned int scifb1_ctrl_mux[] = {
3037         SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3038 };
3039 static const unsigned int scifb1_data_b_pins[] = {
3040         /* RXD, TXD */
3041         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3042 };
3043 static const unsigned int scifb1_data_b_mux[] = {
3044         SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3045 };
3046 static const unsigned int scifb1_clk_b_pins[] = {
3047         /* SCK */
3048         RCAR_GP_PIN(1, 3),
3049 };
3050 static const unsigned int scifb1_clk_b_mux[] = {
3051         SCIFB1_SCK_B_MARK,
3052 };
3053 static const unsigned int scifb1_data_c_pins[] = {
3054         /* RXD, TXD */
3055         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3056 };
3057 static const unsigned int scifb1_data_c_mux[] = {
3058         SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3059 };
3060 static const unsigned int scifb1_clk_c_pins[] = {
3061         /* SCK */
3062         RCAR_GP_PIN(7, 11),
3063 };
3064 static const unsigned int scifb1_clk_c_mux[] = {
3065         SCIFB1_SCK_C_MARK,
3066 };
3067 static const unsigned int scifb1_data_d_pins[] = {
3068         /* RXD, TXD */
3069         RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3070 };
3071 static const unsigned int scifb1_data_d_mux[] = {
3072         SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3073 };
3074 /* - SCIFB2 ----------------------------------------------------------------- */
3075 static const unsigned int scifb2_data_pins[] = {
3076         /* RXD, TXD */
3077         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3078 };
3079 static const unsigned int scifb2_data_mux[] = {
3080         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3081 };
3082 static const unsigned int scifb2_clk_pins[] = {
3083         /* SCK */
3084         RCAR_GP_PIN(4, 15),
3085 };
3086 static const unsigned int scifb2_clk_mux[] = {
3087         SCIFB2_SCK_MARK,
3088 };
3089 static const unsigned int scifb2_ctrl_pins[] = {
3090         /* RTS, CTS */
3091         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3092 };
3093 static const unsigned int scifb2_ctrl_mux[] = {
3094         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3095 };
3096 static const unsigned int scifb2_data_b_pins[] = {
3097         /* RXD, TXD */
3098         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3099 };
3100 static const unsigned int scifb2_data_b_mux[] = {
3101         SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3102 };
3103 static const unsigned int scifb2_clk_b_pins[] = {
3104         /* SCK */
3105         RCAR_GP_PIN(5, 31),
3106 };
3107 static const unsigned int scifb2_clk_b_mux[] = {
3108         SCIFB2_SCK_B_MARK,
3109 };
3110 static const unsigned int scifb2_ctrl_b_pins[] = {
3111         /* RTS, CTS */
3112         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3113 };
3114 static const unsigned int scifb2_ctrl_b_mux[] = {
3115         SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3116 };
3117 static const unsigned int scifb2_data_c_pins[] = {
3118         /* RXD, TXD */
3119         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3120 };
3121 static const unsigned int scifb2_data_c_mux[] = {
3122         SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3123 };
3124 static const unsigned int scifb2_clk_c_pins[] = {
3125         /* SCK */
3126         RCAR_GP_PIN(5, 27),
3127 };
3128 static const unsigned int scifb2_clk_c_mux[] = {
3129         SCIFB2_SCK_C_MARK,
3130 };
3131 static const unsigned int scifb2_data_d_pins[] = {
3132         /* RXD, TXD */
3133         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3134 };
3135 static const unsigned int scifb2_data_d_mux[] = {
3136         SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3137 };
3138 /* - SDHI0 ------------------------------------------------------------------ */
3139 static const unsigned int sdhi0_data1_pins[] = {
3140         /* D0 */
3141         RCAR_GP_PIN(6, 2),
3142 };
3143 static const unsigned int sdhi0_data1_mux[] = {
3144         SD0_DATA0_MARK,
3145 };
3146 static const unsigned int sdhi0_data4_pins[] = {
3147         /* D[0:3] */
3148         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3149         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3150 };
3151 static const unsigned int sdhi0_data4_mux[] = {
3152         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3153 };
3154 static const unsigned int sdhi0_ctrl_pins[] = {
3155         /* CLK, CMD */
3156         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3157 };
3158 static const unsigned int sdhi0_ctrl_mux[] = {
3159         SD0_CLK_MARK, SD0_CMD_MARK,
3160 };
3161 static const unsigned int sdhi0_cd_pins[] = {
3162         /* CD */
3163         RCAR_GP_PIN(6, 6),
3164 };
3165 static const unsigned int sdhi0_cd_mux[] = {
3166         SD0_CD_MARK,
3167 };
3168 static const unsigned int sdhi0_wp_pins[] = {
3169         /* WP */
3170         RCAR_GP_PIN(6, 7),
3171 };
3172 static const unsigned int sdhi0_wp_mux[] = {
3173         SD0_WP_MARK,
3174 };
3175 /* - SDHI1 ------------------------------------------------------------------ */
3176 static const unsigned int sdhi1_data1_pins[] = {
3177         /* D0 */
3178         RCAR_GP_PIN(6, 10),
3179 };
3180 static const unsigned int sdhi1_data1_mux[] = {
3181         SD1_DATA0_MARK,
3182 };
3183 static const unsigned int sdhi1_data4_pins[] = {
3184         /* D[0:3] */
3185         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3186         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3187 };
3188 static const unsigned int sdhi1_data4_mux[] = {
3189         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3190 };
3191 static const unsigned int sdhi1_ctrl_pins[] = {
3192         /* CLK, CMD */
3193         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3194 };
3195 static const unsigned int sdhi1_ctrl_mux[] = {
3196         SD1_CLK_MARK, SD1_CMD_MARK,
3197 };
3198 static const unsigned int sdhi1_cd_pins[] = {
3199         /* CD */
3200         RCAR_GP_PIN(6, 14),
3201 };
3202 static const unsigned int sdhi1_cd_mux[] = {
3203         SD1_CD_MARK,
3204 };
3205 static const unsigned int sdhi1_wp_pins[] = {
3206         /* WP */
3207         RCAR_GP_PIN(6, 15),
3208 };
3209 static const unsigned int sdhi1_wp_mux[] = {
3210         SD1_WP_MARK,
3211 };
3212 /* - SDHI2 ------------------------------------------------------------------ */
3213 static const unsigned int sdhi2_data1_pins[] = {
3214         /* D0 */
3215         RCAR_GP_PIN(6, 18),
3216 };
3217 static const unsigned int sdhi2_data1_mux[] = {
3218         SD2_DATA0_MARK,
3219 };
3220 static const unsigned int sdhi2_data4_pins[] = {
3221         /* D[0:3] */
3222         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3223         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3224 };
3225 static const unsigned int sdhi2_data4_mux[] = {
3226         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3227 };
3228 static const unsigned int sdhi2_ctrl_pins[] = {
3229         /* CLK, CMD */
3230         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3231 };
3232 static const unsigned int sdhi2_ctrl_mux[] = {
3233         SD2_CLK_MARK, SD2_CMD_MARK,
3234 };
3235 static const unsigned int sdhi2_cd_pins[] = {
3236         /* CD */
3237         RCAR_GP_PIN(6, 22),
3238 };
3239 static const unsigned int sdhi2_cd_mux[] = {
3240         SD2_CD_MARK,
3241 };
3242 static const unsigned int sdhi2_wp_pins[] = {
3243         /* WP */
3244         RCAR_GP_PIN(6, 23),
3245 };
3246 static const unsigned int sdhi2_wp_mux[] = {
3247         SD2_WP_MARK,
3248 };
3249 /* - USB0 ------------------------------------------------------------------- */
3250 static const unsigned int usb0_pins[] = {
3251         RCAR_GP_PIN(7, 23), /* PWEN */
3252         RCAR_GP_PIN(7, 24), /* OVC */
3253 };
3254 static const unsigned int usb0_mux[] = {
3255         USB0_PWEN_MARK,
3256         USB0_OVC_MARK,
3257 };
3258 /* - USB1 ------------------------------------------------------------------- */
3259 static const unsigned int usb1_pins[] = {
3260         RCAR_GP_PIN(7, 25), /* PWEN */
3261         RCAR_GP_PIN(6, 30), /* OVC */
3262 };
3263 static const unsigned int usb1_mux[] = {
3264         USB1_PWEN_MARK,
3265         USB1_OVC_MARK,
3266 };
3267
3268 union vin_data {
3269         unsigned int data24[24];
3270         unsigned int data20[20];
3271         unsigned int data16[16];
3272         unsigned int data12[12];
3273         unsigned int data10[10];
3274         unsigned int data8[8];
3275 };
3276
3277 #define VIN_DATA_PIN_GROUP(n, s)                                \
3278         {                                                       \
3279                 .name = #n#s,                                   \
3280                 .pins = n##_pins.data##s,                       \
3281                 .mux = n##_mux.data##s,                         \
3282                 .nr_pins = ARRAY_SIZE(n##_pins.data##s),        \
3283         }
3284
3285 /* - VIN0 ------------------------------------------------------------------- */
3286 static const union vin_data vin0_data_pins = {
3287         .data24 = {
3288                 /* B */
3289                 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
3290                 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3291                 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3292                 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3293                 /* G */
3294                 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3295                 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3296                 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3297                 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
3298                 /* R */
3299                 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
3300                 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
3301                 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
3302                 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3303         },
3304 };
3305 static const union vin_data vin0_data_mux = {
3306         .data24 = {
3307                 /* B */
3308                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3309                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3310                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3311                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3312                 /* G */
3313                 VI0_G0_MARK, VI0_G1_MARK,
3314                 VI0_G2_MARK, VI0_G3_MARK,
3315                 VI0_G4_MARK, VI0_G5_MARK,
3316                 VI0_G6_MARK, VI0_G7_MARK,
3317                 /* R */
3318                 VI0_R0_MARK, VI0_R1_MARK,
3319                 VI0_R2_MARK, VI0_R3_MARK,
3320                 VI0_R4_MARK, VI0_R5_MARK,
3321                 VI0_R6_MARK, VI0_R7_MARK,
3322         },
3323 };
3324 static const unsigned int vin0_data18_pins[] = {
3325         /* B */
3326         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3327         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3328         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3329         /* G */
3330         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3331         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3332         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
3333         /* R */
3334         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
3335         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
3336         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3337 };
3338 static const unsigned int vin0_data18_mux[] = {
3339         /* B */
3340         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3341         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3342         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3343         /* G */
3344         VI0_G2_MARK, VI0_G3_MARK,
3345         VI0_G4_MARK, VI0_G5_MARK,
3346         VI0_G6_MARK, VI0_G7_MARK,
3347         /* R */
3348         VI0_R2_MARK, VI0_R3_MARK,
3349         VI0_R4_MARK, VI0_R5_MARK,
3350         VI0_R6_MARK, VI0_R7_MARK,
3351 };
3352 static const unsigned int vin0_sync_pins[] = {
3353         RCAR_GP_PIN(4, 3), /* HSYNC */
3354         RCAR_GP_PIN(4, 4), /* VSYNC */
3355 };
3356 static const unsigned int vin0_sync_mux[] = {
3357         VI0_HSYNC_N_MARK,
3358         VI0_VSYNC_N_MARK,
3359 };
3360 static const unsigned int vin0_field_pins[] = {
3361         RCAR_GP_PIN(4, 2),
3362 };
3363 static const unsigned int vin0_field_mux[] = {
3364         VI0_FIELD_MARK,
3365 };
3366 static const unsigned int vin0_clkenb_pins[] = {
3367         RCAR_GP_PIN(4, 1),
3368 };
3369 static const unsigned int vin0_clkenb_mux[] = {
3370         VI0_CLKENB_MARK,
3371 };
3372 static const unsigned int vin0_clk_pins[] = {
3373         RCAR_GP_PIN(4, 0),
3374 };
3375 static const unsigned int vin0_clk_mux[] = {
3376         VI0_CLK_MARK,
3377 };
3378 /* - VIN1 ----------------------------------------------------------------- */
3379 static const unsigned int vin1_data8_pins[] = {
3380         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3381         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
3382         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
3383         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
3384 };
3385 static const unsigned int vin1_data8_mux[] = {
3386         VI1_DATA0_MARK, VI1_DATA1_MARK,
3387         VI1_DATA2_MARK, VI1_DATA3_MARK,
3388         VI1_DATA4_MARK, VI1_DATA5_MARK,
3389         VI1_DATA6_MARK, VI1_DATA7_MARK,
3390 };
3391 static const unsigned int vin1_sync_pins[] = {
3392         RCAR_GP_PIN(5, 0), /* HSYNC */
3393         RCAR_GP_PIN(5, 1), /* VSYNC */
3394 };
3395 static const unsigned int vin1_sync_mux[] = {
3396         VI1_HSYNC_N_MARK,
3397         VI1_VSYNC_N_MARK,
3398 };
3399 static const unsigned int vin1_field_pins[] = {
3400         RCAR_GP_PIN(5, 3),
3401 };
3402 static const unsigned int vin1_field_mux[] = {
3403         VI1_FIELD_MARK,
3404 };
3405 static const unsigned int vin1_clkenb_pins[] = {
3406         RCAR_GP_PIN(5, 2),
3407 };
3408 static const unsigned int vin1_clkenb_mux[] = {
3409         VI1_CLKENB_MARK,
3410 };
3411 static const unsigned int vin1_clk_pins[] = {
3412         RCAR_GP_PIN(5, 4),
3413 };
3414 static const unsigned int vin1_clk_mux[] = {
3415         VI1_CLK_MARK,
3416 };
3417 static const union vin_data vin1_b_data_pins = {
3418         .data24 = {
3419                 /* B */
3420                 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3421                 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3422                 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3423                 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3424                 /* G */
3425                 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3426                 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3427                 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3428                 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
3429                 /* R */
3430                 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3431                 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3432                 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
3433                 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
3434         },
3435 };
3436 static const union vin_data vin1_b_data_mux = {
3437         .data24 = {
3438                 /* B */
3439                 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
3440                 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
3441                 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
3442                 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
3443                 /* G */
3444                 VI1_G0_B_MARK, VI1_G1_B_MARK,
3445                 VI1_G2_B_MARK, VI1_G3_B_MARK,
3446                 VI1_G4_B_MARK, VI1_G5_B_MARK,
3447                 VI1_G6_B_MARK, VI1_G7_B_MARK,
3448                 /* R */
3449                 VI1_R0_B_MARK, VI1_R1_B_MARK,
3450                 VI1_R2_B_MARK, VI1_R3_B_MARK,
3451                 VI1_R4_B_MARK, VI1_R5_B_MARK,
3452                 VI1_R6_B_MARK, VI1_R7_B_MARK,
3453         },
3454 };
3455 static const unsigned int vin1_b_data18_pins[] = {
3456         /* B */
3457         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3458         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3459         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3460         /* G */
3461         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3462         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3463         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
3464         /* R */
3465         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3466         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
3467         RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
3468 };
3469 static const unsigned int vin1_b_data18_mux[] = {
3470         /* B */
3471         VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
3472         VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
3473         VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
3474         VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
3475         /* G */
3476         VI1_G0_B_MARK, VI1_G1_B_MARK,
3477         VI1_G2_B_MARK, VI1_G3_B_MARK,
3478         VI1_G4_B_MARK, VI1_G5_B_MARK,
3479         VI1_G6_B_MARK, VI1_G7_B_MARK,
3480         /* R */
3481         VI1_R0_B_MARK, VI1_R1_B_MARK,
3482         VI1_R2_B_MARK, VI1_R3_B_MARK,
3483         VI1_R4_B_MARK, VI1_R5_B_MARK,
3484         VI1_R6_B_MARK, VI1_R7_B_MARK,
3485 };
3486 static const unsigned int vin1_b_sync_pins[] = {
3487         RCAR_GP_PIN(3, 17), /* HSYNC */
3488         RCAR_GP_PIN(3, 18), /* VSYNC */
3489 };
3490 static const unsigned int vin1_b_sync_mux[] = {
3491         VI1_HSYNC_N_B_MARK,
3492         VI1_VSYNC_N_B_MARK,
3493 };
3494 static const unsigned int vin1_b_field_pins[] = {
3495         RCAR_GP_PIN(3, 20),
3496 };
3497 static const unsigned int vin1_b_field_mux[] = {
3498         VI1_FIELD_B_MARK,
3499 };
3500 static const unsigned int vin1_b_clkenb_pins[] = {
3501         RCAR_GP_PIN(3, 19),
3502 };
3503 static const unsigned int vin1_b_clkenb_mux[] = {
3504         VI1_CLKENB_B_MARK,
3505 };
3506 static const unsigned int vin1_b_clk_pins[] = {
3507         RCAR_GP_PIN(3, 16),
3508 };
3509 static const unsigned int vin1_b_clk_mux[] = {
3510         VI1_CLK_B_MARK,
3511 };
3512 /* - VIN2 ----------------------------------------------------------------- */
3513 static const unsigned int vin2_data8_pins[] = {
3514         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3515         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3516         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
3517         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
3518 };
3519 static const unsigned int vin2_data8_mux[] = {
3520         VI2_DATA0_MARK, VI2_DATA1_MARK,
3521         VI2_DATA2_MARK, VI2_DATA3_MARK,
3522         VI2_DATA4_MARK, VI2_DATA5_MARK,
3523         VI2_DATA6_MARK, VI2_DATA7_MARK,
3524 };
3525 static const unsigned int vin2_sync_pins[] = {
3526         RCAR_GP_PIN(4, 15), /* HSYNC */
3527         RCAR_GP_PIN(4, 16), /* VSYNC */
3528 };
3529 static const unsigned int vin2_sync_mux[] = {
3530         VI2_HSYNC_N_MARK,
3531         VI2_VSYNC_N_MARK,
3532 };
3533 static const unsigned int vin2_field_pins[] = {
3534         RCAR_GP_PIN(4, 18),
3535 };
3536 static const unsigned int vin2_field_mux[] = {
3537         VI2_FIELD_MARK,
3538 };
3539 static const unsigned int vin2_clkenb_pins[] = {
3540         RCAR_GP_PIN(4, 17),
3541 };
3542 static const unsigned int vin2_clkenb_mux[] = {
3543         VI2_CLKENB_MARK,
3544 };
3545 static const unsigned int vin2_clk_pins[] = {
3546         RCAR_GP_PIN(4, 19),
3547 };
3548 static const unsigned int vin2_clk_mux[] = {
3549         VI2_CLK_MARK,
3550 };
3551
3552 static const struct sh_pfc_pin_group pinmux_groups[] = {
3553         SH_PFC_PIN_GROUP(du_rgb666),
3554         SH_PFC_PIN_GROUP(du_rgb888),
3555         SH_PFC_PIN_GROUP(du_clk_out_0),
3556         SH_PFC_PIN_GROUP(du_clk_out_1),
3557         SH_PFC_PIN_GROUP(du_sync),
3558         SH_PFC_PIN_GROUP(du_cde_disp),
3559         SH_PFC_PIN_GROUP(du0_clk_in),
3560         SH_PFC_PIN_GROUP(du1_clk_in),
3561         SH_PFC_PIN_GROUP(du1_clk_in_b),
3562         SH_PFC_PIN_GROUP(du1_clk_in_c),
3563         SH_PFC_PIN_GROUP(eth_link),
3564         SH_PFC_PIN_GROUP(eth_magic),
3565         SH_PFC_PIN_GROUP(eth_mdio),
3566         SH_PFC_PIN_GROUP(eth_rmii),
3567         SH_PFC_PIN_GROUP(i2c0),
3568         SH_PFC_PIN_GROUP(i2c0_b),
3569         SH_PFC_PIN_GROUP(i2c0_c),
3570         SH_PFC_PIN_GROUP(i2c1),
3571         SH_PFC_PIN_GROUP(i2c1_b),
3572         SH_PFC_PIN_GROUP(i2c1_c),
3573         SH_PFC_PIN_GROUP(i2c1_d),
3574         SH_PFC_PIN_GROUP(i2c1_e),
3575         SH_PFC_PIN_GROUP(i2c2),
3576         SH_PFC_PIN_GROUP(i2c2_b),
3577         SH_PFC_PIN_GROUP(i2c2_c),
3578         SH_PFC_PIN_GROUP(i2c2_d),
3579         SH_PFC_PIN_GROUP(i2c3),
3580         SH_PFC_PIN_GROUP(i2c3_b),
3581         SH_PFC_PIN_GROUP(i2c3_c),
3582         SH_PFC_PIN_GROUP(i2c3_d),
3583         SH_PFC_PIN_GROUP(i2c4),
3584         SH_PFC_PIN_GROUP(i2c4_b),
3585         SH_PFC_PIN_GROUP(i2c4_c),
3586         SH_PFC_PIN_GROUP(i2c7),
3587         SH_PFC_PIN_GROUP(i2c7_b),
3588         SH_PFC_PIN_GROUP(i2c7_c),
3589         SH_PFC_PIN_GROUP(i2c8),
3590         SH_PFC_PIN_GROUP(i2c8_b),
3591         SH_PFC_PIN_GROUP(i2c8_c),
3592         SH_PFC_PIN_GROUP(intc_irq0),
3593         SH_PFC_PIN_GROUP(intc_irq1),
3594         SH_PFC_PIN_GROUP(intc_irq2),
3595         SH_PFC_PIN_GROUP(intc_irq3),
3596         SH_PFC_PIN_GROUP(mmc_data1),
3597         SH_PFC_PIN_GROUP(mmc_data4),
3598         SH_PFC_PIN_GROUP(mmc_data8),
3599         SH_PFC_PIN_GROUP(mmc_ctrl),
3600         SH_PFC_PIN_GROUP(msiof0_clk),
3601         SH_PFC_PIN_GROUP(msiof0_sync),
3602         SH_PFC_PIN_GROUP(msiof0_ss1),
3603         SH_PFC_PIN_GROUP(msiof0_ss2),
3604         SH_PFC_PIN_GROUP(msiof0_rx),
3605         SH_PFC_PIN_GROUP(msiof0_tx),
3606         SH_PFC_PIN_GROUP(msiof0_clk_b),
3607         SH_PFC_PIN_GROUP(msiof0_sync_b),
3608         SH_PFC_PIN_GROUP(msiof0_ss1_b),
3609         SH_PFC_PIN_GROUP(msiof0_ss2_b),
3610         SH_PFC_PIN_GROUP(msiof0_rx_b),
3611         SH_PFC_PIN_GROUP(msiof0_tx_b),
3612         SH_PFC_PIN_GROUP(msiof0_clk_c),
3613         SH_PFC_PIN_GROUP(msiof0_sync_c),
3614         SH_PFC_PIN_GROUP(msiof0_ss1_c),
3615         SH_PFC_PIN_GROUP(msiof0_ss2_c),
3616         SH_PFC_PIN_GROUP(msiof0_rx_c),
3617         SH_PFC_PIN_GROUP(msiof0_tx_c),
3618         SH_PFC_PIN_GROUP(msiof1_clk),
3619         SH_PFC_PIN_GROUP(msiof1_sync),
3620         SH_PFC_PIN_GROUP(msiof1_ss1),
3621         SH_PFC_PIN_GROUP(msiof1_ss2),
3622         SH_PFC_PIN_GROUP(msiof1_rx),
3623         SH_PFC_PIN_GROUP(msiof1_tx),
3624         SH_PFC_PIN_GROUP(msiof1_clk_b),
3625         SH_PFC_PIN_GROUP(msiof1_sync_b),
3626         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3627         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3628         SH_PFC_PIN_GROUP(msiof1_rx_b),
3629         SH_PFC_PIN_GROUP(msiof1_tx_b),
3630         SH_PFC_PIN_GROUP(msiof1_clk_c),
3631         SH_PFC_PIN_GROUP(msiof1_sync_c),
3632         SH_PFC_PIN_GROUP(msiof1_rx_c),
3633         SH_PFC_PIN_GROUP(msiof1_tx_c),
3634         SH_PFC_PIN_GROUP(msiof1_clk_d),
3635         SH_PFC_PIN_GROUP(msiof1_sync_d),
3636         SH_PFC_PIN_GROUP(msiof1_ss1_d),
3637         SH_PFC_PIN_GROUP(msiof1_rx_d),
3638         SH_PFC_PIN_GROUP(msiof1_tx_d),
3639         SH_PFC_PIN_GROUP(msiof1_clk_e),
3640         SH_PFC_PIN_GROUP(msiof1_sync_e),
3641         SH_PFC_PIN_GROUP(msiof1_rx_e),
3642         SH_PFC_PIN_GROUP(msiof1_tx_e),
3643         SH_PFC_PIN_GROUP(msiof2_clk),
3644         SH_PFC_PIN_GROUP(msiof2_sync),
3645         SH_PFC_PIN_GROUP(msiof2_ss1),
3646         SH_PFC_PIN_GROUP(msiof2_ss2),
3647         SH_PFC_PIN_GROUP(msiof2_rx),
3648         SH_PFC_PIN_GROUP(msiof2_tx),
3649         SH_PFC_PIN_GROUP(msiof2_clk_b),
3650         SH_PFC_PIN_GROUP(msiof2_sync_b),
3651         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3652         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3653         SH_PFC_PIN_GROUP(msiof2_rx_b),
3654         SH_PFC_PIN_GROUP(msiof2_tx_b),
3655         SH_PFC_PIN_GROUP(msiof2_clk_c),
3656         SH_PFC_PIN_GROUP(msiof2_sync_c),
3657         SH_PFC_PIN_GROUP(msiof2_rx_c),
3658         SH_PFC_PIN_GROUP(msiof2_tx_c),
3659         SH_PFC_PIN_GROUP(msiof2_clk_d),
3660         SH_PFC_PIN_GROUP(msiof2_sync_d),
3661         SH_PFC_PIN_GROUP(msiof2_ss1_d),
3662         SH_PFC_PIN_GROUP(msiof2_ss2_d),
3663         SH_PFC_PIN_GROUP(msiof2_rx_d),
3664         SH_PFC_PIN_GROUP(msiof2_tx_d),
3665         SH_PFC_PIN_GROUP(msiof2_clk_e),
3666         SH_PFC_PIN_GROUP(msiof2_sync_e),
3667         SH_PFC_PIN_GROUP(msiof2_rx_e),
3668         SH_PFC_PIN_GROUP(msiof2_tx_e),
3669         SH_PFC_PIN_GROUP(qspi_ctrl),
3670         SH_PFC_PIN_GROUP(qspi_data2),
3671         SH_PFC_PIN_GROUP(qspi_data4),
3672         SH_PFC_PIN_GROUP(qspi_ctrl_b),
3673         SH_PFC_PIN_GROUP(qspi_data2_b),
3674         SH_PFC_PIN_GROUP(qspi_data4_b),
3675         SH_PFC_PIN_GROUP(scif0_data),
3676         SH_PFC_PIN_GROUP(scif0_data_b),
3677         SH_PFC_PIN_GROUP(scif0_data_c),
3678         SH_PFC_PIN_GROUP(scif0_data_d),
3679         SH_PFC_PIN_GROUP(scif0_data_e),
3680         SH_PFC_PIN_GROUP(scif1_data),
3681         SH_PFC_PIN_GROUP(scif1_data_b),
3682         SH_PFC_PIN_GROUP(scif1_clk_b),
3683         SH_PFC_PIN_GROUP(scif1_data_c),
3684         SH_PFC_PIN_GROUP(scif1_data_d),
3685         SH_PFC_PIN_GROUP(scif2_data),
3686         SH_PFC_PIN_GROUP(scif2_data_b),
3687         SH_PFC_PIN_GROUP(scif2_clk_b),
3688         SH_PFC_PIN_GROUP(scif2_data_c),
3689         SH_PFC_PIN_GROUP(scif2_data_e),
3690         SH_PFC_PIN_GROUP(scif3_data),
3691         SH_PFC_PIN_GROUP(scif3_clk),
3692         SH_PFC_PIN_GROUP(scif3_data_b),
3693         SH_PFC_PIN_GROUP(scif3_clk_b),
3694         SH_PFC_PIN_GROUP(scif3_data_c),
3695         SH_PFC_PIN_GROUP(scif3_data_d),
3696         SH_PFC_PIN_GROUP(scif4_data),
3697         SH_PFC_PIN_GROUP(scif4_data_b),
3698         SH_PFC_PIN_GROUP(scif4_data_c),
3699         SH_PFC_PIN_GROUP(scif5_data),
3700         SH_PFC_PIN_GROUP(scif5_data_b),
3701         SH_PFC_PIN_GROUP(scifa0_data),
3702         SH_PFC_PIN_GROUP(scifa0_data_b),
3703         SH_PFC_PIN_GROUP(scifa1_data),
3704         SH_PFC_PIN_GROUP(scifa1_clk),
3705         SH_PFC_PIN_GROUP(scifa1_data_b),
3706         SH_PFC_PIN_GROUP(scifa1_clk_b),
3707         SH_PFC_PIN_GROUP(scifa1_data_c),
3708         SH_PFC_PIN_GROUP(scifa2_data),
3709         SH_PFC_PIN_GROUP(scifa2_clk),
3710         SH_PFC_PIN_GROUP(scifa2_data_b),
3711         SH_PFC_PIN_GROUP(scifa3_data),
3712         SH_PFC_PIN_GROUP(scifa3_clk),
3713         SH_PFC_PIN_GROUP(scifa3_data_b),
3714         SH_PFC_PIN_GROUP(scifa3_clk_b),
3715         SH_PFC_PIN_GROUP(scifa3_data_c),
3716         SH_PFC_PIN_GROUP(scifa3_clk_c),
3717         SH_PFC_PIN_GROUP(scifa4_data),
3718         SH_PFC_PIN_GROUP(scifa4_data_b),
3719         SH_PFC_PIN_GROUP(scifa4_data_c),
3720         SH_PFC_PIN_GROUP(scifa5_data),
3721         SH_PFC_PIN_GROUP(scifa5_data_b),
3722         SH_PFC_PIN_GROUP(scifa5_data_c),
3723         SH_PFC_PIN_GROUP(scifb0_data),
3724         SH_PFC_PIN_GROUP(scifb0_clk),
3725         SH_PFC_PIN_GROUP(scifb0_ctrl),
3726         SH_PFC_PIN_GROUP(scifb0_data_b),
3727         SH_PFC_PIN_GROUP(scifb0_clk_b),
3728         SH_PFC_PIN_GROUP(scifb0_ctrl_b),
3729         SH_PFC_PIN_GROUP(scifb0_data_c),
3730         SH_PFC_PIN_GROUP(scifb0_clk_c),
3731         SH_PFC_PIN_GROUP(scifb0_data_d),
3732         SH_PFC_PIN_GROUP(scifb0_clk_d),
3733         SH_PFC_PIN_GROUP(scifb1_data),
3734         SH_PFC_PIN_GROUP(scifb1_clk),
3735         SH_PFC_PIN_GROUP(scifb1_ctrl),
3736         SH_PFC_PIN_GROUP(scifb1_data_b),
3737         SH_PFC_PIN_GROUP(scifb1_clk_b),
3738         SH_PFC_PIN_GROUP(scifb1_data_c),
3739         SH_PFC_PIN_GROUP(scifb1_clk_c),
3740         SH_PFC_PIN_GROUP(scifb1_data_d),
3741         SH_PFC_PIN_GROUP(scifb2_data),
3742         SH_PFC_PIN_GROUP(scifb2_clk),
3743         SH_PFC_PIN_GROUP(scifb2_ctrl),
3744         SH_PFC_PIN_GROUP(scifb2_data_b),
3745         SH_PFC_PIN_GROUP(scifb2_clk_b),
3746         SH_PFC_PIN_GROUP(scifb2_ctrl_b),
3747         SH_PFC_PIN_GROUP(scifb2_data_c),
3748         SH_PFC_PIN_GROUP(scifb2_clk_c),
3749         SH_PFC_PIN_GROUP(scifb2_data_d),
3750         SH_PFC_PIN_GROUP(sdhi0_data1),
3751         SH_PFC_PIN_GROUP(sdhi0_data4),
3752         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3753         SH_PFC_PIN_GROUP(sdhi0_cd),
3754         SH_PFC_PIN_GROUP(sdhi0_wp),
3755         SH_PFC_PIN_GROUP(sdhi1_data1),
3756         SH_PFC_PIN_GROUP(sdhi1_data4),
3757         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3758         SH_PFC_PIN_GROUP(sdhi1_cd),
3759         SH_PFC_PIN_GROUP(sdhi1_wp),
3760         SH_PFC_PIN_GROUP(sdhi2_data1),
3761         SH_PFC_PIN_GROUP(sdhi2_data4),
3762         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3763         SH_PFC_PIN_GROUP(sdhi2_cd),
3764         SH_PFC_PIN_GROUP(sdhi2_wp),
3765         SH_PFC_PIN_GROUP(usb0),
3766         SH_PFC_PIN_GROUP(usb1),
3767         VIN_DATA_PIN_GROUP(vin0_data, 24),
3768         VIN_DATA_PIN_GROUP(vin0_data, 20),
3769         SH_PFC_PIN_GROUP(vin0_data18),
3770         VIN_DATA_PIN_GROUP(vin0_data, 16),
3771         VIN_DATA_PIN_GROUP(vin0_data, 12),
3772         VIN_DATA_PIN_GROUP(vin0_data, 10),
3773         VIN_DATA_PIN_GROUP(vin0_data, 8),
3774         SH_PFC_PIN_GROUP(vin0_sync),
3775         SH_PFC_PIN_GROUP(vin0_field),
3776         SH_PFC_PIN_GROUP(vin0_clkenb),
3777         SH_PFC_PIN_GROUP(vin0_clk),
3778         SH_PFC_PIN_GROUP(vin1_data8),
3779         SH_PFC_PIN_GROUP(vin1_sync),
3780         SH_PFC_PIN_GROUP(vin1_field),
3781         SH_PFC_PIN_GROUP(vin1_clkenb),
3782         SH_PFC_PIN_GROUP(vin1_clk),
3783         VIN_DATA_PIN_GROUP(vin1_b_data, 24),
3784         VIN_DATA_PIN_GROUP(vin1_b_data, 20),
3785         SH_PFC_PIN_GROUP(vin1_b_data18),
3786         VIN_DATA_PIN_GROUP(vin1_b_data, 16),
3787         VIN_DATA_PIN_GROUP(vin1_b_data, 12),
3788         VIN_DATA_PIN_GROUP(vin1_b_data, 10),
3789         VIN_DATA_PIN_GROUP(vin1_b_data, 8),
3790         SH_PFC_PIN_GROUP(vin1_b_sync),
3791         SH_PFC_PIN_GROUP(vin1_b_field),
3792         SH_PFC_PIN_GROUP(vin1_b_clkenb),
3793         SH_PFC_PIN_GROUP(vin1_b_clk),
3794         SH_PFC_PIN_GROUP(vin2_data8),
3795         SH_PFC_PIN_GROUP(vin2_sync),
3796         SH_PFC_PIN_GROUP(vin2_field),
3797         SH_PFC_PIN_GROUP(vin2_clkenb),
3798         SH_PFC_PIN_GROUP(vin2_clk),
3799 };
3800
3801 static const char * const du_groups[] = {
3802         "du_rgb666",
3803         "du_rgb888",
3804         "du_clk_out_0",
3805         "du_clk_out_1",
3806         "du_sync",
3807         "du_cde_disp",
3808 };
3809
3810 static const char * const du0_groups[] = {
3811         "du0_clk_in",
3812 };
3813
3814 static const char * const du1_groups[] = {
3815         "du1_clk_in",
3816         "du1_clk_in_b",
3817         "du1_clk_in_c",
3818 };
3819
3820 static const char * const eth_groups[] = {
3821         "eth_link",
3822         "eth_magic",
3823         "eth_mdio",
3824         "eth_rmii",
3825 };
3826
3827 static const char * const i2c0_groups[] = {
3828         "i2c0",
3829         "i2c0_b",
3830         "i2c0_c",
3831 };
3832
3833 static const char * const i2c1_groups[] = {
3834         "i2c1",
3835         "i2c1_b",
3836         "i2c1_c",
3837         "i2c1_d",
3838         "i2c1_e",
3839 };
3840
3841 static const char * const i2c2_groups[] = {
3842         "i2c2",
3843         "i2c2_b",
3844         "i2c2_c",
3845         "i2c2_d",
3846 };
3847
3848 static const char * const i2c3_groups[] = {
3849         "i2c3",
3850         "i2c3_b",
3851         "i2c3_c",
3852         "i2c3_d",
3853 };
3854
3855 static const char * const i2c4_groups[] = {
3856         "i2c4",
3857         "i2c4_b",
3858         "i2c4_c",
3859 };
3860
3861 static const char * const i2c7_groups[] = {
3862         "i2c7",
3863         "i2c7_b",
3864         "i2c7_c",
3865 };
3866
3867 static const char * const i2c8_groups[] = {
3868         "i2c8",
3869         "i2c8_b",
3870         "i2c8_c",
3871 };
3872
3873 static const char * const intc_groups[] = {
3874         "intc_irq0",
3875         "intc_irq1",
3876         "intc_irq2",
3877         "intc_irq3",
3878 };
3879
3880 static const char * const mmc_groups[] = {
3881         "mmc_data1",
3882         "mmc_data4",
3883         "mmc_data8",
3884         "mmc_ctrl",
3885 };
3886
3887 static const char * const msiof0_groups[] = {
3888         "msiof0_clk",
3889         "msiof0_sync",
3890         "msiof0_ss1",
3891         "msiof0_ss2",
3892         "msiof0_rx",
3893         "msiof0_tx",
3894         "msiof0_clk_b",
3895         "msiof0_sync_b",
3896         "msiof0_ss1_b",
3897         "msiof0_ss2_b",
3898         "msiof0_rx_b",
3899         "msiof0_tx_b",
3900         "msiof0_clk_c",
3901         "msiof0_sync_c",
3902         "msiof0_ss1_c",
3903         "msiof0_ss2_c",
3904         "msiof0_rx_c",
3905         "msiof0_tx_c",
3906 };
3907
3908 static const char * const msiof1_groups[] = {
3909         "msiof1_clk",
3910         "msiof1_sync",
3911         "msiof1_ss1",
3912         "msiof1_ss2",
3913         "msiof1_rx",
3914         "msiof1_tx",
3915         "msiof1_clk_b",
3916         "msiof1_sync_b",
3917         "msiof1_ss1_b",
3918         "msiof1_ss2_b",
3919         "msiof1_rx_b",
3920         "msiof1_tx_b",
3921         "msiof1_clk_c",
3922         "msiof1_sync_c",
3923         "msiof1_rx_c",
3924         "msiof1_tx_c",
3925         "msiof1_clk_d",
3926         "msiof1_sync_d",
3927         "msiof1_ss1_d",
3928         "msiof1_rx_d",
3929         "msiof1_tx_d",
3930         "msiof1_clk_e",
3931         "msiof1_sync_e",
3932         "msiof1_rx_e",
3933         "msiof1_tx_e",
3934 };
3935
3936 static const char * const msiof2_groups[] = {
3937         "msiof2_clk",
3938         "msiof2_sync",
3939         "msiof2_ss1",
3940         "msiof2_ss2",
3941         "msiof2_rx",
3942         "msiof2_tx",
3943         "msiof2_clk_b",
3944         "msiof2_sync_b",
3945         "msiof2_ss1_b",
3946         "msiof2_ss2_b",
3947         "msiof2_rx_b",
3948         "msiof2_tx_b",
3949         "msiof2_clk_c",
3950         "msiof2_sync_c",
3951         "msiof2_rx_c",
3952         "msiof2_tx_c",
3953         "msiof2_clk_d",
3954         "msiof2_sync_d",
3955         "msiof2_ss1_d",
3956         "msiof2_ss2_d",
3957         "msiof2_rx_d",
3958         "msiof2_tx_d",
3959         "msiof2_clk_e",
3960         "msiof2_sync_e",
3961         "msiof2_rx_e",
3962         "msiof2_tx_e",
3963 };
3964
3965 static const char * const qspi_groups[] = {
3966         "qspi_ctrl",
3967         "qspi_data2",
3968         "qspi_data4",
3969         "qspi_ctrl_b",
3970         "qspi_data2_b",
3971         "qspi_data4_b",
3972 };
3973
3974 static const char * const scif0_groups[] = {
3975         "scif0_data",
3976         "scif0_data_b",
3977         "scif0_data_c",
3978         "scif0_data_d",
3979         "scif0_data_e",
3980 };
3981
3982 static const char * const scif1_groups[] = {
3983         "scif1_data",
3984         "scif1_data_b",
3985         "scif1_clk_b",
3986         "scif1_data_c",
3987         "scif1_data_d",
3988 };
3989
3990 static const char * const scif2_groups[] = {
3991         "scif2_data",
3992         "scif2_data_b",
3993         "scif2_clk_b",
3994         "scif2_data_c",
3995         "scif2_data_e",
3996 };
3997 static const char * const scif3_groups[] = {
3998         "scif3_data",
3999         "scif3_clk",
4000         "scif3_data_b",
4001         "scif3_clk_b",
4002         "scif3_data_c",
4003         "scif3_data_d",
4004 };
4005 static const char * const scif4_groups[] = {
4006         "scif4_data",
4007         "scif4_data_b",
4008         "scif4_data_c",
4009 };
4010 static const char * const scif5_groups[] = {
4011         "scif5_data",
4012         "scif5_data_b",
4013 };
4014 static const char * const scifa0_groups[] = {
4015         "scifa0_data",
4016         "scifa0_data_b",
4017 };
4018 static const char * const scifa1_groups[] = {
4019         "scifa1_data",
4020         "scifa1_clk",
4021         "scifa1_data_b",
4022         "scifa1_clk_b",
4023         "scifa1_data_c",
4024 };
4025 static const char * const scifa2_groups[] = {
4026         "scifa2_data",
4027         "scifa2_clk",
4028         "scifa2_data_b",
4029 };
4030 static const char * const scifa3_groups[] = {
4031         "scifa3_data",
4032         "scifa3_clk",
4033         "scifa3_data_b",
4034         "scifa3_clk_b",
4035         "scifa3_data_c",
4036         "scifa3_clk_c",
4037 };
4038 static const char * const scifa4_groups[] = {
4039         "scifa4_data",
4040         "scifa4_data_b",
4041         "scifa4_data_c",
4042 };
4043 static const char * const scifa5_groups[] = {
4044         "scifa5_data",
4045         "scifa5_data_b",
4046         "scifa5_data_c",
4047 };
4048 static const char * const scifb0_groups[] = {
4049         "scifb0_data",
4050         "scifb0_clk",
4051         "scifb0_ctrl",
4052         "scifb0_data_b",
4053         "scifb0_clk_b",
4054         "scifb0_ctrl_b",
4055         "scifb0_data_c",
4056         "scifb0_clk_c",
4057         "scifb0_data_d",
4058         "scifb0_clk_d",
4059 };
4060 static const char * const scifb1_groups[] = {
4061         "scifb1_data",
4062         "scifb1_clk",
4063         "scifb1_ctrl",
4064         "scifb1_data_b",
4065         "scifb1_clk_b",
4066         "scifb1_data_c",
4067         "scifb1_clk_c",
4068         "scifb1_data_d",
4069 };
4070 static const char * const scifb2_groups[] = {
4071         "scifb2_data",
4072         "scifb2_clk",
4073         "scifb2_ctrl",
4074         "scifb2_data_b",
4075         "scifb2_clk_b",
4076         "scifb2_ctrl_b",
4077         "scifb0_data_c",
4078         "scifb2_clk_c",
4079         "scifb2_data_d",
4080 };
4081
4082 static const char * const sdhi0_groups[] = {
4083         "sdhi0_data1",
4084         "sdhi0_data4",
4085         "sdhi0_ctrl",
4086         "sdhi0_cd",
4087         "sdhi0_wp",
4088 };
4089
4090 static const char * const sdhi1_groups[] = {
4091         "sdhi1_data1",
4092         "sdhi1_data4",
4093         "sdhi1_ctrl",
4094         "sdhi1_cd",
4095         "sdhi1_wp",
4096 };
4097
4098 static const char * const sdhi2_groups[] = {
4099         "sdhi2_data1",
4100         "sdhi2_data4",
4101         "sdhi2_ctrl",
4102         "sdhi2_cd",
4103         "sdhi2_wp",
4104 };
4105
4106 static const char * const usb0_groups[] = {
4107         "usb0",
4108 };
4109 static const char * const usb1_groups[] = {
4110         "usb1",
4111 };
4112
4113 static const char * const vin0_groups[] = {
4114         "vin0_data24",
4115         "vin0_data20",
4116         "vin0_data18",
4117         "vin0_data16",
4118         "vin0_data12",
4119         "vin0_data10",
4120         "vin0_data8",
4121         "vin0_sync",
4122         "vin0_field",
4123         "vin0_clkenb",
4124         "vin0_clk",
4125 };
4126
4127 static const char * const vin1_groups[] = {
4128         "vin1_data8",
4129         "vin1_sync",
4130         "vin1_field",
4131         "vin1_clkenb",
4132         "vin1_clk",
4133         "vin1_b_data24",
4134         "vin1_b_data20",
4135         "vin1_b_data18",
4136         "vin1_b_data16",
4137         "vin1_b_data12",
4138         "vin1_b_data10",
4139         "vin1_b_data8",
4140         "vin1_b_sync",
4141         "vin1_b_field",
4142         "vin1_b_clkenb",
4143         "vin1_b_clk",
4144 };
4145
4146 static const char * const vin2_groups[] = {
4147         "vin2_data8",
4148         "vin2_sync",
4149         "vin2_field",
4150         "vin2_clkenb",
4151         "vin2_clk",
4152 };
4153
4154 static const struct sh_pfc_function pinmux_functions[] = {
4155         SH_PFC_FUNCTION(du),
4156         SH_PFC_FUNCTION(du0),
4157         SH_PFC_FUNCTION(du1),
4158         SH_PFC_FUNCTION(eth),
4159         SH_PFC_FUNCTION(i2c0),
4160         SH_PFC_FUNCTION(i2c1),
4161         SH_PFC_FUNCTION(i2c2),
4162         SH_PFC_FUNCTION(i2c3),
4163         SH_PFC_FUNCTION(i2c4),
4164         SH_PFC_FUNCTION(i2c7),
4165         SH_PFC_FUNCTION(i2c8),
4166         SH_PFC_FUNCTION(intc),
4167         SH_PFC_FUNCTION(mmc),
4168         SH_PFC_FUNCTION(msiof0),
4169         SH_PFC_FUNCTION(msiof1),
4170         SH_PFC_FUNCTION(msiof2),
4171         SH_PFC_FUNCTION(qspi),
4172         SH_PFC_FUNCTION(scif0),
4173         SH_PFC_FUNCTION(scif1),
4174         SH_PFC_FUNCTION(scif2),
4175         SH_PFC_FUNCTION(scif3),
4176         SH_PFC_FUNCTION(scif4),
4177         SH_PFC_FUNCTION(scif5),
4178         SH_PFC_FUNCTION(scifa0),
4179         SH_PFC_FUNCTION(scifa1),
4180         SH_PFC_FUNCTION(scifa2),
4181         SH_PFC_FUNCTION(scifa3),
4182         SH_PFC_FUNCTION(scifa4),
4183         SH_PFC_FUNCTION(scifa5),
4184         SH_PFC_FUNCTION(scifb0),
4185         SH_PFC_FUNCTION(scifb1),
4186         SH_PFC_FUNCTION(scifb2),
4187         SH_PFC_FUNCTION(sdhi0),
4188         SH_PFC_FUNCTION(sdhi1),
4189         SH_PFC_FUNCTION(sdhi2),
4190         SH_PFC_FUNCTION(usb0),
4191         SH_PFC_FUNCTION(usb1),
4192         SH_PFC_FUNCTION(vin0),
4193         SH_PFC_FUNCTION(vin1),
4194         SH_PFC_FUNCTION(vin2),
4195 };
4196
4197 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4198         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4199                 GP_0_31_FN, FN_IP1_22_20,
4200                 GP_0_30_FN, FN_IP1_19_17,
4201                 GP_0_29_FN, FN_IP1_16_14,
4202                 GP_0_28_FN, FN_IP1_13_11,
4203                 GP_0_27_FN, FN_IP1_10_8,
4204                 GP_0_26_FN, FN_IP1_7_6,
4205                 GP_0_25_FN, FN_IP1_5_4,
4206                 GP_0_24_FN, FN_IP1_3_2,
4207                 GP_0_23_FN, FN_IP1_1_0,
4208                 GP_0_22_FN, FN_IP0_30_29,
4209                 GP_0_21_FN, FN_IP0_28_27,
4210                 GP_0_20_FN, FN_IP0_26_25,
4211                 GP_0_19_FN, FN_IP0_24_23,
4212                 GP_0_18_FN, FN_IP0_22_21,
4213                 GP_0_17_FN, FN_IP0_20_19,
4214                 GP_0_16_FN, FN_IP0_18_16,
4215                 GP_0_15_FN, FN_IP0_15,
4216                 GP_0_14_FN, FN_IP0_14,
4217                 GP_0_13_FN, FN_IP0_13,
4218                 GP_0_12_FN, FN_IP0_12,
4219                 GP_0_11_FN, FN_IP0_11,
4220                 GP_0_10_FN, FN_IP0_10,
4221                 GP_0_9_FN, FN_IP0_9,
4222                 GP_0_8_FN, FN_IP0_8,
4223                 GP_0_7_FN, FN_IP0_7,
4224                 GP_0_6_FN, FN_IP0_6,
4225                 GP_0_5_FN, FN_IP0_5,
4226                 GP_0_4_FN, FN_IP0_4,
4227                 GP_0_3_FN, FN_IP0_3,
4228                 GP_0_2_FN, FN_IP0_2,
4229                 GP_0_1_FN, FN_IP0_1,
4230                 GP_0_0_FN, FN_IP0_0, }
4231         },
4232         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4233                 0, 0,
4234                 0, 0,
4235                 0, 0,
4236                 0, 0,
4237                 0, 0,
4238                 0, 0,
4239                 GP_1_25_FN, FN_IP3_21_20,
4240                 GP_1_24_FN, FN_IP3_19_18,
4241                 GP_1_23_FN, FN_IP3_17_16,
4242                 GP_1_22_FN, FN_IP3_15_14,
4243                 GP_1_21_FN, FN_IP3_13_12,
4244                 GP_1_20_FN, FN_IP3_11_9,
4245                 GP_1_19_FN, FN_RD_N,
4246                 GP_1_18_FN, FN_IP3_8_6,
4247                 GP_1_17_FN, FN_IP3_5_3,
4248                 GP_1_16_FN, FN_IP3_2_0,
4249                 GP_1_15_FN, FN_IP2_29_27,
4250                 GP_1_14_FN, FN_IP2_26_25,
4251                 GP_1_13_FN, FN_IP2_24_23,
4252                 GP_1_12_FN, FN_EX_CS0_N,
4253                 GP_1_11_FN, FN_IP2_22_21,
4254                 GP_1_10_FN, FN_IP2_20_19,
4255                 GP_1_9_FN, FN_IP2_18_16,
4256                 GP_1_8_FN, FN_IP2_15_13,
4257                 GP_1_7_FN, FN_IP2_12_10,
4258                 GP_1_6_FN, FN_IP2_9_7,
4259                 GP_1_5_FN, FN_IP2_6_5,
4260                 GP_1_4_FN, FN_IP2_4_3,
4261                 GP_1_3_FN, FN_IP2_2_0,
4262                 GP_1_2_FN, FN_IP1_31_29,
4263                 GP_1_1_FN, FN_IP1_28_26,
4264                 GP_1_0_FN, FN_IP1_25_23, }
4265         },
4266         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4267                 GP_2_31_FN, FN_IP6_7_6,
4268                 GP_2_30_FN, FN_IP6_5_3,
4269                 GP_2_29_FN, FN_IP6_2_0,
4270                 GP_2_28_FN, FN_AUDIO_CLKA,
4271                 GP_2_27_FN, FN_IP5_31_29,
4272                 GP_2_26_FN, FN_IP5_28_26,
4273                 GP_2_25_FN, FN_IP5_25_24,
4274                 GP_2_24_FN, FN_IP5_23_22,
4275                 GP_2_23_FN, FN_IP5_21_20,
4276                 GP_2_22_FN, FN_IP5_19_17,
4277                 GP_2_21_FN, FN_IP5_16_15,
4278                 GP_2_20_FN, FN_IP5_14_12,
4279                 GP_2_19_FN, FN_IP5_11_9,
4280                 GP_2_18_FN, FN_IP5_8_6,
4281                 GP_2_17_FN, FN_IP5_5_3,
4282                 GP_2_16_FN, FN_IP5_2_0,
4283                 GP_2_15_FN, FN_IP4_30_28,
4284                 GP_2_14_FN, FN_IP4_27_26,
4285                 GP_2_13_FN, FN_IP4_25_24,
4286                 GP_2_12_FN, FN_IP4_23_22,
4287                 GP_2_11_FN, FN_IP4_21,
4288                 GP_2_10_FN, FN_IP4_20,
4289                 GP_2_9_FN, FN_IP4_19,
4290                 GP_2_8_FN, FN_IP4_18_16,
4291                 GP_2_7_FN, FN_IP4_15_13,
4292                 GP_2_6_FN, FN_IP4_12_10,
4293                 GP_2_5_FN, FN_IP4_9_8,
4294                 GP_2_4_FN, FN_IP4_7_5,
4295                 GP_2_3_FN, FN_IP4_4_2,
4296                 GP_2_2_FN, FN_IP4_1_0,
4297                 GP_2_1_FN, FN_IP3_30_28,
4298                 GP_2_0_FN, FN_IP3_27_25 }
4299         },
4300         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4301                 GP_3_31_FN, FN_IP9_18_17,
4302                 GP_3_30_FN, FN_IP9_16,
4303                 GP_3_29_FN, FN_IP9_15_13,
4304                 GP_3_28_FN, FN_IP9_12,
4305                 GP_3_27_FN, FN_IP9_11,
4306                 GP_3_26_FN, FN_IP9_10_8,
4307                 GP_3_25_FN, FN_IP9_7,
4308                 GP_3_24_FN, FN_IP9_6,
4309                 GP_3_23_FN, FN_IP9_5_3,
4310                 GP_3_22_FN, FN_IP9_2_0,
4311                 GP_3_21_FN, FN_IP8_30_28,
4312                 GP_3_20_FN, FN_IP8_27_26,
4313                 GP_3_19_FN, FN_IP8_25_24,
4314                 GP_3_18_FN, FN_IP8_23_21,
4315                 GP_3_17_FN, FN_IP8_20_18,
4316                 GP_3_16_FN, FN_IP8_17_15,
4317                 GP_3_15_FN, FN_IP8_14_12,
4318                 GP_3_14_FN, FN_IP8_11_9,
4319                 GP_3_13_FN, FN_IP8_8_6,
4320                 GP_3_12_FN, FN_IP8_5_3,
4321                 GP_3_11_FN, FN_IP8_2_0,
4322                 GP_3_10_FN, FN_IP7_29_27,
4323                 GP_3_9_FN, FN_IP7_26_24,
4324                 GP_3_8_FN, FN_IP7_23_21,
4325                 GP_3_7_FN, FN_IP7_20_19,
4326                 GP_3_6_FN, FN_IP7_18_17,
4327                 GP_3_5_FN, FN_IP7_16_15,
4328                 GP_3_4_FN, FN_IP7_14_13,
4329                 GP_3_3_FN, FN_IP7_12_11,
4330                 GP_3_2_FN, FN_IP7_10_9,
4331                 GP_3_1_FN, FN_IP7_8_6,
4332                 GP_3_0_FN, FN_IP7_5_3 }
4333         },
4334         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4335                 GP_4_31_FN, FN_IP15_5_4,
4336                 GP_4_30_FN, FN_IP15_3_2,
4337                 GP_4_29_FN, FN_IP15_1_0,
4338                 GP_4_28_FN, FN_IP11_8_6,
4339                 GP_4_27_FN, FN_IP11_5_3,
4340                 GP_4_26_FN, FN_IP11_2_0,
4341                 GP_4_25_FN, FN_IP10_31_29,
4342                 GP_4_24_FN, FN_IP10_28_27,
4343                 GP_4_23_FN, FN_IP10_26_25,
4344                 GP_4_22_FN, FN_IP10_24_22,
4345                 GP_4_21_FN, FN_IP10_21_19,
4346                 GP_4_20_FN, FN_IP10_18_17,
4347                 GP_4_19_FN, FN_IP10_16_15,
4348                 GP_4_18_FN, FN_IP10_14_12,
4349                 GP_4_17_FN, FN_IP10_11_9,
4350                 GP_4_16_FN, FN_IP10_8_6,
4351                 GP_4_15_FN, FN_IP10_5_3,
4352                 GP_4_14_FN, FN_IP10_2_0,
4353                 GP_4_13_FN, FN_IP9_31_29,
4354                 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
4355                 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
4356                 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
4357                 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
4358                 GP_4_8_FN, FN_IP9_28_27,
4359                 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
4360                 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
4361                 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
4362                 GP_4_4_FN, FN_IP9_26_25,
4363                 GP_4_3_FN, FN_IP9_24_23,
4364                 GP_4_2_FN, FN_IP9_22_21,
4365                 GP_4_1_FN, FN_IP9_20_19,
4366                 GP_4_0_FN, FN_VI0_CLK }
4367         },
4368         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4369                 GP_5_31_FN, FN_IP3_24_22,
4370                 GP_5_30_FN, FN_IP13_9_7,
4371                 GP_5_29_FN, FN_IP13_6_5,
4372                 GP_5_28_FN, FN_IP13_4_3,
4373                 GP_5_27_FN, FN_IP13_2_0,
4374                 GP_5_26_FN, FN_IP12_29_27,
4375                 GP_5_25_FN, FN_IP12_26_24,
4376                 GP_5_24_FN, FN_IP12_23_22,
4377                 GP_5_23_FN, FN_IP12_21_20,
4378                 GP_5_22_FN, FN_IP12_19_18,
4379                 GP_5_21_FN, FN_IP12_17_16,
4380                 GP_5_20_FN, FN_IP12_15_13,
4381                 GP_5_19_FN, FN_IP12_12_10,
4382                 GP_5_18_FN, FN_IP12_9_7,
4383                 GP_5_17_FN, FN_IP12_6_4,
4384                 GP_5_16_FN, FN_IP12_3_2,
4385                 GP_5_15_FN, FN_IP12_1_0,
4386                 GP_5_14_FN, FN_IP11_31_30,
4387                 GP_5_13_FN, FN_IP11_29_28,
4388                 GP_5_12_FN, FN_IP11_27,
4389                 GP_5_11_FN, FN_IP11_26,
4390                 GP_5_10_FN, FN_IP11_25,
4391                 GP_5_9_FN, FN_IP11_24,
4392                 GP_5_8_FN, FN_IP11_23,
4393                 GP_5_7_FN, FN_IP11_22,
4394                 GP_5_6_FN, FN_IP11_21,
4395                 GP_5_5_FN, FN_IP11_20,
4396                 GP_5_4_FN, FN_IP11_19,
4397                 GP_5_3_FN, FN_IP11_18_17,
4398                 GP_5_2_FN, FN_IP11_16_15,
4399                 GP_5_1_FN, FN_IP11_14_12,
4400                 GP_5_0_FN, FN_IP11_11_9 }
4401         },
4402         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
4403                 GP_6_31_FN, FN_DU0_DOTCLKIN,
4404                 GP_6_30_FN, FN_USB1_OVC,
4405                 GP_6_29_FN, FN_IP14_31_29,
4406                 GP_6_28_FN, FN_IP14_28_26,
4407                 GP_6_27_FN, FN_IP14_25_23,
4408                 GP_6_26_FN, FN_IP14_22_20,
4409                 GP_6_25_FN, FN_IP14_19_17,
4410                 GP_6_24_FN, FN_IP14_16_14,
4411                 GP_6_23_FN, FN_IP14_13_11,
4412                 GP_6_22_FN, FN_IP14_10_8,
4413                 GP_6_21_FN, FN_IP14_7,
4414                 GP_6_20_FN, FN_IP14_6,
4415                 GP_6_19_FN, FN_IP14_5,
4416                 GP_6_18_FN, FN_IP14_4,
4417                 GP_6_17_FN, FN_IP14_3,
4418                 GP_6_16_FN, FN_IP14_2,
4419                 GP_6_15_FN, FN_IP14_1_0,
4420                 GP_6_14_FN, FN_IP13_30_28,
4421                 GP_6_13_FN, FN_IP13_27,
4422                 GP_6_12_FN, FN_IP13_26,
4423                 GP_6_11_FN, FN_IP13_25,
4424                 GP_6_10_FN, FN_IP13_24_23,
4425                 GP_6_9_FN, FN_IP13_22,
4426                 GP_6_8_FN, FN_SD1_CLK,
4427                 GP_6_7_FN, FN_IP13_21_19,
4428                 GP_6_6_FN, FN_IP13_18_16,
4429                 GP_6_5_FN, FN_IP13_15,
4430                 GP_6_4_FN, FN_IP13_14,
4431                 GP_6_3_FN, FN_IP13_13,
4432                 GP_6_2_FN, FN_IP13_12,
4433                 GP_6_1_FN, FN_IP13_11,
4434                 GP_6_0_FN, FN_IP13_10 }
4435         },
4436         { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
4437                 0, 0,
4438                 0, 0,
4439                 0, 0,
4440                 0, 0,
4441                 0, 0,
4442                 0, 0,
4443                 GP_7_25_FN, FN_USB1_PWEN,
4444                 GP_7_24_FN, FN_USB0_OVC,
4445                 GP_7_23_FN, FN_USB0_PWEN,
4446                 GP_7_22_FN, FN_IP15_14_12,
4447                 GP_7_21_FN, FN_IP15_11_9,
4448                 GP_7_20_FN, FN_IP15_8_6,
4449                 GP_7_19_FN, FN_IP7_2_0,
4450                 GP_7_18_FN, FN_IP6_29_27,
4451                 GP_7_17_FN, FN_IP6_26_24,
4452                 GP_7_16_FN, FN_IP6_23_21,
4453                 GP_7_15_FN, FN_IP6_20_19,
4454                 GP_7_14_FN, FN_IP6_18_16,
4455                 GP_7_13_FN, FN_IP6_15_14,
4456                 GP_7_12_FN, FN_IP6_13_12,
4457                 GP_7_11_FN, FN_IP6_11_10,
4458                 GP_7_10_FN, FN_IP6_9_8,
4459                 GP_7_9_FN, FN_IP16_11_10,
4460                 GP_7_8_FN, FN_IP16_9_8,
4461                 GP_7_7_FN, FN_IP16_7_6,
4462                 GP_7_6_FN, FN_IP16_5_3,
4463                 GP_7_5_FN, FN_IP16_2_0,
4464                 GP_7_4_FN, FN_IP15_29_27,
4465                 GP_7_3_FN, FN_IP15_26_24,
4466                 GP_7_2_FN, FN_IP15_23_21,
4467                 GP_7_1_FN, FN_IP15_20_18,
4468                 GP_7_0_FN, FN_IP15_17_15 }
4469         },
4470         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4471                              1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
4472                              1, 1, 1, 1, 1, 1, 1, 1) {
4473                 /* IP0_31 [1] */
4474                 0, 0,
4475                 /* IP0_30_29 [2] */
4476                 FN_A6, FN_MSIOF1_SCK,
4477                 0, 0,
4478                 /* IP0_28_27 [2] */
4479                 FN_A5, FN_MSIOF0_RXD_B,
4480                 0, 0,
4481                 /* IP0_26_25 [2] */
4482                 FN_A4, FN_MSIOF0_TXD_B,
4483                 0, 0,
4484                 /* IP0_24_23 [2] */
4485                 FN_A3, FN_MSIOF0_SS2_B,
4486                 0, 0,
4487                 /* IP0_22_21 [2] */
4488                 FN_A2, FN_MSIOF0_SS1_B,
4489                 0, 0,
4490                 /* IP0_20_19 [2] */
4491                 FN_A1, FN_MSIOF0_SYNC_B,
4492                 0, 0,
4493                 /* IP0_18_16 [3] */
4494                 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
4495                 0, 0, 0,
4496                 /* IP0_15 [1] */
4497                 FN_D15, 0,
4498                 /* IP0_14 [1] */
4499                 FN_D14, 0,
4500                 /* IP0_13 [1] */
4501                 FN_D13, 0,
4502                 /* IP0_12 [1] */
4503                 FN_D12, 0,
4504                 /* IP0_11 [1] */
4505                 FN_D11, 0,
4506                 /* IP0_10 [1] */
4507                 FN_D10, 0,
4508                 /* IP0_9 [1] */
4509                 FN_D9, 0,
4510                 /* IP0_8 [1] */
4511                 FN_D8, 0,
4512                 /* IP0_7 [1] */
4513                 FN_D7, 0,
4514                 /* IP0_6 [1] */
4515                 FN_D6, 0,
4516                 /* IP0_5 [1] */
4517                 FN_D5, 0,
4518                 /* IP0_4 [1] */
4519                 FN_D4, 0,
4520                 /* IP0_3 [1] */
4521                 FN_D3, 0,
4522                 /* IP0_2 [1] */
4523                 FN_D2, 0,
4524                 /* IP0_1 [1] */
4525                 FN_D1, 0,
4526                 /* IP0_0 [1] */
4527                 FN_D0, 0, }
4528         },
4529         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4530                              3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
4531                 /* IP1_31_29 [3] */
4532                 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
4533                 0, 0, 0,
4534                 /* IP1_28_26 [3] */
4535                 FN_A17, FN_DACK2_B, 0, FN_SDA0_C,
4536                 0, 0, 0, 0,
4537                 /* IP1_25_23 [3] */
4538                 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
4539                 0, 0, 0,
4540                 /* IP1_22_20 [3] */
4541                 FN_A15, FN_BPFCLK_C,
4542                 0, 0, 0, 0, 0, 0,
4543                 /* IP1_19_17 [3] */
4544                 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
4545                 0, 0, 0,
4546                 /* IP1_16_14 [3] */
4547                 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
4548                 0, 0, 0, 0,
4549                 /* IP1_13_11 [3] */
4550                 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
4551                 0, 0, 0, 0,
4552                 /* IP1_10_8 [3] */
4553                 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
4554                 0, 0, 0, 0,
4555                 /* IP1_7_6 [2] */
4556                 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
4557                 /* IP1_5_4 [2] */
4558                 FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0,
4559                 /* IP1_3_2 [2] */
4560                 FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0,
4561                 /* IP1_1_0 [2] */
4562                 FN_A7, FN_MSIOF1_SYNC,
4563                 0, 0, }
4564         },
4565         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4566                              2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
4567                 /* IP2_31_20 [2] */
4568                 0, 0, 0, 0,
4569                 /* IP2_29_27 [3] */
4570                 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
4571                 FN_ATAG0_N, 0, FN_EX_WAIT1,
4572                 0, 0,
4573                 /* IP2_26_25 [2] */
4574                 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
4575                 /* IP2_24_23 [2] */
4576                 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
4577                 /* IP2_22_21 [2] */
4578                 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0,
4579                 /* IP2_20_19 [2] */
4580                 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0,
4581                 /* IP2_18_16 [3] */
4582                 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
4583                 0, 0,
4584                 /* IP2_15_13 [3] */
4585                 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
4586                 0, 0, 0,
4587                 /* IP2_12_0 [3] */
4588                 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
4589                 0, 0, 0,
4590                 /* IP2_9_7 [3] */
4591                 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
4592                 0, 0, 0,
4593                 /* IP2_6_5 [2] */
4594                 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
4595                 /* IP2_4_3 [2] */
4596                 FN_A20, FN_SPCLK, 0, 0,
4597                 /* IP2_2_0 [3] */
4598                 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
4599                 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
4600         },
4601         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4602                              1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
4603                 /* IP3_31 [1] */
4604                 0, 0,
4605                 /* IP3_30_28 [3] */
4606                 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
4607                 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
4608                 0, 0, 0,
4609                 /* IP3_27_25 [3] */
4610                 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
4611                 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
4612                 0, 0, 0,
4613                 /* IP3_24_22 [3] */
4614                 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
4615                 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
4616                 /* IP3_21_20 [2] */
4617                 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
4618                 /* IP3_19_18 [2] */
4619                 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
4620                 /* IP3_17_16 [2] */
4621                 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
4622                 /* IP3_15_14 [2] */
4623                 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
4624                 /* IP3_13_12 [2] */
4625                 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
4626                 /* IP3_11_9 [3] */
4627                 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
4628                 0, 0, 0,
4629                 /* IP3_8_6 [3] */
4630                 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
4631                 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
4632                 /* IP3_5_3 [3] */
4633                 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
4634                 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
4635                 /* IP3_2_0 [3] */
4636                 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
4637                 0, 0, 0, }
4638         },
4639         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
4640                              1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
4641                 /* IP4_31 [1] */
4642                 0, 0,
4643                 /* IP4_30_28 [3] */
4644                 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
4645                 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
4646                 0, 0,
4647                 /* IP4_27_26 [2] */
4648                 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
4649                 /* IP4_25_24 [2] */
4650                 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
4651                 /* IP4_23_22 [2] */
4652                 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
4653                 /* IP4_21 [1] */
4654                 FN_SSI_SDATA3, 0,
4655                 /* IP4_20 [1] */
4656                 FN_SSI_WS34, 0,
4657                 /* IP4_19 [1] */
4658                 FN_SSI_SCK34, 0,
4659                 /* IP4_18_16 [3] */
4660                 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
4661                 0, 0, 0, 0,
4662                 /* IP4_15_13 [3] */
4663                 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
4664                 FN_GLO_Q1_D, FN_HCTS1_N_E,
4665                 0, 0,
4666                 /* IP4_12_10 [3] */
4667                 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
4668                 0, 0, 0,
4669                 /* IP4_9_8 [2] */
4670                 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
4671                 /* IP4_7_5 [3] */
4672                 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
4673                 0, 0, 0,
4674                 /* IP4_4_2 [3] */
4675                 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B,
4676                 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
4677                 0, 0, 0,
4678                 /* IP4_1_0 [2] */
4679                 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, }
4680         },
4681         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
4682                              3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
4683                 /* IP5_31_29 [3] */
4684                 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
4685                 0, 0, 0, 0, 0,
4686                 /* IP5_28_26 [3] */
4687                 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
4688                 0, 0, 0, 0,
4689                 /* IP5_25_24 [2] */
4690                 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
4691                 /* IP5_23_22 [2] */
4692                 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
4693                 /* IP5_21_20 [2] */
4694                 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
4695                 /* IP5_19_17 [3] */
4696                 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
4697                 0, 0, 0, 0,
4698                 /* IP5_16_15 [2] */
4699                 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
4700                 /* IP5_14_12 [3] */
4701                 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
4702                 0, 0, 0, 0,
4703                 /* IP5_11_9 [3] */
4704                 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
4705                 0, 0, 0, 0,
4706                 /* IP5_8_6 [3] */
4707                 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
4708                 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
4709                 0, 0,
4710                 /* IP5_5_3 [3] */
4711                 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
4712                 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
4713                 0, 0,
4714                 /* IP5_2_0 [3] */
4715                 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
4716                 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
4717                 0, 0, }
4718         },
4719         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
4720                              2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
4721                 /* IP6_31_30 [2] */
4722                 0, 0, 0, 0,
4723                 /* IP6_29_27 [3] */
4724                 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
4725                 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
4726                 0, 0, 0,
4727                 /* IP6_26_24 [3] */
4728                 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
4729                 FN_GPS_CLK_C, FN_GPS_CLK_D,
4730                 0, 0, 0,
4731                 /* IP6_23_21 [3] */
4732                 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
4733                 FN_SDA1_E, FN_MSIOF2_SYNC_E,
4734                 0, 0, 0,
4735                 /* IP6_20_19 [2] */
4736                 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
4737                 /* IP6_18_16 [3] */
4738                 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
4739                 0, 0, 0,
4740                 /* IP6_15_14 [2] */
4741                 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
4742                 /* IP6_13_12 [2] */
4743                 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
4744                 /* IP6_11_10 [2] */
4745                 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
4746                 /* IP6_9_8 [2] */
4747                 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
4748                 /* IP6_7_6 [2] */
4749                 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
4750                 /* IP6_5_3 [3] */
4751                 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
4752                 FN_SCIFA2_RXD, FN_FMIN_E,
4753                 0, 0,
4754                 /* IP6_2_0 [3] */
4755                 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
4756                 FN_SCIF_CLK, 0, FN_BPFCLK_E,
4757                 0, 0, }
4758         },
4759         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4760                              2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
4761                 /* IP7_31_30 [2] */
4762                 0, 0, 0, 0,
4763                 /* IP7_29_27 [3] */
4764                 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
4765                 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
4766                 0, 0,
4767                 /* IP7_26_24 [3] */
4768                 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
4769                 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
4770                 0, 0,
4771                 /* IP7_23_21 [3] */
4772                 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
4773                 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
4774                 0, 0,
4775                 /* IP7_20_19 [2] */
4776                 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
4777                 /* IP7_18_17 [2] */
4778                 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
4779                 /* IP7_16_15 [2] */
4780                 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
4781                 /* IP7_14_13 [2] */
4782                 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
4783                 /* IP7_12_11 [2] */
4784                 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
4785                 /* IP7_10_9 [2] */
4786                 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
4787                 /* IP7_8_6 [3] */
4788                 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
4789                 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
4790                 0, 0,
4791                 /* IP7_5_3 [3] */
4792                 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
4793                 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
4794                 0, 0,
4795                 /* IP7_2_0 [3] */
4796                 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
4797                 FN_SCIF_CLK_B, FN_GPS_MAG_D,
4798                 0, 0, }
4799         },
4800         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4801                              1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
4802                 /* IP8_31 [1] */
4803                 0, 0,
4804                 /* IP8_30_28 [3] */
4805                 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
4806                 0, 0, 0,
4807                 /* IP8_27_26 [2] */
4808                 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
4809                 /* IP8_25_24 [2] */
4810                 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
4811                 /* IP8_23_21 [3] */
4812                 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
4813                 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
4814                 0, 0,
4815                 /* IP8_20_18 [3] */
4816                 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
4817                 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
4818                 0, 0,
4819                 /* IP8_17_15 [3] */
4820                 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
4821                 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
4822                 0, 0,
4823                 /* IP8_14_12 [3] */
4824                 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
4825                 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
4826                 0, 0, 0,
4827                 /* IP8_11_9 [3] */
4828                 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
4829                 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
4830                 0, 0, 0,
4831                 /* IP8_8_6 [3] */
4832                 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
4833                 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
4834                 0, 0,
4835                 /* IP8_5_3 [3] */
4836                 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
4837                 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
4838                 0, 0,
4839                 /* IP8_2_0 [3] */
4840                 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
4841                 0, 0, 0, }
4842         },
4843         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
4844                              3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
4845                 /* IP9_31_29 [3] */
4846                 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
4847                 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
4848                 /* IP9_28_27 [2] */
4849                 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
4850                 /* IP9_26_25 [2] */
4851                 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
4852                 /* IP9_24_23 [2] */
4853                 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
4854                 /* IP9_22_21 [2] */
4855                 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
4856                 /* IP9_20_19 [2] */
4857                 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
4858                 /* IP9_18_17 [2] */
4859                 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
4860                 /* IP9_16 [1] */
4861                 FN_DU1_DISP, FN_QPOLA,
4862                 /* IP9_15_13 [3] */
4863                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
4864                 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
4865                 0, 0, 0,
4866                 /* IP9_12 [1] */
4867                 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
4868                 /* IP9_11 [1] */
4869                 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
4870                 /* IP9_10_8 [3] */
4871                 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
4872                 FN_TX3_B, FN_SCL2_B, FN_PWM4,
4873                 0, 0,
4874                 /* IP9_7 [1] */
4875                 FN_DU1_DOTCLKOUT0, FN_QCLK,
4876                 /* IP9_6 [1] */
4877                 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
4878                 /* IP9_5_3 [3] */
4879                 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C,
4880                 FN_SCIF3_SCK, FN_SCIFA3_SCK,
4881                 0, 0, 0,
4882                 /* IP9_2_0 [3] */
4883                 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
4884                 0, 0, 0, }
4885         },
4886         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
4887                              3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
4888                 /* IP10_31_29 [3] */
4889                 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
4890                 0, 0, 0,
4891                 /* IP10_28_27 [2] */
4892                 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
4893                 /* IP10_26_25 [2] */
4894                 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
4895                 /* IP10_24_22 [3] */
4896                 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
4897                 0, 0, 0,
4898                 /* IP10_21_29 [3] */
4899                 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
4900                 FN_TS_SDATA0_C, FN_ATACS11_N,
4901                 0, 0, 0,
4902                 /* IP10_18_17 [2] */
4903                 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
4904                 /* IP10_16_15 [2] */
4905                 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
4906                 /* IP10_14_12 [3] */
4907                 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
4908                 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
4909                 /* IP10_11_9 [3] */
4910                 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
4911                 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
4912                 0, 0,
4913                 /* IP10_8_6 [3] */
4914                 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
4915                 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
4916                 /* IP10_5_3 [3] */
4917                 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
4918                 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
4919                 /* IP10_2_0 [3] */
4920                 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
4921                 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
4922         },
4923         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
4924                              2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
4925                              3, 3, 3, 3, 3) {
4926                 /* IP11_31_30 [2] */
4927                 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
4928                 /* IP11_29_28 [2] */
4929                 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
4930                 /* IP11_27 [1] */
4931                 FN_VI1_DATA7, FN_AVB_MDC,
4932                 /* IP11_26 [1] */
4933                 FN_VI1_DATA6, FN_AVB_MAGIC,
4934                 /* IP11_25 [1] */
4935                 FN_VI1_DATA5, FN_AVB_RX_DV,
4936                 /* IP11_24 [1] */
4937                 FN_VI1_DATA4, FN_AVB_MDIO,
4938                 /* IP11_23 [1] */
4939                 FN_VI1_DATA3, FN_AVB_RX_ER,
4940                 /* IP11_22 [1] */
4941                 FN_VI1_DATA2, FN_AVB_RXD7,
4942                 /* IP11_21 [1] */
4943                 FN_VI1_DATA1, FN_AVB_RXD6,
4944                 /* IP11_20 [1] */
4945                 FN_VI1_DATA0, FN_AVB_RXD5,
4946                 /* IP11_19 [1] */
4947                 FN_VI1_CLK, FN_AVB_RXD4,
4948                 /* IP11_18_17 [2] */
4949                 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
4950                 /* IP11_16_15 [2] */
4951                 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
4952                 /* IP11_14_12 [3] */
4953                 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
4954                 FN_RX4_B, FN_SCIFA4_RXD_B,
4955                 0, 0, 0,
4956                 /* IP11_11_9 [3] */
4957                 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
4958                 FN_TX4_B, FN_SCIFA4_TXD_B,
4959                 0, 0, 0,
4960                 /* IP11_8_6 [3] */
4961                 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
4962                 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
4963                 /* IP11_5_3 [3] */
4964                 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
4965                 0, 0, 0,
4966                 /* IP11_2_0 [3] */
4967                 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
4968                 0, 0, 0, }
4969         },
4970         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
4971                              2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
4972                 /* IP12_31_30 [2] */
4973                 0, 0, 0, 0,
4974                 /* IP12_29_27 [3] */
4975                 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
4976                 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
4977                 0, 0, 0,
4978                 /* IP12_26_24 [3] */
4979                 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
4980                 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
4981                 0, 0, 0,
4982                 /* IP12_23_22 [2] */
4983                 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
4984                 /* IP12_21_20 [2] */
4985                 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
4986                 /* IP12_19_18 [2] */
4987                 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
4988                 /* IP12_17_16 [2] */
4989                 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
4990                 /* IP12_15_13 [3] */
4991                 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
4992                 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
4993                 0, 0, 0,
4994                 /* IP12_12_10 [3] */
4995                 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
4996                 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
4997                 0, 0, 0,
4998                 /* IP12_9_7 [3] */
4999                 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
5000                 FN_SDA2_D, FN_MSIOF1_SCK_E,
5001                 0, 0, 0,
5002                 /* IP12_6_4 [3] */
5003                 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
5004                 FN_SCL2_D, FN_MSIOF1_RXD_E,
5005                 0, 0, 0,
5006                 /* IP12_3_2 [2] */
5007                 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
5008                 /* IP12_1_0 [2] */
5009                 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
5010         },
5011         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5012                              1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
5013                              3, 2, 2, 3) {
5014                 /* IP13_31 [1] */
5015                 0, 0,
5016                 /* IP13_30_28 [3] */
5017                 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
5018                 0, 0, 0, 0,
5019                 /* IP13_27 [1] */
5020                 FN_SD1_DATA3, FN_IERX_B,
5021                 /* IP13_26 [1] */
5022                 FN_SD1_DATA2, FN_IECLK_B,
5023                 /* IP13_25 [1] */
5024                 FN_SD1_DATA1, FN_IETX_B,
5025                 /* IP13_24_23 [2] */
5026                 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
5027                 /* IP13_22 [1] */
5028                 FN_SD1_CMD, FN_REMOCON_B,
5029                 /* IP13_21_19 [3] */
5030                 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
5031                 FN_SCIFA5_RXD_B, FN_RX3_C,
5032                 0, 0,
5033                 /* IP13_18_16 [3] */
5034                 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
5035                 FN_SCIFA5_TXD_B, FN_TX3_C,
5036                 0, 0,
5037                 /* IP13_15 [1] */
5038                 FN_SD0_DATA3, FN_SSL_B,
5039                 /* IP13_14 [1] */
5040                 FN_SD0_DATA2, FN_IO3_B,
5041                 /* IP13_13 [1] */
5042                 FN_SD0_DATA1, FN_IO2_B,
5043                 /* IP13_12 [1] */
5044                 FN_SD0_DATA0, FN_MISO_IO1_B,
5045                 /* IP13_11 [1] */
5046                 FN_SD0_CMD, FN_MOSI_IO0_B,
5047                 /* IP13_10 [1] */
5048                 FN_SD0_CLK, FN_SPCLK_B,
5049                 /* IP13_9_7 [3] */
5050                 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
5051                 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
5052                 0, 0, 0,
5053                 /* IP13_6_5 [2] */
5054                 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
5055                 /* IP13_4_3 [2] */
5056                 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
5057                 /* IP13_2_0 [3] */
5058                 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
5059                 FN_ADICLK_B, FN_MSIOF0_SS1_C,
5060                 0, 0, 0, }
5061         },
5062         { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5063                              3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
5064                 /* IP14_31_29 [3] */
5065                 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
5066                 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
5067                 /* IP14_28_26 [3] */
5068                 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
5069                 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
5070                 /* IP14_25_23 [3] */
5071                 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
5072                 0, 0, 0,
5073                 /* IP14_22_20 [3] */
5074                 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
5075                 0, 0, 0,
5076                 /* IP14_19_17 [3] */
5077                 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
5078                 FN_VI1_CLKENB_C, FN_VI1_G1_B,
5079                 0, 0,
5080                 /* IP14_16_14 [3] */
5081                 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
5082                 FN_VI1_CLK_C, FN_VI1_G0_B,
5083                 0, 0,
5084                 /* IP14_13_11 [3] */
5085                 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
5086                 0, 0, 0,
5087                 /* IP14_10_8 [3] */
5088                 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
5089                 0, 0, 0,
5090                 /* IP14_7 [1] */
5091                 FN_SD2_DATA3, FN_MMC_D3,
5092                 /* IP14_6 [1] */
5093                 FN_SD2_DATA2, FN_MMC_D2,
5094                 /* IP14_5 [1] */
5095                 FN_SD2_DATA1, FN_MMC_D1,
5096                 /* IP14_4 [1] */
5097                 FN_SD2_DATA0, FN_MMC_D0,
5098                 /* IP14_3 [1] */
5099                 FN_SD2_CMD, FN_MMC_CMD,
5100                 /* IP14_2 [1] */
5101                 FN_SD2_CLK, FN_MMC_CLK,
5102                 /* IP14_1_0 [2] */
5103                 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
5104         },
5105         { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5106                              2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
5107                 /* IP15_31_30 [2] */
5108                 0, 0, 0, 0,
5109                 /* IP15_29_27 [3] */
5110                 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
5111                 FN_CAN0_TX_B, FN_VI1_DATA5_C,
5112                 0, 0,
5113                 /* IP15_26_24 [3] */
5114                 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
5115                 FN_CAN0_RX_B, FN_VI1_DATA4_C,
5116                 0, 0,
5117                 /* IP15_23_21 [3] */
5118                 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
5119                 FN_TCLK2, FN_VI1_DATA3_C, 0,
5120                 /* IP15_20_18 [3] */
5121                 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
5122                 0, 0, 0,
5123                 /* IP15_17_15 [3] */
5124                 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
5125                 FN_TCLK1, FN_VI1_DATA1_C,
5126                 0, 0,
5127                 /* IP15_14_12 [3] */
5128                 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
5129                 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
5130                 0, 0,
5131                 /* IP15_11_9 [3] */
5132                 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
5133                 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
5134                 0, 0,
5135                 /* IP15_8_6 [3] */
5136                 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
5137                 FN_PWM5_B, FN_SCIFA3_TXD_C,
5138                 0, 0, 0,
5139                 /* IP15_5_4 [2] */
5140                 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
5141                 /* IP15_3_2 [2] */
5142                 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
5143                 /* IP15_1_0 [2] */
5144                 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
5145         },
5146         { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5147                              4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
5148                 /* IP16_31_28 [4] */
5149                 0, 0, 0, 0, 0, 0, 0, 0,
5150                 0, 0, 0, 0, 0, 0, 0, 0,
5151                 /* IP16_27_24 [4] */
5152                 0, 0, 0, 0, 0, 0, 0, 0,
5153                 0, 0, 0, 0, 0, 0, 0, 0,
5154                 /* IP16_23_20 [4] */
5155                 0, 0, 0, 0, 0, 0, 0, 0,
5156                 0, 0, 0, 0, 0, 0, 0, 0,
5157                 /* IP16_19_16 [4] */
5158                 0, 0, 0, 0, 0, 0, 0, 0,
5159                 0, 0, 0, 0, 0, 0, 0, 0,
5160                 /* IP16_15_12 [4] */
5161                 0, 0, 0, 0, 0, 0, 0, 0,
5162                 0, 0, 0, 0, 0, 0, 0, 0,
5163                 /* IP16_11_10 [2] */
5164                 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
5165                 /* IP16_9_8 [2] */
5166                 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
5167                 /* IP16_7_6 [2] */
5168                 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
5169                 /* IP16_5_3 [3] */
5170                 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
5171                 FN_GLO_SS_C, FN_VI1_DATA7_C,
5172                 0, 0, 0,
5173                 /* IP16_2_0 [3] */
5174                 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
5175                 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
5176                 0, 0, 0, }
5177         },
5178         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5179                              1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
5180                              3, 2, 2, 2, 1, 2, 2, 2) {
5181                 /* RESEVED [1] */
5182                 0, 0,
5183                 /* SEL_SCIF1 [2] */
5184                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5185                 /* SEL_SCIFB [2] */
5186                 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
5187                 /* SEL_SCIFB2 [2] */
5188                 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
5189                 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
5190                 /* SEL_SCIFB1 [3] */
5191                 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
5192                 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
5193                 0, 0, 0, 0,
5194                 /* SEL_SCIFA1 [2] */
5195                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
5196                 /* SEL_SSI9 [1] */
5197                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
5198                 /* SEL_SCFA [1] */
5199                 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5200                 /* SEL_QSP [1] */
5201                 FN_SEL_QSP_0, FN_SEL_QSP_1,
5202                 /* SEL_SSI7 [1] */
5203                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
5204                 /* SEL_HSCIF1 [3] */
5205                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
5206                 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
5207                 0, 0, 0,
5208                 /* RESEVED [2] */
5209                 0, 0, 0, 0,
5210                 /* SEL_VI1 [2] */
5211                 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
5212                 /* RESEVED [2] */
5213                 0, 0, 0, 0,
5214                 /* SEL_TMU [1] */
5215                 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5216                 /* SEL_LBS [2] */
5217                 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
5218                 /* SEL_TSIF0 [2] */
5219                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5220                 /* SEL_SOF0 [2] */
5221                 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
5222         },
5223         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5224                              3, 1, 1, 3, 2, 1, 1, 2, 2,
5225                              1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
5226                 /* SEL_SCIF0 [3] */
5227                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
5228                 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
5229                 0, 0, 0,
5230                 /* RESEVED [1] */
5231                 0, 0,
5232                 /* SEL_SCIF [1] */
5233                 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
5234                 /* SEL_CAN0 [3] */
5235                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5236                 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
5237                 0, 0,
5238                 /* SEL_CAN1 [2] */
5239                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
5240                 /* RESEVED [1] */
5241                 0, 0,
5242                 /* SEL_SCIFA2 [1] */
5243                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
5244                 /* SEL_SCIF4 [2] */
5245                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
5246                 /* RESEVED [2] */
5247                 0, 0, 0, 0,
5248                 /* SEL_ADG [1] */
5249                 FN_SEL_ADG_0, FN_SEL_ADG_1,
5250                 /* SEL_FM [3] */
5251                 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
5252                 FN_SEL_FM_3, FN_SEL_FM_4,
5253                 0, 0, 0,
5254                 /* SEL_SCIFA5 [2] */
5255                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
5256                 /* RESEVED [1] */
5257                 0, 0,
5258                 /* SEL_GPS [2] */
5259                 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
5260                 /* SEL_SCIFA4 [2] */
5261                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
5262                 /* SEL_SCIFA3 [2] */
5263                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
5264                 /* SEL_SIM [1] */
5265                 FN_SEL_SIM_0, FN_SEL_SIM_1,
5266                 /* RESEVED [1] */
5267                 0, 0,
5268                 /* SEL_SSI8 [1] */
5269                 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
5270         },
5271         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5272                              2, 2, 2, 2, 2, 2, 2, 2,
5273                              1, 1, 2, 2, 3, 2, 2, 2, 1) {
5274                 /* SEL_HSCIF2 [2] */
5275                 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
5276                 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
5277                 /* SEL_CANCLK [2] */
5278                 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5279                 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
5280                 /* SEL_IIC8 [2] */
5281                 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
5282                 /* SEL_IIC7 [2] */
5283                 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
5284                 /* SEL_IIC4 [2] */
5285                 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
5286                 /* SEL_IIC3 [2] */
5287                 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
5288                 /* SEL_SCIF3 [2] */
5289                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
5290                 /* SEL_IEB [2] */
5291                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5292                 /* SEL_MMC [1] */
5293                 FN_SEL_MMC_0, FN_SEL_MMC_1,
5294                 /* SEL_SCIF5 [1] */
5295                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
5296                 /* RESEVED [2] */
5297                 0, 0, 0, 0,
5298                 /* SEL_IIC2 [2] */
5299                 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5300                 /* SEL_IIC1 [3] */
5301                 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
5302                 FN_SEL_IIC1_4,
5303                 0, 0, 0,
5304                 /* SEL_IIC0 [2] */
5305                 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
5306                 /* RESEVED [2] */
5307                 0, 0, 0, 0,
5308                 /* RESEVED [2] */
5309                 0, 0, 0, 0,
5310                 /* RESEVED [1] */
5311                 0, 0, }
5312         },
5313         { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
5314                              3, 2, 2, 1, 1, 1, 1, 3, 2,
5315                              2, 3, 1, 1, 1, 2, 2, 2, 2) {
5316                 /* SEL_SOF1 [3] */
5317                 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
5318                 FN_SEL_SOF1_4,
5319                 0, 0, 0,
5320                 /* SEL_HSCIF0 [2] */
5321                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
5322                 /* SEL_DIS [2] */
5323                 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
5324                 /* RESEVED [1] */
5325                 0, 0,
5326                 /* SEL_RAD [1] */
5327                 FN_SEL_RAD_0, FN_SEL_RAD_1,
5328                 /* SEL_RCN [1] */
5329                 FN_SEL_RCN_0, FN_SEL_RCN_1,
5330                 /* SEL_RSP [1] */
5331                 FN_SEL_RSP_0, FN_SEL_RSP_1,
5332                 /* SEL_SCIF2 [3] */
5333                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
5334                 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
5335                 0, 0, 0,
5336                 /* RESEVED [2] */
5337                 0, 0, 0, 0,
5338                 /* RESEVED [2] */
5339                 0, 0, 0, 0,
5340                 /* SEL_SOF2 [3] */
5341                 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
5342                 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
5343                 0, 0, 0,
5344                 /* RESEVED [1] */
5345                 0, 0,
5346                 /* SEL_SSI1 [1] */
5347                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
5348                 /* SEL_SSI0 [1] */
5349                 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
5350                 /* SEL_SSP [2] */
5351                 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
5352                 /* RESEVED [2] */
5353                 0, 0, 0, 0,
5354                 /* RESEVED [2] */
5355                 0, 0, 0, 0,
5356                 /* RESEVED [2] */
5357                 0, 0, 0, 0, }
5358         },
5359         { },
5360 };
5361
5362 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
5363         .name = "r8a77910_pfc",
5364         .unlock_reg = 0xe6060000, /* PMMR */
5365
5366         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5367
5368         .pins = pinmux_pins,
5369         .nr_pins = ARRAY_SIZE(pinmux_pins),
5370         .groups = pinmux_groups,
5371         .nr_groups = ARRAY_SIZE(pinmux_groups),
5372         .functions = pinmux_functions,
5373         .nr_functions = ARRAY_SIZE(pinmux_functions),
5374
5375         .cfg_regs = pinmux_config_regs,
5376
5377         .gpio_data = pinmux_data,
5378         .gpio_data_size = ARRAY_SIZE(pinmux_data),
5379 };