drivers/pinctrl/sh-pfc/pfc-r8a7791.c

   1 /*
   2  * r8a7791 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2
   8  * as published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/platform_data/gpio-rcar.h>
  13
  14 #include "core.h"
  15 #include "sh_pfc.h"
  16
  17 #define CPU_ALL_PORT(fn, sfx)                                           \
  18         PORT_GP_32(0, fn, sfx),                                         \
  19         PORT_GP_32(1, fn, sfx),                                         \
  20         PORT_GP_32(2, fn, sfx),                                         \
  21         PORT_GP_32(3, fn, sfx),                                         \
  22         PORT_GP_32(4, fn, sfx),                                         \
  23         PORT_GP_32(5, fn, sfx),                                         \
  24         PORT_GP_32(6, fn, sfx),                                         \
  25         PORT_GP_32(7, fn, sfx)
  26
  27 enum {
  28         PINMUX_RESERVED = 0,
  29
  30         PINMUX_DATA_BEGIN,
  31         GP_ALL(DATA),
  32         PINMUX_DATA_END,
  33
  34         PINMUX_FUNCTION_BEGIN,
  35         GP_ALL(FN),
  36
  37         /* GPSR0 */
  38         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  39         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  40         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
  41         FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
  42         FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
  43         FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
  44
  45         /* GPSR1 */
  46         FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
  47         FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
  48         FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
  49         FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
  50         FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
  51         FN_IP3_21_20,
  52
  53         /* GPSR2 */
  54         FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
  55         FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
  56         FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
  57         FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
  58         FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
  59         FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
  60         FN_IP6_5_3, FN_IP6_7_6,
  61
  62         /* GPSR3 */
  63         FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
  64         FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
  65         FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
  66         FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
  67         FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
  68         FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
  69         FN_IP9_18_17,
  70
  71         /* GPSR4 */
  72         FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
  73         FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
  74         FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
  75         FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
  76         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
  77         FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
  78         FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
  79         FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
  80
  81         /* GPSR5 */
  82         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
  83         FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
  84         FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
  85         FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
  86         FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
  87         FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
  88         FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
  89
  90         /* GPSR6 */
  91         FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
  92         FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
  93         FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
  94         FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
  95         FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
  96         FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
  97         FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
  98         FN_USB1_OVC, FN_DU0_DOTCLKIN,
  99
 100         /* GPSR7 */
 101         FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
 102         FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
 103         FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
 104         FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
 105         FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
 106         FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
 107
 108         /* IPSR0 */
 109         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
 110         FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
 111         FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
 112         FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
 113         FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
 114         FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
 115
 116         /* IPSR1 */
 117         FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0,
 118         FN_A9, FN_MSIOF1_SS2, FN_SDA0,
 119         FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
 120         FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
 121         FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
 122         FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
 123         FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
 124         FN_A15, FN_BPFCLK_C,
 125         FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
 126         FN_A17, FN_DACK2_B, FN_SDA0_C,
 127         FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
 128
 129         /* IPSR2 */
 130         FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
 131         FN_A20, FN_SPCLK,
 132         FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
 133         FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
 134         FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
 135         FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
 136         FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
 137         FN_CS0_N, FN_ATAG0_N_B, FN_SCL1,
 138         FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1,
 139         FN_EX_CS1_N, FN_MSIOF2_SCK,
 140         FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
 141         FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
 142
 143         /* IPSR3 */
 144         FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
 145         FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
 146         FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
 147         FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
 148         FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
 149         FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
 150         FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
 151         FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
 152         FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
 153         FN_DREQ0, FN_PWM3, FN_TPU_TO3,
 154         FN_DACK0, FN_DRACK0, FN_REMOCON,
 155         FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
 156         FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
 157         FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
 158         FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
 159
 160         /* IPSR4 */
 161         FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C,
 162         FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
 163         FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
 164         FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
 165         FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
 166         FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
 167         FN_GLO_Q1_D, FN_HCTS1_N_E,
 168         FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
 169         FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
 170         FN_SSI_SCK4, FN_GLO_SS_D,
 171         FN_SSI_WS4, FN_GLO_RFON_D,
 172         FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
 173         FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
 174         FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
 175
 176         /* IPSR5 */
 177         FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
 178         FN_MSIOF2_TXD_D, FN_VI1_R3_B,
 179         FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
 180         FN_MSIOF2_SS1_D, FN_VI1_R4_B,
 181         FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
 182         FN_MSIOF2_RXD_D, FN_VI1_R5_B,
 183         FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
 184         FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
 185         FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
 186         FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
 187         FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
 188         FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
 189         FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
 190         FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
 191         FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
 192
 193         /* IPSR6 */
 194         FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
 195         FN_SCIF_CLK, FN_BPFCLK_E,
 196         FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
 197         FN_SCIFA2_RXD, FN_FMIN_E,
 198         FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
 199         FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
 200         FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
 201         FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
 202         FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
 203         FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
 204         FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
 205         FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
 206         FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
 207         FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
 208
 209         /* IPSR7 */
 210         FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
 211         FN_SCIF_CLK_B, FN_GPS_MAG_D,
 212         FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
 213         FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
 214         FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
 215         FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
 216         FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
 217         FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
 218         FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
 219         FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
 220         FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
 221         FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
 222         FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
 223         FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
 224         FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
 225         FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
 226         FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
 227         FN_SCIFA1_SCK, FN_SSI_SCK78_B,
 228
 229         /* IPSR8 */
 230         FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
 231         FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
 232         FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
 233         FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
 234         FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
 235         FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
 236         FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
 237         FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
 238         FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
 239         FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
 240         FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
 241         FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
 242         FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
 243         FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
 244         FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
 245         FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
 246         FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
 247
 248         /* IPSR9 */
 249         FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
 250         FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
 251         FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
 252         FN_DU1_DOTCLKOUT0, FN_QCLK,
 253         FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
 254         FN_TX3_B, FN_SCL2_B, FN_PWM4,
 255         FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
 256         FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
 257         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
 258         FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
 259         FN_DU1_DISP, FN_QPOLA,
 260         FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
 261         FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
 262         FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
 263         FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
 264         FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
 265         FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
 266         FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
 267         FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
 268
 269         /* IPSR10 */
 270         FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
 271         FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
 272         FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
 273         FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
 274         FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
 275         FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
 276         FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
 277         FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
 278         FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
 279         FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
 280         FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
 281         FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
 282         FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
 283         FN_TS_SDATA0_C, FN_ATACS11_N,
 284         FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
 285         FN_TS_SCK0_C, FN_ATAG1_N,
 286         FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
 287         FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
 288         FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
 289
 290         /* IPSR11 */
 291         FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
 292         FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
 293         FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
 294         FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
 295         FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
 296         FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
 297         FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
 298         FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
 299         FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
 300         FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
 301         FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
 302         FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
 303         FN_VI1_DATA7, FN_AVB_MDC,
 304         FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
 305         FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
 306
 307         /* IPSR12 */
 308         FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
 309         FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
 310         FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
 311         FN_SCL2_D, FN_MSIOF1_RXD_E,
 312         FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
 313         FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
 314         FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
 315         FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
 316         FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
 317         FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
 318         FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
 319         FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
 320         FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
 321         FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
 322         FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
 323         FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
 324         FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
 325
 326         /* IPSR13 */
 327         FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
 328         FN_ADICLK_B, FN_MSIOF0_SS1_C,
 329         FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
 330         FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
 331         FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
 332         FN_ADICHS2_B, FN_MSIOF0_TXD_C,
 333         FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
 334         FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
 335         FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
 336         FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
 337         FN_SCIFA5_TXD_B, FN_TX3_C,
 338         FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
 339         FN_SCIFA5_RXD_B, FN_RX3_C,
 340         FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
 341         FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
 342         FN_SD1_DATA3, FN_IERX_B,
 343         FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
 344
 345         /* IPSR14 */
 346         FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
 347         FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
 348         FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
 349         FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
 350         FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
 351         FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
 352         FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
 353         FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
 354         FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
 355         FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
 356         FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
 357         FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
 358         FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
 359         FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
 360
 361         /* IPSR15 */
 362         FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
 363         FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
 364         FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
 365         FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
 366         FN_PWM5_B, FN_SCIFA3_TXD_C,
 367         FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
 368         FN_VI1_G6_B, FN_SCIFA3_RXD_C,
 369         FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
 370         FN_VI1_G7_B, FN_SCIFA3_SCK_C,
 371         FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
 372         FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
 373         FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
 374         FN_TCLK2, FN_VI1_DATA3_C,
 375         FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
 376         FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
 377
 378         /* IPSR16 */
 379         FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
 380         FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
 381         FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
 382         FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
 383         FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
 384
 385         /* MOD_SEL */
 386         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 387         FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
 388         FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
 389         FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 390         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
 391         FN_SEL_SSI9_0, FN_SEL_SSI9_1,
 392         FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 393         FN_SEL_QSP_0, FN_SEL_QSP_1,
 394         FN_SEL_SSI7_0, FN_SEL_SSI7_1,
 395         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
 396         FN_SEL_HSCIF1_4,
 397         FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
 398         FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 399         FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
 400         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 401         FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
 402
 403         /* MOD_SEL2 */
 404         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 405         FN_SEL_SCIF0_4,
 406         FN_SEL_SCIF_0, FN_SEL_SCIF_1,
 407         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 408         FN_SEL_CAN0_4, FN_SEL_CAN0_5,
 409         FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
 410         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
 411         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
 412         FN_SEL_ADG_0, FN_SEL_ADG_1,
 413         FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
 414         FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
 415         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 416         FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
 417         FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
 418         FN_SEL_SIM_0, FN_SEL_SIM_1,
 419         FN_SEL_SSI8_0, FN_SEL_SSI8_1,
 420
 421         /* MOD_SEL3 */
 422         FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
 423         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
 424         FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
 425         FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
 426         FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
 427         FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
 428         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
 429         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 430         FN_SEL_MMC_0, FN_SEL_MMC_1,
 431         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
 432         FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
 433         FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
 434         FN_SEL_IIC1_4,
 435         FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
 436
 437         /* MOD_SEL4 */
 438         FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
 439         FN_SEL_SOF1_4,
 440         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
 441         FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
 442         FN_SEL_RAD_0, FN_SEL_RAD_1,
 443         FN_SEL_RCN_0, FN_SEL_RCN_1,
 444         FN_SEL_RSP_0, FN_SEL_RSP_1,
 445         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
 446         FN_SEL_SCIF2_4,
 447         FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
 448         FN_SEL_SOF2_4,
 449         FN_SEL_SSI1_0, FN_SEL_SSI1_1,
 450         FN_SEL_SSI0_0, FN_SEL_SSI0_1,
 451         FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
 452         PINMUX_FUNCTION_END,
 453
 454         PINMUX_MARK_BEGIN,
 455
 456         EX_CS0_N_MARK, RD_N_MARK,
 457
 458         AUDIO_CLKA_MARK,
 459
 460         VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
 461         VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
 462         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
 463
 464         SD1_CLK_MARK,
 465
 466         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 467         DU0_DOTCLKIN_MARK,
 468
 469         /* IPSR0 */
 470         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
 471         D6_MARK, D7_MARK, D8_MARK,
 472         D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
 473         A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK,
 474         A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
 475         A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
 476         A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
 477
 478         /* IPSR1 */
 479         A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK,
 480         A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK,
 481         A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
 482         A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK,
 483         A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK,
 484         A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
 485         A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
 486         A15_MARK, BPFCLK_C_MARK,
 487         A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
 488         A17_MARK, DACK2_B_MARK, SDA0_C_MARK,
 489         A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
 490
 491         /* IPSR2 */
 492         A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
 493         SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
 494         A20_MARK, SPCLK_MARK,
 495         A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
 496         A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
 497         A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
 498         A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
 499         A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
 500         RX1_MARK, SCIFA1_RXD_MARK,
 501         CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK,
 502         CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK,
 503         EX_CS1_N_MARK, MSIOF2_SCK_MARK,
 504         EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
 505         EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
 506         ATAG0_N_MARK, EX_WAIT1_MARK,
 507
 508         /* IPSR3 */
 509         EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
 510         EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
 511         SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
 512         BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
 513         SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
 514         RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
 515         SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
 516         WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
 517         WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
 518         EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
 519         DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
 520         DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
 521         SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
 522         SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
 523         SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
 524         SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
 525         SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
 526         SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
 527
 528         /* IPSR4 */
 529         SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK,
 530         SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK,
 531         MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
 532         SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK,
 533         MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
 534         SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK,
 535         SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK,
 536         SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
 537         GLO_Q1_D_MARK, HCTS1_N_E_MARK,
 538         SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
 539         SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
 540         SSI_SCK4_MARK, GLO_SS_D_MARK,
 541         SSI_WS4_MARK, GLO_RFON_D_MARK,
 542         SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
 543         SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
 544         MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
 545
 546         /* IPSR5 */
 547         SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
 548         MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
 549         SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
 550         MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
 551         SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
 552         MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
 553         SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
 554         SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
 555         SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
 556         SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
 557         SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
 558         SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
 559         SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
 560         SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
 561         SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
 562
 563         /* IPSR6 */
 564         AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
 565         SCIF_CLK_MARK, BPFCLK_E_MARK,
 566         AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
 567         SCIFA2_RXD_MARK, FMIN_E_MARK,
 568         AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
 569         IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
 570         IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
 571         IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
 572         IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
 573         IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
 574         MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
 575         IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
 576         IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
 577         SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
 578         IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
 579         GPS_CLK_C_MARK, GPS_CLK_D_MARK,
 580         IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
 581         GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
 582
 583         /* IPSR7 */
 584         IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
 585         SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
 586         DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
 587         SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
 588         DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
 589         SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
 590         DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
 591         DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
 592         DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
 593         DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
 594         DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
 595         DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
 596         DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
 597         SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
 598         DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
 599         SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
 600         DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
 601         SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
 602
 603         /* IPSR8 */
 604         DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
 605         DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
 606         SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
 607         DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
 608         SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
 609         DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
 610         SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
 611         DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
 612         SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
 613         DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
 614         SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
 615         DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
 616         SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
 617         DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
 618         SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
 619         DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
 620         DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
 621         DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
 622
 623         /* IPSR9 */
 624         DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
 625         DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK,
 626         SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
 627         DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 628         DU1_DOTCLKOUT0_MARK, QCLK_MARK,
 629         DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
 630         TX3_B_MARK, SCL2_B_MARK, PWM4_MARK,
 631         DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
 632         DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
 633         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 634         CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK,
 635         DU1_DISP_MARK, QPOLA_MARK,
 636         DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
 637         VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
 638         VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
 639         VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
 640         VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
 641         VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
 642         VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK,
 643         HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
 644
 645         /* IPSR10 */
 646         VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK,
 647         HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
 648         VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK,
 649         HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
 650         VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK,
 651         HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
 652         VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
 653         HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
 654         VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
 655         CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
 656         VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
 657         VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
 658         VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
 659         TS_SDATA0_C_MARK, ATACS11_N_MARK,
 660         VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
 661         TS_SCK0_C_MARK, ATAG1_N_MARK,
 662         VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
 663         VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
 664         VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK,
 665
 666         /* IPSR11 */
 667         VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
 668         VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
 669         VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
 670         SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
 671         VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
 672         TX4_B_MARK, SCIFA4_TXD_B_MARK,
 673         VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
 674         RX4_B_MARK, SCIFA4_RXD_B_MARK,
 675         VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
 676         VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
 677         VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
 678         VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
 679         VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
 680         VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
 681         VI1_DATA7_MARK, AVB_MDC_MARK,
 682         ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
 683         ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
 684
 685         /* IPSR12 */
 686         ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
 687         ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
 688         ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
 689         SCL2_D_MARK, MSIOF1_RXD_E_MARK,
 690         ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
 691         SDA2_D_MARK, MSIOF1_SCK_E_MARK,
 692         ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
 693         CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
 694         ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
 695         CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
 696         ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
 697         ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
 698         ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
 699         ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
 700         STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
 701         ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
 702         STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
 703         ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
 704
 705         /* IPSR13 */
 706         STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
 707         ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
 708         STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
 709         STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
 710         STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
 711         ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
 712         SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
 713         SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
 714         SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
 715         SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
 716         SCIFA5_TXD_B_MARK, TX3_C_MARK,
 717         SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
 718         SCIFA5_RXD_B_MARK, RX3_C_MARK,
 719         SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
 720         SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
 721         SD1_DATA3_MARK, IERX_B_MARK,
 722         SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
 723
 724         /* IPSR14 */
 725         SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
 726         SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
 727         SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
 728         SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
 729         SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
 730         SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
 731         MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
 732         VI1_CLK_C_MARK, VI1_G0_B_MARK,
 733         MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
 734         VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
 735         MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
 736         MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
 737         MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
 738         VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
 739         MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
 740         VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
 741
 742         /* IPSR15 */
 743         SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
 744         SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
 745         SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
 746         GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
 747         PWM5_B_MARK, SCIFA3_TXD_C_MARK,
 748         GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
 749         VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
 750         GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
 751         VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
 752         HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
 753         TCLK1_MARK, VI1_DATA1_C_MARK,
 754         HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
 755         HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
 756         TCLK2_MARK, VI1_DATA3_C_MARK,
 757         HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
 758         CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
 759         HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
 760         CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
 761
 762         /* IPSR16 */
 763         HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
 764         GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
 765         HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
 766         GLO_SS_C_MARK, VI1_DATA7_C_MARK,
 767         HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK,
 768         HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
 769         HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
 770         PINMUX_MARK_END,
 771 };
 772
 773 static const u16 pinmux_data[] = {
 774         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 775
 776         PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N),
 777         PINMUX_DATA(RD_N_MARK, FN_RD_N),
 778         PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
 779         PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
 780         PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0),
 781         PINMUX_DATA(VI0_DATA1_VI0_B1_MARK, FN_VI0_DATA1_VI0_B1),
 782         PINMUX_DATA(VI0_DATA2_VI0_B2_MARK, FN_VI0_DATA2_VI0_B2),
 783         PINMUX_DATA(VI0_DATA4_VI0_B4_MARK, FN_VI0_DATA4_VI0_B4),
 784         PINMUX_DATA(VI0_DATA5_VI0_B5_MARK, FN_VI0_DATA5_VI0_B5),
 785         PINMUX_DATA(VI0_DATA6_VI0_B6_MARK, FN_VI0_DATA6_VI0_B6),
 786         PINMUX_DATA(VI0_DATA7_VI0_B7_MARK, FN_VI0_DATA7_VI0_B7),
 787         PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
 788         PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
 789         PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
 790         PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
 791         PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN),
 792         PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK),
 793
 794         /* IPSR0 */
 795         PINMUX_IPSR_DATA(IP0_0, D0),
 796         PINMUX_IPSR_DATA(IP0_1, D1),
 797         PINMUX_IPSR_DATA(IP0_2, D2),
 798         PINMUX_IPSR_DATA(IP0_3, D3),
 799         PINMUX_IPSR_DATA(IP0_4, D4),
 800         PINMUX_IPSR_DATA(IP0_5, D5),
 801         PINMUX_IPSR_DATA(IP0_6, D6),
 802         PINMUX_IPSR_DATA(IP0_7, D7),
 803         PINMUX_IPSR_DATA(IP0_8, D8),
 804         PINMUX_IPSR_DATA(IP0_9, D9),
 805         PINMUX_IPSR_DATA(IP0_10, D10),
 806         PINMUX_IPSR_DATA(IP0_11, D11),
 807         PINMUX_IPSR_DATA(IP0_12, D12),
 808         PINMUX_IPSR_DATA(IP0_13, D13),
 809         PINMUX_IPSR_DATA(IP0_14, D14),
 810         PINMUX_IPSR_DATA(IP0_15, D15),
 811         PINMUX_IPSR_DATA(IP0_18_16, A0),
 812         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
 813         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
 814         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SCL0_C, SEL_IIC0_2),
 815         PINMUX_IPSR_DATA(IP0_18_16, PWM2_B),
 816         PINMUX_IPSR_DATA(IP0_20_19, A1),
 817         PINMUX_IPSR_MODSEL_DATA(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
 818         PINMUX_IPSR_DATA(IP0_22_21, A2),
 819         PINMUX_IPSR_MODSEL_DATA(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
 820         PINMUX_IPSR_DATA(IP0_24_23, A3),
 821         PINMUX_IPSR_MODSEL_DATA(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
 822         PINMUX_IPSR_DATA(IP0_26_25, A4),
 823         PINMUX_IPSR_MODSEL_DATA(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
 824         PINMUX_IPSR_DATA(IP0_28_27, A5),
 825         PINMUX_IPSR_MODSEL_DATA(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
 826         PINMUX_IPSR_DATA(IP0_30_29, A6),
 827         PINMUX_IPSR_MODSEL_DATA(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
 828
 829         /* IPSR1 */
 830         PINMUX_IPSR_DATA(IP1_1_0, A7),
 831         PINMUX_IPSR_MODSEL_DATA(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
 832         PINMUX_IPSR_DATA(IP1_3_2, A8),
 833         PINMUX_IPSR_MODSEL_DATA(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
 834         PINMUX_IPSR_MODSEL_DATA(IP1_3_2, SCL0, SEL_IIC0_0),
 835         PINMUX_IPSR_DATA(IP1_5_4, A9),
 836         PINMUX_IPSR_MODSEL_DATA(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
 837         PINMUX_IPSR_MODSEL_DATA(IP1_5_4, SDA0, SEL_IIC0_0),
 838         PINMUX_IPSR_DATA(IP1_7_6, A10),
 839         PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
 840         PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
 841         PINMUX_IPSR_DATA(IP1_10_8, A11),
 842         PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
 843         PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCL3_D, SEL_IIC3_3),
 844         PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
 845         PINMUX_IPSR_DATA(IP1_13_11, A12),
 846         PINMUX_IPSR_MODSEL_DATA(IP1_13_11, FMCLK, SEL_FM_0),
 847         PINMUX_IPSR_MODSEL_DATA(IP1_13_11, SDA3_D, SEL_IIC3_3),
 848         PINMUX_IPSR_MODSEL_DATA(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
 849         PINMUX_IPSR_DATA(IP1_16_14, A13),
 850         PINMUX_IPSR_MODSEL_DATA(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
 851         PINMUX_IPSR_MODSEL_DATA(IP1_16_14, BPFCLK, SEL_FM_0),
 852         PINMUX_IPSR_MODSEL_DATA(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
 853         PINMUX_IPSR_DATA(IP1_19_17, A14),
 854         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
 855         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN, SEL_FM_0),
 856         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN_C, SEL_FM_2),
 857         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
 858         PINMUX_IPSR_DATA(IP1_22_20, A15),
 859         PINMUX_IPSR_MODSEL_DATA(IP1_22_20, BPFCLK_C, SEL_FM_2),
 860         PINMUX_IPSR_DATA(IP1_25_23, A16),
 861         PINMUX_IPSR_MODSEL_DATA(IP1_25_23, DREQ2_B, SEL_LBS_1),
 862         PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FMCLK_C, SEL_FM_2),
 863         PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
 864         PINMUX_IPSR_DATA(IP1_28_26, A17),
 865         PINMUX_IPSR_MODSEL_DATA(IP1_28_26, DACK2_B, SEL_LBS_1),
 866         PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SDA0_C, SEL_IIC0_2),
 867         PINMUX_IPSR_DATA(IP1_31_29, A18),
 868         PINMUX_IPSR_MODSEL_DATA(IP1_31_29, DREQ1, SEL_LBS_0),
 869         PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
 870         PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
 871
 872         /* IPSR2 */
 873         PINMUX_IPSR_DATA(IP2_2_0, A19),
 874         PINMUX_IPSR_DATA(IP2_2_0, DACK1),
 875         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
 876         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
 877         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_0),
 878         PINMUX_IPSR_DATA(IP2_2_0, A20),
 879         PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SPCLK, SEL_QSP_0),
 880         PINMUX_IPSR_DATA(IP2_6_5, A21),
 881         PINMUX_IPSR_MODSEL_DATA(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
 882         PINMUX_IPSR_MODSEL_DATA(IP2_6_5, MOSI_IO0, SEL_QSP_0),
 883         PINMUX_IPSR_DATA(IP2_9_7, A22),
 884         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, MISO_IO1, SEL_QSP_0),
 885         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, FMCLK_B, SEL_FM_1),
 886         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, TX0, SEL_SCIF0_0),
 887         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
 888         PINMUX_IPSR_DATA(IP2_12_10, A23),
 889         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, IO2, SEL_QSP_0),
 890         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, BPFCLK_B, SEL_FM_1),
 891         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, RX0, SEL_SCIF0_0),
 892         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
 893         PINMUX_IPSR_DATA(IP2_15_13, A24),
 894         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, DREQ2, SEL_LBS_0),
 895         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, IO3, SEL_QSP_0),
 896         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, TX1, SEL_SCIF1_0),
 897         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
 898         PINMUX_IPSR_DATA(IP2_18_16, A25),
 899         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DACK2, SEL_LBS_0),
 900         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SSL, SEL_QSP_0),
 901         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ1_C, SEL_LBS_2),
 902         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, RX1, SEL_SCIF1_0),
 903         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
 904         PINMUX_IPSR_DATA(IP2_20_19, CS0_N),
 905         PINMUX_IPSR_MODSEL_DATA(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
 906         PINMUX_IPSR_MODSEL_DATA(IP2_20_19, SCL1, SEL_IIC1_0),
 907         PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26),
 908         PINMUX_IPSR_MODSEL_DATA(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
 909         PINMUX_IPSR_MODSEL_DATA(IP2_22_21, SDA1, SEL_IIC1_0),
 910         PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N),
 911         PINMUX_IPSR_MODSEL_DATA(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
 912         PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N),
 913         PINMUX_IPSR_MODSEL_DATA(IP2_26_25, ATAWR0_N, SEL_LBS_0),
 914         PINMUX_IPSR_MODSEL_DATA(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
 915         PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N),
 916         PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATADIR0_N, SEL_LBS_0),
 917         PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
 918         PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATAG0_N, SEL_LBS_0),
 919         PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1),
 920
 921         /* IPSR3 */
 922         PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N),
 923         PINMUX_IPSR_MODSEL_DATA(IP3_2_0, ATARD0_N, SEL_LBS_0),
 924         PINMUX_IPSR_MODSEL_DATA(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
 925         PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2),
 926         PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N),
 927         PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N),
 928         PINMUX_IPSR_MODSEL_DATA(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
 929         PINMUX_IPSR_MODSEL_DATA(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
 930         PINMUX_IPSR_MODSEL_DATA(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
 931         PINMUX_IPSR_DATA(IP3_5_3, PWM1),
 932         PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1),
 933         PINMUX_IPSR_DATA(IP3_8_6, BS_N),
 934         PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N),
 935         PINMUX_IPSR_MODSEL_DATA(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
 936         PINMUX_IPSR_MODSEL_DATA(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
 937         PINMUX_IPSR_MODSEL_DATA(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
 938         PINMUX_IPSR_DATA(IP3_8_6, PWM2),
 939         PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2),
 940         PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N),
 941         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
 942         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, FMIN_B, SEL_FM_1),
 943         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
 944         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, DREQ1_D, SEL_LBS_1),
 945         PINMUX_IPSR_DATA(IP3_13_12, WE0_N),
 946         PINMUX_IPSR_MODSEL_DATA(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
 947         PINMUX_IPSR_MODSEL_DATA(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
 948         PINMUX_IPSR_DATA(IP3_15_14, WE1_N),
 949         PINMUX_IPSR_MODSEL_DATA(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
 950         PINMUX_IPSR_MODSEL_DATA(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
 951         PINMUX_IPSR_MODSEL_DATA(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
 952         PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0),
 953         PINMUX_IPSR_MODSEL_DATA(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
 954         PINMUX_IPSR_MODSEL_DATA(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
 955         PINMUX_IPSR_DATA(IP3_19_18, DREQ0),
 956         PINMUX_IPSR_DATA(IP3_19_18, PWM3),
 957         PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3),
 958         PINMUX_IPSR_DATA(IP3_21_20, DACK0),
 959         PINMUX_IPSR_DATA(IP3_21_20, DRACK0),
 960         PINMUX_IPSR_MODSEL_DATA(IP3_21_20, REMOCON, SEL_RCN_0),
 961         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SPEEDIN, SEL_RSP_0),
 962         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
 963         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
 964         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
 965         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
 966         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, DREQ2_C, SEL_LBS_2),
 967         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 968         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
 969         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
 970         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
 971         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
 972         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
 973         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
 974         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
 975         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 976         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
 977         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
 978
 979         /* IPSR4 */
 980         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
 981         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL0_B, SEL_IIC0_1),
 982         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL7_B, SEL_IIC7_1),
 983         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
 984         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
 985         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA0_B, SEL_IIC0_1),
 986         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA7_B, SEL_IIC7_1),
 987         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
 988         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, GLO_I0_D, SEL_GPS_3),
 989         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SSI_WS1, SEL_SSI1_0),
 990         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL1_B, SEL_IIC1_1),
 991         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL8_B, SEL_IIC8_1),
 992         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
 993         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, GLO_I1_D, SEL_GPS_3),
 994         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
 995         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA1_B, SEL_IIC1_1),
 996         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA8_B, SEL_IIC8_1),
 997         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
 998         PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2),
 999         PINMUX_IPSR_MODSEL_DATA(IP4_12_10, SCL2, SEL_IIC2_0),
1000         PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1001         PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1002         PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2),
1003         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, SDA2, SEL_IIC2_0),
1004         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1005         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, RX2_E, SEL_SCIF2_4),
1006         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1007         PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2),
1008         PINMUX_IPSR_MODSEL_DATA(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1009         PINMUX_IPSR_MODSEL_DATA(IP4_18_16, TX2_E, SEL_SCIF2_4),
1010         PINMUX_IPSR_DATA(IP4_19, SSI_SCK34),
1011         PINMUX_IPSR_DATA(IP4_20, SSI_WS34),
1012         PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3),
1013         PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4),
1014         PINMUX_IPSR_MODSEL_DATA(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1015         PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4),
1016         PINMUX_IPSR_MODSEL_DATA(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1017         PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4),
1018         PINMUX_IPSR_MODSEL_DATA(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1019         PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5),
1020         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1021         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1022         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, GLO_I0, SEL_GPS_0),
1023         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1024         PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B),
1025
1026         /* IPSR5 */
1027         PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5),
1028         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1029         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1030         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, GLO_I1, SEL_GPS_0),
1031         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1032         PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B),
1033         PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5),
1034         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1035         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1036         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, GLO_Q0, SEL_GPS_0),
1037         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1038         PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B),
1039         PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6),
1040         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1041         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1042         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, GLO_Q1, SEL_GPS_0),
1043         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1044         PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B),
1045         PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6),
1046         PINMUX_IPSR_MODSEL_DATA(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1047         PINMUX_IPSR_MODSEL_DATA(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1048         PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B),
1049         PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6),
1050         PINMUX_IPSR_MODSEL_DATA(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1051         PINMUX_IPSR_MODSEL_DATA(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1052         PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B),
1053         PINMUX_IPSR_MODSEL_DATA(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1054         PINMUX_IPSR_MODSEL_DATA(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1055         PINMUX_IPSR_MODSEL_DATA(IP5_16_15, GLO_SS, SEL_GPS_0),
1056         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1057         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, TX0_D, SEL_SCIF0_3),
1058         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1059         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, GLO_RFON, SEL_GPS_0),
1060         PINMUX_IPSR_MODSEL_DATA(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1061         PINMUX_IPSR_MODSEL_DATA(IP5_21_20, RX0_D, SEL_SCIF0_3),
1062         PINMUX_IPSR_MODSEL_DATA(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1063         PINMUX_IPSR_MODSEL_DATA(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1064         PINMUX_IPSR_MODSEL_DATA(IP5_23_22, TX1_D, SEL_SCIF1_3),
1065         PINMUX_IPSR_MODSEL_DATA(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1066         PINMUX_IPSR_MODSEL_DATA(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1067         PINMUX_IPSR_MODSEL_DATA(IP5_25_24, RX1_D, SEL_SCIF1_3),
1068         PINMUX_IPSR_MODSEL_DATA(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1069         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1070         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, TX3_D, SEL_SCIF3_3),
1071         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1072         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1073         PINMUX_IPSR_MODSEL_DATA(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1074         PINMUX_IPSR_MODSEL_DATA(IP5_31_29, RX3_D, SEL_SCIF3_3),
1075         PINMUX_IPSR_MODSEL_DATA(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1076
1077         /* IPSR6 */
1078         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1079         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1080         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1081         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1082         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4),
1083         PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
1084         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1085         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1086         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0),
1087         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1088         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4),
1089         PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
1090         PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1091         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0),
1092         PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1093         PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
1094         PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1095         PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
1096         PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
1097         PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1098         PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
1099         PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
1100         PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1101         PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
1102         PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
1103         PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2),
1104         PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1105         PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
1106         PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
1107         PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1108         PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2),
1109         PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1110         PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
1111         PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
1112         PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1113         PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4),
1114         PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1115         PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
1116         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1117         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1118         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4),
1119         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1120         PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
1121         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1122         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1123         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1124         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1125         PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
1126         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1127         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1128         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1129         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1130
1131         /* IPSR7 */
1132         PINMUX_IPSR_DATA(IP7_2_0, IRQ9),
1133         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1134         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1135         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1136         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1137         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1138         PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0),
1139         PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0),
1140         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1141         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TX0_B, SEL_SCIF0_1),
1142         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1143         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1144         PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1),
1145         PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1),
1146         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1147         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX0_B, SEL_SCIF0_1),
1148         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1149         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1150         PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2),
1151         PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2),
1152         PINMUX_IPSR_MODSEL_DATA(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1153         PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3),
1154         PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3),
1155         PINMUX_IPSR_MODSEL_DATA(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1156         PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4),
1157         PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4),
1158         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1159         PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5),
1160         PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5),
1161         PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1162         PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6),
1163         PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6),
1164         PINMUX_IPSR_MODSEL_DATA(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1165         PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7),
1166         PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7),
1167         PINMUX_IPSR_MODSEL_DATA(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1168         PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0),
1169         PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8),
1170         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1171         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX1_B, SEL_SCIF1_1),
1172         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1173         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1174         PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1),
1175         PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9),
1176         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1177         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX1_B, SEL_SCIF1_1),
1178         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1179         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1180         PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2),
1181         PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10),
1182         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1183         PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B),
1184         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1185         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1186
1187         /* IPSR8 */
1188         PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3),
1189         PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11),
1190         PINMUX_IPSR_MODSEL_DATA(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1191         PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1192         PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4),
1193         PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12),
1194         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1195         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1196         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1197         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1198         PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5),
1199         PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13),
1200         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1201         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1202         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1203         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1204         PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6),
1205         PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14),
1206         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1207         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1208         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1209         PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7),
1210         PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15),
1211         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1212         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1213         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1214         PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0),
1215         PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16),
1216         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1217         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, TX2_B, SEL_SCIF2_1),
1218         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1219         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1220         PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1),
1221         PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17),
1222         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1223         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, RX2_B, SEL_SCIF2_1),
1224         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1225         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1226         PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2),
1227         PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18),
1228         PINMUX_IPSR_MODSEL_DATA(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1229         PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B),
1230         PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1231         PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1232         PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3),
1233         PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19),
1234         PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1235         PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4),
1236         PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20),
1237         PINMUX_IPSR_MODSEL_DATA(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1238         PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1239         PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5),
1240         PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21),
1241         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, TX3, SEL_SCIF3_0),
1242         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1243         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1244
1245         /* IPSR9 */
1246         PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6),
1247         PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22),
1248         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCL3_C, SEL_IIC3_2),
1249         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RX3, SEL_SCIF3_0),
1250         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1251         PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7),
1252         PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23),
1253         PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SDA3_C, SEL_IIC3_2),
1254         PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1255         PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1256         PINMUX_IPSR_MODSEL_DATA(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1257         PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS),
1258         PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0),
1259         PINMUX_IPSR_DATA(IP9_7, QCLK),
1260         PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1),
1261         PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE),
1262         PINMUX_IPSR_MODSEL_DATA(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1263         PINMUX_IPSR_MODSEL_DATA(IP9_10_8, TX3_B, SEL_SCIF3_1),
1264         PINMUX_IPSR_MODSEL_DATA(IP9_10_8, SCL2_B, SEL_IIC2_1),
1265         PINMUX_IPSR_DATA(IP9_10_8, PWM4),
1266         PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1267         PINMUX_IPSR_DATA(IP9_11, QSTH_QHS),
1268         PINMUX_IPSR_DATA(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1269         PINMUX_IPSR_DATA(IP9_12, QSTB_QHE),
1270         PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1271         PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE),
1272         PINMUX_IPSR_MODSEL_DATA(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1273         PINMUX_IPSR_MODSEL_DATA(IP9_15_13, RX3_B, SEL_SCIF3_1),
1274         PINMUX_IPSR_MODSEL_DATA(IP9_15_13, SDA2_B, SEL_IIC2_1),
1275         PINMUX_IPSR_DATA(IP9_16, DU1_DISP),
1276         PINMUX_IPSR_DATA(IP9_16, QPOLA),
1277         PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE),
1278         PINMUX_IPSR_DATA(IP9_18_17, QPOLB),
1279         PINMUX_IPSR_DATA(IP9_18_17, PWM4_B),
1280         PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB),
1281         PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TX4, SEL_SCIF4_0),
1282         PINMUX_IPSR_MODSEL_DATA(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1283         PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1284         PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD),
1285         PINMUX_IPSR_MODSEL_DATA(IP9_22_21, RX4, SEL_SCIF4_0),
1286         PINMUX_IPSR_MODSEL_DATA(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1287         PINMUX_IPSR_MODSEL_DATA(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1288         PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N),
1289         PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TX5, SEL_SCIF5_0),
1290         PINMUX_IPSR_MODSEL_DATA(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1291         PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1292         PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N),
1293         PINMUX_IPSR_MODSEL_DATA(IP9_26_25, RX5, SEL_SCIF5_0),
1294         PINMUX_IPSR_MODSEL_DATA(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1295         PINMUX_IPSR_MODSEL_DATA(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1296         PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3),
1297         PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1298         PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1299         PINMUX_IPSR_DATA(IP9_31_29, VI0_G0),
1300         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL8, SEL_IIC8_0),
1301         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1302         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL4, SEL_IIC4_0),
1303         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1304         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1305         PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N),
1306
1307         /* IPSR10 */
1308         PINMUX_IPSR_DATA(IP10_2_0, VI0_G1),
1309         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA8, SEL_IIC8_0),
1310         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1311         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA4, SEL_IIC4_0),
1312         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1313         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1314         PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N),
1315         PINMUX_IPSR_DATA(IP10_5_3, VI0_G2),
1316         PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N),
1317         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1318         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCL3_B, SEL_IIC3_1),
1319         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1320         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1321         PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N),
1322         PINMUX_IPSR_DATA(IP10_8_6, VI0_G3),
1323         PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N),
1324         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1325         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SDA3_B, SEL_IIC3_1),
1326         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX2, SEL_HSCIF2_0),
1327         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1328         PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N),
1329         PINMUX_IPSR_DATA(IP10_11_9, VI0_G4),
1330         PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB),
1331         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1332         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX2, SEL_HSCIF2_0),
1333         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1334         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1335         PINMUX_IPSR_DATA(IP10_14_12, VI0_G5),
1336         PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD),
1337         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1338         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, FMCLK_D, SEL_FM_3),
1339         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1340         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1341         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1342         PINMUX_IPSR_DATA(IP10_16_15, VI0_G6),
1343         PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK),
1344         PINMUX_IPSR_MODSEL_DATA(IP10_16_15, BPFCLK_D, SEL_FM_3),
1345         PINMUX_IPSR_DATA(IP10_18_17, VI0_G7),
1346         PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0),
1347         PINMUX_IPSR_MODSEL_DATA(IP10_18_17, FMIN_D, SEL_FM_3),
1348         PINMUX_IPSR_DATA(IP10_21_19, VI0_R0),
1349         PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1),
1350         PINMUX_IPSR_MODSEL_DATA(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1351         PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1352         PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N),
1353         PINMUX_IPSR_DATA(IP10_24_22, VI0_R1),
1354         PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2),
1355         PINMUX_IPSR_MODSEL_DATA(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1356         PINMUX_IPSR_MODSEL_DATA(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1357         PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N),
1358         PINMUX_IPSR_DATA(IP10_26_25, VI0_R2),
1359         PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3),
1360         PINMUX_IPSR_MODSEL_DATA(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1361         PINMUX_IPSR_MODSEL_DATA(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1362         PINMUX_IPSR_DATA(IP10_28_27, VI0_R3),
1363         PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4),
1364         PINMUX_IPSR_MODSEL_DATA(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1365         PINMUX_IPSR_MODSEL_DATA(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1366         PINMUX_IPSR_DATA(IP10_31_29, VI0_R4),
1367         PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5),
1368         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1369         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, TX0_C, SEL_SCIF0_2),
1370         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL1_D, SEL_IIC1_3),
1371
1372         /* IPSR11 */
1373         PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
1374         PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
1375         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1376         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
1377         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
1378         PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
1379         PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
1380         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1381         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
1382         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
1383         PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
1384         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1385         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
1386         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1387         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
1388         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1389         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1390         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1391         PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
1392         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1393         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
1394         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1395         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1396         PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
1397         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1398         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
1399         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1400         PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1401         PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
1402         PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1403         PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1404         PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
1405         PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1406         PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
1407         PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
1408         PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
1409         PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
1410         PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
1411         PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
1412         PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
1413         PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
1414         PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
1415         PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
1416         PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
1417         PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
1418         PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
1419         PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
1420         PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
1421         PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
1422         PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
1423         PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
1424         PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
1425         PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
1426         PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
1427         PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
1428         PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
1429         PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
1430
1431         /* IPSR12 */
1432         PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
1433         PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
1434         PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
1435         PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
1436         PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
1437         PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
1438         PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
1439         PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
1440         PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
1441         PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
1442         PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1443         PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
1444         PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1445         PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
1446         PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
1447         PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1448         PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
1449         PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1450         PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
1451         PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
1452         PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1453         PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1454         PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1455         PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
1456         PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
1457         PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1458         PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1459         PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1460         PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
1461         PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
1462         PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1463         PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1464         PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
1465         PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
1466         PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
1467         PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
1468         PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
1469         PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
1470         PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
1471         PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
1472         PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
1473         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1474         PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
1475         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1476         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1477         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1478         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1479         PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
1480         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1481         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1482         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1483
1484         /* IPSR13 */
1485         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1486         PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
1487         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1488         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1),
1489         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1490         PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1491         PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
1492         PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1493         PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1494         PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1495         PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
1496         PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1497         PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1498         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1499         PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
1500         PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
1501         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1502         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1503         PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
1504         PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1),
1505         PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
1506         PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1507         PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
1508         PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1),
1509         PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
1510         PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1),
1511         PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
1512         PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1),
1513         PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
1514         PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1),
1515         PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
1516         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1517         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1518         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1519         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1520         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2),
1521         PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
1522         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1523         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1524         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1525         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1526         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2),
1527         PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
1528         PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1),
1529         PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
1530         PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1531         PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
1532         PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1),
1533         PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
1534         PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1),
1535         PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
1536         PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1),
1537         PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
1538         PINMUX_IPSR_DATA(IP13_30_28, PWM0),
1539         PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
1540         PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2),
1541
1542         /* IPSR14 */
1543         PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
1544         PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
1545         PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2),
1546         PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
1547         PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
1548         PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
1549         PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
1550         PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
1551         PINMUX_IPSR_DATA(IP14_4, MMC_D0),
1552         PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
1553         PINMUX_IPSR_DATA(IP14_5, MMC_D1),
1554         PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
1555         PINMUX_IPSR_DATA(IP14_6, MMC_D2),
1556         PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
1557         PINMUX_IPSR_DATA(IP14_7, MMC_D3),
1558         PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
1559         PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
1560         PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2),
1561         PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1),
1562         PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1563         PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
1564         PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
1565         PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2),
1566         PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1),
1567         PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1568         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1569         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2),
1570         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0),
1571         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1572         PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
1573         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1574         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2),
1575         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1576         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1577         PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
1578         PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1579         PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0),
1580         PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1581         PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
1582         PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1583         PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0),
1584         PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1585         PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
1586         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1587         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0),
1588         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0),
1589         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4),
1590         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1591         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2),
1592         PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
1593         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1594         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0),
1595         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0),
1596         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4),
1597         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1598         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2),
1599         PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
1600
1601         /* IPSR15 */
1602         PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0),
1603         PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0),
1604         PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1605         PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
1606         PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0),
1607         PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1608         PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0),
1609         PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0),
1610         PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1611         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0),
1612         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1613         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1614         PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
1615         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1616         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1617         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2),
1618         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1619         PINMUX_IPSR_DATA(IP15_11_9, PWM5),
1620         PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
1621         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1622         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0),
1623         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2),
1624         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1625         PINMUX_IPSR_DATA(IP15_14_12, PWM6),
1626         PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
1627         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1628         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1629         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1630         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1631         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0),
1632         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1633         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1634         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1635         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1636         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1637         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1638         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1639         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1640         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1641         PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
1642         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1643         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0),
1644         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1645         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1646         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1647         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1648         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0),
1649         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1650         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1651         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1652         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1653
1654         /* IPSR16 */
1655         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0),
1656         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1657         PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
1658         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1659         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1660         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0),
1661         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1662         PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
1663         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1664         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1665         PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1666         PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1667         PINMUX_IPSR_DATA(IP16_7_6, MLB_CK),
1668         PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1669         PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1670         PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
1671         PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
1672         PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1673         PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1674         PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
1675         PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
1676         PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1677 };
1678
1679 static const struct sh_pfc_pin pinmux_pins[] = {
1680         PINMUX_GPIO_GP_ALL(),
1681 };
1682
1683 /* - Audio Clock ------------------------------------------------------------ */
1684 static const unsigned int audio_clk_a_pins[] = {
1685         /* CLK */
1686         RCAR_GP_PIN(2, 28),
1687 };
1688
1689 static const unsigned int audio_clk_a_mux[] = {
1690         AUDIO_CLKA_MARK,
1691 };
1692
1693 static const unsigned int audio_clk_b_pins[] = {
1694         /* CLK */
1695         RCAR_GP_PIN(2, 29),
1696 };
1697
1698 static const unsigned int audio_clk_b_mux[] = {
1699         AUDIO_CLKB_MARK,
1700 };
1701
1702 static const unsigned int audio_clk_b_b_pins[] = {
1703         /* CLK */
1704         RCAR_GP_PIN(7, 20),
1705 };
1706
1707 static const unsigned int audio_clk_b_b_mux[] = {
1708         AUDIO_CLKB_B_MARK,
1709 };
1710
1711 static const unsigned int audio_clk_c_pins[] = {
1712         /* CLK */
1713         RCAR_GP_PIN(2, 30),
1714 };
1715
1716 static const unsigned int audio_clk_c_mux[] = {
1717         AUDIO_CLKC_MARK,
1718 };
1719
1720 static const unsigned int audio_clkout_pins[] = {
1721         /* CLK */
1722         RCAR_GP_PIN(2, 31),
1723 };
1724
1725 static const unsigned int audio_clkout_mux[] = {
1726         AUDIO_CLKOUT_MARK,
1727 };
1728
1729
1730 /* - DU --------------------------------------------------------------------- */
1731 static const unsigned int du_rgb666_pins[] = {
1732         /* R[7:2], G[7:2], B[7:2] */
1733         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
1734         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
1735         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1736         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1737         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1738         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1739 };
1740 static const unsigned int du_rgb666_mux[] = {
1741         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1742         DU1_DR3_MARK, DU1_DR2_MARK,
1743         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1744         DU1_DG3_MARK, DU1_DG2_MARK,
1745         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1746         DU1_DB3_MARK, DU1_DB2_MARK,
1747 };
1748 static const unsigned int du_rgb888_pins[] = {
1749         /* R[7:0], G[7:0], B[7:0] */
1750         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
1751         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
1752         RCAR_GP_PIN(3, 1),  RCAR_GP_PIN(3, 0),
1753         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1754         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1755         RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 8),
1756         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1757         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1758         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
1759 };
1760 static const unsigned int du_rgb888_mux[] = {
1761         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1762         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1763         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1764         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1765         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1766         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1767 };
1768 static const unsigned int du_clk_out_0_pins[] = {
1769         /* CLKOUT */
1770         RCAR_GP_PIN(3, 25),
1771 };
1772 static const unsigned int du_clk_out_0_mux[] = {
1773         DU1_DOTCLKOUT0_MARK
1774 };
1775 static const unsigned int du_clk_out_1_pins[] = {
1776         /* CLKOUT */
1777         RCAR_GP_PIN(3, 26),
1778 };
1779 static const unsigned int du_clk_out_1_mux[] = {
1780         DU1_DOTCLKOUT1_MARK
1781 };
1782 static const unsigned int du_sync_pins[] = {
1783         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1784         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1785 };
1786 static const unsigned int du_sync_mux[] = {
1787         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1788 };
1789 static const unsigned int du_oddf_pins[] = {
1790         /* EXDISP/EXODDF/EXCDE */
1791         RCAR_GP_PIN(3, 29),
1792 };
1793 static const unsigned int du_oddf_mux[] = {
1794         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1795 };
1796 static const unsigned int du_cde_pins[] = {
1797         /* CDE */
1798         RCAR_GP_PIN(3, 31),
1799 };
1800 static const unsigned int du_cde_mux[] = {
1801         DU1_CDE_MARK,
1802 };
1803 static const unsigned int du_disp_pins[] = {
1804         /* DISP */
1805         RCAR_GP_PIN(3, 30),
1806 };
1807 static const unsigned int du_disp_mux[] = {
1808         DU1_DISP_MARK,
1809 };
1810 static const unsigned int du0_clk_in_pins[] = {
1811         /* CLKIN */
1812         RCAR_GP_PIN(6, 31),
1813 };
1814 static const unsigned int du0_clk_in_mux[] = {
1815         DU0_DOTCLKIN_MARK
1816 };
1817 static const unsigned int du1_clk_in_pins[] = {
1818         /* CLKIN */
1819         RCAR_GP_PIN(3, 24),
1820 };
1821 static const unsigned int du1_clk_in_mux[] = {
1822         DU1_DOTCLKIN_MARK
1823 };
1824 static const unsigned int du1_clk_in_b_pins[] = {
1825         /* CLKIN */
1826         RCAR_GP_PIN(7, 19),
1827 };
1828 static const unsigned int du1_clk_in_b_mux[] = {
1829         DU1_DOTCLKIN_B_MARK,
1830 };
1831 static const unsigned int du1_clk_in_c_pins[] = {
1832         /* CLKIN */
1833         RCAR_GP_PIN(7, 20),
1834 };
1835 static const unsigned int du1_clk_in_c_mux[] = {
1836         DU1_DOTCLKIN_C_MARK,
1837 };
1838 /* - ETH -------------------------------------------------------------------- */
1839 static const unsigned int eth_link_pins[] = {
1840         /* LINK */
1841         RCAR_GP_PIN(5, 18),
1842 };
1843 static const unsigned int eth_link_mux[] = {
1844         ETH_LINK_MARK,
1845 };
1846 static const unsigned int eth_magic_pins[] = {
1847         /* MAGIC */
1848         RCAR_GP_PIN(5, 22),
1849 };
1850 static const unsigned int eth_magic_mux[] = {
1851         ETH_MAGIC_MARK,
1852 };
1853 static const unsigned int eth_mdio_pins[] = {
1854         /* MDC, MDIO */
1855         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
1856 };
1857 static const unsigned int eth_mdio_mux[] = {
1858         ETH_MDC_MARK, ETH_MDIO_MARK,
1859 };
1860 static const unsigned int eth_rmii_pins[] = {
1861         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1862         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
1863         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
1864         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
1865 };
1866 static const unsigned int eth_rmii_mux[] = {
1867         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1868         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1869 };
1870 /* - I2C0 ------------------------------------------------------------------- */
1871 static const unsigned int i2c0_pins[] = {
1872         /* SCL, SDA */
1873         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
1874 };
1875 static const unsigned int i2c0_mux[] = {
1876         SCL0_MARK, SDA0_MARK,
1877 };
1878 static const unsigned int i2c0_b_pins[] = {
1879         /* SCL, SDA */
1880         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1881 };
1882 static const unsigned int i2c0_b_mux[] = {
1883         SCL0_B_MARK, SDA0_B_MARK,
1884 };
1885 static const unsigned int i2c0_c_pins[] = {
1886         /* SCL, SDA */
1887         RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
1888 };
1889 static const unsigned int i2c0_c_mux[] = {
1890         SCL0_C_MARK, SDA0_C_MARK,
1891 };
1892 /* - I2C1 ------------------------------------------------------------------- */
1893 static const unsigned int i2c1_pins[] = {
1894         /* SCL, SDA */
1895         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
1896 };
1897 static const unsigned int i2c1_mux[] = {
1898         SCL1_MARK, SDA1_MARK,
1899 };
1900 static const unsigned int i2c1_b_pins[] = {
1901         /* SCL, SDA */
1902         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1903 };
1904 static const unsigned int i2c1_b_mux[] = {
1905         SCL1_B_MARK, SDA1_B_MARK,
1906 };
1907 static const unsigned int i2c1_c_pins[] = {
1908         /* SCL, SDA */
1909         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1910 };
1911 static const unsigned int i2c1_c_mux[] = {
1912         SCL1_C_MARK, SDA1_C_MARK,
1913 };
1914 static const unsigned int i2c1_d_pins[] = {
1915         /* SCL, SDA */
1916         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
1917 };
1918 static const unsigned int i2c1_d_mux[] = {
1919         SCL1_D_MARK, SDA1_D_MARK,
1920 };
1921 static const unsigned int i2c1_e_pins[] = {
1922         /* SCL, SDA */
1923         RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
1924 };
1925 static const unsigned int i2c1_e_mux[] = {
1926         SCL1_E_MARK, SDA1_E_MARK,
1927 };
1928 /* - I2C2 ------------------------------------------------------------------- */
1929 static const unsigned int i2c2_pins[] = {
1930         /* SCL, SDA */
1931         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1932 };
1933 static const unsigned int i2c2_mux[] = {
1934         SCL2_MARK, SDA2_MARK,
1935 };
1936 static const unsigned int i2c2_b_pins[] = {
1937         /* SCL, SDA */
1938         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1939 };
1940 static const unsigned int i2c2_b_mux[] = {
1941         SCL2_B_MARK, SDA2_B_MARK,
1942 };
1943 static const unsigned int i2c2_c_pins[] = {
1944         /* SCL, SDA */
1945         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1946 };
1947 static const unsigned int i2c2_c_mux[] = {
1948         SCL2_C_MARK, SDA2_C_MARK,
1949 };
1950 static const unsigned int i2c2_d_pins[] = {
1951         /* SCL, SDA */
1952         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1953 };
1954 static const unsigned int i2c2_d_mux[] = {
1955         SCL2_D_MARK, SDA2_D_MARK,
1956 };
1957 /* - I2C3 ------------------------------------------------------------------- */
1958 static const unsigned int i2c3_pins[] = {
1959         /* SCL, SDA */
1960         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1961 };
1962 static const unsigned int i2c3_mux[] = {
1963         SCL3_MARK, SDA3_MARK,
1964 };
1965 static const unsigned int i2c3_b_pins[] = {
1966         /* SCL, SDA */
1967         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
1968 };
1969 static const unsigned int i2c3_b_mux[] = {
1970         SCL3_B_MARK, SDA3_B_MARK,
1971 };
1972 static const unsigned int i2c3_c_pins[] = {
1973         /* SCL, SDA */
1974         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
1975 };
1976 static const unsigned int i2c3_c_mux[] = {
1977         SCL3_C_MARK, SDA3_C_MARK,
1978 };
1979 static const unsigned int i2c3_d_pins[] = {
1980         /* SCL, SDA */
1981         RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
1982 };
1983 static const unsigned int i2c3_d_mux[] = {
1984         SCL3_D_MARK, SDA3_D_MARK,
1985 };
1986 /* - I2C4 ------------------------------------------------------------------- */
1987 static const unsigned int i2c4_pins[] = {
1988         /* SCL, SDA */
1989         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
1990 };
1991 static const unsigned int i2c4_mux[] = {
1992         SCL4_MARK, SDA4_MARK,
1993 };
1994 static const unsigned int i2c4_b_pins[] = {
1995         /* SCL, SDA */
1996         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
1997 };
1998 static const unsigned int i2c4_b_mux[] = {
1999         SCL4_B_MARK, SDA4_B_MARK,
2000 };
2001 static const unsigned int i2c4_c_pins[] = {
2002         /* SCL, SDA */
2003         RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
2004 };
2005 static const unsigned int i2c4_c_mux[] = {
2006         SCL4_C_MARK, SDA4_C_MARK,
2007 };
2008 /* - I2C7 ------------------------------------------------------------------- */
2009 static const unsigned int i2c7_pins[] = {
2010         /* SCL, SDA */
2011         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2012 };
2013 static const unsigned int i2c7_mux[] = {
2014         SCL7_MARK, SDA7_MARK,
2015 };
2016 static const unsigned int i2c7_b_pins[] = {
2017         /* SCL, SDA */
2018         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2019 };
2020 static const unsigned int i2c7_b_mux[] = {
2021         SCL7_B_MARK, SDA7_B_MARK,
2022 };
2023 static const unsigned int i2c7_c_pins[] = {
2024         /* SCL, SDA */
2025         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2026 };
2027 static const unsigned int i2c7_c_mux[] = {
2028         SCL7_C_MARK, SDA7_C_MARK,
2029 };
2030 /* - I2C8 ------------------------------------------------------------------- */
2031 static const unsigned int i2c8_pins[] = {
2032         /* SCL, SDA */
2033         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2034 };
2035 static const unsigned int i2c8_mux[] = {
2036         SCL8_MARK, SDA8_MARK,
2037 };
2038 static const unsigned int i2c8_b_pins[] = {
2039         /* SCL, SDA */
2040         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2041 };
2042 static const unsigned int i2c8_b_mux[] = {
2043         SCL8_B_MARK, SDA8_B_MARK,
2044 };
2045 static const unsigned int i2c8_c_pins[] = {
2046         /* SCL, SDA */
2047         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2048 };
2049 static const unsigned int i2c8_c_mux[] = {
2050         SCL8_C_MARK, SDA8_C_MARK,
2051 };
2052 /* - INTC ------------------------------------------------------------------- */
2053 static const unsigned int intc_irq0_pins[] = {
2054         /* IRQ */
2055         RCAR_GP_PIN(7, 10),
2056 };
2057 static const unsigned int intc_irq0_mux[] = {
2058         IRQ0_MARK,
2059 };
2060 static const unsigned int intc_irq1_pins[] = {
2061         /* IRQ */
2062         RCAR_GP_PIN(7, 11),
2063 };
2064 static const unsigned int intc_irq1_mux[] = {
2065         IRQ1_MARK,
2066 };
2067 static const unsigned int intc_irq2_pins[] = {
2068         /* IRQ */
2069         RCAR_GP_PIN(7, 12),
2070 };
2071 static const unsigned int intc_irq2_mux[] = {
2072         IRQ2_MARK,
2073 };
2074 static const unsigned int intc_irq3_pins[] = {
2075         /* IRQ */
2076         RCAR_GP_PIN(7, 13),
2077 };
2078 static const unsigned int intc_irq3_mux[] = {
2079         IRQ3_MARK,
2080 };
2081 /* - MMCIF ------------------------------------------------------------------ */
2082 static const unsigned int mmc_data1_pins[] = {
2083         /* D[0] */
2084         RCAR_GP_PIN(6, 18),
2085 };
2086 static const unsigned int mmc_data1_mux[] = {
2087         MMC_D0_MARK,
2088 };
2089 static const unsigned int mmc_data4_pins[] = {
2090         /* D[0:3] */
2091         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2092         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2093 };
2094 static const unsigned int mmc_data4_mux[] = {
2095         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2096 };
2097 static const unsigned int mmc_data8_pins[] = {
2098         /* D[0:7] */
2099         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2100         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2101         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2102         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2103 };
2104 static const unsigned int mmc_data8_mux[] = {
2105         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2106         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2107 };
2108 static const unsigned int mmc_ctrl_pins[] = {
2109         /* CLK, CMD */
2110         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2111 };
2112 static const unsigned int mmc_ctrl_mux[] = {
2113         MMC_CLK_MARK, MMC_CMD_MARK,
2114 };
2115 /* - MSIOF0 ----------------------------------------------------------------- */
2116 static const unsigned int msiof0_clk_pins[] = {
2117         /* SCK */
2118         RCAR_GP_PIN(6, 24),
2119 };
2120 static const unsigned int msiof0_clk_mux[] = {
2121         MSIOF0_SCK_MARK,
2122 };
2123 static const unsigned int msiof0_sync_pins[] = {
2124         /* SYNC */
2125         RCAR_GP_PIN(6, 25),
2126 };
2127 static const unsigned int msiof0_sync_mux[] = {
2128         MSIOF0_SYNC_MARK,
2129 };
2130 static const unsigned int msiof0_ss1_pins[] = {
2131         /* SS1 */
2132         RCAR_GP_PIN(6, 28),
2133 };
2134 static const unsigned int msiof0_ss1_mux[] = {
2135         MSIOF0_SS1_MARK,
2136 };
2137 static const unsigned int msiof0_ss2_pins[] = {
2138         /* SS2 */
2139         RCAR_GP_PIN(6, 29),
2140 };
2141 static const unsigned int msiof0_ss2_mux[] = {
2142         MSIOF0_SS2_MARK,
2143 };
2144 static const unsigned int msiof0_rx_pins[] = {
2145         /* RXD */
2146         RCAR_GP_PIN(6, 27),
2147 };
2148 static const unsigned int msiof0_rx_mux[] = {
2149         MSIOF0_RXD_MARK,
2150 };
2151 static const unsigned int msiof0_tx_pins[] = {
2152         /* TXD */
2153         RCAR_GP_PIN(6, 26),
2154 };
2155 static const unsigned int msiof0_tx_mux[] = {
2156         MSIOF0_TXD_MARK,
2157 };
2158
2159 static const unsigned int msiof0_clk_b_pins[] = {
2160         /* SCK */
2161         RCAR_GP_PIN(0, 16),
2162 };
2163 static const unsigned int msiof0_clk_b_mux[] = {
2164         MSIOF0_SCK_B_MARK,
2165 };
2166 static const unsigned int msiof0_sync_b_pins[] = {
2167         /* SYNC */
2168         RCAR_GP_PIN(0, 17),
2169 };
2170 static const unsigned int msiof0_sync_b_mux[] = {
2171         MSIOF0_SYNC_B_MARK,
2172 };
2173 static const unsigned int msiof0_ss1_b_pins[] = {
2174         /* SS1 */
2175         RCAR_GP_PIN(0, 18),
2176 };
2177 static const unsigned int msiof0_ss1_b_mux[] = {
2178         MSIOF0_SS1_B_MARK,
2179 };
2180 static const unsigned int msiof0_ss2_b_pins[] = {
2181         /* SS2 */
2182         RCAR_GP_PIN(0, 19),
2183 };
2184 static const unsigned int msiof0_ss2_b_mux[] = {
2185         MSIOF0_SS2_B_MARK,
2186 };
2187 static const unsigned int msiof0_rx_b_pins[] = {
2188         /* RXD */
2189         RCAR_GP_PIN(0, 21),
2190 };
2191 static const unsigned int msiof0_rx_b_mux[] = {
2192         MSIOF0_RXD_B_MARK,
2193 };
2194 static const unsigned int msiof0_tx_b_pins[] = {
2195         /* TXD */
2196         RCAR_GP_PIN(0, 20),
2197 };
2198 static const unsigned int msiof0_tx_b_mux[] = {
2199         MSIOF0_TXD_B_MARK,
2200 };
2201
2202 static const unsigned int msiof0_clk_c_pins[] = {
2203         /* SCK */
2204         RCAR_GP_PIN(5, 26),
2205 };
2206 static const unsigned int msiof0_clk_c_mux[] = {
2207         MSIOF0_SCK_C_MARK,
2208 };
2209 static const unsigned int msiof0_sync_c_pins[] = {
2210         /* SYNC */
2211         RCAR_GP_PIN(5, 25),
2212 };
2213 static const unsigned int msiof0_sync_c_mux[] = {
2214         MSIOF0_SYNC_C_MARK,
2215 };
2216 static const unsigned int msiof0_ss1_c_pins[] = {
2217         /* SS1 */
2218         RCAR_GP_PIN(5, 27),
2219 };
2220 static const unsigned int msiof0_ss1_c_mux[] = {
2221         MSIOF0_SS1_C_MARK,
2222 };
2223 static const unsigned int msiof0_ss2_c_pins[] = {
2224         /* SS2 */
2225         RCAR_GP_PIN(5, 28),
2226 };
2227 static const unsigned int msiof0_ss2_c_mux[] = {
2228         MSIOF0_SS2_C_MARK,
2229 };
2230 static const unsigned int msiof0_rx_c_pins[] = {
2231         /* RXD */
2232         RCAR_GP_PIN(5, 29),
2233 };
2234 static const unsigned int msiof0_rx_c_mux[] = {
2235         MSIOF0_RXD_C_MARK,
2236 };
2237 static const unsigned int msiof0_tx_c_pins[] = {
2238         /* TXD */
2239         RCAR_GP_PIN(5, 30),
2240 };
2241 static const unsigned int msiof0_tx_c_mux[] = {
2242         MSIOF0_TXD_C_MARK,
2243 };
2244 /* - MSIOF1 ----------------------------------------------------------------- */
2245 static const unsigned int msiof1_clk_pins[] = {
2246         /* SCK */
2247         RCAR_GP_PIN(0, 22),
2248 };
2249 static const unsigned int msiof1_clk_mux[] = {
2250         MSIOF1_SCK_MARK,
2251 };
2252 static const unsigned int msiof1_sync_pins[] = {
2253         /* SYNC */
2254         RCAR_GP_PIN(0, 23),
2255 };
2256 static const unsigned int msiof1_sync_mux[] = {
2257         MSIOF1_SYNC_MARK,
2258 };
2259 static const unsigned int msiof1_ss1_pins[] = {
2260         /* SS1 */
2261         RCAR_GP_PIN(0, 24),
2262 };
2263 static const unsigned int msiof1_ss1_mux[] = {
2264         MSIOF1_SS1_MARK,
2265 };
2266 static const unsigned int msiof1_ss2_pins[] = {
2267         /* SS2 */
2268         RCAR_GP_PIN(0, 25),
2269 };
2270 static const unsigned int msiof1_ss2_mux[] = {
2271         MSIOF1_SS2_MARK,
2272 };
2273 static const unsigned int msiof1_rx_pins[] = {
2274         /* RXD */
2275         RCAR_GP_PIN(0, 27),
2276 };
2277 static const unsigned int msiof1_rx_mux[] = {
2278         MSIOF1_RXD_MARK,
2279 };
2280 static const unsigned int msiof1_tx_pins[] = {
2281         /* TXD */
2282         RCAR_GP_PIN(0, 26),
2283 };
2284 static const unsigned int msiof1_tx_mux[] = {
2285         MSIOF1_TXD_MARK,
2286 };
2287
2288 static const unsigned int msiof1_clk_b_pins[] = {
2289         /* SCK */
2290         RCAR_GP_PIN(2, 29),
2291 };
2292 static const unsigned int msiof1_clk_b_mux[] = {
2293         MSIOF1_SCK_B_MARK,
2294 };
2295 static const unsigned int msiof1_sync_b_pins[] = {
2296         /* SYNC */
2297         RCAR_GP_PIN(2, 30),
2298 };
2299 static const unsigned int msiof1_sync_b_mux[] = {
2300         MSIOF1_SYNC_B_MARK,
2301 };
2302 static const unsigned int msiof1_ss1_b_pins[] = {
2303         /* SS1 */
2304         RCAR_GP_PIN(2, 31),
2305 };
2306 static const unsigned int msiof1_ss1_b_mux[] = {
2307         MSIOF1_SS1_B_MARK,
2308 };
2309 static const unsigned int msiof1_ss2_b_pins[] = {
2310         /* SS2 */
2311         RCAR_GP_PIN(7, 16),
2312 };
2313 static const unsigned int msiof1_ss2_b_mux[] = {
2314         MSIOF1_SS2_B_MARK,
2315 };
2316 static const unsigned int msiof1_rx_b_pins[] = {
2317         /* RXD */
2318         RCAR_GP_PIN(7, 18),
2319 };
2320 static const unsigned int msiof1_rx_b_mux[] = {
2321         MSIOF1_RXD_B_MARK,
2322 };
2323 static const unsigned int msiof1_tx_b_pins[] = {
2324         /* TXD */
2325         RCAR_GP_PIN(7, 17),
2326 };
2327 static const unsigned int msiof1_tx_b_mux[] = {
2328         MSIOF1_TXD_B_MARK,
2329 };
2330
2331 static const unsigned int msiof1_clk_c_pins[] = {
2332         /* SCK */
2333         RCAR_GP_PIN(2, 15),
2334 };
2335 static const unsigned int msiof1_clk_c_mux[] = {
2336         MSIOF1_SCK_C_MARK,
2337 };
2338 static const unsigned int msiof1_sync_c_pins[] = {
2339         /* SYNC */
2340         RCAR_GP_PIN(2, 16),
2341 };
2342 static const unsigned int msiof1_sync_c_mux[] = {
2343         MSIOF1_SYNC_C_MARK,
2344 };
2345 static const unsigned int msiof1_rx_c_pins[] = {
2346         /* RXD */
2347         RCAR_GP_PIN(2, 18),
2348 };
2349 static const unsigned int msiof1_rx_c_mux[] = {
2350         MSIOF1_RXD_C_MARK,
2351 };
2352 static const unsigned int msiof1_tx_c_pins[] = {
2353         /* TXD */
2354         RCAR_GP_PIN(2, 17),
2355 };
2356 static const unsigned int msiof1_tx_c_mux[] = {
2357         MSIOF1_TXD_C_MARK,
2358 };
2359
2360 static const unsigned int msiof1_clk_d_pins[] = {
2361         /* SCK */
2362         RCAR_GP_PIN(0, 28),
2363 };
2364 static const unsigned int msiof1_clk_d_mux[] = {
2365         MSIOF1_SCK_D_MARK,
2366 };
2367 static const unsigned int msiof1_sync_d_pins[] = {
2368         /* SYNC */
2369         RCAR_GP_PIN(0, 30),
2370 };
2371 static const unsigned int msiof1_sync_d_mux[] = {
2372         MSIOF1_SYNC_D_MARK,
2373 };
2374 static const unsigned int msiof1_ss1_d_pins[] = {
2375         /* SS1 */
2376         RCAR_GP_PIN(0, 29),
2377 };
2378 static const unsigned int msiof1_ss1_d_mux[] = {
2379         MSIOF1_SS1_D_MARK,
2380 };
2381 static const unsigned int msiof1_rx_d_pins[] = {
2382         /* RXD */
2383         RCAR_GP_PIN(0, 27),
2384 };
2385 static const unsigned int msiof1_rx_d_mux[] = {
2386         MSIOF1_RXD_D_MARK,
2387 };
2388 static const unsigned int msiof1_tx_d_pins[] = {
2389         /* TXD */
2390         RCAR_GP_PIN(0, 26),
2391 };
2392 static const unsigned int msiof1_tx_d_mux[] = {
2393         MSIOF1_TXD_D_MARK,
2394 };
2395
2396 static const unsigned int msiof1_clk_e_pins[] = {
2397         /* SCK */
2398         RCAR_GP_PIN(5, 18),
2399 };
2400 static const unsigned int msiof1_clk_e_mux[] = {
2401         MSIOF1_SCK_E_MARK,
2402 };
2403 static const unsigned int msiof1_sync_e_pins[] = {
2404         /* SYNC */
2405         RCAR_GP_PIN(5, 19),
2406 };
2407 static const unsigned int msiof1_sync_e_mux[] = {
2408         MSIOF1_SYNC_E_MARK,
2409 };
2410 static const unsigned int msiof1_rx_e_pins[] = {
2411         /* RXD */
2412         RCAR_GP_PIN(5, 17),
2413 };
2414 static const unsigned int msiof1_rx_e_mux[] = {
2415         MSIOF1_RXD_E_MARK,
2416 };
2417 static const unsigned int msiof1_tx_e_pins[] = {
2418         /* TXD */
2419         RCAR_GP_PIN(5, 20),
2420 };
2421 static const unsigned int msiof1_tx_e_mux[] = {
2422         MSIOF1_TXD_E_MARK,
2423 };
2424 /* - MSIOF2 ----------------------------------------------------------------- */
2425 static const unsigned int msiof2_clk_pins[] = {
2426         /* SCK */
2427         RCAR_GP_PIN(1, 13),
2428 };
2429 static const unsigned int msiof2_clk_mux[] = {
2430         MSIOF2_SCK_MARK,
2431 };
2432 static const unsigned int msiof2_sync_pins[] = {
2433         /* SYNC */
2434         RCAR_GP_PIN(1, 14),
2435 };
2436 static const unsigned int msiof2_sync_mux[] = {
2437         MSIOF2_SYNC_MARK,
2438 };
2439 static const unsigned int msiof2_ss1_pins[] = {
2440         /* SS1 */
2441         RCAR_GP_PIN(1, 17),
2442 };
2443 static const unsigned int msiof2_ss1_mux[] = {
2444         MSIOF2_SS1_MARK,
2445 };
2446 static const unsigned int msiof2_ss2_pins[] = {
2447         /* SS2 */
2448         RCAR_GP_PIN(1, 18),
2449 };
2450 static const unsigned int msiof2_ss2_mux[] = {
2451         MSIOF2_SS2_MARK,
2452 };
2453 static const unsigned int msiof2_rx_pins[] = {
2454         /* RXD */
2455         RCAR_GP_PIN(1, 16),
2456 };
2457 static const unsigned int msiof2_rx_mux[] = {
2458         MSIOF2_RXD_MARK,
2459 };
2460 static const unsigned int msiof2_tx_pins[] = {
2461         /* TXD */
2462         RCAR_GP_PIN(1, 15),
2463 };
2464 static const unsigned int msiof2_tx_mux[] = {
2465         MSIOF2_TXD_MARK,
2466 };
2467
2468 static const unsigned int msiof2_clk_b_pins[] = {
2469         /* SCK */
2470         RCAR_GP_PIN(3, 0),
2471 };
2472 static const unsigned int msiof2_clk_b_mux[] = {
2473         MSIOF2_SCK_B_MARK,
2474 };
2475 static const unsigned int msiof2_sync_b_pins[] = {
2476         /* SYNC */
2477         RCAR_GP_PIN(3, 1),
2478 };
2479 static const unsigned int msiof2_sync_b_mux[] = {
2480         MSIOF2_SYNC_B_MARK,
2481 };
2482 static const unsigned int msiof2_ss1_b_pins[] = {
2483         /* SS1 */
2484         RCAR_GP_PIN(3, 8),
2485 };
2486 static const unsigned int msiof2_ss1_b_mux[] = {
2487         MSIOF2_SS1_B_MARK,
2488 };
2489 static const unsigned int msiof2_ss2_b_pins[] = {
2490         /* SS2 */
2491         RCAR_GP_PIN(3, 9),
2492 };
2493 static const unsigned int msiof2_ss2_b_mux[] = {
2494         MSIOF2_SS2_B_MARK,
2495 };
2496 static const unsigned int msiof2_rx_b_pins[] = {
2497         /* RXD */
2498         RCAR_GP_PIN(3, 17),
2499 };
2500 static const unsigned int msiof2_rx_b_mux[] = {
2501         MSIOF2_RXD_B_MARK,
2502 };
2503 static const unsigned int msiof2_tx_b_pins[] = {
2504         /* TXD */
2505         RCAR_GP_PIN(3, 16),
2506 };
2507 static const unsigned int msiof2_tx_b_mux[] = {
2508         MSIOF2_TXD_B_MARK,
2509 };
2510
2511 static const unsigned int msiof2_clk_c_pins[] = {
2512         /* SCK */
2513         RCAR_GP_PIN(2, 2),
2514 };
2515 static const unsigned int msiof2_clk_c_mux[] = {
2516         MSIOF2_SCK_C_MARK,
2517 };
2518 static const unsigned int msiof2_sync_c_pins[] = {
2519         /* SYNC */
2520         RCAR_GP_PIN(2, 3),
2521 };
2522 static const unsigned int msiof2_sync_c_mux[] = {
2523         MSIOF2_SYNC_C_MARK,
2524 };
2525 static const unsigned int msiof2_rx_c_pins[] = {
2526         /* RXD */
2527         RCAR_GP_PIN(2, 5),
2528 };
2529 static const unsigned int msiof2_rx_c_mux[] = {
2530         MSIOF2_RXD_C_MARK,
2531 };
2532 static const unsigned int msiof2_tx_c_pins[] = {
2533         /* TXD */
2534         RCAR_GP_PIN(2, 4),
2535 };
2536 static const unsigned int msiof2_tx_c_mux[] = {
2537         MSIOF2_TXD_C_MARK,
2538 };
2539
2540 static const unsigned int msiof2_clk_d_pins[] = {
2541         /* SCK */
2542         RCAR_GP_PIN(2, 14),
2543 };
2544 static const unsigned int msiof2_clk_d_mux[] = {
2545         MSIOF2_SCK_D_MARK,
2546 };
2547 static const unsigned int msiof2_sync_d_pins[] = {
2548         /* SYNC */
2549         RCAR_GP_PIN(2, 15),
2550 };
2551 static const unsigned int msiof2_sync_d_mux[] = {
2552         MSIOF2_SYNC_D_MARK,
2553 };
2554 static const unsigned int msiof2_ss1_d_pins[] = {
2555         /* SS1 */
2556         RCAR_GP_PIN(2, 17),
2557 };
2558 static const unsigned int msiof2_ss1_d_mux[] = {
2559         MSIOF2_SS1_D_MARK,
2560 };
2561 static const unsigned int msiof2_ss2_d_pins[] = {
2562         /* SS2 */
2563         RCAR_GP_PIN(2, 19),
2564 };
2565 static const unsigned int msiof2_ss2_d_mux[] = {
2566         MSIOF2_SS2_D_MARK,
2567 };
2568 static const unsigned int msiof2_rx_d_pins[] = {
2569         /* RXD */
2570         RCAR_GP_PIN(2, 18),
2571 };
2572 static const unsigned int msiof2_rx_d_mux[] = {
2573         MSIOF2_RXD_D_MARK,
2574 };
2575 static const unsigned int msiof2_tx_d_pins[] = {
2576         /* TXD */
2577         RCAR_GP_PIN(2, 16),
2578 };
2579 static const unsigned int msiof2_tx_d_mux[] = {
2580         MSIOF2_TXD_D_MARK,
2581 };
2582
2583 static const unsigned int msiof2_clk_e_pins[] = {
2584         /* SCK */
2585         RCAR_GP_PIN(7, 15),
2586 };
2587 static const unsigned int msiof2_clk_e_mux[] = {
2588         MSIOF2_SCK_E_MARK,
2589 };
2590 static const unsigned int msiof2_sync_e_pins[] = {
2591         /* SYNC */
2592         RCAR_GP_PIN(7, 16),
2593 };
2594 static const unsigned int msiof2_sync_e_mux[] = {
2595         MSIOF2_SYNC_E_MARK,
2596 };
2597 static const unsigned int msiof2_rx_e_pins[] = {
2598         /* RXD */
2599         RCAR_GP_PIN(7, 14),
2600 };
2601 static const unsigned int msiof2_rx_e_mux[] = {
2602         MSIOF2_RXD_E_MARK,
2603 };
2604 static const unsigned int msiof2_tx_e_pins[] = {
2605         /* TXD */
2606         RCAR_GP_PIN(7, 13),
2607 };
2608 static const unsigned int msiof2_tx_e_mux[] = {
2609         MSIOF2_TXD_E_MARK,
2610 };
2611 /* - QSPI ------------------------------------------------------------------- */
2612 static const unsigned int qspi_ctrl_pins[] = {
2613         /* SPCLK, SSL */
2614         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2615 };
2616 static const unsigned int qspi_ctrl_mux[] = {
2617         SPCLK_MARK, SSL_MARK,
2618 };
2619 static const unsigned int qspi_data2_pins[] = {
2620         /* MOSI_IO0, MISO_IO1 */
2621         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2622 };
2623 static const unsigned int qspi_data2_mux[] = {
2624         MOSI_IO0_MARK, MISO_IO1_MARK,
2625 };
2626 static const unsigned int qspi_data4_pins[] = {
2627         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2628         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2629         RCAR_GP_PIN(1, 8),
2630 };
2631 static const unsigned int qspi_data4_mux[] = {
2632         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2633 };
2634
2635 static const unsigned int qspi_ctrl_b_pins[] = {
2636         /* SPCLK, SSL */
2637         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
2638 };
2639 static const unsigned int qspi_ctrl_b_mux[] = {
2640         SPCLK_B_MARK, SSL_B_MARK,
2641 };
2642 static const unsigned int qspi_data2_b_pins[] = {
2643         /* MOSI_IO0, MISO_IO1 */
2644         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
2645 };
2646 static const unsigned int qspi_data2_b_mux[] = {
2647         MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
2648 };
2649 static const unsigned int qspi_data4_b_pins[] = {
2650         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2651         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
2652         RCAR_GP_PIN(6, 4),
2653 };
2654 static const unsigned int qspi_data4_b_mux[] = {
2655         SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
2656         IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
2657 };
2658 /* - SCIF0 ------------------------------------------------------------------ */
2659 static const unsigned int scif0_data_pins[] = {
2660         /* RX, TX */
2661         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2662 };
2663 static const unsigned int scif0_data_mux[] = {
2664         RX0_MARK, TX0_MARK,
2665 };
2666 static const unsigned int scif0_data_b_pins[] = {
2667         /* RX, TX */
2668         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2669 };
2670 static const unsigned int scif0_data_b_mux[] = {
2671         RX0_B_MARK, TX0_B_MARK,
2672 };
2673 static const unsigned int scif0_data_c_pins[] = {
2674         /* RX, TX */
2675         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
2676 };
2677 static const unsigned int scif0_data_c_mux[] = {
2678         RX0_C_MARK, TX0_C_MARK,
2679 };
2680 static const unsigned int scif0_data_d_pins[] = {
2681         /* RX, TX */
2682         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
2683 };
2684 static const unsigned int scif0_data_d_mux[] = {
2685         RX0_D_MARK, TX0_D_MARK,
2686 };
2687 static const unsigned int scif0_data_e_pins[] = {
2688         /* RX, TX */
2689         RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
2690 };
2691 static const unsigned int scif0_data_e_mux[] = {
2692         RX0_E_MARK, TX0_E_MARK,
2693 };
2694 /* - SCIF1 ------------------------------------------------------------------ */
2695 static const unsigned int scif1_data_pins[] = {
2696         /* RX, TX */
2697         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2698 };
2699 static const unsigned int scif1_data_mux[] = {
2700         RX1_MARK, TX1_MARK,
2701 };
2702 static const unsigned int scif1_data_b_pins[] = {
2703         /* RX, TX */
2704         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2705 };
2706 static const unsigned int scif1_data_b_mux[] = {
2707         RX1_B_MARK, TX1_B_MARK,
2708 };
2709 static const unsigned int scif1_clk_b_pins[] = {
2710         /* SCK */
2711         RCAR_GP_PIN(3, 10),
2712 };
2713 static const unsigned int scif1_clk_b_mux[] = {
2714         SCIF1_SCK_B_MARK,
2715 };
2716 static const unsigned int scif1_data_c_pins[] = {
2717         /* RX, TX */
2718         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
2719 };
2720 static const unsigned int scif1_data_c_mux[] = {
2721         RX1_C_MARK, TX1_C_MARK,
2722 };
2723 static const unsigned int scif1_data_d_pins[] = {
2724         /* RX, TX */
2725         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
2726 };
2727 static const unsigned int scif1_data_d_mux[] = {
2728         RX1_D_MARK, TX1_D_MARK,
2729 };
2730 /* - SCIF2 ------------------------------------------------------------------ */
2731 static const unsigned int scif2_data_pins[] = {
2732         /* RX, TX */
2733         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
2734 };
2735 static const unsigned int scif2_data_mux[] = {
2736         RX2_MARK, TX2_MARK,
2737 };
2738 static const unsigned int scif2_data_b_pins[] = {
2739         /* RX, TX */
2740         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2741 };
2742 static const unsigned int scif2_data_b_mux[] = {
2743         RX2_B_MARK, TX2_B_MARK,
2744 };
2745 static const unsigned int scif2_clk_b_pins[] = {
2746         /* SCK */
2747         RCAR_GP_PIN(3, 18),
2748 };
2749 static const unsigned int scif2_clk_b_mux[] = {
2750         SCIF2_SCK_B_MARK,
2751 };
2752 static const unsigned int scif2_data_c_pins[] = {
2753         /* RX, TX */
2754         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2755 };
2756 static const unsigned int scif2_data_c_mux[] = {
2757         RX2_C_MARK, TX2_C_MARK,
2758 };
2759 static const unsigned int scif2_data_e_pins[] = {
2760         /* RX, TX */
2761         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2762 };
2763 static const unsigned int scif2_data_e_mux[] = {
2764         RX2_E_MARK, TX2_E_MARK,
2765 };
2766 /* - SCIF3 ------------------------------------------------------------------ */
2767 static const unsigned int scif3_data_pins[] = {
2768         /* RX, TX */
2769         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2770 };
2771 static const unsigned int scif3_data_mux[] = {
2772         RX3_MARK, TX3_MARK,
2773 };
2774 static const unsigned int scif3_clk_pins[] = {
2775         /* SCK */
2776         RCAR_GP_PIN(3, 23),
2777 };
2778 static const unsigned int scif3_clk_mux[] = {
2779         SCIF3_SCK_MARK,
2780 };
2781 static const unsigned int scif3_data_b_pins[] = {
2782         /* RX, TX */
2783         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
2784 };
2785 static const unsigned int scif3_data_b_mux[] = {
2786         RX3_B_MARK, TX3_B_MARK,
2787 };
2788 static const unsigned int scif3_clk_b_pins[] = {
2789         /* SCK */
2790         RCAR_GP_PIN(4, 8),
2791 };
2792 static const unsigned int scif3_clk_b_mux[] = {
2793         SCIF3_SCK_B_MARK,
2794 };
2795 static const unsigned int scif3_data_c_pins[] = {
2796         /* RX, TX */
2797         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2798 };
2799 static const unsigned int scif3_data_c_mux[] = {
2800         RX3_C_MARK, TX3_C_MARK,
2801 };
2802 static const unsigned int scif3_data_d_pins[] = {
2803         /* RX, TX */
2804         RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
2805 };
2806 static const unsigned int scif3_data_d_mux[] = {
2807         RX3_D_MARK, TX3_D_MARK,
2808 };
2809 /* - SCIF4 ------------------------------------------------------------------ */
2810 static const unsigned int scif4_data_pins[] = {
2811         /* RX, TX */
2812         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
2813 };
2814 static const unsigned int scif4_data_mux[] = {
2815         RX4_MARK, TX4_MARK,
2816 };
2817 static const unsigned int scif4_data_b_pins[] = {
2818         /* RX, TX */
2819         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
2820 };
2821 static const unsigned int scif4_data_b_mux[] = {
2822         RX4_B_MARK, TX4_B_MARK,
2823 };
2824 static const unsigned int scif4_data_c_pins[] = {
2825         /* RX, TX */
2826         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
2827 };
2828 static const unsigned int scif4_data_c_mux[] = {
2829         RX4_C_MARK, TX4_C_MARK,
2830 };
2831 /* - SCIF5 ------------------------------------------------------------------ */
2832 static const unsigned int scif5_data_pins[] = {
2833         /* RX, TX */
2834         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
2835 };
2836 static const unsigned int scif5_data_mux[] = {
2837         RX5_MARK, TX5_MARK,
2838 };
2839 static const unsigned int scif5_data_b_pins[] = {
2840         /* RX, TX */
2841         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
2842 };
2843 static const unsigned int scif5_data_b_mux[] = {
2844         RX5_B_MARK, TX5_B_MARK,
2845 };
2846 /* - SCIFA0 ----------------------------------------------------------------- */
2847 static const unsigned int scifa0_data_pins[] = {
2848         /* RXD, TXD */
2849         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2850 };
2851 static const unsigned int scifa0_data_mux[] = {
2852         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2853 };
2854 static const unsigned int scifa0_data_b_pins[] = {
2855         /* RXD, TXD */
2856         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2857 };
2858 static const unsigned int scifa0_data_b_mux[] = {
2859         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2860 };
2861 /* - SCIFA1 ----------------------------------------------------------------- */
2862 static const unsigned int scifa1_data_pins[] = {
2863         /* RXD, TXD */
2864         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2865 };
2866 static const unsigned int scifa1_data_mux[] = {
2867         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2868 };
2869 static const unsigned int scifa1_clk_pins[] = {
2870         /* SCK */
2871         RCAR_GP_PIN(3, 10),
2872 };
2873 static const unsigned int scifa1_clk_mux[] = {
2874         SCIFA1_SCK_MARK,
2875 };
2876 static const unsigned int scifa1_data_b_pins[] = {
2877         /* RXD, TXD */
2878         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2879 };
2880 static const unsigned int scifa1_data_b_mux[] = {
2881         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2882 };
2883 static const unsigned int scifa1_clk_b_pins[] = {
2884         /* SCK */
2885         RCAR_GP_PIN(1, 0),
2886 };
2887 static const unsigned int scifa1_clk_b_mux[] = {
2888         SCIFA1_SCK_B_MARK,
2889 };
2890 static const unsigned int scifa1_data_c_pins[] = {
2891         /* RXD, TXD */
2892         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2893 };
2894 static const unsigned int scifa1_data_c_mux[] = {
2895         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2896 };
2897 /* - SCIFA2 ----------------------------------------------------------------- */
2898 static const unsigned int scifa2_data_pins[] = {
2899         /* RXD, TXD */
2900         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
2901 };
2902 static const unsigned int scifa2_data_mux[] = {
2903         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2904 };
2905 static const unsigned int scifa2_clk_pins[] = {
2906         /* SCK */
2907         RCAR_GP_PIN(3, 18),
2908 };
2909 static const unsigned int scifa2_clk_mux[] = {
2910         SCIFA2_SCK_MARK,
2911 };
2912 static const unsigned int scifa2_data_b_pins[] = {
2913         /* RXD, TXD */
2914         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2915 };
2916 static const unsigned int scifa2_data_b_mux[] = {
2917         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2918 };
2919 /* - SCIFA3 ----------------------------------------------------------------- */
2920 static const unsigned int scifa3_data_pins[] = {
2921         /* RXD, TXD */
2922         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2923 };
2924 static const unsigned int scifa3_data_mux[] = {
2925         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2926 };
2927 static const unsigned int scifa3_clk_pins[] = {
2928         /* SCK */
2929         RCAR_GP_PIN(3, 23),
2930 };
2931 static const unsigned int scifa3_clk_mux[] = {
2932         SCIFA3_SCK_MARK,
2933 };
2934 static const unsigned int scifa3_data_b_pins[] = {
2935         /* RXD, TXD */
2936         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
2937 };
2938 static const unsigned int scifa3_data_b_mux[] = {
2939         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
2940 };
2941 static const unsigned int scifa3_clk_b_pins[] = {
2942         /* SCK */
2943         RCAR_GP_PIN(4, 8),
2944 };
2945 static const unsigned int scifa3_clk_b_mux[] = {
2946         SCIFA3_SCK_B_MARK,
2947 };
2948 static const unsigned int scifa3_data_c_pins[] = {
2949         /* RXD, TXD */
2950         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
2951 };
2952 static const unsigned int scifa3_data_c_mux[] = {
2953         SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
2954 };
2955 static const unsigned int scifa3_clk_c_pins[] = {
2956         /* SCK */
2957         RCAR_GP_PIN(7, 22),
2958 };
2959 static const unsigned int scifa3_clk_c_mux[] = {
2960         SCIFA3_SCK_C_MARK,
2961 };
2962 /* - SCIFA4 ----------------------------------------------------------------- */
2963 static const unsigned int scifa4_data_pins[] = {
2964         /* RXD, TXD */
2965         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
2966 };
2967 static const unsigned int scifa4_data_mux[] = {
2968         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2969 };
2970 static const unsigned int scifa4_data_b_pins[] = {
2971         /* RXD, TXD */
2972         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
2973 };
2974 static const unsigned int scifa4_data_b_mux[] = {
2975         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
2976 };
2977 static const unsigned int scifa4_data_c_pins[] = {
2978         /* RXD, TXD */
2979         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
2980 };
2981 static const unsigned int scifa4_data_c_mux[] = {
2982         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
2983 };
2984 /* - SCIFA5 ----------------------------------------------------------------- */
2985 static const unsigned int scifa5_data_pins[] = {
2986         /* RXD, TXD */
2987         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
2988 };
2989 static const unsigned int scifa5_data_mux[] = {
2990         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
2991 };
2992 static const unsigned int scifa5_data_b_pins[] = {
2993         /* RXD, TXD */
2994         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2995 };
2996 static const unsigned int scifa5_data_b_mux[] = {
2997         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
2998 };
2999 static const unsigned int scifa5_data_c_pins[] = {
3000         /* RXD, TXD */
3001         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3002 };
3003 static const unsigned int scifa5_data_c_mux[] = {
3004         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3005 };
3006 /* - SCIFB0 ----------------------------------------------------------------- */
3007 static const unsigned int scifb0_data_pins[] = {
3008         /* RXD, TXD */
3009         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
3010 };
3011 static const unsigned int scifb0_data_mux[] = {
3012         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3013 };
3014 static const unsigned int scifb0_clk_pins[] = {
3015         /* SCK */
3016         RCAR_GP_PIN(7, 2),
3017 };
3018 static const unsigned int scifb0_clk_mux[] = {
3019         SCIFB0_SCK_MARK,
3020 };
3021 static const unsigned int scifb0_ctrl_pins[] = {
3022         /* RTS, CTS */
3023         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3024 };
3025 static const unsigned int scifb0_ctrl_mux[] = {
3026         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3027 };
3028 static const unsigned int scifb0_data_b_pins[] = {
3029         /* RXD, TXD */
3030         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
3031 };
3032 static const unsigned int scifb0_data_b_mux[] = {
3033         SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3034 };
3035 static const unsigned int scifb0_clk_b_pins[] = {
3036         /* SCK */
3037         RCAR_GP_PIN(5, 31),
3038 };
3039 static const unsigned int scifb0_clk_b_mux[] = {
3040         SCIFB0_SCK_B_MARK,
3041 };
3042 static const unsigned int scifb0_ctrl_b_pins[] = {
3043         /* RTS, CTS */
3044         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
3045 };
3046 static const unsigned int scifb0_ctrl_b_mux[] = {
3047         SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3048 };
3049 static const unsigned int scifb0_data_c_pins[] = {
3050         /* RXD, TXD */
3051         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3052 };
3053 static const unsigned int scifb0_data_c_mux[] = {
3054         SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3055 };
3056 static const unsigned int scifb0_clk_c_pins[] = {
3057         /* SCK */
3058         RCAR_GP_PIN(2, 30),
3059 };
3060 static const unsigned int scifb0_clk_c_mux[] = {
3061         SCIFB0_SCK_C_MARK,
3062 };
3063 static const unsigned int scifb0_data_d_pins[] = {
3064         /* RXD, TXD */
3065         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3066 };
3067 static const unsigned int scifb0_data_d_mux[] = {
3068         SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3069 };
3070 static const unsigned int scifb0_clk_d_pins[] = {
3071         /* SCK */
3072         RCAR_GP_PIN(4, 17),
3073 };
3074 static const unsigned int scifb0_clk_d_mux[] = {
3075         SCIFB0_SCK_D_MARK,
3076 };
3077 /* - SCIFB1 ----------------------------------------------------------------- */
3078 static const unsigned int scifb1_data_pins[] = {
3079         /* RXD, TXD */
3080         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3081 };
3082 static const unsigned int scifb1_data_mux[] = {
3083         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3084 };
3085 static const unsigned int scifb1_clk_pins[] = {
3086         /* SCK */
3087         RCAR_GP_PIN(7, 7),
3088 };
3089 static const unsigned int scifb1_clk_mux[] = {
3090         SCIFB1_SCK_MARK,
3091 };
3092 static const unsigned int scifb1_ctrl_pins[] = {
3093         /* RTS, CTS */
3094         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3095 };
3096 static const unsigned int scifb1_ctrl_mux[] = {
3097         SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3098 };
3099 static const unsigned int scifb1_data_b_pins[] = {
3100         /* RXD, TXD */
3101         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3102 };
3103 static const unsigned int scifb1_data_b_mux[] = {
3104         SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3105 };
3106 static const unsigned int scifb1_clk_b_pins[] = {
3107         /* SCK */
3108         RCAR_GP_PIN(1, 3),
3109 };
3110 static const unsigned int scifb1_clk_b_mux[] = {
3111         SCIFB1_SCK_B_MARK,
3112 };
3113 static const unsigned int scifb1_data_c_pins[] = {
3114         /* RXD, TXD */
3115         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3116 };
3117 static const unsigned int scifb1_data_c_mux[] = {
3118         SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3119 };
3120 static const unsigned int scifb1_clk_c_pins[] = {
3121         /* SCK */
3122         RCAR_GP_PIN(7, 11),
3123 };
3124 static const unsigned int scifb1_clk_c_mux[] = {
3125         SCIFB1_SCK_C_MARK,
3126 };
3127 static const unsigned int scifb1_data_d_pins[] = {
3128         /* RXD, TXD */
3129         RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3130 };
3131 static const unsigned int scifb1_data_d_mux[] = {
3132         SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3133 };
3134 /* - SCIFB2 ----------------------------------------------------------------- */
3135 static const unsigned int scifb2_data_pins[] = {
3136         /* RXD, TXD */
3137         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3138 };
3139 static const unsigned int scifb2_data_mux[] = {
3140         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3141 };
3142 static const unsigned int scifb2_clk_pins[] = {
3143         /* SCK */
3144         RCAR_GP_PIN(4, 15),
3145 };
3146 static const unsigned int scifb2_clk_mux[] = {
3147         SCIFB2_SCK_MARK,
3148 };
3149 static const unsigned int scifb2_ctrl_pins[] = {
3150         /* RTS, CTS */
3151         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3152 };
3153 static const unsigned int scifb2_ctrl_mux[] = {
3154         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3155 };
3156 static const unsigned int scifb2_data_b_pins[] = {
3157         /* RXD, TXD */
3158         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3159 };
3160 static const unsigned int scifb2_data_b_mux[] = {
3161         SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3162 };
3163 static const unsigned int scifb2_clk_b_pins[] = {
3164         /* SCK */
3165         RCAR_GP_PIN(5, 31),
3166 };
3167 static const unsigned int scifb2_clk_b_mux[] = {
3168         SCIFB2_SCK_B_MARK,
3169 };
3170 static const unsigned int scifb2_ctrl_b_pins[] = {
3171         /* RTS, CTS */
3172         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3173 };
3174 static const unsigned int scifb2_ctrl_b_mux[] = {
3175         SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3176 };
3177 static const unsigned int scifb2_data_c_pins[] = {
3178         /* RXD, TXD */
3179         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3180 };
3181 static const unsigned int scifb2_data_c_mux[] = {
3182         SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3183 };
3184 static const unsigned int scifb2_clk_c_pins[] = {
3185         /* SCK */
3186         RCAR_GP_PIN(5, 27),
3187 };
3188 static const unsigned int scifb2_clk_c_mux[] = {
3189         SCIFB2_SCK_C_MARK,
3190 };
3191 static const unsigned int scifb2_data_d_pins[] = {
3192         /* RXD, TXD */
3193         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3194 };
3195 static const unsigned int scifb2_data_d_mux[] = {
3196         SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3197 };
3198 /* - SDHI0 ------------------------------------------------------------------ */
3199 static const unsigned int sdhi0_data1_pins[] = {
3200         /* D0 */
3201         RCAR_GP_PIN(6, 2),
3202 };
3203 static const unsigned int sdhi0_data1_mux[] = {
3204         SD0_DATA0_MARK,
3205 };
3206 static const unsigned int sdhi0_data4_pins[] = {
3207         /* D[0:3] */
3208         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3209         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3210 };
3211 static const unsigned int sdhi0_data4_mux[] = {
3212         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3213 };
3214 static const unsigned int sdhi0_ctrl_pins[] = {
3215         /* CLK, CMD */
3216         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3217 };
3218 static const unsigned int sdhi0_ctrl_mux[] = {
3219         SD0_CLK_MARK, SD0_CMD_MARK,
3220 };
3221 static const unsigned int sdhi0_cd_pins[] = {
3222         /* CD */
3223         RCAR_GP_PIN(6, 6),
3224 };
3225 static const unsigned int sdhi0_cd_mux[] = {
3226         SD0_CD_MARK,
3227 };
3228 static const unsigned int sdhi0_wp_pins[] = {
3229         /* WP */
3230         RCAR_GP_PIN(6, 7),
3231 };
3232 static const unsigned int sdhi0_wp_mux[] = {
3233         SD0_WP_MARK,
3234 };
3235 /* - SDHI1 ------------------------------------------------------------------ */
3236 static const unsigned int sdhi1_data1_pins[] = {
3237         /* D0 */
3238         RCAR_GP_PIN(6, 10),
3239 };
3240 static const unsigned int sdhi1_data1_mux[] = {
3241         SD1_DATA0_MARK,
3242 };
3243 static const unsigned int sdhi1_data4_pins[] = {
3244         /* D[0:3] */
3245         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3246         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3247 };
3248 static const unsigned int sdhi1_data4_mux[] = {
3249         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3250 };
3251 static const unsigned int sdhi1_ctrl_pins[] = {
3252         /* CLK, CMD */
3253         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3254 };
3255 static const unsigned int sdhi1_ctrl_mux[] = {
3256         SD1_CLK_MARK, SD1_CMD_MARK,
3257 };
3258 static const unsigned int sdhi1_cd_pins[] = {
3259         /* CD */
3260         RCAR_GP_PIN(6, 14),
3261 };
3262 static const unsigned int sdhi1_cd_mux[] = {
3263         SD1_CD_MARK,
3264 };
3265 static const unsigned int sdhi1_wp_pins[] = {
3266         /* WP */
3267         RCAR_GP_PIN(6, 15),
3268 };
3269 static const unsigned int sdhi1_wp_mux[] = {
3270         SD1_WP_MARK,
3271 };
3272 /* - SDHI2 ------------------------------------------------------------------ */
3273 static const unsigned int sdhi2_data1_pins[] = {
3274         /* D0 */
3275         RCAR_GP_PIN(6, 18),
3276 };
3277 static const unsigned int sdhi2_data1_mux[] = {
3278         SD2_DATA0_MARK,
3279 };
3280 static const unsigned int sdhi2_data4_pins[] = {
3281         /* D[0:3] */
3282         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3283         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3284 };
3285 static const unsigned int sdhi2_data4_mux[] = {
3286         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3287 };
3288 static const unsigned int sdhi2_ctrl_pins[] = {
3289         /* CLK, CMD */
3290         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3291 };
3292 static const unsigned int sdhi2_ctrl_mux[] = {
3293         SD2_CLK_MARK, SD2_CMD_MARK,
3294 };
3295 static const unsigned int sdhi2_cd_pins[] = {
3296         /* CD */
3297         RCAR_GP_PIN(6, 22),
3298 };
3299 static const unsigned int sdhi2_cd_mux[] = {
3300         SD2_CD_MARK,
3301 };
3302 static const unsigned int sdhi2_wp_pins[] = {
3303         /* WP */
3304         RCAR_GP_PIN(6, 23),
3305 };
3306 static const unsigned int sdhi2_wp_mux[] = {
3307         SD2_WP_MARK,
3308 };
3309
3310 /* - SSI -------------------------------------------------------------------- */
3311 static const unsigned int ssi0_data_pins[] = {
3312         /* SDATA */
3313         RCAR_GP_PIN(2, 2),
3314 };
3315
3316 static const unsigned int ssi0_data_mux[] = {
3317         SSI_SDATA0_MARK,
3318 };
3319
3320 static const unsigned int ssi0_data_b_pins[] = {
3321         /* SDATA */
3322         RCAR_GP_PIN(3, 4),
3323 };
3324
3325 static const unsigned int ssi0_data_b_mux[] = {
3326         SSI_SDATA0_B_MARK,
3327 };
3328
3329 static const unsigned int ssi0129_ctrl_pins[] = {
3330         /* SCK, WS */
3331         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3332 };
3333
3334 static const unsigned int ssi0129_ctrl_mux[] = {
3335         SSI_SCK0129_MARK, SSI_WS0129_MARK,
3336 };
3337
3338 static const unsigned int ssi0129_ctrl_b_pins[] = {
3339         /* SCK, WS */
3340         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3341 };
3342
3343 static const unsigned int ssi0129_ctrl_b_mux[] = {
3344         SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
3345 };
3346
3347 static const unsigned int ssi1_data_pins[] = {
3348         /* SDATA */
3349         RCAR_GP_PIN(2, 5),
3350 };
3351
3352 static const unsigned int ssi1_data_mux[] = {
3353         SSI_SDATA1_MARK,
3354 };
3355
3356 static const unsigned int ssi1_data_b_pins[] = {
3357         /* SDATA */
3358         RCAR_GP_PIN(3, 7),
3359 };
3360
3361 static const unsigned int ssi1_data_b_mux[] = {
3362         SSI_SDATA1_B_MARK,
3363 };
3364
3365 static const unsigned int ssi1_ctrl_pins[] = {
3366         /* SCK, WS */
3367         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3368 };
3369
3370 static const unsigned int ssi1_ctrl_mux[] = {
3371         SSI_SCK1_MARK, SSI_WS1_MARK,
3372 };
3373
3374 static const unsigned int ssi1_ctrl_b_pins[] = {
3375         /* SCK, WS */
3376         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3377 };
3378
3379 static const unsigned int ssi1_ctrl_b_mux[] = {
3380         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3381 };
3382
3383 static const unsigned int ssi2_data_pins[] = {
3384         /* SDATA */
3385         RCAR_GP_PIN(2, 8),
3386 };
3387
3388 static const unsigned int ssi2_data_mux[] = {
3389         SSI_SDATA2_MARK,
3390 };
3391
3392 static const unsigned int ssi2_ctrl_pins[] = {
3393         /* SCK, WS */
3394         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3395 };
3396
3397 static const unsigned int ssi2_ctrl_mux[] = {
3398         SSI_SCK2_MARK, SSI_WS2_MARK,
3399 };
3400
3401 static const unsigned int ssi3_data_pins[] = {
3402         /* SDATA */
3403         RCAR_GP_PIN(2, 11),
3404 };
3405
3406 static const unsigned int ssi3_data_mux[] = {
3407         SSI_SDATA3_MARK,
3408 };
3409
3410 static const unsigned int ssi34_ctrl_pins[] = {
3411         /* SCK, WS */
3412         RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
3413 };
3414
3415 static const unsigned int ssi34_ctrl_mux[] = {
3416         SSI_SCK34_MARK, SSI_WS34_MARK,
3417 };
3418
3419 static const unsigned int ssi4_data_pins[] = {
3420         /* SDATA */
3421         RCAR_GP_PIN(2, 14),
3422 };
3423
3424 static const unsigned int ssi4_data_mux[] = {
3425         SSI_SDATA4_MARK,
3426 };
3427
3428 static const unsigned int ssi4_ctrl_pins[] = {
3429         /* SCK, WS */
3430         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3431 };
3432
3433 static const unsigned int ssi4_ctrl_mux[] = {
3434         SSI_SCK4_MARK, SSI_WS4_MARK,
3435 };
3436
3437 static const unsigned int ssi5_data_pins[] = {
3438         /* SDATA */
3439         RCAR_GP_PIN(2, 17),
3440 };
3441
3442 static const unsigned int ssi5_data_mux[] = {
3443         SSI_SDATA5_MARK,
3444 };
3445
3446 static const unsigned int ssi5_ctrl_pins[] = {
3447         /* SCK, WS */
3448         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3449 };
3450
3451 static const unsigned int ssi5_ctrl_mux[] = {
3452         SSI_SCK5_MARK, SSI_WS5_MARK,
3453 };
3454
3455 static const unsigned int ssi6_data_pins[] = {
3456         /* SDATA */
3457         RCAR_GP_PIN(2, 20),
3458 };
3459
3460 static const unsigned int ssi6_data_mux[] = {
3461         SSI_SDATA6_MARK,
3462 };
3463
3464 static const unsigned int ssi6_ctrl_pins[] = {
3465         /* SCK, WS */
3466         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
3467 };
3468
3469 static const unsigned int ssi6_ctrl_mux[] = {
3470         SSI_SCK6_MARK, SSI_WS6_MARK,
3471 };
3472
3473 static const unsigned int ssi7_data_pins[] = {
3474         /* SDATA */
3475         RCAR_GP_PIN(2, 23),
3476 };
3477
3478 static const unsigned int ssi7_data_mux[] = {
3479         SSI_SDATA7_MARK,
3480 };
3481
3482 static const unsigned int ssi7_data_b_pins[] = {
3483         /* SDATA */
3484         RCAR_GP_PIN(3, 12),
3485 };
3486
3487 static const unsigned int ssi7_data_b_mux[] = {
3488         SSI_SDATA7_B_MARK,
3489 };
3490
3491 static const unsigned int ssi78_ctrl_pins[] = {
3492         /* SCK, WS */
3493         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3494 };
3495
3496 static const unsigned int ssi78_ctrl_mux[] = {
3497         SSI_SCK78_MARK, SSI_WS78_MARK,
3498 };
3499
3500 static const unsigned int ssi78_ctrl_b_pins[] = {
3501         /* SCK, WS */
3502         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3503 };
3504
3505 static const unsigned int ssi78_ctrl_b_mux[] = {
3506         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3507 };
3508
3509 static const unsigned int ssi8_data_pins[] = {
3510         /* SDATA */
3511         RCAR_GP_PIN(2, 24),
3512 };
3513
3514 static const unsigned int ssi8_data_mux[] = {
3515         SSI_SDATA8_MARK,
3516 };
3517
3518 static const unsigned int ssi8_data_b_pins[] = {
3519         /* SDATA */
3520         RCAR_GP_PIN(3, 13),
3521 };
3522
3523 static const unsigned int ssi8_data_b_mux[] = {
3524         SSI_SDATA8_B_MARK,
3525 };
3526
3527 static const unsigned int ssi9_data_pins[] = {
3528         /* SDATA */
3529         RCAR_GP_PIN(2, 27),
3530 };
3531
3532 static const unsigned int ssi9_data_mux[] = {
3533         SSI_SDATA9_MARK,
3534 };
3535
3536 static const unsigned int ssi9_data_b_pins[] = {
3537         /* SDATA */
3538         RCAR_GP_PIN(3, 18),
3539 };
3540
3541 static const unsigned int ssi9_data_b_mux[] = {
3542         SSI_SDATA9_B_MARK,
3543 };
3544
3545 static const unsigned int ssi9_ctrl_pins[] = {
3546         /* SCK, WS */
3547         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
3548 };
3549
3550 static const unsigned int ssi9_ctrl_mux[] = {
3551         SSI_SCK9_MARK, SSI_WS9_MARK,
3552 };
3553
3554 static const unsigned int ssi9_ctrl_b_pins[] = {
3555         /* SCK, WS */
3556         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
3557 };
3558
3559 static const unsigned int ssi9_ctrl_b_mux[] = {
3560         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3561 };
3562
3563 /* - USB0 ------------------------------------------------------------------- */
3564 static const unsigned int usb0_pins[] = {
3565         RCAR_GP_PIN(7, 23), /* PWEN */
3566         RCAR_GP_PIN(7, 24), /* OVC */
3567 };
3568 static const unsigned int usb0_mux[] = {
3569         USB0_PWEN_MARK,
3570         USB0_OVC_MARK,
3571 };
3572 /* - USB1 ------------------------------------------------------------------- */
3573 static const unsigned int usb1_pins[] = {
3574         RCAR_GP_PIN(7, 25), /* PWEN */
3575         RCAR_GP_PIN(6, 30), /* OVC */
3576 };
3577 static const unsigned int usb1_mux[] = {
3578         USB1_PWEN_MARK,
3579         USB1_OVC_MARK,
3580 };
3581
3582 union vin_data {
3583         unsigned int data24[24];
3584         unsigned int data20[20];
3585         unsigned int data16[16];
3586         unsigned int data12[12];
3587         unsigned int data10[10];
3588         unsigned int data8[8];
3589 };
3590
3591 #define VIN_DATA_PIN_GROUP(n, s)                                \
3592         {                                                       \
3593                 .name = #n#s,                                   \
3594                 .pins = n##_pins.data##s,                       \
3595                 .mux = n##_mux.data##s,                         \
3596                 .nr_pins = ARRAY_SIZE(n##_pins.data##s),        \
3597         }
3598
3599 /* - VIN0 ------------------------------------------------------------------- */
3600 static const union vin_data vin0_data_pins = {
3601         .data24 = {
3602                 /* B */
3603                 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
3604                 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3605                 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3606                 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3607                 /* G */
3608                 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3609                 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3610                 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3611                 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
3612                 /* R */
3613                 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
3614                 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
3615                 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
3616                 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3617         },
3618 };
3619 static const union vin_data vin0_data_mux = {
3620         .data24 = {
3621                 /* B */
3622                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3623                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3624                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3625                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3626                 /* G */
3627                 VI0_G0_MARK, VI0_G1_MARK,
3628                 VI0_G2_MARK, VI0_G3_MARK,
3629                 VI0_G4_MARK, VI0_G5_MARK,
3630                 VI0_G6_MARK, VI0_G7_MARK,
3631                 /* R */
3632                 VI0_R0_MARK, VI0_R1_MARK,
3633                 VI0_R2_MARK, VI0_R3_MARK,
3634                 VI0_R4_MARK, VI0_R5_MARK,
3635                 VI0_R6_MARK, VI0_R7_MARK,
3636         },
3637 };
3638 static const unsigned int vin0_data18_pins[] = {
3639         /* B */
3640         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3641         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3642         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3643         /* G */
3644         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3645         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3646         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
3647         /* R */
3648         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
3649         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
3650         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3651 };
3652 static const unsigned int vin0_data18_mux[] = {
3653         /* B */
3654         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3655         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3656         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3657         /* G */
3658         VI0_G2_MARK, VI0_G3_MARK,
3659         VI0_G4_MARK, VI0_G5_MARK,
3660         VI0_G6_MARK, VI0_G7_MARK,
3661         /* R */
3662         VI0_R2_MARK, VI0_R3_MARK,
3663         VI0_R4_MARK, VI0_R5_MARK,
3664         VI0_R6_MARK, VI0_R7_MARK,
3665 };
3666 static const unsigned int vin0_sync_pins[] = {
3667         RCAR_GP_PIN(4, 3), /* HSYNC */
3668         RCAR_GP_PIN(4, 4), /* VSYNC */
3669 };
3670 static const unsigned int vin0_sync_mux[] = {
3671         VI0_HSYNC_N_MARK,
3672         VI0_VSYNC_N_MARK,
3673 };
3674 static const unsigned int vin0_field_pins[] = {
3675         RCAR_GP_PIN(4, 2),
3676 };
3677 static const unsigned int vin0_field_mux[] = {
3678         VI0_FIELD_MARK,
3679 };
3680 static const unsigned int vin0_clkenb_pins[] = {
3681         RCAR_GP_PIN(4, 1),
3682 };
3683 static const unsigned int vin0_clkenb_mux[] = {
3684         VI0_CLKENB_MARK,
3685 };
3686 static const unsigned int vin0_clk_pins[] = {
3687         RCAR_GP_PIN(4, 0),
3688 };
3689 static const unsigned int vin0_clk_mux[] = {
3690         VI0_CLK_MARK,
3691 };
3692 /* - VIN1 ----------------------------------------------------------------- */
3693 static const unsigned int vin1_data8_pins[] = {
3694         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3695         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
3696         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
3697         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
3698 };
3699 static const unsigned int vin1_data8_mux[] = {
3700         VI1_DATA0_MARK, VI1_DATA1_MARK,
3701         VI1_DATA2_MARK, VI1_DATA3_MARK,
3702         VI1_DATA4_MARK, VI1_DATA5_MARK,
3703         VI1_DATA6_MARK, VI1_DATA7_MARK,
3704 };
3705 static const unsigned int vin1_sync_pins[] = {
3706         RCAR_GP_PIN(5, 0), /* HSYNC */
3707         RCAR_GP_PIN(5, 1), /* VSYNC */
3708 };
3709 static const unsigned int vin1_sync_mux[] = {
3710         VI1_HSYNC_N_MARK,
3711         VI1_VSYNC_N_MARK,
3712 };
3713 static const unsigned int vin1_field_pins[] = {
3714         RCAR_GP_PIN(5, 3),
3715 };
3716 static const unsigned int vin1_field_mux[] = {
3717         VI1_FIELD_MARK,
3718 };
3719 static const unsigned int vin1_clkenb_pins[] = {
3720         RCAR_GP_PIN(5, 2),
3721 };
3722 static const unsigned int vin1_clkenb_mux[] = {
3723         VI1_CLKENB_MARK,
3724 };
3725 static const unsigned int vin1_clk_pins[] = {
3726         RCAR_GP_PIN(5, 4),
3727 };
3728 static const unsigned int vin1_clk_mux[] = {
3729         VI1_CLK_MARK,
3730 };
3731 static const union vin_data vin1_b_data_pins = {
3732         .data24 = {
3733                 /* B */
3734                 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3735                 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3736                 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3737                 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3738                 /* G */
3739                 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3740                 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3741                 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3742                 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
3743                 /* R */
3744                 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3745                 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3746                 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
3747                 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
3748         },
3749 };
3750 static const union vin_data vin1_b_data_mux = {
3751         .data24 = {
3752                 /* B */
3753                 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
3754                 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
3755                 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
3756                 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
3757                 /* G */
3758                 VI1_G0_B_MARK, VI1_G1_B_MARK,
3759                 VI1_G2_B_MARK, VI1_G3_B_MARK,
3760                 VI1_G4_B_MARK, VI1_G5_B_MARK,
3761                 VI1_G6_B_MARK, VI1_G7_B_MARK,
3762                 /* R */
3763                 VI1_R0_B_MARK, VI1_R1_B_MARK,
3764                 VI1_R2_B_MARK, VI1_R3_B_MARK,
3765                 VI1_R4_B_MARK, VI1_R5_B_MARK,
3766                 VI1_R6_B_MARK, VI1_R7_B_MARK,
3767         },
3768 };
3769 static const unsigned int vin1_b_data18_pins[] = {
3770         /* B */
3771         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3772         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3773         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3774         /* G */
3775         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3776         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3777         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
3778         /* R */
3779         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3780         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
3781         RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
3782 };
3783 static const unsigned int vin1_b_data18_mux[] = {
3784         /* B */
3785         VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
3786         VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
3787         VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
3788         VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
3789         /* G */
3790         VI1_G0_B_MARK, VI1_G1_B_MARK,
3791         VI1_G2_B_MARK, VI1_G3_B_MARK,
3792         VI1_G4_B_MARK, VI1_G5_B_MARK,
3793         VI1_G6_B_MARK, VI1_G7_B_MARK,
3794         /* R */
3795         VI1_R0_B_MARK, VI1_R1_B_MARK,
3796         VI1_R2_B_MARK, VI1_R3_B_MARK,
3797         VI1_R4_B_MARK, VI1_R5_B_MARK,
3798         VI1_R6_B_MARK, VI1_R7_B_MARK,
3799 };
3800 static const unsigned int vin1_b_sync_pins[] = {
3801         RCAR_GP_PIN(3, 17), /* HSYNC */
3802         RCAR_GP_PIN(3, 18), /* VSYNC */
3803 };
3804 static const unsigned int vin1_b_sync_mux[] = {
3805         VI1_HSYNC_N_B_MARK,
3806         VI1_VSYNC_N_B_MARK,
3807 };
3808 static const unsigned int vin1_b_field_pins[] = {
3809         RCAR_GP_PIN(3, 20),
3810 };
3811 static const unsigned int vin1_b_field_mux[] = {
3812         VI1_FIELD_B_MARK,
3813 };
3814 static const unsigned int vin1_b_clkenb_pins[] = {
3815         RCAR_GP_PIN(3, 19),
3816 };
3817 static const unsigned int vin1_b_clkenb_mux[] = {
3818         VI1_CLKENB_B_MARK,
3819 };
3820 static const unsigned int vin1_b_clk_pins[] = {
3821         RCAR_GP_PIN(3, 16),
3822 };
3823 static const unsigned int vin1_b_clk_mux[] = {
3824         VI1_CLK_B_MARK,
3825 };
3826 /* - VIN2 ----------------------------------------------------------------- */
3827 static const unsigned int vin2_data8_pins[] = {
3828         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3829         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3830         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
3831         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
3832 };
3833 static const unsigned int vin2_data8_mux[] = {
3834         VI2_DATA0_MARK, VI2_DATA1_MARK,
3835         VI2_DATA2_MARK, VI2_DATA3_MARK,
3836         VI2_DATA4_MARK, VI2_DATA5_MARK,
3837         VI2_DATA6_MARK, VI2_DATA7_MARK,
3838 };
3839 static const unsigned int vin2_sync_pins[] = {
3840         RCAR_GP_PIN(4, 15), /* HSYNC */
3841         RCAR_GP_PIN(4, 16), /* VSYNC */
3842 };
3843 static const unsigned int vin2_sync_mux[] = {
3844         VI2_HSYNC_N_MARK,
3845         VI2_VSYNC_N_MARK,
3846 };
3847 static const unsigned int vin2_field_pins[] = {
3848         RCAR_GP_PIN(4, 18),
3849 };
3850 static const unsigned int vin2_field_mux[] = {
3851         VI2_FIELD_MARK,
3852 };
3853 static const unsigned int vin2_clkenb_pins[] = {
3854         RCAR_GP_PIN(4, 17),
3855 };
3856 static const unsigned int vin2_clkenb_mux[] = {
3857         VI2_CLKENB_MARK,
3858 };
3859 static const unsigned int vin2_clk_pins[] = {
3860         RCAR_GP_PIN(4, 19),
3861 };
3862 static const unsigned int vin2_clk_mux[] = {
3863         VI2_CLK_MARK,
3864 };
3865
3866 static const struct sh_pfc_pin_group pinmux_groups[] = {
3867         SH_PFC_PIN_GROUP(audio_clk_a),
3868         SH_PFC_PIN_GROUP(audio_clk_b),
3869         SH_PFC_PIN_GROUP(audio_clk_b_b),
3870         SH_PFC_PIN_GROUP(audio_clk_c),
3871         SH_PFC_PIN_GROUP(audio_clkout),
3872         SH_PFC_PIN_GROUP(du_rgb666),
3873         SH_PFC_PIN_GROUP(du_rgb888),
3874         SH_PFC_PIN_GROUP(du_clk_out_0),
3875         SH_PFC_PIN_GROUP(du_clk_out_1),
3876         SH_PFC_PIN_GROUP(du_sync),
3877         SH_PFC_PIN_GROUP(du_oddf),
3878         SH_PFC_PIN_GROUP(du_cde),
3879         SH_PFC_PIN_GROUP(du_disp),
3880         SH_PFC_PIN_GROUP(du0_clk_in),
3881         SH_PFC_PIN_GROUP(du1_clk_in),
3882         SH_PFC_PIN_GROUP(du1_clk_in_b),
3883         SH_PFC_PIN_GROUP(du1_clk_in_c),
3884         SH_PFC_PIN_GROUP(eth_link),
3885         SH_PFC_PIN_GROUP(eth_magic),
3886         SH_PFC_PIN_GROUP(eth_mdio),
3887         SH_PFC_PIN_GROUP(eth_rmii),
3888         SH_PFC_PIN_GROUP(i2c0),
3889         SH_PFC_PIN_GROUP(i2c0_b),
3890         SH_PFC_PIN_GROUP(i2c0_c),
3891         SH_PFC_PIN_GROUP(i2c1),
3892         SH_PFC_PIN_GROUP(i2c1_b),
3893         SH_PFC_PIN_GROUP(i2c1_c),
3894         SH_PFC_PIN_GROUP(i2c1_d),
3895         SH_PFC_PIN_GROUP(i2c1_e),
3896         SH_PFC_PIN_GROUP(i2c2),
3897         SH_PFC_PIN_GROUP(i2c2_b),
3898         SH_PFC_PIN_GROUP(i2c2_c),
3899         SH_PFC_PIN_GROUP(i2c2_d),
3900         SH_PFC_PIN_GROUP(i2c3),
3901         SH_PFC_PIN_GROUP(i2c3_b),
3902         SH_PFC_PIN_GROUP(i2c3_c),
3903         SH_PFC_PIN_GROUP(i2c3_d),
3904         SH_PFC_PIN_GROUP(i2c4),
3905         SH_PFC_PIN_GROUP(i2c4_b),
3906         SH_PFC_PIN_GROUP(i2c4_c),
3907         SH_PFC_PIN_GROUP(i2c7),
3908         SH_PFC_PIN_GROUP(i2c7_b),
3909         SH_PFC_PIN_GROUP(i2c7_c),
3910         SH_PFC_PIN_GROUP(i2c8),
3911         SH_PFC_PIN_GROUP(i2c8_b),
3912         SH_PFC_PIN_GROUP(i2c8_c),
3913         SH_PFC_PIN_GROUP(intc_irq0),
3914         SH_PFC_PIN_GROUP(intc_irq1),
3915         SH_PFC_PIN_GROUP(intc_irq2),
3916         SH_PFC_PIN_GROUP(intc_irq3),
3917         SH_PFC_PIN_GROUP(mmc_data1),
3918         SH_PFC_PIN_GROUP(mmc_data4),
3919         SH_PFC_PIN_GROUP(mmc_data8),
3920         SH_PFC_PIN_GROUP(mmc_ctrl),
3921         SH_PFC_PIN_GROUP(msiof0_clk),
3922         SH_PFC_PIN_GROUP(msiof0_sync),
3923         SH_PFC_PIN_GROUP(msiof0_ss1),
3924         SH_PFC_PIN_GROUP(msiof0_ss2),
3925         SH_PFC_PIN_GROUP(msiof0_rx),
3926         SH_PFC_PIN_GROUP(msiof0_tx),
3927         SH_PFC_PIN_GROUP(msiof0_clk_b),
3928         SH_PFC_PIN_GROUP(msiof0_sync_b),
3929         SH_PFC_PIN_GROUP(msiof0_ss1_b),
3930         SH_PFC_PIN_GROUP(msiof0_ss2_b),
3931         SH_PFC_PIN_GROUP(msiof0_rx_b),
3932         SH_PFC_PIN_GROUP(msiof0_tx_b),
3933         SH_PFC_PIN_GROUP(msiof0_clk_c),
3934         SH_PFC_PIN_GROUP(msiof0_sync_c),
3935         SH_PFC_PIN_GROUP(msiof0_ss1_c),
3936         SH_PFC_PIN_GROUP(msiof0_ss2_c),
3937         SH_PFC_PIN_GROUP(msiof0_rx_c),
3938         SH_PFC_PIN_GROUP(msiof0_tx_c),
3939         SH_PFC_PIN_GROUP(msiof1_clk),
3940         SH_PFC_PIN_GROUP(msiof1_sync),
3941         SH_PFC_PIN_GROUP(msiof1_ss1),
3942         SH_PFC_PIN_GROUP(msiof1_ss2),
3943         SH_PFC_PIN_GROUP(msiof1_rx),
3944         SH_PFC_PIN_GROUP(msiof1_tx),
3945         SH_PFC_PIN_GROUP(msiof1_clk_b),
3946         SH_PFC_PIN_GROUP(msiof1_sync_b),
3947         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3948         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3949         SH_PFC_PIN_GROUP(msiof1_rx_b),
3950         SH_PFC_PIN_GROUP(msiof1_tx_b),
3951         SH_PFC_PIN_GROUP(msiof1_clk_c),
3952         SH_PFC_PIN_GROUP(msiof1_sync_c),
3953         SH_PFC_PIN_GROUP(msiof1_rx_c),
3954         SH_PFC_PIN_GROUP(msiof1_tx_c),
3955         SH_PFC_PIN_GROUP(msiof1_clk_d),
3956         SH_PFC_PIN_GROUP(msiof1_sync_d),
3957         SH_PFC_PIN_GROUP(msiof1_ss1_d),
3958         SH_PFC_PIN_GROUP(msiof1_rx_d),
3959         SH_PFC_PIN_GROUP(msiof1_tx_d),
3960         SH_PFC_PIN_GROUP(msiof1_clk_e),
3961         SH_PFC_PIN_GROUP(msiof1_sync_e),
3962         SH_PFC_PIN_GROUP(msiof1_rx_e),
3963         SH_PFC_PIN_GROUP(msiof1_tx_e),
3964         SH_PFC_PIN_GROUP(msiof2_clk),
3965         SH_PFC_PIN_GROUP(msiof2_sync),
3966         SH_PFC_PIN_GROUP(msiof2_ss1),
3967         SH_PFC_PIN_GROUP(msiof2_ss2),
3968         SH_PFC_PIN_GROUP(msiof2_rx),
3969         SH_PFC_PIN_GROUP(msiof2_tx),
3970         SH_PFC_PIN_GROUP(msiof2_clk_b),
3971         SH_PFC_PIN_GROUP(msiof2_sync_b),
3972         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3973         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3974         SH_PFC_PIN_GROUP(msiof2_rx_b),
3975         SH_PFC_PIN_GROUP(msiof2_tx_b),
3976         SH_PFC_PIN_GROUP(msiof2_clk_c),
3977         SH_PFC_PIN_GROUP(msiof2_sync_c),
3978         SH_PFC_PIN_GROUP(msiof2_rx_c),
3979         SH_PFC_PIN_GROUP(msiof2_tx_c),
3980         SH_PFC_PIN_GROUP(msiof2_clk_d),
3981         SH_PFC_PIN_GROUP(msiof2_sync_d),
3982         SH_PFC_PIN_GROUP(msiof2_ss1_d),
3983         SH_PFC_PIN_GROUP(msiof2_ss2_d),
3984         SH_PFC_PIN_GROUP(msiof2_rx_d),
3985         SH_PFC_PIN_GROUP(msiof2_tx_d),
3986         SH_PFC_PIN_GROUP(msiof2_clk_e),
3987         SH_PFC_PIN_GROUP(msiof2_sync_e),
3988         SH_PFC_PIN_GROUP(msiof2_rx_e),
3989         SH_PFC_PIN_GROUP(msiof2_tx_e),
3990         SH_PFC_PIN_GROUP(qspi_ctrl),
3991         SH_PFC_PIN_GROUP(qspi_data2),
3992         SH_PFC_PIN_GROUP(qspi_data4),
3993         SH_PFC_PIN_GROUP(qspi_ctrl_b),
3994         SH_PFC_PIN_GROUP(qspi_data2_b),
3995         SH_PFC_PIN_GROUP(qspi_data4_b),
3996         SH_PFC_PIN_GROUP(scif0_data),
3997         SH_PFC_PIN_GROUP(scif0_data_b),
3998         SH_PFC_PIN_GROUP(scif0_data_c),
3999         SH_PFC_PIN_GROUP(scif0_data_d),
4000         SH_PFC_PIN_GROUP(scif0_data_e),
4001         SH_PFC_PIN_GROUP(scif1_data),
4002         SH_PFC_PIN_GROUP(scif1_data_b),
4003         SH_PFC_PIN_GROUP(scif1_clk_b),
4004         SH_PFC_PIN_GROUP(scif1_data_c),
4005         SH_PFC_PIN_GROUP(scif1_data_d),
4006         SH_PFC_PIN_GROUP(scif2_data),
4007         SH_PFC_PIN_GROUP(scif2_data_b),
4008         SH_PFC_PIN_GROUP(scif2_clk_b),
4009         SH_PFC_PIN_GROUP(scif2_data_c),
4010         SH_PFC_PIN_GROUP(scif2_data_e),
4011         SH_PFC_PIN_GROUP(scif3_data),
4012         SH_PFC_PIN_GROUP(scif3_clk),
4013         SH_PFC_PIN_GROUP(scif3_data_b),
4014         SH_PFC_PIN_GROUP(scif3_clk_b),
4015         SH_PFC_PIN_GROUP(scif3_data_c),
4016         SH_PFC_PIN_GROUP(scif3_data_d),
4017         SH_PFC_PIN_GROUP(scif4_data),
4018         SH_PFC_PIN_GROUP(scif4_data_b),
4019         SH_PFC_PIN_GROUP(scif4_data_c),
4020         SH_PFC_PIN_GROUP(scif5_data),
4021         SH_PFC_PIN_GROUP(scif5_data_b),
4022         SH_PFC_PIN_GROUP(scifa0_data),
4023         SH_PFC_PIN_GROUP(scifa0_data_b),
4024         SH_PFC_PIN_GROUP(scifa1_data),
4025         SH_PFC_PIN_GROUP(scifa1_clk),
4026         SH_PFC_PIN_GROUP(scifa1_data_b),
4027         SH_PFC_PIN_GROUP(scifa1_clk_b),
4028         SH_PFC_PIN_GROUP(scifa1_data_c),
4029         SH_PFC_PIN_GROUP(scifa2_data),
4030         SH_PFC_PIN_GROUP(scifa2_clk),
4031         SH_PFC_PIN_GROUP(scifa2_data_b),
4032         SH_PFC_PIN_GROUP(scifa3_data),
4033         SH_PFC_PIN_GROUP(scifa3_clk),
4034         SH_PFC_PIN_GROUP(scifa3_data_b),
4035         SH_PFC_PIN_GROUP(scifa3_clk_b),
4036         SH_PFC_PIN_GROUP(scifa3_data_c),
4037         SH_PFC_PIN_GROUP(scifa3_clk_c),
4038         SH_PFC_PIN_GROUP(scifa4_data),
4039         SH_PFC_PIN_GROUP(scifa4_data_b),
4040         SH_PFC_PIN_GROUP(scifa4_data_c),
4041         SH_PFC_PIN_GROUP(scifa5_data),
4042         SH_PFC_PIN_GROUP(scifa5_data_b),
4043         SH_PFC_PIN_GROUP(scifa5_data_c),
4044         SH_PFC_PIN_GROUP(scifb0_data),
4045         SH_PFC_PIN_GROUP(scifb0_clk),
4046         SH_PFC_PIN_GROUP(scifb0_ctrl),
4047         SH_PFC_PIN_GROUP(scifb0_data_b),
4048         SH_PFC_PIN_GROUP(scifb0_clk_b),
4049         SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4050         SH_PFC_PIN_GROUP(scifb0_data_c),
4051         SH_PFC_PIN_GROUP(scifb0_clk_c),
4052         SH_PFC_PIN_GROUP(scifb0_data_d),
4053         SH_PFC_PIN_GROUP(scifb0_clk_d),
4054         SH_PFC_PIN_GROUP(scifb1_data),
4055         SH_PFC_PIN_GROUP(scifb1_clk),
4056         SH_PFC_PIN_GROUP(scifb1_ctrl),
4057         SH_PFC_PIN_GROUP(scifb1_data_b),
4058         SH_PFC_PIN_GROUP(scifb1_clk_b),
4059         SH_PFC_PIN_GROUP(scifb1_data_c),
4060         SH_PFC_PIN_GROUP(scifb1_clk_c),
4061         SH_PFC_PIN_GROUP(scifb1_data_d),
4062         SH_PFC_PIN_GROUP(scifb2_data),
4063         SH_PFC_PIN_GROUP(scifb2_clk),
4064         SH_PFC_PIN_GROUP(scifb2_ctrl),
4065         SH_PFC_PIN_GROUP(scifb2_data_b),
4066         SH_PFC_PIN_GROUP(scifb2_clk_b),
4067         SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4068         SH_PFC_PIN_GROUP(scifb2_data_c),
4069         SH_PFC_PIN_GROUP(scifb2_clk_c),
4070         SH_PFC_PIN_GROUP(scifb2_data_d),
4071         SH_PFC_PIN_GROUP(sdhi0_data1),
4072         SH_PFC_PIN_GROUP(sdhi0_data4),
4073         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4074         SH_PFC_PIN_GROUP(sdhi0_cd),
4075         SH_PFC_PIN_GROUP(sdhi0_wp),
4076         SH_PFC_PIN_GROUP(sdhi1_data1),
4077         SH_PFC_PIN_GROUP(sdhi1_data4),
4078         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4079         SH_PFC_PIN_GROUP(sdhi1_cd),
4080         SH_PFC_PIN_GROUP(sdhi1_wp),
4081         SH_PFC_PIN_GROUP(sdhi2_data1),
4082         SH_PFC_PIN_GROUP(sdhi2_data4),
4083         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4084         SH_PFC_PIN_GROUP(sdhi2_cd),
4085         SH_PFC_PIN_GROUP(sdhi2_wp),
4086         SH_PFC_PIN_GROUP(ssi0_data),
4087         SH_PFC_PIN_GROUP(ssi0_data_b),
4088         SH_PFC_PIN_GROUP(ssi0129_ctrl),
4089         SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
4090         SH_PFC_PIN_GROUP(ssi1_data),
4091         SH_PFC_PIN_GROUP(ssi1_data_b),
4092         SH_PFC_PIN_GROUP(ssi1_ctrl),
4093         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4094         SH_PFC_PIN_GROUP(ssi2_data),
4095         SH_PFC_PIN_GROUP(ssi2_ctrl),
4096         SH_PFC_PIN_GROUP(ssi3_data),
4097         SH_PFC_PIN_GROUP(ssi34_ctrl),
4098         SH_PFC_PIN_GROUP(ssi4_data),
4099         SH_PFC_PIN_GROUP(ssi4_ctrl),
4100         SH_PFC_PIN_GROUP(ssi5_data),
4101         SH_PFC_PIN_GROUP(ssi5_ctrl),
4102         SH_PFC_PIN_GROUP(ssi6_data),
4103         SH_PFC_PIN_GROUP(ssi6_ctrl),
4104         SH_PFC_PIN_GROUP(ssi7_data),
4105         SH_PFC_PIN_GROUP(ssi7_data_b),
4106         SH_PFC_PIN_GROUP(ssi78_ctrl),
4107         SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4108         SH_PFC_PIN_GROUP(ssi8_data),
4109         SH_PFC_PIN_GROUP(ssi8_data_b),
4110         SH_PFC_PIN_GROUP(ssi9_data),
4111         SH_PFC_PIN_GROUP(ssi9_data_b),
4112         SH_PFC_PIN_GROUP(ssi9_ctrl),
4113         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4114         SH_PFC_PIN_GROUP(usb0),
4115         SH_PFC_PIN_GROUP(usb1),
4116         VIN_DATA_PIN_GROUP(vin0_data, 24),
4117         VIN_DATA_PIN_GROUP(vin0_data, 20),
4118         SH_PFC_PIN_GROUP(vin0_data18),
4119         VIN_DATA_PIN_GROUP(vin0_data, 16),
4120         VIN_DATA_PIN_GROUP(vin0_data, 12),
4121         VIN_DATA_PIN_GROUP(vin0_data, 10),
4122         VIN_DATA_PIN_GROUP(vin0_data, 8),
4123         SH_PFC_PIN_GROUP(vin0_sync),
4124         SH_PFC_PIN_GROUP(vin0_field),
4125         SH_PFC_PIN_GROUP(vin0_clkenb),
4126         SH_PFC_PIN_GROUP(vin0_clk),
4127         SH_PFC_PIN_GROUP(vin1_data8),
4128         SH_PFC_PIN_GROUP(vin1_sync),
4129         SH_PFC_PIN_GROUP(vin1_field),
4130         SH_PFC_PIN_GROUP(vin1_clkenb),
4131         SH_PFC_PIN_GROUP(vin1_clk),
4132         VIN_DATA_PIN_GROUP(vin1_b_data, 24),
4133         VIN_DATA_PIN_GROUP(vin1_b_data, 20),
4134         SH_PFC_PIN_GROUP(vin1_b_data18),
4135         VIN_DATA_PIN_GROUP(vin1_b_data, 16),
4136         VIN_DATA_PIN_GROUP(vin1_b_data, 12),
4137         VIN_DATA_PIN_GROUP(vin1_b_data, 10),
4138         VIN_DATA_PIN_GROUP(vin1_b_data, 8),
4139         SH_PFC_PIN_GROUP(vin1_b_sync),
4140         SH_PFC_PIN_GROUP(vin1_b_field),
4141         SH_PFC_PIN_GROUP(vin1_b_clkenb),
4142         SH_PFC_PIN_GROUP(vin1_b_clk),
4143         SH_PFC_PIN_GROUP(vin2_data8),
4144         SH_PFC_PIN_GROUP(vin2_sync),
4145         SH_PFC_PIN_GROUP(vin2_field),
4146         SH_PFC_PIN_GROUP(vin2_clkenb),
4147         SH_PFC_PIN_GROUP(vin2_clk),
4148 };
4149
4150 static const char * const audio_clk_groups[] = {
4151         "audio_clk_a",
4152         "audio_clk_b",
4153         "audio_clk_b_b",
4154         "audio_clk_c",
4155         "audio_clkout",
4156 };
4157
4158 static const char * const du_groups[] = {
4159         "du_rgb666",
4160         "du_rgb888",
4161         "du_clk_out_0",
4162         "du_clk_out_1",
4163         "du_sync",
4164         "du_oddf",
4165         "du_cde",
4166         "du_disp",
4167 };
4168
4169 static const char * const du0_groups[] = {
4170         "du0_clk_in",
4171 };
4172
4173 static const char * const du1_groups[] = {
4174         "du1_clk_in",
4175         "du1_clk_in_b",
4176         "du1_clk_in_c",
4177 };
4178
4179 static const char * const eth_groups[] = {
4180         "eth_link",
4181         "eth_magic",
4182         "eth_mdio",
4183         "eth_rmii",
4184 };
4185
4186 static const char * const i2c0_groups[] = {
4187         "i2c0",
4188         "i2c0_b",
4189         "i2c0_c",
4190 };
4191
4192 static const char * const i2c1_groups[] = {
4193         "i2c1",
4194         "i2c1_b",
4195         "i2c1_c",
4196         "i2c1_d",
4197         "i2c1_e",
4198 };
4199
4200 static const char * const i2c2_groups[] = {
4201         "i2c2",
4202         "i2c2_b",
4203         "i2c2_c",
4204         "i2c2_d",
4205 };
4206
4207 static const char * const i2c3_groups[] = {
4208         "i2c3",
4209         "i2c3_b",
4210         "i2c3_c",
4211         "i2c3_d",
4212 };
4213
4214 static const char * const i2c4_groups[] = {
4215         "i2c4",
4216         "i2c4_b",
4217         "i2c4_c",
4218 };
4219
4220 static const char * const i2c7_groups[] = {
4221         "i2c7",
4222         "i2c7_b",
4223         "i2c7_c",
4224 };
4225
4226 static const char * const i2c8_groups[] = {
4227         "i2c8",
4228         "i2c8_b",
4229         "i2c8_c",
4230 };
4231
4232 static const char * const intc_groups[] = {
4233         "intc_irq0",
4234         "intc_irq1",
4235         "intc_irq2",
4236         "intc_irq3",
4237 };
4238
4239 static const char * const mmc_groups[] = {
4240         "mmc_data1",
4241         "mmc_data4",
4242         "mmc_data8",
4243         "mmc_ctrl",
4244 };
4245
4246 static const char * const msiof0_groups[] = {
4247         "msiof0_clk",
4248         "msiof0_sync",
4249         "msiof0_ss1",
4250         "msiof0_ss2",
4251         "msiof0_rx",
4252         "msiof0_tx",
4253         "msiof0_clk_b",
4254         "msiof0_sync_b",
4255         "msiof0_ss1_b",
4256         "msiof0_ss2_b",
4257         "msiof0_rx_b",
4258         "msiof0_tx_b",
4259         "msiof0_clk_c",
4260         "msiof0_sync_c",
4261         "msiof0_ss1_c",
4262         "msiof0_ss2_c",
4263         "msiof0_rx_c",
4264         "msiof0_tx_c",
4265 };
4266
4267 static const char * const msiof1_groups[] = {
4268         "msiof1_clk",
4269         "msiof1_sync",
4270         "msiof1_ss1",
4271         "msiof1_ss2",
4272         "msiof1_rx",
4273         "msiof1_tx",
4274         "msiof1_clk_b",
4275         "msiof1_sync_b",
4276         "msiof1_ss1_b",
4277         "msiof1_ss2_b",
4278         "msiof1_rx_b",
4279         "msiof1_tx_b",
4280         "msiof1_clk_c",
4281         "msiof1_sync_c",
4282         "msiof1_rx_c",
4283         "msiof1_tx_c",
4284         "msiof1_clk_d",
4285         "msiof1_sync_d",
4286         "msiof1_ss1_d",
4287         "msiof1_rx_d",
4288         "msiof1_tx_d",
4289         "msiof1_clk_e",
4290         "msiof1_sync_e",
4291         "msiof1_rx_e",
4292         "msiof1_tx_e",
4293 };
4294
4295 static const char * const msiof2_groups[] = {
4296         "msiof2_clk",
4297         "msiof2_sync",
4298         "msiof2_ss1",
4299         "msiof2_ss2",
4300         "msiof2_rx",
4301         "msiof2_tx",
4302         "msiof2_clk_b",
4303         "msiof2_sync_b",
4304         "msiof2_ss1_b",
4305         "msiof2_ss2_b",
4306         "msiof2_rx_b",
4307         "msiof2_tx_b",
4308         "msiof2_clk_c",
4309         "msiof2_sync_c",
4310         "msiof2_rx_c",
4311         "msiof2_tx_c",
4312         "msiof2_clk_d",
4313         "msiof2_sync_d",
4314         "msiof2_ss1_d",
4315         "msiof2_ss2_d",
4316         "msiof2_rx_d",
4317         "msiof2_tx_d",
4318         "msiof2_clk_e",
4319         "msiof2_sync_e",
4320         "msiof2_rx_e",
4321         "msiof2_tx_e",
4322 };
4323
4324 static const char * const qspi_groups[] = {
4325         "qspi_ctrl",
4326         "qspi_data2",
4327         "qspi_data4",
4328         "qspi_ctrl_b",
4329         "qspi_data2_b",
4330         "qspi_data4_b",
4331 };
4332
4333 static const char * const scif0_groups[] = {
4334         "scif0_data",
4335         "scif0_data_b",
4336         "scif0_data_c",
4337         "scif0_data_d",
4338         "scif0_data_e",
4339 };
4340
4341 static const char * const scif1_groups[] = {
4342         "scif1_data",
4343         "scif1_data_b",
4344         "scif1_clk_b",
4345         "scif1_data_c",
4346         "scif1_data_d",
4347 };
4348
4349 static const char * const scif2_groups[] = {
4350         "scif2_data",
4351         "scif2_data_b",
4352         "scif2_clk_b",
4353         "scif2_data_c",
4354         "scif2_data_e",
4355 };
4356 static const char * const scif3_groups[] = {
4357         "scif3_data",
4358         "scif3_clk",
4359         "scif3_data_b",
4360         "scif3_clk_b",
4361         "scif3_data_c",
4362         "scif3_data_d",
4363 };
4364 static const char * const scif4_groups[] = {
4365         "scif4_data",
4366         "scif4_data_b",
4367         "scif4_data_c",
4368 };
4369 static const char * const scif5_groups[] = {
4370         "scif5_data",
4371         "scif5_data_b",
4372 };
4373 static const char * const scifa0_groups[] = {
4374         "scifa0_data",
4375         "scifa0_data_b",
4376 };
4377 static const char * const scifa1_groups[] = {
4378         "scifa1_data",
4379         "scifa1_clk",
4380         "scifa1_data_b",
4381         "scifa1_clk_b",
4382         "scifa1_data_c",
4383 };
4384 static const char * const scifa2_groups[] = {
4385         "scifa2_data",
4386         "scifa2_clk",
4387         "scifa2_data_b",
4388 };
4389 static const char * const scifa3_groups[] = {
4390         "scifa3_data",
4391         "scifa3_clk",
4392         "scifa3_data_b",
4393         "scifa3_clk_b",
4394         "scifa3_data_c",
4395         "scifa3_clk_c",
4396 };
4397 static const char * const scifa4_groups[] = {
4398         "scifa4_data",
4399         "scifa4_data_b",
4400         "scifa4_data_c",
4401 };
4402 static const char * const scifa5_groups[] = {
4403         "scifa5_data",
4404         "scifa5_data_b",
4405         "scifa5_data_c",
4406 };
4407 static const char * const scifb0_groups[] = {
4408         "scifb0_data",
4409         "scifb0_clk",
4410         "scifb0_ctrl",
4411         "scifb0_data_b",
4412         "scifb0_clk_b",
4413         "scifb0_ctrl_b",
4414         "scifb0_data_c",
4415         "scifb0_clk_c",
4416         "scifb0_data_d",
4417         "scifb0_clk_d",
4418 };
4419 static const char * const scifb1_groups[] = {
4420         "scifb1_data",
4421         "scifb1_clk",
4422         "scifb1_ctrl",
4423         "scifb1_data_b",
4424         "scifb1_clk_b",
4425         "scifb1_data_c",
4426         "scifb1_clk_c",
4427         "scifb1_data_d",
4428 };
4429 static const char * const scifb2_groups[] = {
4430         "scifb2_data",
4431         "scifb2_clk",
4432         "scifb2_ctrl",
4433         "scifb2_data_b",
4434         "scifb2_clk_b",
4435         "scifb2_ctrl_b",
4436         "scifb0_data_c",
4437         "scifb2_clk_c",
4438         "scifb2_data_d",
4439 };
4440
4441 static const char * const sdhi0_groups[] = {
4442         "sdhi0_data1",
4443         "sdhi0_data4",
4444         "sdhi0_ctrl",
4445         "sdhi0_cd",
4446         "sdhi0_wp",
4447 };
4448
4449 static const char * const sdhi1_groups[] = {
4450         "sdhi1_data1",
4451         "sdhi1_data4",
4452         "sdhi1_ctrl",
4453         "sdhi1_cd",
4454         "sdhi1_wp",
4455 };
4456
4457 static const char * const sdhi2_groups[] = {
4458         "sdhi2_data1",
4459         "sdhi2_data4",
4460         "sdhi2_ctrl",
4461         "sdhi2_cd",
4462         "sdhi2_wp",
4463 };
4464
4465 static const char * const ssi_groups[] = {
4466         "ssi0_data",
4467         "ssi0_data_b",
4468         "ssi0129_ctrl",
4469         "ssi0129_ctrl_b",
4470         "ssi1_data",
4471         "ssi1_data_b",
4472         "ssi1_ctrl",
4473         "ssi1_ctrl_b",
4474         "ssi2_data",
4475         "ssi2_ctrl",
4476         "ssi3_data",
4477         "ssi34_ctrl",
4478         "ssi4_data",
4479         "ssi4_ctrl",
4480         "ssi5_data",
4481         "ssi5_ctrl",
4482         "ssi6_data",
4483         "ssi6_ctrl",
4484         "ssi7_data",
4485         "ssi7_data_b",
4486         "ssi78_ctrl",
4487         "ssi78_ctrl_b",
4488         "ssi8_data",
4489         "ssi8_data_b",
4490         "ssi9_data",
4491         "ssi9_data_b",
4492         "ssi9_ctrl",
4493         "ssi9_ctrl_b",
4494 };
4495
4496 static const char * const usb0_groups[] = {
4497         "usb0",
4498 };
4499 static const char * const usb1_groups[] = {
4500         "usb1",
4501 };
4502
4503 static const char * const vin0_groups[] = {
4504         "vin0_data24",
4505         "vin0_data20",
4506         "vin0_data18",
4507         "vin0_data16",
4508         "vin0_data12",
4509         "vin0_data10",
4510         "vin0_data8",
4511         "vin0_sync",
4512         "vin0_field",
4513         "vin0_clkenb",
4514         "vin0_clk",
4515 };
4516
4517 static const char * const vin1_groups[] = {
4518         "vin1_data8",
4519         "vin1_sync",
4520         "vin1_field",
4521         "vin1_clkenb",
4522         "vin1_clk",
4523         "vin1_b_data24",
4524         "vin1_b_data20",
4525         "vin1_b_data18",
4526         "vin1_b_data16",
4527         "vin1_b_data12",
4528         "vin1_b_data10",
4529         "vin1_b_data8",
4530         "vin1_b_sync",
4531         "vin1_b_field",
4532         "vin1_b_clkenb",
4533         "vin1_b_clk",
4534 };
4535
4536 static const char * const vin2_groups[] = {
4537         "vin2_data8",
4538         "vin2_sync",
4539         "vin2_field",
4540         "vin2_clkenb",
4541         "vin2_clk",
4542 };
4543
4544 static const struct sh_pfc_function pinmux_functions[] = {
4545         SH_PFC_FUNCTION(audio_clk),
4546         SH_PFC_FUNCTION(du),
4547         SH_PFC_FUNCTION(du0),
4548         SH_PFC_FUNCTION(du1),
4549         SH_PFC_FUNCTION(eth),
4550         SH_PFC_FUNCTION(i2c0),
4551         SH_PFC_FUNCTION(i2c1),
4552         SH_PFC_FUNCTION(i2c2),
4553         SH_PFC_FUNCTION(i2c3),
4554         SH_PFC_FUNCTION(i2c4),
4555         SH_PFC_FUNCTION(i2c7),
4556         SH_PFC_FUNCTION(i2c8),
4557         SH_PFC_FUNCTION(intc),
4558         SH_PFC_FUNCTION(mmc),
4559         SH_PFC_FUNCTION(msiof0),
4560         SH_PFC_FUNCTION(msiof1),
4561         SH_PFC_FUNCTION(msiof2),
4562         SH_PFC_FUNCTION(qspi),
4563         SH_PFC_FUNCTION(scif0),
4564         SH_PFC_FUNCTION(scif1),
4565         SH_PFC_FUNCTION(scif2),
4566         SH_PFC_FUNCTION(scif3),
4567         SH_PFC_FUNCTION(scif4),
4568         SH_PFC_FUNCTION(scif5),
4569         SH_PFC_FUNCTION(scifa0),
4570         SH_PFC_FUNCTION(scifa1),
4571         SH_PFC_FUNCTION(scifa2),
4572         SH_PFC_FUNCTION(scifa3),
4573         SH_PFC_FUNCTION(scifa4),
4574         SH_PFC_FUNCTION(scifa5),
4575         SH_PFC_FUNCTION(scifb0),
4576         SH_PFC_FUNCTION(scifb1),
4577         SH_PFC_FUNCTION(scifb2),
4578         SH_PFC_FUNCTION(sdhi0),
4579         SH_PFC_FUNCTION(sdhi1),
4580         SH_PFC_FUNCTION(sdhi2),
4581         SH_PFC_FUNCTION(ssi),
4582         SH_PFC_FUNCTION(usb0),
4583         SH_PFC_FUNCTION(usb1),
4584         SH_PFC_FUNCTION(vin0),
4585         SH_PFC_FUNCTION(vin1),
4586         SH_PFC_FUNCTION(vin2),
4587 };
4588
4589 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4590         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4591                 GP_0_31_FN, FN_IP1_22_20,
4592                 GP_0_30_FN, FN_IP1_19_17,
4593                 GP_0_29_FN, FN_IP1_16_14,
4594                 GP_0_28_FN, FN_IP1_13_11,
4595                 GP_0_27_FN, FN_IP1_10_8,
4596                 GP_0_26_FN, FN_IP1_7_6,
4597                 GP_0_25_FN, FN_IP1_5_4,
4598                 GP_0_24_FN, FN_IP1_3_2,
4599                 GP_0_23_FN, FN_IP1_1_0,
4600                 GP_0_22_FN, FN_IP0_30_29,
4601                 GP_0_21_FN, FN_IP0_28_27,
4602                 GP_0_20_FN, FN_IP0_26_25,
4603                 GP_0_19_FN, FN_IP0_24_23,
4604                 GP_0_18_FN, FN_IP0_22_21,
4605                 GP_0_17_FN, FN_IP0_20_19,
4606                 GP_0_16_FN, FN_IP0_18_16,
4607                 GP_0_15_FN, FN_IP0_15,
4608                 GP_0_14_FN, FN_IP0_14,
4609                 GP_0_13_FN, FN_IP0_13,
4610                 GP_0_12_FN, FN_IP0_12,
4611                 GP_0_11_FN, FN_IP0_11,
4612                 GP_0_10_FN, FN_IP0_10,
4613                 GP_0_9_FN, FN_IP0_9,
4614                 GP_0_8_FN, FN_IP0_8,
4615                 GP_0_7_FN, FN_IP0_7,
4616                 GP_0_6_FN, FN_IP0_6,
4617                 GP_0_5_FN, FN_IP0_5,
4618                 GP_0_4_FN, FN_IP0_4,
4619                 GP_0_3_FN, FN_IP0_3,
4620                 GP_0_2_FN, FN_IP0_2,
4621                 GP_0_1_FN, FN_IP0_1,
4622                 GP_0_0_FN, FN_IP0_0, }
4623         },
4624         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4625                 0, 0,
4626                 0, 0,
4627                 0, 0,
4628                 0, 0,
4629                 0, 0,
4630                 0, 0,
4631                 GP_1_25_FN, FN_IP3_21_20,
4632                 GP_1_24_FN, FN_IP3_19_18,
4633                 GP_1_23_FN, FN_IP3_17_16,
4634                 GP_1_22_FN, FN_IP3_15_14,
4635                 GP_1_21_FN, FN_IP3_13_12,
4636                 GP_1_20_FN, FN_IP3_11_9,
4637                 GP_1_19_FN, FN_RD_N,
4638                 GP_1_18_FN, FN_IP3_8_6,
4639                 GP_1_17_FN, FN_IP3_5_3,
4640                 GP_1_16_FN, FN_IP3_2_0,
4641                 GP_1_15_FN, FN_IP2_29_27,
4642                 GP_1_14_FN, FN_IP2_26_25,
4643                 GP_1_13_FN, FN_IP2_24_23,
4644                 GP_1_12_FN, FN_EX_CS0_N,
4645                 GP_1_11_FN, FN_IP2_22_21,
4646                 GP_1_10_FN, FN_IP2_20_19,
4647                 GP_1_9_FN, FN_IP2_18_16,
4648                 GP_1_8_FN, FN_IP2_15_13,
4649                 GP_1_7_FN, FN_IP2_12_10,
4650                 GP_1_6_FN, FN_IP2_9_7,
4651                 GP_1_5_FN, FN_IP2_6_5,
4652                 GP_1_4_FN, FN_IP2_4_3,
4653                 GP_1_3_FN, FN_IP2_2_0,
4654                 GP_1_2_FN, FN_IP1_31_29,
4655                 GP_1_1_FN, FN_IP1_28_26,
4656                 GP_1_0_FN, FN_IP1_25_23, }
4657         },
4658         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4659                 GP_2_31_FN, FN_IP6_7_6,
4660                 GP_2_30_FN, FN_IP6_5_3,
4661                 GP_2_29_FN, FN_IP6_2_0,
4662                 GP_2_28_FN, FN_AUDIO_CLKA,
4663                 GP_2_27_FN, FN_IP5_31_29,
4664                 GP_2_26_FN, FN_IP5_28_26,
4665                 GP_2_25_FN, FN_IP5_25_24,
4666                 GP_2_24_FN, FN_IP5_23_22,
4667                 GP_2_23_FN, FN_IP5_21_20,
4668                 GP_2_22_FN, FN_IP5_19_17,
4669                 GP_2_21_FN, FN_IP5_16_15,
4670                 GP_2_20_FN, FN_IP5_14_12,
4671                 GP_2_19_FN, FN_IP5_11_9,
4672                 GP_2_18_FN, FN_IP5_8_6,
4673                 GP_2_17_FN, FN_IP5_5_3,
4674                 GP_2_16_FN, FN_IP5_2_0,
4675                 GP_2_15_FN, FN_IP4_30_28,
4676                 GP_2_14_FN, FN_IP4_27_26,
4677                 GP_2_13_FN, FN_IP4_25_24,
4678                 GP_2_12_FN, FN_IP4_23_22,
4679                 GP_2_11_FN, FN_IP4_21,
4680                 GP_2_10_FN, FN_IP4_20,
4681                 GP_2_9_FN, FN_IP4_19,
4682                 GP_2_8_FN, FN_IP4_18_16,
4683                 GP_2_7_FN, FN_IP4_15_13,
4684                 GP_2_6_FN, FN_IP4_12_10,
4685                 GP_2_5_FN, FN_IP4_9_8,
4686                 GP_2_4_FN, FN_IP4_7_5,
4687                 GP_2_3_FN, FN_IP4_4_2,
4688                 GP_2_2_FN, FN_IP4_1_0,
4689                 GP_2_1_FN, FN_IP3_30_28,
4690                 GP_2_0_FN, FN_IP3_27_25 }
4691         },
4692         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4693                 GP_3_31_FN, FN_IP9_18_17,
4694                 GP_3_30_FN, FN_IP9_16,
4695                 GP_3_29_FN, FN_IP9_15_13,
4696                 GP_3_28_FN, FN_IP9_12,
4697                 GP_3_27_FN, FN_IP9_11,
4698                 GP_3_26_FN, FN_IP9_10_8,
4699                 GP_3_25_FN, FN_IP9_7,
4700                 GP_3_24_FN, FN_IP9_6,
4701                 GP_3_23_FN, FN_IP9_5_3,
4702                 GP_3_22_FN, FN_IP9_2_0,
4703                 GP_3_21_FN, FN_IP8_30_28,
4704                 GP_3_20_FN, FN_IP8_27_26,
4705                 GP_3_19_FN, FN_IP8_25_24,
4706                 GP_3_18_FN, FN_IP8_23_21,
4707                 GP_3_17_FN, FN_IP8_20_18,
4708                 GP_3_16_FN, FN_IP8_17_15,
4709                 GP_3_15_FN, FN_IP8_14_12,
4710                 GP_3_14_FN, FN_IP8_11_9,
4711                 GP_3_13_FN, FN_IP8_8_6,
4712                 GP_3_12_FN, FN_IP8_5_3,
4713                 GP_3_11_FN, FN_IP8_2_0,
4714                 GP_3_10_FN, FN_IP7_29_27,
4715                 GP_3_9_FN, FN_IP7_26_24,
4716                 GP_3_8_FN, FN_IP7_23_21,
4717                 GP_3_7_FN, FN_IP7_20_19,
4718                 GP_3_6_FN, FN_IP7_18_17,
4719                 GP_3_5_FN, FN_IP7_16_15,
4720                 GP_3_4_FN, FN_IP7_14_13,
4721                 GP_3_3_FN, FN_IP7_12_11,
4722                 GP_3_2_FN, FN_IP7_10_9,
4723                 GP_3_1_FN, FN_IP7_8_6,
4724                 GP_3_0_FN, FN_IP7_5_3 }
4725         },
4726         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4727                 GP_4_31_FN, FN_IP15_5_4,
4728                 GP_4_30_FN, FN_IP15_3_2,
4729                 GP_4_29_FN, FN_IP15_1_0,
4730                 GP_4_28_FN, FN_IP11_8_6,
4731                 GP_4_27_FN, FN_IP11_5_3,
4732                 GP_4_26_FN, FN_IP11_2_0,
4733                 GP_4_25_FN, FN_IP10_31_29,
4734                 GP_4_24_FN, FN_IP10_28_27,
4735                 GP_4_23_FN, FN_IP10_26_25,
4736                 GP_4_22_FN, FN_IP10_24_22,
4737                 GP_4_21_FN, FN_IP10_21_19,
4738                 GP_4_20_FN, FN_IP10_18_17,
4739                 GP_4_19_FN, FN_IP10_16_15,
4740                 GP_4_18_FN, FN_IP10_14_12,
4741                 GP_4_17_FN, FN_IP10_11_9,
4742                 GP_4_16_FN, FN_IP10_8_6,
4743                 GP_4_15_FN, FN_IP10_5_3,
4744                 GP_4_14_FN, FN_IP10_2_0,
4745                 GP_4_13_FN, FN_IP9_31_29,
4746                 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
4747                 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
4748                 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
4749                 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
4750                 GP_4_8_FN, FN_IP9_28_27,
4751                 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
4752                 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
4753                 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
4754                 GP_4_4_FN, FN_IP9_26_25,
4755                 GP_4_3_FN, FN_IP9_24_23,
4756                 GP_4_2_FN, FN_IP9_22_21,
4757                 GP_4_1_FN, FN_IP9_20_19,
4758                 GP_4_0_FN, FN_VI0_CLK }
4759         },
4760         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4761                 GP_5_31_FN, FN_IP3_24_22,
4762                 GP_5_30_FN, FN_IP13_9_7,
4763                 GP_5_29_FN, FN_IP13_6_5,
4764                 GP_5_28_FN, FN_IP13_4_3,
4765                 GP_5_27_FN, FN_IP13_2_0,
4766                 GP_5_26_FN, FN_IP12_29_27,
4767                 GP_5_25_FN, FN_IP12_26_24,
4768                 GP_5_24_FN, FN_IP12_23_22,
4769                 GP_5_23_FN, FN_IP12_21_20,
4770                 GP_5_22_FN, FN_IP12_19_18,
4771                 GP_5_21_FN, FN_IP12_17_16,
4772                 GP_5_20_FN, FN_IP12_15_13,
4773                 GP_5_19_FN, FN_IP12_12_10,
4774                 GP_5_18_FN, FN_IP12_9_7,
4775                 GP_5_17_FN, FN_IP12_6_4,
4776                 GP_5_16_FN, FN_IP12_3_2,
4777                 GP_5_15_FN, FN_IP12_1_0,
4778                 GP_5_14_FN, FN_IP11_31_30,
4779                 GP_5_13_FN, FN_IP11_29_28,
4780                 GP_5_12_FN, FN_IP11_27,
4781                 GP_5_11_FN, FN_IP11_26,
4782                 GP_5_10_FN, FN_IP11_25,
4783                 GP_5_9_FN, FN_IP11_24,
4784                 GP_5_8_FN, FN_IP11_23,
4785                 GP_5_7_FN, FN_IP11_22,
4786                 GP_5_6_FN, FN_IP11_21,
4787                 GP_5_5_FN, FN_IP11_20,
4788                 GP_5_4_FN, FN_IP11_19,
4789                 GP_5_3_FN, FN_IP11_18_17,
4790                 GP_5_2_FN, FN_IP11_16_15,
4791                 GP_5_1_FN, FN_IP11_14_12,
4792                 GP_5_0_FN, FN_IP11_11_9 }
4793         },
4794         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
4795                 GP_6_31_FN, FN_DU0_DOTCLKIN,
4796                 GP_6_30_FN, FN_USB1_OVC,
4797                 GP_6_29_FN, FN_IP14_31_29,
4798                 GP_6_28_FN, FN_IP14_28_26,
4799                 GP_6_27_FN, FN_IP14_25_23,
4800                 GP_6_26_FN, FN_IP14_22_20,
4801                 GP_6_25_FN, FN_IP14_19_17,
4802                 GP_6_24_FN, FN_IP14_16_14,
4803                 GP_6_23_FN, FN_IP14_13_11,
4804                 GP_6_22_FN, FN_IP14_10_8,
4805                 GP_6_21_FN, FN_IP14_7,
4806                 GP_6_20_FN, FN_IP14_6,
4807                 GP_6_19_FN, FN_IP14_5,
4808                 GP_6_18_FN, FN_IP14_4,
4809                 GP_6_17_FN, FN_IP14_3,
4810                 GP_6_16_FN, FN_IP14_2,
4811                 GP_6_15_FN, FN_IP14_1_0,
4812                 GP_6_14_FN, FN_IP13_30_28,
4813                 GP_6_13_FN, FN_IP13_27,
4814                 GP_6_12_FN, FN_IP13_26,
4815                 GP_6_11_FN, FN_IP13_25,
4816                 GP_6_10_FN, FN_IP13_24_23,
4817                 GP_6_9_FN, FN_IP13_22,
4818                 GP_6_8_FN, FN_SD1_CLK,
4819                 GP_6_7_FN, FN_IP13_21_19,
4820                 GP_6_6_FN, FN_IP13_18_16,
4821                 GP_6_5_FN, FN_IP13_15,
4822                 GP_6_4_FN, FN_IP13_14,
4823                 GP_6_3_FN, FN_IP13_13,
4824                 GP_6_2_FN, FN_IP13_12,
4825                 GP_6_1_FN, FN_IP13_11,
4826                 GP_6_0_FN, FN_IP13_10 }
4827         },
4828         { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
4829                 0, 0,
4830                 0, 0,
4831                 0, 0,
4832                 0, 0,
4833                 0, 0,
4834                 0, 0,
4835                 GP_7_25_FN, FN_USB1_PWEN,
4836                 GP_7_24_FN, FN_USB0_OVC,
4837                 GP_7_23_FN, FN_USB0_PWEN,
4838                 GP_7_22_FN, FN_IP15_14_12,
4839                 GP_7_21_FN, FN_IP15_11_9,
4840                 GP_7_20_FN, FN_IP15_8_6,
4841                 GP_7_19_FN, FN_IP7_2_0,
4842                 GP_7_18_FN, FN_IP6_29_27,
4843                 GP_7_17_FN, FN_IP6_26_24,
4844                 GP_7_16_FN, FN_IP6_23_21,
4845                 GP_7_15_FN, FN_IP6_20_19,
4846                 GP_7_14_FN, FN_IP6_18_16,
4847                 GP_7_13_FN, FN_IP6_15_14,
4848                 GP_7_12_FN, FN_IP6_13_12,
4849                 GP_7_11_FN, FN_IP6_11_10,
4850                 GP_7_10_FN, FN_IP6_9_8,
4851                 GP_7_9_FN, FN_IP16_11_10,
4852                 GP_7_8_FN, FN_IP16_9_8,
4853                 GP_7_7_FN, FN_IP16_7_6,
4854                 GP_7_6_FN, FN_IP16_5_3,
4855                 GP_7_5_FN, FN_IP16_2_0,
4856                 GP_7_4_FN, FN_IP15_29_27,
4857                 GP_7_3_FN, FN_IP15_26_24,
4858                 GP_7_2_FN, FN_IP15_23_21,
4859                 GP_7_1_FN, FN_IP15_20_18,
4860                 GP_7_0_FN, FN_IP15_17_15 }
4861         },
4862         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4863                              1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
4864                              1, 1, 1, 1, 1, 1, 1, 1) {
4865                 /* IP0_31 [1] */
4866                 0, 0,
4867                 /* IP0_30_29 [2] */
4868                 FN_A6, FN_MSIOF1_SCK,
4869                 0, 0,
4870                 /* IP0_28_27 [2] */
4871                 FN_A5, FN_MSIOF0_RXD_B,
4872                 0, 0,
4873                 /* IP0_26_25 [2] */
4874                 FN_A4, FN_MSIOF0_TXD_B,
4875                 0, 0,
4876                 /* IP0_24_23 [2] */
4877                 FN_A3, FN_MSIOF0_SS2_B,
4878                 0, 0,
4879                 /* IP0_22_21 [2] */
4880                 FN_A2, FN_MSIOF0_SS1_B,
4881                 0, 0,
4882                 /* IP0_20_19 [2] */
4883                 FN_A1, FN_MSIOF0_SYNC_B,
4884                 0, 0,
4885                 /* IP0_18_16 [3] */
4886                 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
4887                 0, 0, 0,
4888                 /* IP0_15 [1] */
4889                 FN_D15, 0,
4890                 /* IP0_14 [1] */
4891                 FN_D14, 0,
4892                 /* IP0_13 [1] */
4893                 FN_D13, 0,
4894                 /* IP0_12 [1] */
4895                 FN_D12, 0,
4896                 /* IP0_11 [1] */
4897                 FN_D11, 0,
4898                 /* IP0_10 [1] */
4899                 FN_D10, 0,
4900                 /* IP0_9 [1] */
4901                 FN_D9, 0,
4902                 /* IP0_8 [1] */
4903                 FN_D8, 0,
4904                 /* IP0_7 [1] */
4905                 FN_D7, 0,
4906                 /* IP0_6 [1] */
4907                 FN_D6, 0,
4908                 /* IP0_5 [1] */
4909                 FN_D5, 0,
4910                 /* IP0_4 [1] */
4911                 FN_D4, 0,
4912                 /* IP0_3 [1] */
4913                 FN_D3, 0,
4914                 /* IP0_2 [1] */
4915                 FN_D2, 0,
4916                 /* IP0_1 [1] */
4917                 FN_D1, 0,
4918                 /* IP0_0 [1] */
4919                 FN_D0, 0, }
4920         },
4921         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4922                              3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
4923                 /* IP1_31_29 [3] */
4924                 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
4925                 0, 0, 0,
4926                 /* IP1_28_26 [3] */
4927                 FN_A17, FN_DACK2_B, 0, FN_SDA0_C,
4928                 0, 0, 0, 0,
4929                 /* IP1_25_23 [3] */
4930                 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
4931                 0, 0, 0,
4932                 /* IP1_22_20 [3] */
4933                 FN_A15, FN_BPFCLK_C,
4934                 0, 0, 0, 0, 0, 0,
4935                 /* IP1_19_17 [3] */
4936                 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
4937                 0, 0, 0,
4938                 /* IP1_16_14 [3] */
4939                 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
4940                 0, 0, 0, 0,
4941                 /* IP1_13_11 [3] */
4942                 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
4943                 0, 0, 0, 0,
4944                 /* IP1_10_8 [3] */
4945                 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
4946                 0, 0, 0, 0,
4947                 /* IP1_7_6 [2] */
4948                 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
4949                 /* IP1_5_4 [2] */
4950                 FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0,
4951                 /* IP1_3_2 [2] */
4952                 FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0,
4953                 /* IP1_1_0 [2] */
4954                 FN_A7, FN_MSIOF1_SYNC,
4955                 0, 0, }
4956         },
4957         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4958                              2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
4959                 /* IP2_31_20 [2] */
4960                 0, 0, 0, 0,
4961                 /* IP2_29_27 [3] */
4962                 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
4963                 FN_ATAG0_N, 0, FN_EX_WAIT1,
4964                 0, 0,
4965                 /* IP2_26_25 [2] */
4966                 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
4967                 /* IP2_24_23 [2] */
4968                 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
4969                 /* IP2_22_21 [2] */
4970                 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0,
4971                 /* IP2_20_19 [2] */
4972                 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0,
4973                 /* IP2_18_16 [3] */
4974                 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
4975                 0, 0,
4976                 /* IP2_15_13 [3] */
4977                 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
4978                 0, 0, 0,
4979                 /* IP2_12_0 [3] */
4980                 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
4981                 0, 0, 0,
4982                 /* IP2_9_7 [3] */
4983                 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
4984                 0, 0, 0,
4985                 /* IP2_6_5 [2] */
4986                 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
4987                 /* IP2_4_3 [2] */
4988                 FN_A20, FN_SPCLK, 0, 0,
4989                 /* IP2_2_0 [3] */
4990                 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
4991                 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
4992         },
4993         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4994                              1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
4995                 /* IP3_31 [1] */
4996                 0, 0,
4997                 /* IP3_30_28 [3] */
4998                 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
4999                 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
5000                 0, 0, 0,
5001                 /* IP3_27_25 [3] */
5002                 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
5003                 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
5004                 0, 0, 0,
5005                 /* IP3_24_22 [3] */
5006                 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5007                 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
5008                 /* IP3_21_20 [2] */
5009                 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5010                 /* IP3_19_18 [2] */
5011                 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5012                 /* IP3_17_16 [2] */
5013                 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5014                 /* IP3_15_14 [2] */
5015                 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
5016                 /* IP3_13_12 [2] */
5017                 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5018                 /* IP3_11_9 [3] */
5019                 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
5020                 0, 0, 0,
5021                 /* IP3_8_6 [3] */
5022                 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
5023                 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5024                 /* IP3_5_3 [3] */
5025                 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
5026                 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5027                 /* IP3_2_0 [3] */
5028                 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5029                 0, 0, 0, }
5030         },
5031         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5032                              1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
5033                 /* IP4_31 [1] */
5034                 0, 0,
5035                 /* IP4_30_28 [3] */
5036                 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
5037                 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
5038                 0, 0,
5039                 /* IP4_27_26 [2] */
5040                 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5041                 /* IP4_25_24 [2] */
5042                 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5043                 /* IP4_23_22 [2] */
5044                 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5045                 /* IP4_21 [1] */
5046                 FN_SSI_SDATA3, 0,
5047                 /* IP4_20 [1] */
5048                 FN_SSI_WS34, 0,
5049                 /* IP4_19 [1] */
5050                 FN_SSI_SCK34, 0,
5051                 /* IP4_18_16 [3] */
5052                 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
5053                 0, 0, 0, 0,
5054                 /* IP4_15_13 [3] */
5055                 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
5056                 FN_GLO_Q1_D, FN_HCTS1_N_E,
5057                 0, 0,
5058                 /* IP4_12_10 [3] */
5059                 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
5060                 0, 0, 0,
5061                 /* IP4_9_8 [2] */
5062                 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
5063                 /* IP4_7_5 [3] */
5064                 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
5065                 0, 0, 0,
5066                 /* IP4_4_2 [3] */
5067                 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B,
5068                 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
5069                 0, 0, 0,
5070                 /* IP4_1_0 [2] */
5071                 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, }
5072         },
5073         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5074                              3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
5075                 /* IP5_31_29 [3] */
5076                 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
5077                 0, 0, 0, 0, 0,
5078                 /* IP5_28_26 [3] */
5079                 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
5080                 0, 0, 0, 0,
5081                 /* IP5_25_24 [2] */
5082                 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5083                 /* IP5_23_22 [2] */
5084                 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5085                 /* IP5_21_20 [2] */
5086                 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5087                 /* IP5_19_17 [3] */
5088                 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
5089                 0, 0, 0, 0,
5090                 /* IP5_16_15 [2] */
5091                 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5092                 /* IP5_14_12 [3] */
5093                 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
5094                 0, 0, 0, 0,
5095                 /* IP5_11_9 [3] */
5096                 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
5097                 0, 0, 0, 0,
5098                 /* IP5_8_6 [3] */
5099                 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
5100                 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
5101                 0, 0,
5102                 /* IP5_5_3 [3] */
5103                 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
5104                 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
5105                 0, 0,
5106                 /* IP5_2_0 [3] */
5107                 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
5108                 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
5109                 0, 0, }
5110         },
5111         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5112                              2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
5113                 /* IP6_31_30 [2] */
5114                 0, 0, 0, 0,
5115                 /* IP6_29_27 [3] */
5116                 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
5117                 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
5118                 0, 0, 0,
5119                 /* IP6_26_24 [3] */
5120                 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
5121                 FN_GPS_CLK_C, FN_GPS_CLK_D,
5122                 0, 0, 0,
5123                 /* IP6_23_21 [3] */
5124                 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
5125                 FN_SDA1_E, FN_MSIOF2_SYNC_E,
5126                 0, 0, 0,
5127                 /* IP6_20_19 [2] */
5128                 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
5129                 /* IP6_18_16 [3] */
5130                 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
5131                 0, 0, 0,
5132                 /* IP6_15_14 [2] */
5133                 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
5134                 /* IP6_13_12 [2] */
5135                 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
5136                 /* IP6_11_10 [2] */
5137                 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
5138                 /* IP6_9_8 [2] */
5139                 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
5140                 /* IP6_7_6 [2] */
5141                 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
5142                 /* IP6_5_3 [3] */
5143                 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
5144                 FN_SCIFA2_RXD, FN_FMIN_E,
5145                 0, 0,
5146                 /* IP6_2_0 [3] */
5147                 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
5148                 FN_SCIF_CLK, 0, FN_BPFCLK_E,
5149                 0, 0, }
5150         },
5151         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5152                              2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
5153                 /* IP7_31_30 [2] */
5154                 0, 0, 0, 0,
5155                 /* IP7_29_27 [3] */
5156                 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
5157                 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
5158                 0, 0,
5159                 /* IP7_26_24 [3] */
5160                 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
5161                 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
5162                 0, 0,
5163                 /* IP7_23_21 [3] */
5164                 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
5165                 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
5166                 0, 0,
5167                 /* IP7_20_19 [2] */
5168                 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
5169                 /* IP7_18_17 [2] */
5170                 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
5171                 /* IP7_16_15 [2] */
5172                 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
5173                 /* IP7_14_13 [2] */
5174                 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
5175                 /* IP7_12_11 [2] */
5176                 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
5177                 /* IP7_10_9 [2] */
5178                 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
5179                 /* IP7_8_6 [3] */
5180                 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
5181                 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
5182                 0, 0,
5183                 /* IP7_5_3 [3] */
5184                 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
5185                 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
5186                 0, 0,
5187                 /* IP7_2_0 [3] */
5188                 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
5189                 FN_SCIF_CLK_B, FN_GPS_MAG_D,
5190                 0, 0, }
5191         },
5192         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5193                              1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
5194                 /* IP8_31 [1] */
5195                 0, 0,
5196                 /* IP8_30_28 [3] */
5197                 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
5198                 0, 0, 0,
5199                 /* IP8_27_26 [2] */
5200                 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
5201                 /* IP8_25_24 [2] */
5202                 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
5203                 /* IP8_23_21 [3] */
5204                 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
5205                 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
5206                 0, 0,
5207                 /* IP8_20_18 [3] */
5208                 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
5209                 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
5210                 0, 0,
5211                 /* IP8_17_15 [3] */
5212                 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
5213                 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
5214                 0, 0,
5215                 /* IP8_14_12 [3] */
5216                 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
5217                 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
5218                 0, 0, 0,
5219                 /* IP8_11_9 [3] */
5220                 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
5221                 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
5222                 0, 0, 0,
5223                 /* IP8_8_6 [3] */
5224                 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
5225                 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
5226                 0, 0,
5227                 /* IP8_5_3 [3] */
5228                 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
5229                 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
5230                 0, 0,
5231                 /* IP8_2_0 [3] */
5232                 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
5233                 0, 0, 0, }
5234         },
5235         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5236                              3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
5237                 /* IP9_31_29 [3] */
5238                 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
5239                 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
5240                 /* IP9_28_27 [2] */
5241                 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
5242                 /* IP9_26_25 [2] */
5243                 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
5244                 /* IP9_24_23 [2] */
5245                 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
5246                 /* IP9_22_21 [2] */
5247                 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
5248                 /* IP9_20_19 [2] */
5249                 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
5250                 /* IP9_18_17 [2] */
5251                 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
5252                 /* IP9_16 [1] */
5253                 FN_DU1_DISP, FN_QPOLA,
5254                 /* IP9_15_13 [3] */
5255                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
5256                 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
5257                 0, 0, 0,
5258                 /* IP9_12 [1] */
5259                 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
5260                 /* IP9_11 [1] */
5261                 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
5262                 /* IP9_10_8 [3] */
5263                 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
5264                 FN_TX3_B, FN_SCL2_B, FN_PWM4,
5265                 0, 0,
5266                 /* IP9_7 [1] */
5267                 FN_DU1_DOTCLKOUT0, FN_QCLK,
5268                 /* IP9_6 [1] */
5269                 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
5270                 /* IP9_5_3 [3] */
5271                 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C,
5272                 FN_SCIF3_SCK, FN_SCIFA3_SCK,
5273                 0, 0, 0,
5274                 /* IP9_2_0 [3] */
5275                 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
5276                 0, 0, 0, }
5277         },
5278         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5279                              3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
5280                 /* IP10_31_29 [3] */
5281                 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
5282                 0, 0, 0,
5283                 /* IP10_28_27 [2] */
5284                 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
5285                 /* IP10_26_25 [2] */
5286                 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
5287                 /* IP10_24_22 [3] */
5288                 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
5289                 0, 0, 0,
5290                 /* IP10_21_29 [3] */
5291                 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
5292                 FN_TS_SDATA0_C, FN_ATACS11_N,
5293                 0, 0, 0,
5294                 /* IP10_18_17 [2] */
5295                 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
5296                 /* IP10_16_15 [2] */
5297                 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
5298                 /* IP10_14_12 [3] */
5299                 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
5300                 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
5301                 /* IP10_11_9 [3] */
5302                 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
5303                 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
5304                 0, 0,
5305                 /* IP10_8_6 [3] */
5306                 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
5307                 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
5308                 /* IP10_5_3 [3] */
5309                 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
5310                 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
5311                 /* IP10_2_0 [3] */
5312                 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
5313                 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
5314         },
5315         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5316                              2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
5317                              3, 3, 3, 3, 3) {
5318                 /* IP11_31_30 [2] */
5319                 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
5320                 /* IP11_29_28 [2] */
5321                 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
5322                 /* IP11_27 [1] */
5323                 FN_VI1_DATA7, FN_AVB_MDC,
5324                 /* IP11_26 [1] */
5325                 FN_VI1_DATA6, FN_AVB_MAGIC,
5326                 /* IP11_25 [1] */
5327                 FN_VI1_DATA5, FN_AVB_RX_DV,
5328                 /* IP11_24 [1] */
5329                 FN_VI1_DATA4, FN_AVB_MDIO,
5330                 /* IP11_23 [1] */
5331                 FN_VI1_DATA3, FN_AVB_RX_ER,
5332                 /* IP11_22 [1] */
5333                 FN_VI1_DATA2, FN_AVB_RXD7,
5334                 /* IP11_21 [1] */
5335                 FN_VI1_DATA1, FN_AVB_RXD6,
5336                 /* IP11_20 [1] */
5337                 FN_VI1_DATA0, FN_AVB_RXD5,
5338                 /* IP11_19 [1] */
5339                 FN_VI1_CLK, FN_AVB_RXD4,
5340                 /* IP11_18_17 [2] */
5341                 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
5342                 /* IP11_16_15 [2] */
5343                 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
5344                 /* IP11_14_12 [3] */
5345                 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
5346                 FN_RX4_B, FN_SCIFA4_RXD_B,
5347                 0, 0, 0,
5348                 /* IP11_11_9 [3] */
5349                 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
5350                 FN_TX4_B, FN_SCIFA4_TXD_B,
5351                 0, 0, 0,
5352                 /* IP11_8_6 [3] */
5353                 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
5354                 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
5355                 /* IP11_5_3 [3] */
5356                 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
5357                 0, 0, 0,
5358                 /* IP11_2_0 [3] */
5359                 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
5360                 0, 0, 0, }
5361         },
5362         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5363                              2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
5364                 /* IP12_31_30 [2] */
5365                 0, 0, 0, 0,
5366                 /* IP12_29_27 [3] */
5367                 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
5368                 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
5369                 0, 0, 0,
5370                 /* IP12_26_24 [3] */
5371                 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
5372                 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
5373                 0, 0, 0,
5374                 /* IP12_23_22 [2] */
5375                 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
5376                 /* IP12_21_20 [2] */
5377                 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
5378                 /* IP12_19_18 [2] */
5379                 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
5380                 /* IP12_17_16 [2] */
5381                 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
5382                 /* IP12_15_13 [3] */
5383                 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
5384                 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
5385                 0, 0, 0,
5386                 /* IP12_12_10 [3] */
5387                 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
5388                 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
5389                 0, 0, 0,
5390                 /* IP12_9_7 [3] */
5391                 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
5392                 FN_SDA2_D, FN_MSIOF1_SCK_E,
5393                 0, 0, 0,
5394                 /* IP12_6_4 [3] */
5395                 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
5396                 FN_SCL2_D, FN_MSIOF1_RXD_E,
5397                 0, 0, 0,
5398                 /* IP12_3_2 [2] */
5399                 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
5400                 /* IP12_1_0 [2] */
5401                 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
5402         },
5403         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5404                              1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
5405                              3, 2, 2, 3) {
5406                 /* IP13_31 [1] */
5407                 0, 0,
5408                 /* IP13_30_28 [3] */
5409                 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
5410                 0, 0, 0, 0,
5411                 /* IP13_27 [1] */
5412                 FN_SD1_DATA3, FN_IERX_B,
5413                 /* IP13_26 [1] */
5414                 FN_SD1_DATA2, FN_IECLK_B,
5415                 /* IP13_25 [1] */
5416                 FN_SD1_DATA1, FN_IETX_B,
5417                 /* IP13_24_23 [2] */
5418                 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
5419                 /* IP13_22 [1] */
5420                 FN_SD1_CMD, FN_REMOCON_B,
5421                 /* IP13_21_19 [3] */
5422                 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
5423                 FN_SCIFA5_RXD_B, FN_RX3_C,
5424                 0, 0,
5425                 /* IP13_18_16 [3] */
5426                 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
5427                 FN_SCIFA5_TXD_B, FN_TX3_C,
5428                 0, 0,
5429                 /* IP13_15 [1] */
5430                 FN_SD0_DATA3, FN_SSL_B,
5431                 /* IP13_14 [1] */
5432                 FN_SD0_DATA2, FN_IO3_B,
5433                 /* IP13_13 [1] */
5434                 FN_SD0_DATA1, FN_IO2_B,
5435                 /* IP13_12 [1] */
5436                 FN_SD0_DATA0, FN_MISO_IO1_B,
5437                 /* IP13_11 [1] */
5438                 FN_SD0_CMD, FN_MOSI_IO0_B,
5439                 /* IP13_10 [1] */
5440                 FN_SD0_CLK, FN_SPCLK_B,
5441                 /* IP13_9_7 [3] */
5442                 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
5443                 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
5444                 0, 0, 0,
5445                 /* IP13_6_5 [2] */
5446                 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
5447                 /* IP13_4_3 [2] */
5448                 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
5449                 /* IP13_2_0 [3] */
5450                 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
5451                 FN_ADICLK_B, FN_MSIOF0_SS1_C,
5452                 0, 0, 0, }
5453         },
5454         { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5455                              3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
5456                 /* IP14_31_29 [3] */
5457                 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
5458                 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
5459                 /* IP14_28_26 [3] */
5460                 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
5461                 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
5462                 /* IP14_25_23 [3] */
5463                 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
5464                 0, 0, 0,
5465                 /* IP14_22_20 [3] */
5466                 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
5467                 0, 0, 0,
5468                 /* IP14_19_17 [3] */
5469                 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
5470                 FN_VI1_CLKENB_C, FN_VI1_G1_B,
5471                 0, 0,
5472                 /* IP14_16_14 [3] */
5473                 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
5474                 FN_VI1_CLK_C, FN_VI1_G0_B,
5475                 0, 0,
5476                 /* IP14_13_11 [3] */
5477                 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
5478                 0, 0, 0,
5479                 /* IP14_10_8 [3] */
5480                 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
5481                 0, 0, 0,
5482                 /* IP14_7 [1] */
5483                 FN_SD2_DATA3, FN_MMC_D3,
5484                 /* IP14_6 [1] */
5485                 FN_SD2_DATA2, FN_MMC_D2,
5486                 /* IP14_5 [1] */
5487                 FN_SD2_DATA1, FN_MMC_D1,
5488                 /* IP14_4 [1] */
5489                 FN_SD2_DATA0, FN_MMC_D0,
5490                 /* IP14_3 [1] */
5491                 FN_SD2_CMD, FN_MMC_CMD,
5492                 /* IP14_2 [1] */
5493                 FN_SD2_CLK, FN_MMC_CLK,
5494                 /* IP14_1_0 [2] */
5495                 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
5496         },
5497         { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5498                              2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
5499                 /* IP15_31_30 [2] */
5500                 0, 0, 0, 0,
5501                 /* IP15_29_27 [3] */
5502                 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
5503                 FN_CAN0_TX_B, FN_VI1_DATA5_C,
5504                 0, 0,
5505                 /* IP15_26_24 [3] */
5506                 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
5507                 FN_CAN0_RX_B, FN_VI1_DATA4_C,
5508                 0, 0,
5509                 /* IP15_23_21 [3] */
5510                 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
5511                 FN_TCLK2, FN_VI1_DATA3_C, 0,
5512                 /* IP15_20_18 [3] */
5513                 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
5514                 0, 0, 0,
5515                 /* IP15_17_15 [3] */
5516                 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
5517                 FN_TCLK1, FN_VI1_DATA1_C,
5518                 0, 0,
5519                 /* IP15_14_12 [3] */
5520                 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
5521                 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
5522                 0, 0,
5523                 /* IP15_11_9 [3] */
5524                 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
5525                 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
5526                 0, 0,
5527                 /* IP15_8_6 [3] */
5528                 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
5529                 FN_PWM5_B, FN_SCIFA3_TXD_C,
5530                 0, 0, 0,
5531                 /* IP15_5_4 [2] */
5532                 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
5533                 /* IP15_3_2 [2] */
5534                 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
5535                 /* IP15_1_0 [2] */
5536                 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
5537         },
5538         { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5539                              4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
5540                 /* IP16_31_28 [4] */
5541                 0, 0, 0, 0, 0, 0, 0, 0,
5542                 0, 0, 0, 0, 0, 0, 0, 0,
5543                 /* IP16_27_24 [4] */
5544                 0, 0, 0, 0, 0, 0, 0, 0,
5545                 0, 0, 0, 0, 0, 0, 0, 0,
5546                 /* IP16_23_20 [4] */
5547                 0, 0, 0, 0, 0, 0, 0, 0,
5548                 0, 0, 0, 0, 0, 0, 0, 0,
5549                 /* IP16_19_16 [4] */
5550                 0, 0, 0, 0, 0, 0, 0, 0,
5551                 0, 0, 0, 0, 0, 0, 0, 0,
5552                 /* IP16_15_12 [4] */
5553                 0, 0, 0, 0, 0, 0, 0, 0,
5554                 0, 0, 0, 0, 0, 0, 0, 0,
5555                 /* IP16_11_10 [2] */
5556                 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
5557                 /* IP16_9_8 [2] */
5558                 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
5559                 /* IP16_7_6 [2] */
5560                 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
5561                 /* IP16_5_3 [3] */
5562                 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
5563                 FN_GLO_SS_C, FN_VI1_DATA7_C,
5564                 0, 0, 0,
5565                 /* IP16_2_0 [3] */
5566                 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
5567                 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
5568                 0, 0, 0, }
5569         },
5570         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5571                              1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
5572                              3, 2, 2, 2, 1, 2, 2, 2) {
5573                 /* RESEVED [1] */
5574                 0, 0,
5575                 /* SEL_SCIF1 [2] */
5576                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5577                 /* SEL_SCIFB [2] */
5578                 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
5579                 /* SEL_SCIFB2 [2] */
5580                 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
5581                 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
5582                 /* SEL_SCIFB1 [3] */
5583                 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
5584                 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
5585                 0, 0, 0, 0,
5586                 /* SEL_SCIFA1 [2] */
5587                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
5588                 /* SEL_SSI9 [1] */
5589                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
5590                 /* SEL_SCFA [1] */
5591                 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5592                 /* SEL_QSP [1] */
5593                 FN_SEL_QSP_0, FN_SEL_QSP_1,
5594                 /* SEL_SSI7 [1] */
5595                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
5596                 /* SEL_HSCIF1 [3] */
5597                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
5598                 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
5599                 0, 0, 0,
5600                 /* RESEVED [2] */
5601                 0, 0, 0, 0,
5602                 /* SEL_VI1 [2] */
5603                 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
5604                 /* RESEVED [2] */
5605                 0, 0, 0, 0,
5606                 /* SEL_TMU [1] */
5607                 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5608                 /* SEL_LBS [2] */
5609                 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
5610                 /* SEL_TSIF0 [2] */
5611                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5612                 /* SEL_SOF0 [2] */
5613                 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
5614         },
5615         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5616                              3, 1, 1, 3, 2, 1, 1, 2, 2,
5617                              1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
5618                 /* SEL_SCIF0 [3] */
5619                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
5620                 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
5621                 0, 0, 0,
5622                 /* RESEVED [1] */
5623                 0, 0,
5624                 /* SEL_SCIF [1] */
5625                 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
5626                 /* SEL_CAN0 [3] */
5627                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5628                 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
5629                 0, 0,
5630                 /* SEL_CAN1 [2] */
5631                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
5632                 /* RESEVED [1] */
5633                 0, 0,
5634                 /* SEL_SCIFA2 [1] */
5635                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
5636                 /* SEL_SCIF4 [2] */
5637                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
5638                 /* RESEVED [2] */
5639                 0, 0, 0, 0,
5640                 /* SEL_ADG [1] */
5641                 FN_SEL_ADG_0, FN_SEL_ADG_1,
5642                 /* SEL_FM [3] */
5643                 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
5644                 FN_SEL_FM_3, FN_SEL_FM_4,
5645                 0, 0, 0,
5646                 /* SEL_SCIFA5 [2] */
5647                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
5648                 /* RESEVED [1] */
5649                 0, 0,
5650                 /* SEL_GPS [2] */
5651                 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
5652                 /* SEL_SCIFA4 [2] */
5653                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
5654                 /* SEL_SCIFA3 [2] */
5655                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
5656                 /* SEL_SIM [1] */
5657                 FN_SEL_SIM_0, FN_SEL_SIM_1,
5658                 /* RESEVED [1] */
5659                 0, 0,
5660                 /* SEL_SSI8 [1] */
5661                 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
5662         },
5663         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5664                              2, 2, 2, 2, 2, 2, 2, 2,
5665                              1, 1, 2, 2, 3, 2, 2, 2, 1) {
5666                 /* SEL_HSCIF2 [2] */
5667                 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
5668                 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
5669                 /* SEL_CANCLK [2] */
5670                 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5671                 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
5672                 /* SEL_IIC8 [2] */
5673                 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
5674                 /* SEL_IIC7 [2] */
5675                 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
5676                 /* SEL_IIC4 [2] */
5677                 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
5678                 /* SEL_IIC3 [2] */
5679                 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
5680                 /* SEL_SCIF3 [2] */
5681                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
5682                 /* SEL_IEB [2] */
5683                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5684                 /* SEL_MMC [1] */
5685                 FN_SEL_MMC_0, FN_SEL_MMC_1,
5686                 /* SEL_SCIF5 [1] */
5687                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
5688                 /* RESEVED [2] */
5689                 0, 0, 0, 0,
5690                 /* SEL_IIC2 [2] */
5691                 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5692                 /* SEL_IIC1 [3] */
5693                 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
5694                 FN_SEL_IIC1_4,
5695                 0, 0, 0,
5696                 /* SEL_IIC0 [2] */
5697                 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
5698                 /* RESEVED [2] */
5699                 0, 0, 0, 0,
5700                 /* RESEVED [2] */
5701                 0, 0, 0, 0,
5702                 /* RESEVED [1] */
5703                 0, 0, }
5704         },
5705         { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
5706                              3, 2, 2, 1, 1, 1, 1, 3, 2,
5707                              2, 3, 1, 1, 1, 2, 2, 2, 2) {
5708                 /* SEL_SOF1 [3] */
5709                 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
5710                 FN_SEL_SOF1_4,
5711                 0, 0, 0,
5712                 /* SEL_HSCIF0 [2] */
5713                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
5714                 /* SEL_DIS [2] */
5715                 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
5716                 /* RESEVED [1] */
5717                 0, 0,
5718                 /* SEL_RAD [1] */
5719                 FN_SEL_RAD_0, FN_SEL_RAD_1,
5720                 /* SEL_RCN [1] */
5721                 FN_SEL_RCN_0, FN_SEL_RCN_1,
5722                 /* SEL_RSP [1] */
5723                 FN_SEL_RSP_0, FN_SEL_RSP_1,
5724                 /* SEL_SCIF2 [3] */
5725                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
5726                 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
5727                 0, 0, 0,
5728                 /* RESEVED [2] */
5729                 0, 0, 0, 0,
5730                 /* RESEVED [2] */
5731                 0, 0, 0, 0,
5732                 /* SEL_SOF2 [3] */
5733                 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
5734                 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
5735                 0, 0, 0,
5736                 /* RESEVED [1] */
5737                 0, 0,
5738                 /* SEL_SSI1 [1] */
5739                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
5740                 /* SEL_SSI0 [1] */
5741                 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
5742                 /* SEL_SSP [2] */
5743                 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
5744                 /* RESEVED [2] */
5745                 0, 0, 0, 0,
5746                 /* RESEVED [2] */
5747                 0, 0, 0, 0,
5748                 /* RESEVED [2] */
5749                 0, 0, 0, 0, }
5750         },
5751         { },
5752 };
5753
5754 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
5755         .name = "r8a77910_pfc",
5756         .unlock_reg = 0xe6060000, /* PMMR */
5757
5758         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5759
5760         .pins = pinmux_pins,
5761         .nr_pins = ARRAY_SIZE(pinmux_pins),
5762         .groups = pinmux_groups,
5763         .nr_groups = ARRAY_SIZE(pinmux_groups),
5764         .functions = pinmux_functions,
5765         .nr_functions = ARRAY_SIZE(pinmux_functions),
5766
5767         .cfg_regs = pinmux_config_regs,
5768
5769         .gpio_data = pinmux_data,
5770         .gpio_data_size = ARRAY_SIZE(pinmux_data),
5771 };