drivers/pinctrl/sh-pfc/pfc-r8a7779.c

   1 /*
   2  * r8a7779 processor support - PFC hardware block
   3  *
   4  * Copyright (C) 2011, 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/platform_data/gpio-rcar.h>
  24
  25 #include "sh_pfc.h"
  26
  27 #define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
  28
  29 #define PORT_GP_32(bank, fn, sfx)                                       \
  30         PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
  31         PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
  32         PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
  33         PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
  34         PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
  35         PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
  36         PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
  37         PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
  38         PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
  39         PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
  40         PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
  41         PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
  42         PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
  43         PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),     \
  44         PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),     \
  45         PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
  46
  47 #define PORT_GP_32_9(bank, fn, sfx)                                     \
  48         PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx),       \
  49         PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx),       \
  50         PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx),       \
  51         PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx),       \
  52         PORT_GP_1(bank, 8, fn, sfx)
  53
  54 #define PORT_GP_32_REV(bank, fn, sfx)                                   \
  55         PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),     \
  56         PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),     \
  57         PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),     \
  58         PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),     \
  59         PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),     \
  60         PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),     \
  61         PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),     \
  62         PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),     \
  63         PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),     \
  64         PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),     \
  65         PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),     \
  66         PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),     \
  67         PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),     \
  68         PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),     \
  69         PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),     \
  70         PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
  71
  72 #define CPU_ALL_PORT(fn, sfx)                                           \
  73         PORT_GP_32(0, fn, sfx),                                         \
  74         PORT_GP_32(1, fn, sfx),                                         \
  75         PORT_GP_32(2, fn, sfx),                                         \
  76         PORT_GP_32(3, fn, sfx),                                         \
  77         PORT_GP_32(4, fn, sfx),                                         \
  78         PORT_GP_32(5, fn, sfx),                                         \
  79         PORT_GP_32_9(6, fn, sfx)
  80
  81 #define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
  82
  83 #define _GP_GPIO(bank, pin, _name, sfx)                                 \
  84         [RCAR_GP_PIN(bank, pin)] = {                                    \
  85                 .name = __stringify(_name),                             \
  86                 .enum_id = _name##_DATA,                                \
  87         }
  88
  89 #define _GP_DATA(bank, pin, name, sfx)                                  \
  90         PINMUX_DATA(name##_DATA, name##_FN)
  91
  92 #define GP_ALL(str)             CPU_ALL_PORT(_GP_PORT_ALL, str)
  93 #define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, unused)
  94 #define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, unused)
  95
  96 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
  97 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
  98                                                           FN_##ipsr, FN_##fn)
  99
 100 enum {
 101         PINMUX_RESERVED = 0,
 102
 103         PINMUX_DATA_BEGIN,
 104         GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
 105         PINMUX_DATA_END,
 106
 107         PINMUX_FUNCTION_BEGIN,
 108         GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
 109
 110         /* GPSR0 */
 111         FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
 112         FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
 113         FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
 114         FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
 115         FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
 116         FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
 117         FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
 118         FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
 119
 120         /* GPSR1 */
 121         FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,
 122         FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14,
 123         FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20,
 124         FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26,
 125         FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0,
 126         FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
 127         FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11,
 128         FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21,
 129
 130         /* GPSR2 */
 131         FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23,
 132         FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2,
 133         FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7,
 134         FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14,
 135         FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24,
 136         FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
 137         FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
 138         FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26,
 139
 140         /* GPSR3 */
 141         FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
 142         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18,
 143         FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
 144         FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12,
 145         FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27,
 146         FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23,
 147         FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23,
 148         FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2,
 149
 150         /* GPSR4 */
 151         FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9,
 152         FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20,
 153         FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0,
 154         FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
 155         FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
 156         FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
 157         FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
 158         FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
 159
 160         /* GPSR5 */
 161         FN_A1, FN_A2, FN_A3, FN_A4,
 162         FN_A5, FN_A6, FN_A7, FN_A8,
 163         FN_A9, FN_A10, FN_A11, FN_A12,
 164         FN_A13, FN_A14, FN_A15, FN_A16,
 165         FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0,
 166         FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22,
 167         FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26,
 168         FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5,
 169
 170         /* GPSR6 */
 171         FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15,
 172         FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19,
 173         FN_IP3_20,
 174
 175         /* IPSR0 */
 176         FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
 177         FN_HRTS1, FN_RX4_C,
 178         FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B,
 179         FN_CS0, FN_HSPI_CS2_B,
 180         FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B,
 181         FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
 182         FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
 183         FN_CTS0_B,
 184         FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
 185         FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B,
 186         FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
 187         FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
 188         FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B,
 189         FN_A20, FN_TX5_D, FN_HSPI_TX2_B,
 190         FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
 191         FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
 192         FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
 193         FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
 194         FN_SCIF_CLK, FN_TCLK0_C,
 195
 196         /* IPSR1 */
 197         FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6,
 198         FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7,
 199         FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
 200         FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD,
 201         FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B,
 202         FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9,
 203         FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
 204         FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
 205         FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5,
 206         FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0,
 207         FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B,
 208         FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4,
 209         FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT,
 210         FN_PWM4, FN_RX4, FN_HTX0, FN_TX1,
 211         FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2,
 212         FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34,
 213
 214         /* IPSR2 */
 215         FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
 216         FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
 217         FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1,
 218         FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B,
 219         FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16,
 220         FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1,
 221         FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C,
 222         FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0,
 223         FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS,
 224         FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25,
 225         FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0,
 226         FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1,
 227         FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B,
 228         FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2,
 229         FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4,
 230         FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6,
 231         FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
 232         FN_DREQ1, FN_SCL2, FN_AUDATA2,
 233
 234         /* IPSR3 */
 235         FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
 236         FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3,
 237         FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5,
 238         FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7,
 239         FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1,
 240         FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1,
 241         FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B,
 242         FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18,
 243         FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20,
 244         FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22,
 245         FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
 246         FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK,
 247         FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
 248         FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC,
 249         FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
 250         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX,
 251         FN_TX2_C, FN_SCL2_C, FN_REMOCON,
 252
 253         /* IPSR4 */
 254         FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C,
 255         FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
 256         FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0,
 257         FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E,
 258         FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1,
 259         FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC,
 260         FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3,
 261         FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5,
 262         FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7,
 263         FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B,
 264         FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D,
 265         FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
 266         FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2,
 267         FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4,
 268         FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6,
 269         FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0,
 270         FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5,
 271         FN_SCK0_D,
 272
 273         /* IPSR5 */
 274         FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
 275         FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4,
 276         FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6,
 277         FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D,
 278         FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB,
 279         FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD,
 280         FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC,
 281         FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC,
 282         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
 283         FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
 284         FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D,
 285         FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
 286         FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
 287         FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B,
 288         FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD,
 289         FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D,
 290         FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2,
 291         FN_CAN_DEBUGOUT0, FN_MOUT0,
 292
 293         /* IPSR6 */
 294         FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129,
 295         FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3,
 296         FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6,
 297         FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6,
 298         FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34,
 299         FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C,
 300         FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
 301         FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4,
 302         FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK,
 303         FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5,
 304         FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5,
 305         FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6,
 306         FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
 307
 308         /* IPSR7 */
 309         FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B,
 310         FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
 311         FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
 312         FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B,
 313         FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15,
 314         FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8,
 315         FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK,
 316         FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11,
 317         FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1,
 318         FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1,
 319         FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1,
 320         FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1,
 321         FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2,
 322         FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B,
 323
 324         /* IPSR8 */
 325         FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
 326         FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
 327         FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1,
 328         FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21,
 329         FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0,
 330         FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14,
 331         FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0,
 332         FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7,
 333         FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39,
 334         FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK,
 335         FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK,
 336         FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B,
 337         FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B,
 338         FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
 339         FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B,
 340         FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C,
 341
 342         /* IPSR9 */
 343         FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1,
 344         FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
 345         FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
 346         FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4,
 347         FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5,
 348         FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0,
 349         FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1,
 350         FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6,
 351         FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV,
 352         FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4,
 353         FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5,
 354         FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6,
 355         FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7,
 356         FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
 357
 358         /* IPSR10 */
 359         FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
 360         FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C,
 361         FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C,
 362         FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
 363         FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B,
 364         FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK,
 365         FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK,
 366         FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
 367         FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6,
 368         FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK,
 369         FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO,
 370         FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL,
 371         FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3,
 372         FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
 373         FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4,
 374         FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3,
 375
 376         /* IPSR11 */
 377         FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
 378         FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK,
 379         FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2,
 380         FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3,
 381         FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B,
 382         FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
 383         FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD,
 384         FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B,
 385         FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
 386         FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
 387         FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
 388         FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
 389         FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
 390         FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
 391
 392         /* IPSR12 */
 393         FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
 394         FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3,
 395         FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B,
 396         FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
 397         FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5,
 398         FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B,
 399         FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
 400         FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7,
 401         FN_GPS_MAG, FN_FCE, FN_SCK4_B,
 402
 403         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
 404         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 405         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
 406         FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
 407         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
 408         FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
 409         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
 410         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 411         FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2,
 412         FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
 413         FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
 414         FN_SEL_VI0_0, FN_SEL_VI0_1,
 415         FN_SEL_SD2_0, FN_SEL_SD2_1,
 416         FN_SEL_INT3_0, FN_SEL_INT3_1,
 417         FN_SEL_INT2_0, FN_SEL_INT2_1,
 418         FN_SEL_INT1_0, FN_SEL_INT1_1,
 419         FN_SEL_INT0_0, FN_SEL_INT0_1,
 420         FN_SEL_IE_0, FN_SEL_IE_1,
 421         FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2,
 422         FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
 423         FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2,
 424
 425         FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2,
 426         FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
 427         FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
 428         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
 429         FN_SEL_CAN0_0, FN_SEL_CAN0_1,
 430         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 431         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
 432         FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
 433         FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4,
 434         FN_SEL_ADI_0, FN_SEL_ADI_1,
 435         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 436         FN_SEL_SIM_0, FN_SEL_SIM_1,
 437         FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
 438         FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
 439         FN_SEL_I2C3_0, FN_SEL_I2C3_1,
 440         FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 441         FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
 442         PINMUX_FUNCTION_END,
 443
 444         PINMUX_MARK_BEGIN,
 445         AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK,
 446         A19_MARK,
 447
 448         RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK,
 449         HRTS1_MARK, RX4_C_MARK,
 450         CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK,
 451         CS0_MARK, HSPI_CS2_B_MARK,
 452         CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK,
 453         A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK,
 454         HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK,
 455         A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK,
 456         HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK,
 457         A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK,
 458         A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK,
 459         A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK,
 460         A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK,
 461         A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
 462         BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
 463         ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
 464         USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK,
 465         SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
 466         SCIF_CLK_MARK, TCLK0_C_MARK,
 467
 468         EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
 469         FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK,
 470         EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK,
 471         ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK,
 472         FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK,
 473         HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK,
 474         EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK,
 475         ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK,
 476         TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK,
 477         SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK,
 478         VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK,
 479         SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK,
 480         MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK,
 481         PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK,
 482         SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK,
 483         CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK,
 484
 485         HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK,
 486         SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK,
 487         CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK,
 488         MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK,
 489         SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK,
 490         CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK,
 491         STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK,
 492         SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK,
 493         RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK,
 494         CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK,
 495         CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK,
 496         GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK,
 497         LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK,
 498         AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
 499         DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
 500         DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
 501         DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
 502         DREQ1_MARK, SCL2_MARK, AUDATA2_MARK,
 503
 504         DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK,
 505         AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK,
 506         LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK,
 507         LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK,
 508         LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK,
 509         SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK,
 510         LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK,
 511         AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
 512         DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK,
 513         DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK,
 514         DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 515         TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK,
 516         DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK,
 517         SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
 518         QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
 519         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK,
 520         TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK,
 521
 522         DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK,
 523         DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK,
 524         DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK,
 525         VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK,
 526         AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK,
 527         PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK,
 528         CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK,
 529         VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK,
 530         VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK,
 531         VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK,
 532         SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK,
 533         DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK,
 534         SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK,
 535         VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK,
 536         VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK,
 537         VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK,
 538         VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK,
 539         SCK0_D_MARK,
 540
 541         DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK,
 542         RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK,
 543         DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK,
 544         DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK,
 545         DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK,
 546         HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK,
 547         SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK,
 548         VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK,
 549         VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK,
 550         TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK,
 551         VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK,
 552         GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK,
 553         QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK,
 554         GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK,
 555         RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK,
 556         VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK,
 557         GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK,
 558         USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK,
 559
 560         SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK,
 561         CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK,
 562         MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK,
 563         SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK,
 564         CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK,
 565         SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK,
 566         SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK,
 567         CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK,
 568         SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK,
 569         ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK,
 570         SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK,
 571         SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK,
 572         SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK,
 573
 574         SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK,
 575         SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK,
 576         SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK,
 577         HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK,
 578         SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK,
 579         IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK,
 580         VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK,
 581         ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK,
 582         TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK,
 583         RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK,
 584         SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK,
 585         TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK,
 586         RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK,
 587         RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK,
 588
 589         HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK,
 590         CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK,
 591         CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK,
 592         AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK,
 593         CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK,
 594         CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK,
 595         CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK,
 596         CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK,
 597         AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK,
 598         CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK,
 599         PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK,
 600         VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK,
 601         MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK,
 602         VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK,
 603         MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK,
 604         RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK,
 605
 606         VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK,
 607         VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK,
 608         VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK,
 609         MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK,
 610         VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK,
 611         MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK,
 612         MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK,
 613         IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK,
 614         IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK,
 615         MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK,
 616         ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK,
 617         VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK,
 618         VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK,
 619         VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK,
 620         VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK,
 621
 622         VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK,
 623         ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK,
 624         DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK,
 625         VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK,
 626         ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK,
 627         IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK,
 628         SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK,
 629         TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK,
 630         HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK,
 631         VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK,
 632         TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK,
 633         ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK,
 634         TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK,
 635         VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK,
 636         PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK,
 637         SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK,
 638
 639         VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK,
 640         ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK,
 641         SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK,
 642         SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK,
 643         VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK,
 644         ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK,
 645         SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK,
 646         VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK,
 647         HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
 648         MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
 649         SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
 650         VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK,
 651         DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
 652         VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
 653         DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
 654
 655         VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK,
 656         SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK,
 657         SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK,
 658         VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK,
 659         SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK,
 660         GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK,
 661         VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK,
 662         RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK,
 663         GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK,
 664         PINMUX_MARK_END,
 665 };
 666
 667 static const u16 pinmux_data[] = {
 668         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 669
 670         PINMUX_DATA(AVS1_MARK, FN_AVS1),
 671         PINMUX_DATA(AVS1_MARK, FN_AVS1),
 672         PINMUX_DATA(A17_MARK, FN_A17),
 673         PINMUX_DATA(A18_MARK, FN_A18),
 674         PINMUX_DATA(A19_MARK, FN_A19),
 675
 676         PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0),
 677         PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1),
 678
 679         PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
 680         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
 681         PINMUX_IPSR_DATA(IP0_2_0, PWM1),
 682         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
 683         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
 684         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2),
 685         PINMUX_IPSR_DATA(IP0_5_3, BS),
 686         PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
 687         PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
 688         PINMUX_IPSR_DATA(IP0_5_3, FD2),
 689         PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
 690         PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
 691         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0),
 692         PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
 693         PINMUX_IPSR_DATA(IP0_7_6, A0),
 694         PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
 695         PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3),
 696         PINMUX_IPSR_DATA(IP0_7_6, FD3),
 697         PINMUX_IPSR_DATA(IP0_9_8, A20),
 698         PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
 699         PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
 700         PINMUX_IPSR_DATA(IP0_11_10, A21),
 701         PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3),
 702         PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
 703         PINMUX_IPSR_DATA(IP0_13_12, A22),
 704         PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3),
 705         PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
 706         PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
 707         PINMUX_IPSR_DATA(IP0_15_14, A23),
 708         PINMUX_IPSR_DATA(IP0_15_14, FCLE),
 709         PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
 710         PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
 711         PINMUX_IPSR_DATA(IP0_18_16, A24),
 712         PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
 713         PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
 714         PINMUX_IPSR_DATA(IP0_18_16, FD4),
 715         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
 716         PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
 717         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
 718         PINMUX_IPSR_DATA(IP0_22_19, A25),
 719         PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
 720         PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
 721         PINMUX_IPSR_DATA(IP0_22_19, FD5),
 722         PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
 723         PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
 724         PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
 725         PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
 726         PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1),
 727         PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
 728         PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
 729         PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
 730         PINMUX_IPSR_DATA(IP0_25, CS0),
 731         PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
 732         PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
 733         PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
 734         PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
 735         PINMUX_IPSR_DATA(IP0_30_28, RD_WR),
 736         PINMUX_IPSR_DATA(IP0_30_28, FWE),
 737         PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
 738         PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
 739         PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0),
 740         PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2),
 741
 742         PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
 743         PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
 744         PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
 745         PINMUX_IPSR_DATA(IP1_1_0, FD6),
 746         PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
 747         PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7),
 748         PINMUX_IPSR_DATA(IP1_3_2, FD7),
 749         PINMUX_IPSR_DATA(IP1_6_4, EX_CS2),
 750         PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK),
 751         PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK),
 752         PINMUX_IPSR_DATA(IP1_6_4, FALE),
 753         PINMUX_IPSR_DATA(IP1_6_4, ATACS00),
 754         PINMUX_IPSR_DATA(IP1_10_7, EX_CS3),
 755         PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD),
 756         PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD),
 757         PINMUX_IPSR_DATA(IP1_10_7, FRE),
 758         PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
 759         PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
 760         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1),
 761         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0),
 762         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
 763         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
 764         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
 765         PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
 766         PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
 767         PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
 768         PINMUX_IPSR_DATA(IP1_14_11, FD0),
 769         PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
 770         PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
 771         PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1),
 772         PINMUX_IPSR_DATA(IP1_14_11, HTX1),
 773         PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
 774         PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
 775         PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
 776         PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
 777         PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
 778         PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
 779         PINMUX_IPSR_DATA(IP1_18_15, FD1),
 780         PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
 781         PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
 782         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0),
 783         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4),
 784         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1),
 785         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0),
 786         PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
 787         PINMUX_IPSR_DATA(IP1_20_19, PWM2),
 788         PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0),
 789         PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
 790         PINMUX_IPSR_DATA(IP1_22_21, PWM3),
 791         PINMUX_IPSR_DATA(IP1_22_21, TX4),
 792         PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
 793         PINMUX_IPSR_DATA(IP1_24_23, PWM4),
 794         PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0),
 795         PINMUX_IPSR_DATA(IP1_28_25, HTX0),
 796         PINMUX_IPSR_DATA(IP1_28_25, TX1),
 797         PINMUX_IPSR_DATA(IP1_28_25, SDATA),
 798         PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2),
 799         PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
 800         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
 801         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
 802         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18),
 803         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
 804         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
 805
 806         PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0),
 807         PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0),
 808         PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
 809         PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
 810         PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
 811         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
 812         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
 813         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
 814         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
 815         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
 816         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0),
 817         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0),
 818         PINMUX_IPSR_DATA(IP2_7_4, MTS),
 819         PINMUX_IPSR_DATA(IP2_7_4, PWM5),
 820         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2),
 821         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
 822         PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
 823         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
 824         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
 825         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
 826         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
 827         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
 828         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0),
 829         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0),
 830         PINMUX_IPSR_DATA(IP2_11_8, STM),
 831         PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
 832         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2),
 833         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
 834         PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
 835         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1),
 836         PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
 837         PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0),
 838         PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
 839         PINMUX_IPSR_DATA(IP2_15_12, MDATA),
 840         PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
 841         PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
 842         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1),
 843         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9),
 844         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17),
 845         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25),
 846         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
 847         PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
 848         PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
 849         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0),
 850         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
 851         PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
 852         PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
 853         PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
 854         PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
 855         PINMUX_IPSR_DATA(IP2_21_19, DACK0),
 856         PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
 857         PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
 858         PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
 859         PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2),
 860         PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
 861         PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
 862         PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
 863         PINMUX_IPSR_DATA(IP2_23, LCDOUT3),
 864         PINMUX_IPSR_DATA(IP2_24, DU0_DR4),
 865         PINMUX_IPSR_DATA(IP2_24, LCDOUT4),
 866         PINMUX_IPSR_DATA(IP2_25, DU0_DR5),
 867         PINMUX_IPSR_DATA(IP2_25, LCDOUT5),
 868         PINMUX_IPSR_DATA(IP2_26, DU0_DR6),
 869         PINMUX_IPSR_DATA(IP2_26, LCDOUT6),
 870         PINMUX_IPSR_DATA(IP2_27, DU0_DR7),
 871         PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
 872         PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
 873         PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
 874         PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0),
 875         PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0),
 876         PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
 877
 878         PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
 879         PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
 880         PINMUX_IPSR_DATA(IP3_2_0, DACK1),
 881         PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0),
 882         PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
 883         PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
 884         PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
 885         PINMUX_IPSR_DATA(IP3_4, DU0_DG3),
 886         PINMUX_IPSR_DATA(IP3_4, LCDOUT11),
 887         PINMUX_IPSR_DATA(IP3_5, DU0_DG4),
 888         PINMUX_IPSR_DATA(IP3_5, LCDOUT12),
 889         PINMUX_IPSR_DATA(IP3_6, DU0_DG5),
 890         PINMUX_IPSR_DATA(IP3_6, LCDOUT13),
 891         PINMUX_IPSR_DATA(IP3_7, DU0_DG6),
 892         PINMUX_IPSR_DATA(IP3_7, LCDOUT14),
 893         PINMUX_IPSR_DATA(IP3_8, DU0_DG7),
 894         PINMUX_IPSR_DATA(IP3_8, LCDOUT15),
 895         PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
 896         PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
 897         PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
 898         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0),
 899         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0),
 900         PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
 901         PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
 902         PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
 903         PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
 904         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0),
 905         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
 906         PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
 907         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2),
 908         PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
 909         PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
 910         PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
 911         PINMUX_IPSR_DATA(IP3_16, LCDOUT19),
 912         PINMUX_IPSR_DATA(IP3_17, DU0_DB4),
 913         PINMUX_IPSR_DATA(IP3_17, LCDOUT20),
 914         PINMUX_IPSR_DATA(IP3_18, DU0_DB5),
 915         PINMUX_IPSR_DATA(IP3_18, LCDOUT21),
 916         PINMUX_IPSR_DATA(IP3_19, DU0_DB6),
 917         PINMUX_IPSR_DATA(IP3_19, LCDOUT22),
 918         PINMUX_IPSR_DATA(IP3_20, DU0_DB7),
 919         PINMUX_IPSR_DATA(IP3_20, LCDOUT23),
 920         PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
 921         PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
 922         PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
 923         PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1),
 924         PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
 925         PINMUX_IPSR_DATA(IP3_23, QCLK),
 926         PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
 927         PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
 928         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
 929         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1),
 930         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2),
 931         PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
 932         PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
 933         PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
 934         PINMUX_IPSR_DATA(IP3_27, QSTH_QHS),
 935         PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
 936         PINMUX_IPSR_DATA(IP3_28, QSTB_QHE),
 937         PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 938         PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
 939         PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
 940         PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
 941         PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2),
 942         PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
 943
 944         PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
 945         PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
 946         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
 947         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2),
 948         PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
 949         PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
 950         PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
 951         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2),
 952         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
 953         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
 954         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1),
 955         PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
 956         PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
 957         PINMUX_IPSR_DATA(IP4_7_5, PWM6),
 958         PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
 959         PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
 960         PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
 961         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
 962         PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
 963         PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
 964         PINMUX_IPSR_DATA(IP4_10_8, PWM0),
 965         PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
 966         PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
 967         PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
 968         PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3),
 969         PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
 970         PINMUX_IPSR_DATA(IP4_11, VI2_G0),
 971         PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
 972         PINMUX_IPSR_DATA(IP4_12, VI2_G1),
 973         PINMUX_IPSR_DATA(IP4_13, DU1_DR4),
 974         PINMUX_IPSR_DATA(IP4_13, VI2_G2),
 975         PINMUX_IPSR_DATA(IP4_14, DU1_DR5),
 976         PINMUX_IPSR_DATA(IP4_14, VI2_G3),
 977         PINMUX_IPSR_DATA(IP4_15, DU1_DR6),
 978         PINMUX_IPSR_DATA(IP4_15, VI2_G4),
 979         PINMUX_IPSR_DATA(IP4_16, DU1_DR7),
 980         PINMUX_IPSR_DATA(IP4_16, VI2_G5),
 981         PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
 982         PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
 983         PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1),
 984         PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
 985         PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4),
 986         PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
 987         PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
 988         PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
 989         PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
 990         PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1),
 991         PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
 992         PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0),
 993         PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
 994         PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3),
 995         PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
 996         PINMUX_IPSR_DATA(IP4_23, VI2_G6),
 997         PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
 998         PINMUX_IPSR_DATA(IP4_24, VI2_G7),
 999         PINMUX_IPSR_DATA(IP4_25, DU1_DG4),
1000         PINMUX_IPSR_DATA(IP4_25, VI2_R0),
1001         PINMUX_IPSR_DATA(IP4_26, DU1_DG5),
1002         PINMUX_IPSR_DATA(IP4_26, VI2_R1),
1003         PINMUX_IPSR_DATA(IP4_27, DU1_DG6),
1004         PINMUX_IPSR_DATA(IP4_27, VI2_R2),
1005         PINMUX_IPSR_DATA(IP4_28, DU1_DG7),
1006         PINMUX_IPSR_DATA(IP4_28, VI2_R3),
1007         PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
1008         PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
1009         PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1),
1010         PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
1011         PINMUX_IPSR_DATA(IP4_31_29, TX5),
1012         PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3),
1013
1014         PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
1015         PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
1016         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1),
1017         PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
1018         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0),
1019         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
1020         PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
1021         PINMUX_IPSR_DATA(IP5_3, VI2_R4),
1022         PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
1023         PINMUX_IPSR_DATA(IP5_4, VI2_R5),
1024         PINMUX_IPSR_DATA(IP5_5, DU1_DB4),
1025         PINMUX_IPSR_DATA(IP5_5, VI2_R6),
1026         PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
1027         PINMUX_IPSR_DATA(IP5_6, VI2_R7),
1028         PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
1029         PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3),
1030         PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
1031         PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3),
1032         PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
1033         PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
1034         PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
1035         PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3),
1036         PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
1037         PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
1038         PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3),
1039         PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
1040         PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
1041         PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
1042         PINMUX_IPSR_DATA(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
1043         PINMUX_IPSR_DATA(IP5_16_15, VI2_VSYNC),
1044         PINMUX_IPSR_DATA(IP5_16_15, VI3_VSYNC),
1045         PINMUX_IPSR_DATA(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1046         PINMUX_IPSR_DATA(IP5_20_17, VI2_CLK),
1047         PINMUX_IPSR_DATA(IP5_20_17, TX3_B_IRDA_TX_B),
1048         PINMUX_IPSR_DATA(IP5_20_17, SD3_CD),
1049         PINMUX_IPSR_DATA(IP5_20_17, HSPI_TX1),
1050         PINMUX_IPSR_DATA(IP5_20_17, VI1_CLKENB),
1051         PINMUX_IPSR_DATA(IP5_20_17, VI3_CLKENB),
1052         PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
1053         PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
1054         PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
1055         PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
1056         PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
1057         PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
1058         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0),
1059         PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
1060         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
1061         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3),
1062         PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
1063         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
1064         PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
1065         PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
1066         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
1067         PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
1068         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
1069         PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
1070         PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
1071         PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
1072         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3),
1073         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
1074         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
1075         PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
1076         PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
1077         PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
1078         PINMUX_IPSR_DATA(IP5_30_29, USB_OVC2),
1079         PINMUX_IPSR_DATA(IP5_30_29, CAN_DEBUGOUT0),
1080         PINMUX_IPSR_DATA(IP5_30_29, MOUT0),
1081
1082         PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK0129),
1083         PINMUX_IPSR_DATA(IP6_1_0, CAN_DEBUGOUT1),
1084         PINMUX_IPSR_DATA(IP6_1_0, MOUT1),
1085         PINMUX_IPSR_DATA(IP6_3_2, SSI_WS0129),
1086         PINMUX_IPSR_DATA(IP6_3_2, CAN_DEBUGOUT2),
1087         PINMUX_IPSR_DATA(IP6_3_2, MOUT2),
1088         PINMUX_IPSR_DATA(IP6_5_4, SSI_SDATA0),
1089         PINMUX_IPSR_DATA(IP6_5_4, CAN_DEBUGOUT3),
1090         PINMUX_IPSR_DATA(IP6_5_4, MOUT5),
1091         PINMUX_IPSR_DATA(IP6_7_6, SSI_SDATA1),
1092         PINMUX_IPSR_DATA(IP6_7_6, CAN_DEBUGOUT4),
1093         PINMUX_IPSR_DATA(IP6_7_6, MOUT6),
1094         PINMUX_IPSR_DATA(IP6_8, SSI_SDATA2),
1095         PINMUX_IPSR_DATA(IP6_8, CAN_DEBUGOUT5),
1096         PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
1097         PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
1098         PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
1099         PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0),
1100         PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
1101         PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
1102         PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
1103         PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
1104         PINMUX_IPSR_DATA(IP6_14_12, IETX),
1105         PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
1106         PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
1107         PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
1108         PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
1109         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
1110         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0),
1111         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
1112         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1),
1113         PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
1114         PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
1115         PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
1116         PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
1117         PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
1118         PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
1119         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0),
1120         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3),
1121         PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
1122         PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
1123         PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
1124         PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
1125         PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
1126         PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0),
1127         PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
1128         PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
1129         PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
1130         PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
1131         PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
1132         PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1),
1133
1134         PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
1135         PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
1136         PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0),
1137         PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
1138         PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
1139         PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
1140         PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
1141         PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1),
1142         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
1143         PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
1144         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1),
1145         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
1146         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
1147         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0),
1148         PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
1149         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1),
1150         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
1151         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
1152         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
1153         PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
1154         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1),
1155         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2),
1156         PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
1157         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
1158         PINMUX_IPSR_DATA(IP7_14_13, VSP),
1159         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1),
1160         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
1161         PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
1162         PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
1163         PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1),
1164         PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
1165         PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
1166         PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
1167         PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
1168         PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
1169         PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
1170         PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1),
1171         PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
1172         PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
1173         PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
1174         PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1),
1175         PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
1176         PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
1177         PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
1178         PINMUX_IPSR_DATA(IP7_24_23, TX2_B),
1179         PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
1180         PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
1181         PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
1182         PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1),
1183         PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
1184         PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
1185         PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0),
1186         PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
1187         PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
1188         PINMUX_IPSR_DATA(IP7_30_29, DACK2),
1189         PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1),
1190
1191         PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
1192         PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0),
1193         PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
1194         PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
1195         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
1196         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE12),
1197         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE20),
1198         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
1199         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
1200         PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
1201         PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
1202         PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
1203         PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
1204         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
1205         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE13),
1206         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE21),
1207         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE29),
1208         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE37),
1209         PINMUX_IPSR_DATA(IP8_11_8, HSPI_TX0),
1210         PINMUX_IPSR_DATA(IP8_11_8, TX0),
1211         PINMUX_IPSR_DATA(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
1212         PINMUX_IPSR_DATA(IP8_11_8, AD_DO),
1213         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE6),
1214         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE14),
1215         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE22),
1216         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
1217         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
1218         PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
1219         PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0),
1220         PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
1221         PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
1222         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
1223         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE15),
1224         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE23),
1225         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE31),
1226         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE39),
1227         PINMUX_IPSR_DATA(IP8_17_16, FMCLK),
1228         PINMUX_IPSR_DATA(IP8_17_16, RDS_CLK),
1229         PINMUX_IPSR_DATA(IP8_17_16, PCMOE),
1230         PINMUX_IPSR_DATA(IP8_18, BPFCLK),
1231         PINMUX_IPSR_DATA(IP8_18, PCMWE),
1232         PINMUX_IPSR_DATA(IP8_19, FMIN),
1233         PINMUX_IPSR_DATA(IP8_19, RDS_DATA),
1234         PINMUX_IPSR_DATA(IP8_20, VI0_CLK),
1235         PINMUX_IPSR_DATA(IP8_20, MMC1_CLK),
1236         PINMUX_IPSR_DATA(IP8_22_21, VI0_CLKENB),
1237         PINMUX_IPSR_DATA(IP8_22_21, TX1_C),
1238         PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
1239         PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
1240         PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
1241         PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2),
1242         PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
1243         PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
1244         PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
1245         PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2),
1246         PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
1247         PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
1248         PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
1249         PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
1250         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
1251         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
1252         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3),
1253         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
1254
1255         PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
1256         PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
1257         PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
1258         PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
1259         PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
1260         PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
1261         PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
1262         PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
1263         PINMUX_IPSR_DATA(IP9_5, VI0_DATA3_VI0_B3),
1264         PINMUX_IPSR_DATA(IP9_5, MMC1_D1),
1265         PINMUX_IPSR_DATA(IP9_6, VI0_DATA4_VI0_B4),
1266         PINMUX_IPSR_DATA(IP9_6, MMC1_D2),
1267         PINMUX_IPSR_DATA(IP9_7, VI0_DATA5_VI0_B5),
1268         PINMUX_IPSR_DATA(IP9_7, MMC1_D3),
1269         PINMUX_IPSR_DATA(IP9_9_8, VI0_DATA6_VI0_B6),
1270         PINMUX_IPSR_DATA(IP9_9_8, MMC1_D4),
1271         PINMUX_IPSR_DATA(IP9_9_8, ARM_TRACEDATA_0),
1272         PINMUX_IPSR_DATA(IP9_11_10, VI0_DATA7_VI0_B7),
1273         PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
1274         PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
1275         PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
1276         PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
1277         PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0),
1278         PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
1279         PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
1280         PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
1281         PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0),
1282         PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
1283         PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
1284         PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
1285         PINMUX_IPSR_DATA(IP9_18_16, MMC1_D6),
1286         PINMUX_IPSR_DATA(IP9_18_16, ARM_TRACEDATA_4),
1287         PINMUX_IPSR_DATA(IP9_18_16, TS_SPSYNC0),
1288         PINMUX_IPSR_DATA(IP9_21_19, VI0_G3),
1289         PINMUX_IPSR_DATA(IP9_21_19, ETH_CRS_DV),
1290         PINMUX_IPSR_DATA(IP9_21_19, MMC1_D7),
1291         PINMUX_IPSR_DATA(IP9_21_19, ARM_TRACEDATA_5),
1292         PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
1293         PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
1294         PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
1295         PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
1296         PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
1297         PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
1298         PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
1299         PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
1300         PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
1301         PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
1302         PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
1303         PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
1304         PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
1305         PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
1306         PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
1307         PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
1308         PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
1309
1310         PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
1311         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
1312         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2),
1313         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
1314         PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
1315         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
1316         PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
1317         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
1318         PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
1319         PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
1320         PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
1321         PINMUX_IPSR_DATA(IP10_5_3, DRACK0_C),
1322         PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
1323         PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
1324         PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
1325         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0),
1326         PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
1327         PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
1328         PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
1329         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
1330         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0),
1331         PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
1332         PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
1333         PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
1334         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1),
1335         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
1336         PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
1337         PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
1338         PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
1339         PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
1340         PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
1341         PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1),
1342         PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
1343         PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
1344         PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
1345         PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
1346         PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
1347         PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
1348         PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
1349         PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
1350         PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
1351         PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
1352         PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
1353         PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
1354         PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
1355         PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
1356         PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
1357         PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
1358         PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
1359         PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
1360         PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
1361         PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0),
1362         PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0),
1363         PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
1364         PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
1365         PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
1366         PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
1367         PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
1368         PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
1369         PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
1370         PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
1371         PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
1372         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
1373         PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
1374         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0),
1375
1376         PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
1377         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0),
1378         PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
1379         PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
1380         PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
1381         PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
1382         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0),
1383         PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
1384         PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
1385         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
1386         PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
1387         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0),
1388         PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
1389         PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
1390         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1),
1391         PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
1392         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0),
1393         PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
1394         PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
1395         PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
1396         PINMUX_IPSR_DATA(IP11_14_12, VI1_DATA4_VI1_B4),
1397         PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
1398         PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
1399         PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
1400         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
1401         PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
1402         PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
1403         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0),
1404         PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
1405         PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
1406         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
1407         PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
1408         PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
1409         PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0),
1410         PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
1411         PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
1412         PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
1413         PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
1414         PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0),
1415         PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
1416         PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
1417         PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
1418         PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
1419         PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
1420         PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
1421         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
1422         PINMUX_IPSR_DATA(IP11_26_24, TX2),
1423         PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
1424         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
1425         PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
1426         PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
1427         PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
1428         PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
1429         PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
1430         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0),
1431         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
1432
1433         PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
1434         PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
1435         PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
1436         PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
1437         PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0),
1438         PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
1439         PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
1440         PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
1441         PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
1442         PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
1443         PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2),
1444         PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
1445         PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
1446         PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
1447         PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
1448         PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2),
1449         PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
1450         PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
1451         PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
1452         PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
1453         PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0),
1454         PINMUX_IPSR_DATA(IP12_11_9, FSE),
1455         PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
1456         PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1),
1457         PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
1458         PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
1459         PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0),
1460         PINMUX_IPSR_DATA(IP12_14_12, FRB),
1461         PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1),
1462         PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
1463         PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
1464         PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
1465         PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0),
1466         PINMUX_IPSR_DATA(IP12_17_15, FCE),
1467         PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
1468 };
1469
1470 static struct sh_pfc_pin pinmux_pins[] = {
1471         PINMUX_GPIO_GP_ALL(),
1472 };
1473
1474 /* - DU0 -------------------------------------------------------------------- */
1475 static const unsigned int du0_rgb666_pins[] = {
1476         /* R[7:2], G[7:2], B[7:2] */
1477         RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
1478         RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1479         RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),
1480         RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29),
1481         RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),  RCAR_GP_PIN(6, 6),
1482         RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),  RCAR_GP_PIN(6, 3),
1483 };
1484 static const unsigned int du0_rgb666_mux[] = {
1485         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1486         DU0_DR3_MARK, DU0_DR2_MARK,
1487         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1488         DU0_DG3_MARK, DU0_DG2_MARK,
1489         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1490         DU0_DB3_MARK, DU0_DB2_MARK,
1491 };
1492 static const unsigned int du0_rgb888_pins[] = {
1493         /* R[7:0], G[7:0], B[7:0] */
1494         RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
1495         RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1496         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2),
1497         RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(5, 31),
1498         RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26),
1499         RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),
1500         RCAR_GP_PIN(6, 6),  RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),
1501         RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27),
1502 };
1503 static const unsigned int du0_rgb888_mux[] = {
1504         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1505         DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1506         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1507         DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1508         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1509         DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1510 };
1511 static const unsigned int du0_clk_in_pins[] = {
1512         /* CLKIN */
1513         RCAR_GP_PIN(0, 29),
1514 };
1515 static const unsigned int du0_clk_in_mux[] = {
1516         DU0_DOTCLKIN_MARK,
1517 };
1518 static const unsigned int du0_clk_out_0_pins[] = {
1519         /* CLKOUT */
1520         RCAR_GP_PIN(5, 20),
1521 };
1522 static const unsigned int du0_clk_out_0_mux[] = {
1523         DU0_DOTCLKOUT0_MARK,
1524 };
1525 static const unsigned int du0_clk_out_1_pins[] = {
1526         /* CLKOUT */
1527         RCAR_GP_PIN(0, 30),
1528 };
1529 static const unsigned int du0_clk_out_1_mux[] = {
1530         DU0_DOTCLKOUT1_MARK,
1531 };
1532 static const unsigned int du0_sync_0_pins[] = {
1533         /* VSYNC, HSYNC, DISP */
1534         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31),
1535 };
1536 static const unsigned int du0_sync_0_mux[] = {
1537         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1538         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1539 };
1540 static const unsigned int du0_sync_1_pins[] = {
1541         /* VSYNC, HSYNC, DISP */
1542         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0),
1543 };
1544 static const unsigned int du0_sync_1_mux[] = {
1545         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1546         DU0_DISP_MARK
1547 };
1548 static const unsigned int du0_oddf_pins[] = {
1549         /* ODDF */
1550         RCAR_GP_PIN(0, 31),
1551 };
1552 static const unsigned int du0_oddf_mux[] = {
1553         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1554 };
1555 static const unsigned int du0_cde_pins[] = {
1556         /* CDE */
1557         RCAR_GP_PIN(1, 1),
1558 };
1559 static const unsigned int du0_cde_mux[] = {
1560         DU0_CDE_MARK
1561 };
1562 /* - DU1 -------------------------------------------------------------------- */
1563 static const unsigned int du1_rgb666_pins[] = {
1564         /* R[7:2], G[7:2], B[7:2] */
1565         RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
1566         RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
1567         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
1568         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
1569         RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1570         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20),
1571 };
1572 static const unsigned int du1_rgb666_mux[] = {
1573         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1574         DU1_DR3_MARK, DU1_DR2_MARK,
1575         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1576         DU1_DG3_MARK, DU1_DG2_MARK,
1577         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1578         DU1_DB3_MARK, DU1_DB2_MARK,
1579 };
1580 static const unsigned int du1_rgb888_pins[] = {
1581         /* R[7:0], G[7:0], B[7:0] */
1582         RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
1583         RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
1584         RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 17),
1585         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
1586         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11),
1587         RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24),
1588         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1589         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1590 };
1591 static const unsigned int du1_rgb888_mux[] = {
1592         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1593         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1594         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1595         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1596         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1597         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1598 };
1599 static const unsigned int du1_clk_in_pins[] = {
1600         /* CLKIN */
1601         RCAR_GP_PIN(1, 26),
1602 };
1603 static const unsigned int du1_clk_in_mux[] = {
1604         DU1_DOTCLKIN_MARK,
1605 };
1606 static const unsigned int du1_clk_out_pins[] = {
1607         /* CLKOUT */
1608         RCAR_GP_PIN(1, 27),
1609 };
1610 static const unsigned int du1_clk_out_mux[] = {
1611         DU1_DOTCLKOUT_MARK,
1612 };
1613 static const unsigned int du1_sync_0_pins[] = {
1614         /* VSYNC, HSYNC, DISP */
1615         RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30),
1616 };
1617 static const unsigned int du1_sync_0_mux[] = {
1618         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1619         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1620 };
1621 static const unsigned int du1_sync_1_pins[] = {
1622         /* VSYNC, HSYNC, DISP */
1623         RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31),
1624 };
1625 static const unsigned int du1_sync_1_mux[] = {
1626         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1627         DU1_DISP_MARK
1628 };
1629 static const unsigned int du1_oddf_pins[] = {
1630         /* ODDF */
1631         RCAR_GP_PIN(1, 30),
1632 };
1633 static const unsigned int du1_oddf_mux[] = {
1634         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1635 };
1636 static const unsigned int du1_cde_pins[] = {
1637         /* CDE */
1638         RCAR_GP_PIN(2, 0),
1639 };
1640 static const unsigned int du1_cde_mux[] = {
1641         DU1_CDE_MARK
1642 };
1643 /* - Ether ------------------------------------------------------------------ */
1644 static const unsigned int ether_rmii_pins[] = {
1645         /*
1646          * ETH_TXD0, ETH_TXD1, ETH_TX_EN,  ETH_REFCLK,
1647          * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER,
1648          * ETH_MDIO, ETH_MDC
1649          */
1650         RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18),
1651         RCAR_GP_PIN(2, 26),
1652         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17),
1653         RCAR_GP_PIN(2, 19),
1654         RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28),
1655 };
1656 static const unsigned int ether_rmii_mux[] = {
1657         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REFCLK_MARK,
1658         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
1659         ETH_MDIO_MARK, ETH_MDC_MARK,
1660 };
1661 static const unsigned int ether_link_pins[] = {
1662         /* ETH_LINK */
1663         RCAR_GP_PIN(2, 24),
1664 };
1665 static const unsigned int ether_link_mux[] = {
1666         ETH_LINK_MARK,
1667 };
1668 static const unsigned int ether_magic_pins[] = {
1669         /* ETH_MAGIC */
1670         RCAR_GP_PIN(2, 25),
1671 };
1672 static const unsigned int ether_magic_mux[] = {
1673         ETH_MAGIC_MARK,
1674 };
1675 /* - HSPI0 ------------------------------------------------------------------ */
1676 static const unsigned int hspi0_pins[] = {
1677         /* CLK, CS, RX, TX */
1678         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25),
1679         RCAR_GP_PIN(4, 24),
1680 };
1681 static const unsigned int hspi0_mux[] = {
1682         HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
1683 };
1684 /* - HSPI1 ------------------------------------------------------------------ */
1685 static const unsigned int hspi1_pins[] = {
1686         /* CLK, CS, RX, TX */
1687         RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0),
1688         RCAR_GP_PIN(1, 30),
1689 };
1690 static const unsigned int hspi1_mux[] = {
1691         HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
1692 };
1693 static const unsigned int hspi1_b_pins[] = {
1694         /* CLK, CS, RX, TX */
1695         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29),
1696         RCAR_GP_PIN(2, 28),
1697 };
1698 static const unsigned int hspi1_b_mux[] = {
1699         HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
1700 };
1701 static const unsigned int hspi1_c_pins[] = {
1702         /* CLK, CS, RX, TX */
1703         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16),
1704         RCAR_GP_PIN(4, 15),
1705 };
1706 static const unsigned int hspi1_c_mux[] = {
1707         HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
1708 };
1709 static const unsigned int hspi1_d_pins[] = {
1710         /* CLK, CS, RX, TX */
1711         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8),
1712         RCAR_GP_PIN(3, 7),
1713 };
1714 static const unsigned int hspi1_d_mux[] = {
1715         HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
1716 };
1717 /* - HSPI2 ------------------------------------------------------------------ */
1718 static const unsigned int hspi2_pins[] = {
1719         /* CLK, CS, RX, TX */
1720         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1721         RCAR_GP_PIN(0, 14),
1722 };
1723 static const unsigned int hspi2_mux[] = {
1724         HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
1725 };
1726 static const unsigned int hspi2_b_pins[] = {
1727         /* CLK, CS, RX, TX */
1728         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8),
1729         RCAR_GP_PIN(0, 6),
1730 };
1731 static const unsigned int hspi2_b_mux[] = {
1732         HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
1733 };
1734 /* - INTC ------------------------------------------------------------------- */
1735 static const unsigned int intc_irq0_pins[] = {
1736         /* IRQ */
1737         RCAR_GP_PIN(2, 14),
1738 };
1739 static const unsigned int intc_irq0_mux[] = {
1740         IRQ0_MARK,
1741 };
1742 static const unsigned int intc_irq0_b_pins[] = {
1743         /* IRQ */
1744         RCAR_GP_PIN(4, 13),
1745 };
1746 static const unsigned int intc_irq0_b_mux[] = {
1747         IRQ0_B_MARK,
1748 };
1749 static const unsigned int intc_irq1_pins[] = {
1750         /* IRQ */
1751         RCAR_GP_PIN(2, 15),
1752 };
1753 static const unsigned int intc_irq1_mux[] = {
1754         IRQ1_MARK,
1755 };
1756 static const unsigned int intc_irq1_b_pins[] = {
1757         /* IRQ */
1758         RCAR_GP_PIN(4, 14),
1759 };
1760 static const unsigned int intc_irq1_b_mux[] = {
1761         IRQ1_B_MARK,
1762 };
1763 static const unsigned int intc_irq2_pins[] = {
1764         /* IRQ */
1765         RCAR_GP_PIN(2, 24),
1766 };
1767 static const unsigned int intc_irq2_mux[] = {
1768         IRQ2_MARK,
1769 };
1770 static const unsigned int intc_irq2_b_pins[] = {
1771         /* IRQ */
1772         RCAR_GP_PIN(4, 15),
1773 };
1774 static const unsigned int intc_irq2_b_mux[] = {
1775         IRQ2_B_MARK,
1776 };
1777 static const unsigned int intc_irq3_pins[] = {
1778         /* IRQ */
1779         RCAR_GP_PIN(2, 25),
1780 };
1781 static const unsigned int intc_irq3_mux[] = {
1782         IRQ3_MARK,
1783 };
1784 static const unsigned int intc_irq3_b_pins[] = {
1785         /* IRQ */
1786         RCAR_GP_PIN(4, 16),
1787 };
1788 static const unsigned int intc_irq3_b_mux[] = {
1789         IRQ3_B_MARK,
1790 };
1791 /* - LSBC ------------------------------------------------------------------- */
1792 static const unsigned int lbsc_cs0_pins[] = {
1793         /* CS */
1794         RCAR_GP_PIN(0, 13),
1795 };
1796 static const unsigned int lbsc_cs0_mux[] = {
1797         CS0_MARK,
1798 };
1799 static const unsigned int lbsc_cs1_pins[] = {
1800         /* CS */
1801         RCAR_GP_PIN(0, 14),
1802 };
1803 static const unsigned int lbsc_cs1_mux[] = {
1804         CS1_A26_MARK,
1805 };
1806 static const unsigned int lbsc_ex_cs0_pins[] = {
1807         /* CS */
1808         RCAR_GP_PIN(0, 15),
1809 };
1810 static const unsigned int lbsc_ex_cs0_mux[] = {
1811         EX_CS0_MARK,
1812 };
1813 static const unsigned int lbsc_ex_cs1_pins[] = {
1814         /* CS */
1815         RCAR_GP_PIN(0, 16),
1816 };
1817 static const unsigned int lbsc_ex_cs1_mux[] = {
1818         EX_CS1_MARK,
1819 };
1820 static const unsigned int lbsc_ex_cs2_pins[] = {
1821         /* CS */
1822         RCAR_GP_PIN(0, 17),
1823 };
1824 static const unsigned int lbsc_ex_cs2_mux[] = {
1825         EX_CS2_MARK,
1826 };
1827 static const unsigned int lbsc_ex_cs3_pins[] = {
1828         /* CS */
1829         RCAR_GP_PIN(0, 18),
1830 };
1831 static const unsigned int lbsc_ex_cs3_mux[] = {
1832         EX_CS3_MARK,
1833 };
1834 static const unsigned int lbsc_ex_cs4_pins[] = {
1835         /* CS */
1836         RCAR_GP_PIN(0, 19),
1837 };
1838 static const unsigned int lbsc_ex_cs4_mux[] = {
1839         EX_CS4_MARK,
1840 };
1841 static const unsigned int lbsc_ex_cs5_pins[] = {
1842         /* CS */
1843         RCAR_GP_PIN(0, 20),
1844 };
1845 static const unsigned int lbsc_ex_cs5_mux[] = {
1846         EX_CS5_MARK,
1847 };
1848 /* - MMCIF ------------------------------------------------------------------ */
1849 static const unsigned int mmc0_data1_pins[] = {
1850         /* D[0] */
1851         RCAR_GP_PIN(0, 19),
1852 };
1853 static const unsigned int mmc0_data1_mux[] = {
1854         MMC0_D0_MARK,
1855 };
1856 static const unsigned int mmc0_data4_pins[] = {
1857         /* D[0:3] */
1858         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
1859         RCAR_GP_PIN(0, 2),
1860 };
1861 static const unsigned int mmc0_data4_mux[] = {
1862         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1863 };
1864 static const unsigned int mmc0_data8_pins[] = {
1865         /* D[0:7] */
1866         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
1867         RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1868         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1869 };
1870 static const unsigned int mmc0_data8_mux[] = {
1871         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1872         MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
1873 };
1874 static const unsigned int mmc0_ctrl_pins[] = {
1875         /* CMD, CLK */
1876         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
1877 };
1878 static const unsigned int mmc0_ctrl_mux[] = {
1879         MMC0_CMD_MARK, MMC0_CLK_MARK,
1880 };
1881 static const unsigned int mmc1_data1_pins[] = {
1882         /* D[0] */
1883         RCAR_GP_PIN(2, 8),
1884 };
1885 static const unsigned int mmc1_data1_mux[] = {
1886         MMC1_D0_MARK,
1887 };
1888 static const unsigned int mmc1_data4_pins[] = {
1889         /* D[0:3] */
1890         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
1891         RCAR_GP_PIN(2, 11),
1892 };
1893 static const unsigned int mmc1_data4_mux[] = {
1894         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1895 };
1896 static const unsigned int mmc1_data8_pins[] = {
1897         /* D[0:7] */
1898         RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10),
1899         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1900         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1901 };
1902 static const unsigned int mmc1_data8_mux[] = {
1903         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1904         MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
1905 };
1906 static const unsigned int mmc1_ctrl_pins[] = {
1907         /* CMD, CLK */
1908         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1),
1909 };
1910 static const unsigned int mmc1_ctrl_mux[] = {
1911         MMC1_CMD_MARK, MMC1_CLK_MARK,
1912 };
1913 /* - SCIF0 ------------------------------------------------------------------ */
1914 static const unsigned int scif0_data_pins[] = {
1915         /* RXD, TXD */
1916         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
1917 };
1918 static const unsigned int scif0_data_mux[] = {
1919         RX0_MARK, TX0_MARK,
1920 };
1921 static const unsigned int scif0_clk_pins[] = {
1922         /* SCK */
1923         RCAR_GP_PIN(4, 28),
1924 };
1925 static const unsigned int scif0_clk_mux[] = {
1926         SCK0_MARK,
1927 };
1928 static const unsigned int scif0_ctrl_pins[] = {
1929         /* RTS, CTS */
1930         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22),
1931 };
1932 static const unsigned int scif0_ctrl_mux[] = {
1933         RTS0_TANS_MARK, CTS0_MARK,
1934 };
1935 static const unsigned int scif0_data_b_pins[] = {
1936         /* RXD, TXD */
1937         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1938 };
1939 static const unsigned int scif0_data_b_mux[] = {
1940         RX0_B_MARK, TX0_B_MARK,
1941 };
1942 static const unsigned int scif0_clk_b_pins[] = {
1943         /* SCK */
1944         RCAR_GP_PIN(1, 1),
1945 };
1946 static const unsigned int scif0_clk_b_mux[] = {
1947         SCK0_B_MARK,
1948 };
1949 static const unsigned int scif0_ctrl_b_pins[] = {
1950         /* RTS, CTS */
1951         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
1952 };
1953 static const unsigned int scif0_ctrl_b_mux[] = {
1954         RTS0_B_TANS_B_MARK, CTS0_B_MARK,
1955 };
1956 static const unsigned int scif0_data_c_pins[] = {
1957         /* RXD, TXD */
1958         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
1959 };
1960 static const unsigned int scif0_data_c_mux[] = {
1961         RX0_C_MARK, TX0_C_MARK,
1962 };
1963 static const unsigned int scif0_clk_c_pins[] = {
1964         /* SCK */
1965         RCAR_GP_PIN(4, 17),
1966 };
1967 static const unsigned int scif0_clk_c_mux[] = {
1968         SCK0_C_MARK,
1969 };
1970 static const unsigned int scif0_ctrl_c_pins[] = {
1971         /* RTS, CTS */
1972         RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1973 };
1974 static const unsigned int scif0_ctrl_c_mux[] = {
1975         RTS0_C_TANS_C_MARK, CTS0_C_MARK,
1976 };
1977 static const unsigned int scif0_data_d_pins[] = {
1978         /* RXD, TXD */
1979         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1980 };
1981 static const unsigned int scif0_data_d_mux[] = {
1982         RX0_D_MARK, TX0_D_MARK,
1983 };
1984 static const unsigned int scif0_clk_d_pins[] = {
1985         /* SCK */
1986         RCAR_GP_PIN(1, 18),
1987 };
1988 static const unsigned int scif0_clk_d_mux[] = {
1989         SCK0_D_MARK,
1990 };
1991 static const unsigned int scif0_ctrl_d_pins[] = {
1992         /* RTS, CTS */
1993         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3),
1994 };
1995 static const unsigned int scif0_ctrl_d_mux[] = {
1996         RTS0_D_TANS_D_MARK, CTS0_D_MARK,
1997 };
1998 /* - SCIF1 ------------------------------------------------------------------ */
1999 static const unsigned int scif1_data_pins[] = {
2000         /* RXD, TXD */
2001         RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
2002 };
2003 static const unsigned int scif1_data_mux[] = {
2004         RX1_MARK, TX1_MARK,
2005 };
2006 static const unsigned int scif1_clk_pins[] = {
2007         /* SCK */
2008         RCAR_GP_PIN(4, 17),
2009 };
2010 static const unsigned int scif1_clk_mux[] = {
2011         SCK1_MARK,
2012 };
2013 static const unsigned int scif1_ctrl_pins[] = {
2014         /* RTS, CTS */
2015         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2016 };
2017 static const unsigned int scif1_ctrl_mux[] = {
2018         RTS1_TANS_MARK, CTS1_MARK,
2019 };
2020 static const unsigned int scif1_data_b_pins[] = {
2021         /* RXD, TXD */
2022         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18),
2023 };
2024 static const unsigned int scif1_data_b_mux[] = {
2025         RX1_B_MARK, TX1_B_MARK,
2026 };
2027 static const unsigned int scif1_clk_b_pins[] = {
2028         /* SCK */
2029         RCAR_GP_PIN(3, 17),
2030 };
2031 static const unsigned int scif1_clk_b_mux[] = {
2032         SCK1_B_MARK,
2033 };
2034 static const unsigned int scif1_ctrl_b_pins[] = {
2035         /* RTS, CTS */
2036         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
2037 };
2038 static const unsigned int scif1_ctrl_b_mux[] = {
2039         RTS1_B_TANS_B_MARK, CTS1_B_MARK,
2040 };
2041 static const unsigned int scif1_data_c_pins[] = {
2042         /* RXD, TXD */
2043         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
2044 };
2045 static const unsigned int scif1_data_c_mux[] = {
2046         RX1_C_MARK, TX1_C_MARK,
2047 };
2048 static const unsigned int scif1_clk_c_pins[] = {
2049         /* SCK */
2050         RCAR_GP_PIN(2, 22),
2051 };
2052 static const unsigned int scif1_clk_c_mux[] = {
2053         SCK1_C_MARK,
2054 };
2055 static const unsigned int scif1_ctrl_c_pins[] = {
2056         /* RTS, CTS */
2057         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2058 };
2059 static const unsigned int scif1_ctrl_c_mux[] = {
2060         RTS1_C_TANS_C_MARK, CTS1_C_MARK,
2061 };
2062 /* - SCIF2 ------------------------------------------------------------------ */
2063 static const unsigned int scif2_data_pins[] = {
2064         /* RXD, TXD */
2065         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9),
2066 };
2067 static const unsigned int scif2_data_mux[] = {
2068         RX2_MARK, TX2_MARK,
2069 };
2070 static const unsigned int scif2_clk_pins[] = {
2071         /* SCK */
2072         RCAR_GP_PIN(3, 11),
2073 };
2074 static const unsigned int scif2_clk_mux[] = {
2075         SCK2_MARK,
2076 };
2077 static const unsigned int scif2_data_b_pins[] = {
2078         /* RXD, TXD */
2079         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23),
2080 };
2081 static const unsigned int scif2_data_b_mux[] = {
2082         RX2_B_MARK, TX2_B_MARK,
2083 };
2084 static const unsigned int scif2_clk_b_pins[] = {
2085         /* SCK */
2086         RCAR_GP_PIN(3, 22),
2087 };
2088 static const unsigned int scif2_clk_b_mux[] = {
2089         SCK2_B_MARK,
2090 };
2091 static const unsigned int scif2_data_c_pins[] = {
2092         /* RXD, TXD */
2093         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31),
2094 };
2095 static const unsigned int scif2_data_c_mux[] = {
2096         RX2_C_MARK, TX2_C_MARK,
2097 };
2098 static const unsigned int scif2_clk_c_pins[] = {
2099         /* SCK */
2100         RCAR_GP_PIN(1, 0),
2101 };
2102 static const unsigned int scif2_clk_c_mux[] = {
2103         SCK2_C_MARK,
2104 };
2105 static const unsigned int scif2_data_d_pins[] = {
2106         /* RXD, TXD */
2107         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
2108 };
2109 static const unsigned int scif2_data_d_mux[] = {
2110         RX2_D_MARK, TX2_D_MARK,
2111 };
2112 static const unsigned int scif2_clk_d_pins[] = {
2113         /* SCK */
2114         RCAR_GP_PIN(1, 31),
2115 };
2116 static const unsigned int scif2_clk_d_mux[] = {
2117         SCK2_D_MARK,
2118 };
2119 static const unsigned int scif2_data_e_pins[] = {
2120         /* RXD, TXD */
2121         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
2122 };
2123 static const unsigned int scif2_data_e_mux[] = {
2124         RX2_E_MARK, TX2_E_MARK,
2125 };
2126 /* - SCIF3 ------------------------------------------------------------------ */
2127 static const unsigned int scif3_data_pins[] = {
2128         /* RXD, TXD */
2129         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
2130 };
2131 static const unsigned int scif3_data_mux[] = {
2132         RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
2133 };
2134 static const unsigned int scif3_clk_pins[] = {
2135         /* SCK */
2136         RCAR_GP_PIN(4, 7),
2137 };
2138 static const unsigned int scif3_clk_mux[] = {
2139         SCK3_MARK,
2140 };
2141
2142 static const unsigned int scif3_data_b_pins[] = {
2143         /* RXD, TXD */
2144         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
2145 };
2146 static const unsigned int scif3_data_b_mux[] = {
2147         RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
2148 };
2149 static const unsigned int scif3_data_c_pins[] = {
2150         /* RXD, TXD */
2151         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12),
2152 };
2153 static const unsigned int scif3_data_c_mux[] = {
2154         RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
2155 };
2156 static const unsigned int scif3_data_d_pins[] = {
2157         /* RXD, TXD */
2158         RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29),
2159 };
2160 static const unsigned int scif3_data_d_mux[] = {
2161         RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
2162 };
2163 static const unsigned int scif3_data_e_pins[] = {
2164         /* RXD, TXD */
2165         RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2166 };
2167 static const unsigned int scif3_data_e_mux[] = {
2168         RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
2169 };
2170 static const unsigned int scif3_clk_e_pins[] = {
2171         /* SCK */
2172         RCAR_GP_PIN(1, 10),
2173 };
2174 static const unsigned int scif3_clk_e_mux[] = {
2175         SCK3_E_MARK,
2176 };
2177 /* - SCIF4 ------------------------------------------------------------------ */
2178 static const unsigned int scif4_data_pins[] = {
2179         /* RXD, TXD */
2180         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26),
2181 };
2182 static const unsigned int scif4_data_mux[] = {
2183         RX4_MARK, TX4_MARK,
2184 };
2185 static const unsigned int scif4_clk_pins[] = {
2186         /* SCK */
2187         RCAR_GP_PIN(3, 25),
2188 };
2189 static const unsigned int scif4_clk_mux[] = {
2190         SCK4_MARK,
2191 };
2192 static const unsigned int scif4_data_b_pins[] = {
2193         /* RXD, TXD */
2194         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
2195 };
2196 static const unsigned int scif4_data_b_mux[] = {
2197         RX4_B_MARK, TX4_B_MARK,
2198 };
2199 static const unsigned int scif4_clk_b_pins[] = {
2200         /* SCK */
2201         RCAR_GP_PIN(3, 16),
2202 };
2203 static const unsigned int scif4_clk_b_mux[] = {
2204         SCK4_B_MARK,
2205 };
2206 static const unsigned int scif4_data_c_pins[] = {
2207         /* RXD, TXD */
2208         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
2209 };
2210 static const unsigned int scif4_data_c_mux[] = {
2211         RX4_C_MARK, TX4_C_MARK,
2212 };
2213 static const unsigned int scif4_data_d_pins[] = {
2214         /* RXD, TXD */
2215         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2216 };
2217 static const unsigned int scif4_data_d_mux[] = {
2218         RX4_D_MARK, TX4_D_MARK,
2219 };
2220 /* - SCIF5 ------------------------------------------------------------------ */
2221 static const unsigned int scif5_data_pins[] = {
2222         /* RXD, TXD */
2223         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2224 };
2225 static const unsigned int scif5_data_mux[] = {
2226         RX5_MARK, TX5_MARK,
2227 };
2228 static const unsigned int scif5_clk_pins[] = {
2229         /* SCK */
2230         RCAR_GP_PIN(1, 11),
2231 };
2232 static const unsigned int scif5_clk_mux[] = {
2233         SCK5_MARK,
2234 };
2235 static const unsigned int scif5_data_b_pins[] = {
2236         /* RXD, TXD */
2237         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
2238 };
2239 static const unsigned int scif5_data_b_mux[] = {
2240         RX5_B_MARK, TX5_B_MARK,
2241 };
2242 static const unsigned int scif5_clk_b_pins[] = {
2243         /* SCK */
2244         RCAR_GP_PIN(0, 19),
2245 };
2246 static const unsigned int scif5_clk_b_mux[] = {
2247         SCK5_B_MARK,
2248 };
2249 static const unsigned int scif5_data_c_pins[] = {
2250         /* RXD, TXD */
2251         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23),
2252 };
2253 static const unsigned int scif5_data_c_mux[] = {
2254         RX5_C_MARK, TX5_C_MARK,
2255 };
2256 static const unsigned int scif5_clk_c_pins[] = {
2257         /* SCK */
2258         RCAR_GP_PIN(0, 28),
2259 };
2260 static const unsigned int scif5_clk_c_mux[] = {
2261         SCK5_C_MARK,
2262 };
2263 static const unsigned int scif5_data_d_pins[] = {
2264         /* RXD, TXD */
2265         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6),
2266 };
2267 static const unsigned int scif5_data_d_mux[] = {
2268         RX5_D_MARK, TX5_D_MARK,
2269 };
2270 static const unsigned int scif5_clk_d_pins[] = {
2271         /* SCK */
2272         RCAR_GP_PIN(0, 7),
2273 };
2274 static const unsigned int scif5_clk_d_mux[] = {
2275         SCK5_D_MARK,
2276 };
2277 /* - SDHI0 ------------------------------------------------------------------ */
2278 static const unsigned int sdhi0_data1_pins[] = {
2279         /* D0 */
2280         RCAR_GP_PIN(3, 21),
2281 };
2282 static const unsigned int sdhi0_data1_mux[] = {
2283         SD0_DAT0_MARK,
2284 };
2285 static const unsigned int sdhi0_data4_pins[] = {
2286         /* D[0:3] */
2287         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2288         RCAR_GP_PIN(3, 24),
2289 };
2290 static const unsigned int sdhi0_data4_mux[] = {
2291         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2292 };
2293 static const unsigned int sdhi0_ctrl_pins[] = {
2294         /* CMD, CLK */
2295         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17),
2296 };
2297 static const unsigned int sdhi0_ctrl_mux[] = {
2298         SD0_CMD_MARK, SD0_CLK_MARK,
2299 };
2300 static const unsigned int sdhi0_cd_pins[] = {
2301         /* CD */
2302         RCAR_GP_PIN(3, 19),
2303 };
2304 static const unsigned int sdhi0_cd_mux[] = {
2305         SD0_CD_MARK,
2306 };
2307 static const unsigned int sdhi0_wp_pins[] = {
2308         /* WP */
2309         RCAR_GP_PIN(3, 20),
2310 };
2311 static const unsigned int sdhi0_wp_mux[] = {
2312         SD0_WP_MARK,
2313 };
2314 /* - SDHI1 ------------------------------------------------------------------ */
2315 static const unsigned int sdhi1_data1_pins[] = {
2316         /* D0 */
2317         RCAR_GP_PIN(0, 19),
2318 };
2319 static const unsigned int sdhi1_data1_mux[] = {
2320         SD1_DAT0_MARK,
2321 };
2322 static const unsigned int sdhi1_data4_pins[] = {
2323         /* D[0:3] */
2324         RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
2325         RCAR_GP_PIN(0, 2),
2326 };
2327 static const unsigned int sdhi1_data4_mux[] = {
2328         SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2329 };
2330 static const unsigned int sdhi1_ctrl_pins[] = {
2331         /* CMD, CLK */
2332         RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
2333 };
2334 static const unsigned int sdhi1_ctrl_mux[] = {
2335         SD1_CMD_MARK, SD1_CLK_MARK,
2336 };
2337 static const unsigned int sdhi1_cd_pins[] = {
2338         /* CD */
2339         RCAR_GP_PIN(0, 10),
2340 };
2341 static const unsigned int sdhi1_cd_mux[] = {
2342         SD1_CD_MARK,
2343 };
2344 static const unsigned int sdhi1_wp_pins[] = {
2345         /* WP */
2346         RCAR_GP_PIN(0, 11),
2347 };
2348 static const unsigned int sdhi1_wp_mux[] = {
2349         SD1_WP_MARK,
2350 };
2351 /* - SDHI2 ------------------------------------------------------------------ */
2352 static const unsigned int sdhi2_data1_pins[] = {
2353         /* D0 */
2354         RCAR_GP_PIN(3, 1),
2355 };
2356 static const unsigned int sdhi2_data1_mux[] = {
2357         SD2_DAT0_MARK,
2358 };
2359 static const unsigned int sdhi2_data4_pins[] = {
2360         /* D[0:3] */
2361         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2362         RCAR_GP_PIN(3, 4),
2363 };
2364 static const unsigned int sdhi2_data4_mux[] = {
2365         SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2366 };
2367 static const unsigned int sdhi2_ctrl_pins[] = {
2368         /* CMD, CLK */
2369         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
2370 };
2371 static const unsigned int sdhi2_ctrl_mux[] = {
2372         SD2_CMD_MARK, SD2_CLK_MARK,
2373 };
2374 static const unsigned int sdhi2_cd_pins[] = {
2375         /* CD */
2376         RCAR_GP_PIN(3, 7),
2377 };
2378 static const unsigned int sdhi2_cd_mux[] = {
2379         SD2_CD_MARK,
2380 };
2381 static const unsigned int sdhi2_wp_pins[] = {
2382         /* WP */
2383         RCAR_GP_PIN(3, 8),
2384 };
2385 static const unsigned int sdhi2_wp_mux[] = {
2386         SD2_WP_MARK,
2387 };
2388 /* - SDHI3 ------------------------------------------------------------------ */
2389 static const unsigned int sdhi3_data1_pins[] = {
2390         /* D0 */
2391         RCAR_GP_PIN(1, 18),
2392 };
2393 static const unsigned int sdhi3_data1_mux[] = {
2394         SD3_DAT0_MARK,
2395 };
2396 static const unsigned int sdhi3_data4_pins[] = {
2397         /* D[0:3] */
2398         RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
2399         RCAR_GP_PIN(1, 21),
2400 };
2401 static const unsigned int sdhi3_data4_mux[] = {
2402         SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2403 };
2404 static const unsigned int sdhi3_ctrl_pins[] = {
2405         /* CMD, CLK */
2406         RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2407 };
2408 static const unsigned int sdhi3_ctrl_mux[] = {
2409         SD3_CMD_MARK, SD3_CLK_MARK,
2410 };
2411 static const unsigned int sdhi3_cd_pins[] = {
2412         /* CD */
2413         RCAR_GP_PIN(1, 30),
2414 };
2415 static const unsigned int sdhi3_cd_mux[] = {
2416         SD3_CD_MARK,
2417 };
2418 static const unsigned int sdhi3_wp_pins[] = {
2419         /* WP */
2420         RCAR_GP_PIN(2, 0),
2421 };
2422 static const unsigned int sdhi3_wp_mux[] = {
2423         SD3_WP_MARK,
2424 };
2425 /* - USB0 ------------------------------------------------------------------- */
2426 static const unsigned int usb0_pins[] = {
2427         /* PENC */
2428         RCAR_GP_PIN(4, 26),
2429 };
2430 static const unsigned int usb0_mux[] = {
2431         USB_PENC0_MARK,
2432 };
2433 static const unsigned int usb0_ovc_pins[] = {
2434         /* USB_OVC */
2435         RCAR_GP_PIN(4, 22),
2436 };
2437 static const unsigned int usb0_ovc_mux[] = {
2438         USB_OVC0_MARK,
2439 };
2440 /* - USB1 ------------------------------------------------------------------- */
2441 static const unsigned int usb1_pins[] = {
2442         /* PENC */
2443         RCAR_GP_PIN(4, 27),
2444 };
2445 static const unsigned int usb1_mux[] = {
2446         USB_PENC1_MARK,
2447 };
2448 static const unsigned int usb1_ovc_pins[] = {
2449         /* USB_OVC */
2450         RCAR_GP_PIN(4, 24),
2451 };
2452 static const unsigned int usb1_ovc_mux[] = {
2453         USB_OVC1_MARK,
2454 };
2455 /* - USB2 ------------------------------------------------------------------- */
2456 static const unsigned int usb2_pins[] = {
2457         /* PENC */
2458         RCAR_GP_PIN(4, 28),
2459 };
2460 static const unsigned int usb2_mux[] = {
2461         USB_PENC2_MARK,
2462 };
2463 static const unsigned int usb2_ovc_pins[] = {
2464         /* USB_OVC */
2465         RCAR_GP_PIN(3, 29),
2466 };
2467 static const unsigned int usb2_ovc_mux[] = {
2468         USB_OVC2_MARK,
2469 };
2470 /* - VIN0 ------------------------------------------------------------------- */
2471 static const unsigned int vin0_data8_pins[] = {
2472         /* D[0:7] */
2473         RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 8),
2474         RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
2475         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
2476 };
2477 static const unsigned int vin0_data8_mux[] = {
2478         VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
2479         VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2480         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2481 };
2482 static const unsigned int vin0_clk_pins[] = {
2483         /* CLK */
2484         RCAR_GP_PIN(2, 1),
2485 };
2486 static const unsigned int vin0_clk_mux[] = {
2487         VI0_CLK_MARK,
2488 };
2489 static const unsigned int vin0_sync_pins[] = {
2490         /* HSYNC, VSYNC */
2491         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2492 };
2493 static const unsigned int vin0_sync_mux[] = {
2494         VI0_HSYNC_MARK, VI0_VSYNC_MARK,
2495 };
2496 /* - VIN1 ------------------------------------------------------------------- */
2497 static const unsigned int vin1_data8_pins[] = {
2498         /* D[0:7] */
2499         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2500         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
2501         RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
2502 };
2503 static const unsigned int vin1_data8_mux[] = {
2504         VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
2505         VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
2506         VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
2507 };
2508 static const unsigned int vin1_clk_pins[] = {
2509         /* CLK */
2510         RCAR_GP_PIN(2, 30),
2511 };
2512 static const unsigned int vin1_clk_mux[] = {
2513         VI1_CLK_MARK,
2514 };
2515 static const unsigned int vin1_sync_pins[] = {
2516         /* HSYNC, VSYNC */
2517         RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0),
2518 };
2519 static const unsigned int vin1_sync_mux[] = {
2520         VI1_HSYNC_MARK, VI1_VSYNC_MARK,
2521 };
2522 /* - VIN2 ------------------------------------------------------------------- */
2523 static const unsigned int vin2_data8_pins[] = {
2524         /* D[0:7] */
2525         RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
2526         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2527         RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0),
2528 };
2529 static const unsigned int vin2_data8_mux[] = {
2530         VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK,
2531         VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
2532         VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
2533 };
2534 static const unsigned int vin2_clk_pins[] = {
2535         /* CLK */
2536         RCAR_GP_PIN(1, 30),
2537 };
2538 static const unsigned int vin2_clk_mux[] = {
2539         VI2_CLK_MARK,
2540 };
2541 static const unsigned int vin2_sync_pins[] = {
2542         /* HSYNC, VSYNC */
2543         RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
2544 };
2545 static const unsigned int vin2_sync_mux[] = {
2546         VI2_HSYNC_MARK, VI2_VSYNC_MARK,
2547 };
2548 /* - VIN3 ------------------------------------------------------------------- */
2549 static const unsigned int vin3_data8_pins[] = {
2550         /* D[0:7] */
2551         RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2552         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2553         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
2554 };
2555 static const unsigned int vin3_data8_mux[] = {
2556         VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK,
2557         VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK,
2558         VI3_DATA6_MARK, VI3_DATA7_MARK,
2559 };
2560 static const unsigned int vin3_clk_pins[] = {
2561         /* CLK */
2562         RCAR_GP_PIN(2, 31),
2563 };
2564 static const unsigned int vin3_clk_mux[] = {
2565         VI3_CLK_MARK,
2566 };
2567 static const unsigned int vin3_sync_pins[] = {
2568         /* HSYNC, VSYNC */
2569         RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
2570 };
2571 static const unsigned int vin3_sync_mux[] = {
2572         VI3_HSYNC_MARK, VI3_VSYNC_MARK,
2573 };
2574
2575 static const struct sh_pfc_pin_group pinmux_groups[] = {
2576         SH_PFC_PIN_GROUP(du0_rgb666),
2577         SH_PFC_PIN_GROUP(du0_rgb888),
2578         SH_PFC_PIN_GROUP(du0_clk_in),
2579         SH_PFC_PIN_GROUP(du0_clk_out_0),
2580         SH_PFC_PIN_GROUP(du0_clk_out_1),
2581         SH_PFC_PIN_GROUP(du0_sync_0),
2582         SH_PFC_PIN_GROUP(du0_sync_1),
2583         SH_PFC_PIN_GROUP(du0_oddf),
2584         SH_PFC_PIN_GROUP(du0_cde),
2585         SH_PFC_PIN_GROUP(du1_rgb666),
2586         SH_PFC_PIN_GROUP(du1_rgb888),
2587         SH_PFC_PIN_GROUP(du1_clk_in),
2588         SH_PFC_PIN_GROUP(du1_clk_out),
2589         SH_PFC_PIN_GROUP(du1_sync_0),
2590         SH_PFC_PIN_GROUP(du1_sync_1),
2591         SH_PFC_PIN_GROUP(du1_oddf),
2592         SH_PFC_PIN_GROUP(du1_cde),
2593         SH_PFC_PIN_GROUP(ether_rmii),
2594         SH_PFC_PIN_GROUP(ether_link),
2595         SH_PFC_PIN_GROUP(ether_magic),
2596         SH_PFC_PIN_GROUP(hspi0),
2597         SH_PFC_PIN_GROUP(hspi1),
2598         SH_PFC_PIN_GROUP(hspi1_b),
2599         SH_PFC_PIN_GROUP(hspi1_c),
2600         SH_PFC_PIN_GROUP(hspi1_d),
2601         SH_PFC_PIN_GROUP(hspi2),
2602         SH_PFC_PIN_GROUP(hspi2_b),
2603         SH_PFC_PIN_GROUP(intc_irq0),
2604         SH_PFC_PIN_GROUP(intc_irq0_b),
2605         SH_PFC_PIN_GROUP(intc_irq1),
2606         SH_PFC_PIN_GROUP(intc_irq1_b),
2607         SH_PFC_PIN_GROUP(intc_irq2),
2608         SH_PFC_PIN_GROUP(intc_irq2_b),
2609         SH_PFC_PIN_GROUP(intc_irq3),
2610         SH_PFC_PIN_GROUP(intc_irq3_b),
2611         SH_PFC_PIN_GROUP(lbsc_cs0),
2612         SH_PFC_PIN_GROUP(lbsc_cs1),
2613         SH_PFC_PIN_GROUP(lbsc_ex_cs0),
2614         SH_PFC_PIN_GROUP(lbsc_ex_cs1),
2615         SH_PFC_PIN_GROUP(lbsc_ex_cs2),
2616         SH_PFC_PIN_GROUP(lbsc_ex_cs3),
2617         SH_PFC_PIN_GROUP(lbsc_ex_cs4),
2618         SH_PFC_PIN_GROUP(lbsc_ex_cs5),
2619         SH_PFC_PIN_GROUP(mmc0_data1),
2620         SH_PFC_PIN_GROUP(mmc0_data4),
2621         SH_PFC_PIN_GROUP(mmc0_data8),
2622         SH_PFC_PIN_GROUP(mmc0_ctrl),
2623         SH_PFC_PIN_GROUP(mmc1_data1),
2624         SH_PFC_PIN_GROUP(mmc1_data4),
2625         SH_PFC_PIN_GROUP(mmc1_data8),
2626         SH_PFC_PIN_GROUP(mmc1_ctrl),
2627         SH_PFC_PIN_GROUP(scif0_data),
2628         SH_PFC_PIN_GROUP(scif0_clk),
2629         SH_PFC_PIN_GROUP(scif0_ctrl),
2630         SH_PFC_PIN_GROUP(scif0_data_b),
2631         SH_PFC_PIN_GROUP(scif0_clk_b),
2632         SH_PFC_PIN_GROUP(scif0_ctrl_b),
2633         SH_PFC_PIN_GROUP(scif0_data_c),
2634         SH_PFC_PIN_GROUP(scif0_clk_c),
2635         SH_PFC_PIN_GROUP(scif0_ctrl_c),
2636         SH_PFC_PIN_GROUP(scif0_data_d),
2637         SH_PFC_PIN_GROUP(scif0_clk_d),
2638         SH_PFC_PIN_GROUP(scif0_ctrl_d),
2639         SH_PFC_PIN_GROUP(scif1_data),
2640         SH_PFC_PIN_GROUP(scif1_clk),
2641         SH_PFC_PIN_GROUP(scif1_ctrl),
2642         SH_PFC_PIN_GROUP(scif1_data_b),
2643         SH_PFC_PIN_GROUP(scif1_clk_b),
2644         SH_PFC_PIN_GROUP(scif1_ctrl_b),
2645         SH_PFC_PIN_GROUP(scif1_data_c),
2646         SH_PFC_PIN_GROUP(scif1_clk_c),
2647         SH_PFC_PIN_GROUP(scif1_ctrl_c),
2648         SH_PFC_PIN_GROUP(scif2_data),
2649         SH_PFC_PIN_GROUP(scif2_clk),
2650         SH_PFC_PIN_GROUP(scif2_data_b),
2651         SH_PFC_PIN_GROUP(scif2_clk_b),
2652         SH_PFC_PIN_GROUP(scif2_data_c),
2653         SH_PFC_PIN_GROUP(scif2_clk_c),
2654         SH_PFC_PIN_GROUP(scif2_data_d),
2655         SH_PFC_PIN_GROUP(scif2_clk_d),
2656         SH_PFC_PIN_GROUP(scif2_data_e),
2657         SH_PFC_PIN_GROUP(scif3_data),
2658         SH_PFC_PIN_GROUP(scif3_clk),
2659         SH_PFC_PIN_GROUP(scif3_data_b),
2660         SH_PFC_PIN_GROUP(scif3_data_c),
2661         SH_PFC_PIN_GROUP(scif3_data_d),
2662         SH_PFC_PIN_GROUP(scif3_data_e),
2663         SH_PFC_PIN_GROUP(scif3_clk_e),
2664         SH_PFC_PIN_GROUP(scif4_data),
2665         SH_PFC_PIN_GROUP(scif4_clk),
2666         SH_PFC_PIN_GROUP(scif4_data_b),
2667         SH_PFC_PIN_GROUP(scif4_clk_b),
2668         SH_PFC_PIN_GROUP(scif4_data_c),
2669         SH_PFC_PIN_GROUP(scif4_data_d),
2670         SH_PFC_PIN_GROUP(scif5_data),
2671         SH_PFC_PIN_GROUP(scif5_clk),
2672         SH_PFC_PIN_GROUP(scif5_data_b),
2673         SH_PFC_PIN_GROUP(scif5_clk_b),
2674         SH_PFC_PIN_GROUP(scif5_data_c),
2675         SH_PFC_PIN_GROUP(scif5_clk_c),
2676         SH_PFC_PIN_GROUP(scif5_data_d),
2677         SH_PFC_PIN_GROUP(scif5_clk_d),
2678         SH_PFC_PIN_GROUP(sdhi0_data1),
2679         SH_PFC_PIN_GROUP(sdhi0_data4),
2680         SH_PFC_PIN_GROUP(sdhi0_ctrl),
2681         SH_PFC_PIN_GROUP(sdhi0_cd),
2682         SH_PFC_PIN_GROUP(sdhi0_wp),
2683         SH_PFC_PIN_GROUP(sdhi1_data1),
2684         SH_PFC_PIN_GROUP(sdhi1_data4),
2685         SH_PFC_PIN_GROUP(sdhi1_ctrl),
2686         SH_PFC_PIN_GROUP(sdhi1_cd),
2687         SH_PFC_PIN_GROUP(sdhi1_wp),
2688         SH_PFC_PIN_GROUP(sdhi2_data1),
2689         SH_PFC_PIN_GROUP(sdhi2_data4),
2690         SH_PFC_PIN_GROUP(sdhi2_ctrl),
2691         SH_PFC_PIN_GROUP(sdhi2_cd),
2692         SH_PFC_PIN_GROUP(sdhi2_wp),
2693         SH_PFC_PIN_GROUP(sdhi3_data1),
2694         SH_PFC_PIN_GROUP(sdhi3_data4),
2695         SH_PFC_PIN_GROUP(sdhi3_ctrl),
2696         SH_PFC_PIN_GROUP(sdhi3_cd),
2697         SH_PFC_PIN_GROUP(sdhi3_wp),
2698         SH_PFC_PIN_GROUP(usb0),
2699         SH_PFC_PIN_GROUP(usb0_ovc),
2700         SH_PFC_PIN_GROUP(usb1),
2701         SH_PFC_PIN_GROUP(usb1_ovc),
2702         SH_PFC_PIN_GROUP(usb2),
2703         SH_PFC_PIN_GROUP(usb2_ovc),
2704         SH_PFC_PIN_GROUP(vin0_data8),
2705         SH_PFC_PIN_GROUP(vin0_clk),
2706         SH_PFC_PIN_GROUP(vin0_sync),
2707         SH_PFC_PIN_GROUP(vin1_data8),
2708         SH_PFC_PIN_GROUP(vin1_clk),
2709         SH_PFC_PIN_GROUP(vin1_sync),
2710         SH_PFC_PIN_GROUP(vin2_data8),
2711         SH_PFC_PIN_GROUP(vin2_clk),
2712         SH_PFC_PIN_GROUP(vin2_sync),
2713         SH_PFC_PIN_GROUP(vin3_data8),
2714         SH_PFC_PIN_GROUP(vin3_clk),
2715         SH_PFC_PIN_GROUP(vin3_sync),
2716 };
2717
2718 static const char * const du0_groups[] = {
2719         "du0_rgb666",
2720         "du0_rgb888",
2721         "du0_clk_in",
2722         "du0_clk_out_0",
2723         "du0_clk_out_1",
2724         "du0_sync_0",
2725         "du0_sync_1",
2726         "du0_oddf",
2727         "du0_cde",
2728 };
2729
2730 static const char * const du1_groups[] = {
2731         "du1_rgb666",
2732         "du1_rgb888",
2733         "du1_clk_in",
2734         "du1_clk_out",
2735         "du1_sync_0",
2736         "du1_sync_1",
2737         "du1_oddf",
2738         "du1_cde",
2739 };
2740
2741 static const char * const ether_groups[] = {
2742         "ether_rmii",
2743         "ether_link",
2744         "ether_magic",
2745 };
2746
2747 static const char * const hspi0_groups[] = {
2748         "hspi0",
2749 };
2750
2751 static const char * const hspi1_groups[] = {
2752         "hspi1",
2753         "hspi1_b",
2754         "hspi1_c",
2755         "hspi1_d",
2756 };
2757
2758 static const char * const hspi2_groups[] = {
2759         "hspi2",
2760         "hspi2_b",
2761 };
2762
2763 static const char * const intc_groups[] = {
2764         "intc_irq0",
2765         "intc_irq0_b",
2766         "intc_irq1",
2767         "intc_irq1_b",
2768         "intc_irq2",
2769         "intc_irq2_b",
2770         "intc_irq3",
2771         "intc_irq3_b",
2772 };
2773
2774 static const char * const lbsc_groups[] = {
2775         "lbsc_cs0",
2776         "lbsc_cs1",
2777         "lbsc_ex_cs0",
2778         "lbsc_ex_cs1",
2779         "lbsc_ex_cs2",
2780         "lbsc_ex_cs3",
2781         "lbsc_ex_cs4",
2782         "lbsc_ex_cs5",
2783 };
2784
2785 static const char * const mmc0_groups[] = {
2786         "mmc0_data1",
2787         "mmc0_data4",
2788         "mmc0_data8",
2789         "mmc0_ctrl",
2790 };
2791
2792 static const char * const mmc1_groups[] = {
2793         "mmc1_data1",
2794         "mmc1_data4",
2795         "mmc1_data8",
2796         "mmc1_ctrl",
2797 };
2798
2799 static const char * const scif0_groups[] = {
2800         "scif0_data",
2801         "scif0_clk",
2802         "scif0_ctrl",
2803         "scif0_data_b",
2804         "scif0_clk_b",
2805         "scif0_ctrl_b",
2806         "scif0_data_c",
2807         "scif0_clk_c",
2808         "scif0_ctrl_c",
2809         "scif0_data_d",
2810         "scif0_clk_d",
2811         "scif0_ctrl_d",
2812 };
2813
2814 static const char * const scif1_groups[] = {
2815         "scif1_data",
2816         "scif1_clk",
2817         "scif1_ctrl",
2818         "scif1_data_b",
2819         "scif1_clk_b",
2820         "scif1_ctrl_b",
2821         "scif1_data_c",
2822         "scif1_clk_c",
2823         "scif1_ctrl_c",
2824 };
2825
2826 static const char * const scif2_groups[] = {
2827         "scif2_data",
2828         "scif2_clk",
2829         "scif2_data_b",
2830         "scif2_clk_b",
2831         "scif2_data_c",
2832         "scif2_clk_c",
2833         "scif2_data_d",
2834         "scif2_clk_d",
2835         "scif2_data_e",
2836 };
2837
2838 static const char * const scif3_groups[] = {
2839         "scif3_data",
2840         "scif3_clk",
2841         "scif3_data_b",
2842         "scif3_data_c",
2843         "scif3_data_d",
2844         "scif3_data_e",
2845         "scif3_clk_e",
2846 };
2847
2848 static const char * const scif4_groups[] = {
2849         "scif4_data",
2850         "scif4_clk",
2851         "scif4_data_b",
2852         "scif4_clk_b",
2853         "scif4_data_c",
2854         "scif4_data_d",
2855 };
2856
2857 static const char * const scif5_groups[] = {
2858         "scif5_data",
2859         "scif5_clk",
2860         "scif5_data_b",
2861         "scif5_clk_b",
2862         "scif5_data_c",
2863         "scif5_clk_c",
2864         "scif5_data_d",
2865         "scif5_clk_d",
2866 };
2867
2868 static const char * const sdhi0_groups[] = {
2869         "sdhi0_data1",
2870         "sdhi0_data4",
2871         "sdhi0_ctrl",
2872         "sdhi0_cd",
2873         "sdhi0_wp",
2874 };
2875
2876 static const char * const sdhi1_groups[] = {
2877         "sdhi1_data1",
2878         "sdhi1_data4",
2879         "sdhi1_ctrl",
2880         "sdhi1_cd",
2881         "sdhi1_wp",
2882 };
2883
2884 static const char * const sdhi2_groups[] = {
2885         "sdhi2_data1",
2886         "sdhi2_data4",
2887         "sdhi2_ctrl",
2888         "sdhi2_cd",
2889         "sdhi2_wp",
2890 };
2891
2892 static const char * const sdhi3_groups[] = {
2893         "sdhi3_data1",
2894         "sdhi3_data4",
2895         "sdhi3_ctrl",
2896         "sdhi3_cd",
2897         "sdhi3_wp",
2898 };
2899
2900 static const char * const usb0_groups[] = {
2901         "usb0",
2902         "usb0_ovc",
2903 };
2904
2905 static const char * const usb1_groups[] = {
2906         "usb1",
2907         "usb1_ovc",
2908 };
2909
2910 static const char * const usb2_groups[] = {
2911         "usb2",
2912         "usb2_ovc",
2913 };
2914
2915 static const char * const vin0_groups[] = {
2916         "vin0_data8",
2917         "vin0_clk",
2918         "vin0_sync",
2919 };
2920
2921 static const char * const vin1_groups[] = {
2922         "vin1_data8",
2923         "vin1_clk",
2924         "vin1_sync",
2925 };
2926
2927 static const char * const vin2_groups[] = {
2928         "vin2_data8",
2929         "vin2_clk",
2930         "vin2_sync",
2931 };
2932
2933 static const char * const vin3_groups[] = {
2934         "vin3_data8",
2935         "vin3_clk",
2936         "vin3_sync",
2937 };
2938
2939 static const struct sh_pfc_function pinmux_functions[] = {
2940         SH_PFC_FUNCTION(du0),
2941         SH_PFC_FUNCTION(du1),
2942         SH_PFC_FUNCTION(ether),
2943         SH_PFC_FUNCTION(hspi0),
2944         SH_PFC_FUNCTION(hspi1),
2945         SH_PFC_FUNCTION(hspi2),
2946         SH_PFC_FUNCTION(intc),
2947         SH_PFC_FUNCTION(lbsc),
2948         SH_PFC_FUNCTION(mmc0),
2949         SH_PFC_FUNCTION(mmc1),
2950         SH_PFC_FUNCTION(sdhi0),
2951         SH_PFC_FUNCTION(sdhi1),
2952         SH_PFC_FUNCTION(sdhi2),
2953         SH_PFC_FUNCTION(sdhi3),
2954         SH_PFC_FUNCTION(scif0),
2955         SH_PFC_FUNCTION(scif1),
2956         SH_PFC_FUNCTION(scif2),
2957         SH_PFC_FUNCTION(scif3),
2958         SH_PFC_FUNCTION(scif4),
2959         SH_PFC_FUNCTION(scif5),
2960         SH_PFC_FUNCTION(usb0),
2961         SH_PFC_FUNCTION(usb1),
2962         SH_PFC_FUNCTION(usb2),
2963         SH_PFC_FUNCTION(vin0),
2964         SH_PFC_FUNCTION(vin1),
2965         SH_PFC_FUNCTION(vin2),
2966         SH_PFC_FUNCTION(vin3),
2967 };
2968
2969 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2970         { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
2971                 GP_0_31_FN, FN_IP3_31_29,
2972                 GP_0_30_FN, FN_IP3_26_24,
2973                 GP_0_29_FN, FN_IP3_22_21,
2974                 GP_0_28_FN, FN_IP3_14_12,
2975                 GP_0_27_FN, FN_IP3_11_9,
2976                 GP_0_26_FN, FN_IP3_2_0,
2977                 GP_0_25_FN, FN_IP2_30_28,
2978                 GP_0_24_FN, FN_IP2_21_19,
2979                 GP_0_23_FN, FN_IP2_18_16,
2980                 GP_0_22_FN, FN_IP0_30_28,
2981                 GP_0_21_FN, FN_IP0_5_3,
2982                 GP_0_20_FN, FN_IP1_18_15,
2983                 GP_0_19_FN, FN_IP1_14_11,
2984                 GP_0_18_FN, FN_IP1_10_7,
2985                 GP_0_17_FN, FN_IP1_6_4,
2986                 GP_0_16_FN, FN_IP1_3_2,
2987                 GP_0_15_FN, FN_IP1_1_0,
2988                 GP_0_14_FN, FN_IP0_27_26,
2989                 GP_0_13_FN, FN_IP0_25,
2990                 GP_0_12_FN, FN_IP0_24_23,
2991                 GP_0_11_FN, FN_IP0_22_19,
2992                 GP_0_10_FN, FN_IP0_18_16,
2993                 GP_0_9_FN, FN_IP0_15_14,
2994                 GP_0_8_FN, FN_IP0_13_12,
2995                 GP_0_7_FN, FN_IP0_11_10,
2996                 GP_0_6_FN, FN_IP0_9_8,
2997                 GP_0_5_FN, FN_A19,
2998                 GP_0_4_FN, FN_A18,
2999                 GP_0_3_FN, FN_A17,
3000                 GP_0_2_FN, FN_IP0_7_6,
3001                 GP_0_1_FN, FN_AVS2,
3002                 GP_0_0_FN, FN_AVS1 }
3003         },
3004         { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
3005                 GP_1_31_FN, FN_IP5_23_21,
3006                 GP_1_30_FN, FN_IP5_20_17,
3007                 GP_1_29_FN, FN_IP5_16_15,
3008                 GP_1_28_FN, FN_IP5_14_13,
3009                 GP_1_27_FN, FN_IP5_12_11,
3010                 GP_1_26_FN, FN_IP5_10_9,
3011                 GP_1_25_FN, FN_IP5_8,
3012                 GP_1_24_FN, FN_IP5_7,
3013                 GP_1_23_FN, FN_IP5_6,
3014                 GP_1_22_FN, FN_IP5_5,
3015                 GP_1_21_FN, FN_IP5_4,
3016                 GP_1_20_FN, FN_IP5_3,
3017                 GP_1_19_FN, FN_IP5_2_0,
3018                 GP_1_18_FN, FN_IP4_31_29,
3019                 GP_1_17_FN, FN_IP4_28,
3020                 GP_1_16_FN, FN_IP4_27,
3021                 GP_1_15_FN, FN_IP4_26,
3022                 GP_1_14_FN, FN_IP4_25,
3023                 GP_1_13_FN, FN_IP4_24,
3024                 GP_1_12_FN, FN_IP4_23,
3025                 GP_1_11_FN, FN_IP4_22_20,
3026                 GP_1_10_FN, FN_IP4_19_17,
3027                 GP_1_9_FN, FN_IP4_16,
3028                 GP_1_8_FN, FN_IP4_15,
3029                 GP_1_7_FN, FN_IP4_14,
3030                 GP_1_6_FN, FN_IP4_13,
3031                 GP_1_5_FN, FN_IP4_12,
3032                 GP_1_4_FN, FN_IP4_11,
3033                 GP_1_3_FN, FN_IP4_10_8,
3034                 GP_1_2_FN, FN_IP4_7_5,
3035                 GP_1_1_FN, FN_IP4_4_2,
3036                 GP_1_0_FN, FN_IP4_1_0 }
3037         },
3038         { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
3039                 GP_2_31_FN, FN_IP10_28_26,
3040                 GP_2_30_FN, FN_IP10_25_24,
3041                 GP_2_29_FN, FN_IP10_23_21,
3042                 GP_2_28_FN, FN_IP10_20_18,
3043                 GP_2_27_FN, FN_IP10_17_15,
3044                 GP_2_26_FN, FN_IP10_14_12,
3045                 GP_2_25_FN, FN_IP10_11_9,
3046                 GP_2_24_FN, FN_IP10_8_6,
3047                 GP_2_23_FN, FN_IP10_5_3,
3048                 GP_2_22_FN, FN_IP10_2_0,
3049                 GP_2_21_FN, FN_IP9_29_28,
3050                 GP_2_20_FN, FN_IP9_27_26,
3051                 GP_2_19_FN, FN_IP9_25_24,
3052                 GP_2_18_FN, FN_IP9_23_22,
3053                 GP_2_17_FN, FN_IP9_21_19,
3054                 GP_2_16_FN, FN_IP9_18_16,
3055                 GP_2_15_FN, FN_IP9_15_14,
3056                 GP_2_14_FN, FN_IP9_13_12,
3057                 GP_2_13_FN, FN_IP9_11_10,
3058                 GP_2_12_FN, FN_IP9_9_8,
3059                 GP_2_11_FN, FN_IP9_7,
3060                 GP_2_10_FN, FN_IP9_6,
3061                 GP_2_9_FN, FN_IP9_5,
3062                 GP_2_8_FN, FN_IP9_4,
3063                 GP_2_7_FN, FN_IP9_3_2,
3064                 GP_2_6_FN, FN_IP9_1_0,
3065                 GP_2_5_FN, FN_IP8_30_28,
3066                 GP_2_4_FN, FN_IP8_27_25,
3067                 GP_2_3_FN, FN_IP8_24_23,
3068                 GP_2_2_FN, FN_IP8_22_21,
3069                 GP_2_1_FN, FN_IP8_20,
3070                 GP_2_0_FN, FN_IP5_27_24 }
3071         },
3072         { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
3073                 GP_3_31_FN, FN_IP6_3_2,
3074                 GP_3_30_FN, FN_IP6_1_0,
3075                 GP_3_29_FN, FN_IP5_30_29,
3076                 GP_3_28_FN, FN_IP5_28,
3077                 GP_3_27_FN, FN_IP1_24_23,
3078                 GP_3_26_FN, FN_IP1_22_21,
3079                 GP_3_25_FN, FN_IP1_20_19,
3080                 GP_3_24_FN, FN_IP7_26_25,
3081                 GP_3_23_FN, FN_IP7_24_23,
3082                 GP_3_22_FN, FN_IP7_22_21,
3083                 GP_3_21_FN, FN_IP7_20_19,
3084                 GP_3_20_FN, FN_IP7_30_29,
3085                 GP_3_19_FN, FN_IP7_28_27,
3086                 GP_3_18_FN, FN_IP7_18_17,
3087                 GP_3_17_FN, FN_IP7_16_15,
3088                 GP_3_16_FN, FN_IP12_17_15,
3089                 GP_3_15_FN, FN_IP12_14_12,
3090                 GP_3_14_FN, FN_IP12_11_9,
3091                 GP_3_13_FN, FN_IP12_8_6,
3092                 GP_3_12_FN, FN_IP12_5_3,
3093                 GP_3_11_FN, FN_IP12_2_0,
3094                 GP_3_10_FN, FN_IP11_29_27,
3095                 GP_3_9_FN, FN_IP11_26_24,
3096                 GP_3_8_FN, FN_IP11_23_21,
3097                 GP_3_7_FN, FN_IP11_20_18,
3098                 GP_3_6_FN, FN_IP11_17_15,
3099                 GP_3_5_FN, FN_IP11_14_12,
3100                 GP_3_4_FN, FN_IP11_11_9,
3101                 GP_3_3_FN, FN_IP11_8_6,
3102                 GP_3_2_FN, FN_IP11_5_3,
3103                 GP_3_1_FN, FN_IP11_2_0,
3104                 GP_3_0_FN, FN_IP10_31_29 }
3105         },
3106         { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
3107                 GP_4_31_FN, FN_IP8_19,
3108                 GP_4_30_FN, FN_IP8_18,
3109                 GP_4_29_FN, FN_IP8_17_16,
3110                 GP_4_28_FN, FN_IP0_2_0,
3111                 GP_4_27_FN, FN_USB_PENC1,
3112                 GP_4_26_FN, FN_USB_PENC0,
3113                 GP_4_25_FN, FN_IP8_15_12,
3114                 GP_4_24_FN, FN_IP8_11_8,
3115                 GP_4_23_FN, FN_IP8_7_4,
3116                 GP_4_22_FN, FN_IP8_3_0,
3117                 GP_4_21_FN, FN_IP2_3_0,
3118                 GP_4_20_FN, FN_IP1_28_25,
3119                 GP_4_19_FN, FN_IP2_15_12,
3120                 GP_4_18_FN, FN_IP2_11_8,
3121                 GP_4_17_FN, FN_IP2_7_4,
3122                 GP_4_16_FN, FN_IP7_14_13,
3123                 GP_4_15_FN, FN_IP7_12_10,
3124                 GP_4_14_FN, FN_IP7_9_7,
3125                 GP_4_13_FN, FN_IP7_6_4,
3126                 GP_4_12_FN, FN_IP7_3_2,
3127                 GP_4_11_FN, FN_IP7_1_0,
3128                 GP_4_10_FN, FN_IP6_30_29,
3129                 GP_4_9_FN, FN_IP6_26_25,
3130                 GP_4_8_FN, FN_IP6_24_23,
3131                 GP_4_7_FN, FN_IP6_22_20,
3132                 GP_4_6_FN, FN_IP6_19_18,
3133                 GP_4_5_FN, FN_IP6_17_15,
3134                 GP_4_4_FN, FN_IP6_14_12,
3135                 GP_4_3_FN, FN_IP6_11_9,
3136                 GP_4_2_FN, FN_IP6_8,
3137                 GP_4_1_FN, FN_IP6_7_6,
3138                 GP_4_0_FN, FN_IP6_5_4 }
3139         },
3140         { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) {
3141                 GP_5_31_FN, FN_IP3_5,
3142                 GP_5_30_FN, FN_IP3_4,
3143                 GP_5_29_FN, FN_IP3_3,
3144                 GP_5_28_FN, FN_IP2_27,
3145                 GP_5_27_FN, FN_IP2_26,
3146                 GP_5_26_FN, FN_IP2_25,
3147                 GP_5_25_FN, FN_IP2_24,
3148                 GP_5_24_FN, FN_IP2_23,
3149                 GP_5_23_FN, FN_IP2_22,
3150                 GP_5_22_FN, FN_IP3_28,
3151                 GP_5_21_FN, FN_IP3_27,
3152                 GP_5_20_FN, FN_IP3_23,
3153                 GP_5_19_FN, FN_EX_WAIT0,
3154                 GP_5_18_FN, FN_WE1,
3155                 GP_5_17_FN, FN_WE0,
3156                 GP_5_16_FN, FN_RD,
3157                 GP_5_15_FN, FN_A16,
3158                 GP_5_14_FN, FN_A15,
3159                 GP_5_13_FN, FN_A14,
3160                 GP_5_12_FN, FN_A13,
3161                 GP_5_11_FN, FN_A12,
3162                 GP_5_10_FN, FN_A11,
3163                 GP_5_9_FN, FN_A10,
3164                 GP_5_8_FN, FN_A9,
3165                 GP_5_7_FN, FN_A8,
3166                 GP_5_6_FN, FN_A7,
3167                 GP_5_5_FN, FN_A6,
3168                 GP_5_4_FN, FN_A5,
3169                 GP_5_3_FN, FN_A4,
3170                 GP_5_2_FN, FN_A3,
3171                 GP_5_1_FN, FN_A2,
3172                 GP_5_0_FN, FN_A1 }
3173         },
3174         { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) {
3175                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3176                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3177                 0, 0, 0, 0, 0, 0, 0, 0,
3178                 0, 0,
3179                 0, 0,
3180                 0, 0,
3181                 GP_6_8_FN, FN_IP3_20,
3182                 GP_6_7_FN, FN_IP3_19,
3183                 GP_6_6_FN, FN_IP3_18,
3184                 GP_6_5_FN, FN_IP3_17,
3185                 GP_6_4_FN, FN_IP3_16,
3186                 GP_6_3_FN, FN_IP3_15,
3187                 GP_6_2_FN, FN_IP3_8,
3188                 GP_6_1_FN, FN_IP3_7,
3189                 GP_6_0_FN, FN_IP3_6 }
3190         },
3191
3192         { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
3193                              1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) {
3194                 /* IP0_31 [1] */
3195                 0, 0,
3196                 /* IP0_30_28 [3] */
3197                 FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
3198                 FN_HRTS1, FN_RX4_C, 0, 0,
3199                 /* IP0_27_26 [2] */
3200                 FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0,
3201                 /* IP0_25 [1] */
3202                 FN_CS0, FN_HSPI_CS2_B,
3203                 /* IP0_24_23 [2] */
3204                 FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0,
3205                 /* IP0_22_19 [4] */
3206                 FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
3207                 FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
3208                 FN_CTS0_B, 0, 0, 0,
3209                 0, 0, 0, 0,
3210                 /* IP0_18_16 [3] */
3211                 FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
3212                 FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0,
3213                 /* IP0_15_14 [2] */
3214                 FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
3215                 /* IP0_13_12 [2] */
3216                 FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
3217                 /* IP0_11_10 [2] */
3218                 FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0,
3219                 /* IP0_9_8 [2] */
3220                 FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0,
3221                 /* IP0_7_6 [2] */
3222                 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
3223                 /* IP0_5_3 [3] */
3224                 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
3225                 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
3226                 /* IP0_2_0 [3] */
3227                 FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
3228                 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
3229         },
3230         { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3231                              3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) {
3232                 /* IP1_31_29 [3] */
3233                 0, 0, 0, 0, 0, 0, 0, 0,
3234                 /* IP1_28_25 [4] */
3235                 FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
3236                 FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
3237                 FN_CC5_STATE26, FN_CC5_STATE34, 0, 0,
3238                 0, 0, 0, 0,
3239                 /* IP1_24_23 [2] */
3240                 FN_MLB_DAT, FN_PWM4, FN_RX4, 0,
3241                 /* IP1_22_21 [2] */
3242                 FN_MLB_SIG, FN_PWM3, FN_TX4, 0,
3243                 /* IP1_20_19 [2] */
3244                 FN_MLB_CLK, FN_PWM2, FN_SCK4, 0,
3245                 /* IP1_18_15 [4] */
3246                 FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1,
3247                 FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E,
3248                 FN_RX0_B, FN_SSI_WS9, 0, 0,
3249                 0, 0, 0, 0,
3250                 /* IP1_14_11 [4] */
3251                 FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
3252                 FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
3253                 FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0,
3254                 0, 0, 0, 0,
3255                 /* IP1_10_7 [4] */
3256                 FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE,
3257                 FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1,
3258                 FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0,
3259                 0, 0, 0, 0,
3260                 /* IP1_6_4 [3] */
3261                 FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
3262                 FN_ATACS00, 0, 0, 0,
3263                 /* IP1_3_2 [2] */
3264                 FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
3265                 /* IP1_1_0 [2] */
3266                 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 }
3267         },
3268         { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3269                              1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) {
3270                 /* IP2_31 [1] */
3271                 0, 0,
3272                 /* IP2_30_28 [3] */
3273                 FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
3274                 FN_AUDATA2, 0, 0, 0,
3275                 /* IP2_27 [1] */
3276                 FN_DU0_DR7, FN_LCDOUT7,
3277                 /* IP2_26 [1] */
3278                 FN_DU0_DR6, FN_LCDOUT6,
3279                 /* IP2_25 [1] */
3280                 FN_DU0_DR5, FN_LCDOUT5,
3281                 /* IP2_24 [1] */
3282                 FN_DU0_DR4, FN_LCDOUT4,
3283                 /* IP2_23 [1] */
3284                 FN_DU0_DR3, FN_LCDOUT3,
3285                 /* IP2_22 [1] */
3286                 FN_DU0_DR2, FN_LCDOUT2,
3287                 /* IP2_21_19 [3] */
3288                 FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0,
3289                 FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0,
3290                 /* IP2_18_16 [3] */
3291                 FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B,
3292                 FN_AUDATA0, FN_TX5_C, 0, 0,
3293                 /* IP2_15_12 [4] */
3294                 FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C,
3295                 FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17,
3296                 FN_CC5_STATE25, FN_CC5_STATE33, 0, 0,
3297                 0, 0, 0, 0,
3298                 /* IP2_11_8 [4] */
3299                 FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D,
3300                 FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B,
3301                 FN_CC5_OSCOUT, 0, 0, 0,
3302                 0, 0, 0, 0,
3303                 /* IP2_7_4 [4] */
3304                 FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5,
3305                 FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0,
3306                 FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32,
3307                 0, 0, 0, 0,
3308                 /* IP2_3_0 [4] */
3309                 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
3310                 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
3311                 FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
3312                 0, 0, 0, 0 }
3313         },
3314         { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3315                              3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1,
3316                              1, 3, 3, 1, 1, 1, 1, 1, 1, 3) {
3317             /* IP3_31_29 [3] */
3318             FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
3319             FN_SCL2_C, FN_REMOCON, 0, 0,
3320             /* IP3_28 [1] */
3321             FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
3322             /* IP3_27 [1] */
3323             FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
3324             /* IP3_26_24 [3] */
3325             FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
3326             FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0,
3327             /* IP3_23 [1] */
3328             FN_DU0_DOTCLKOUT0, FN_QCLK,
3329             /* IP3_22_21 [2] */
3330             FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B,
3331             /* IP3_20 [1] */
3332             FN_DU0_DB7, FN_LCDOUT23,
3333             /* IP3_19 [1] */
3334             FN_DU0_DB6, FN_LCDOUT22,
3335             /* IP3_18 [1] */
3336             FN_DU0_DB5, FN_LCDOUT21,
3337             /* IP3_17 [1] */
3338             FN_DU0_DB4, FN_LCDOUT20,
3339             /* IP3_16 [1] */
3340             FN_DU0_DB3, FN_LCDOUT19,
3341             /* IP3_15 [1] */
3342             FN_DU0_DB2, FN_LCDOUT18,
3343             /* IP3_14_12 [3] */
3344             FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1,
3345             FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0,
3346             /* IP3_11_9 [3] */
3347             FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1,
3348             FN_TCLK1, FN_AUDATA4, 0, 0,
3349             /* IP3_8 [1] */
3350             FN_DU0_DG7, FN_LCDOUT15,
3351             /* IP3_7 [1] */
3352             FN_DU0_DG6, FN_LCDOUT14,
3353             /* IP3_6 [1] */
3354             FN_DU0_DG5, FN_LCDOUT13,
3355             /* IP3_5 [1] */
3356             FN_DU0_DG4, FN_LCDOUT12,
3357             /* IP3_4 [1] */
3358             FN_DU0_DG3, FN_LCDOUT11,
3359             /* IP3_3 [1] */
3360             FN_DU0_DG2, FN_LCDOUT10,
3361             /* IP3_2_0 [3] */
3362             FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
3363             FN_AUDATA3, 0, 0, 0 }
3364         },
3365         { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3366                              3, 1, 1, 1, 1, 1, 1, 3, 3,
3367                              1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
3368             /* IP4_31_29 [3] */
3369             FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
3370             FN_TX5, FN_SCK0_D, 0, 0,
3371             /* IP4_28 [1] */
3372             FN_DU1_DG7, FN_VI2_R3,
3373             /* IP4_27 [1] */
3374             FN_DU1_DG6, FN_VI2_R2,
3375             /* IP4_26 [1] */
3376             FN_DU1_DG5, FN_VI2_R1,
3377             /* IP4_25 [1] */
3378             FN_DU1_DG4, FN_VI2_R0,
3379             /* IP4_24 [1] */
3380             FN_DU1_DG3, FN_VI2_G7,
3381             /* IP4_23 [1] */
3382             FN_DU1_DG2, FN_VI2_G6,
3383             /* IP4_22_20 [3] */
3384             FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
3385             FN_SCK5, FN_AUDATA7, FN_RX0_D, 0,
3386             /* IP4_19_17 [3] */
3387             FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2,
3388             FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0,
3389             /* IP4_16 [1] */
3390             FN_DU1_DR7, FN_VI2_G5,
3391             /* IP4_15 [1] */
3392             FN_DU1_DR6, FN_VI2_G4,
3393             /* IP4_14 [1] */
3394             FN_DU1_DR5, FN_VI2_G3,
3395             /* IP4_13 [1] */
3396             FN_DU1_DR4, FN_VI2_G2,
3397             /* IP4_12 [1] */
3398             FN_DU1_DR3, FN_VI2_G1,
3399             /* IP4_11 [1] */
3400             FN_DU1_DR2, FN_VI2_G0,
3401             /* IP4_10_8 [3] */
3402             FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD,
3403             FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0,
3404             /* IP4_7_5 [3] */
3405             FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK,
3406             FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0,
3407             /* IP4_4_2 [3] */
3408             FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
3409             FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
3410             /* IP4_1_0 [2] */
3411             FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C }
3412         },
3413         { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3414                              1, 2, 1, 4, 3, 4, 2, 2,
3415                              2, 2, 1, 1, 1, 1, 1, 1, 3) {
3416             /* IP5_31 [1] */
3417             0, 0,
3418             /* IP5_30_29 [2] */
3419             FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
3420             /* IP5_28 [1] */
3421             FN_AUDIO_CLKA, FN_CAN_TXCLK,
3422             /* IP5_27_24 [4] */
3423             FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP,
3424             FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT,
3425             FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0,
3426             0, 0, 0, 0,
3427             /* IP5_23_21 [3] */
3428             FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
3429             FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
3430             /* IP5_20_17 [4] */
3431             FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
3432             FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
3433             FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0,
3434             0, 0, 0, 0,
3435             /* IP5_16_15 [2] */
3436             FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0,
3437             /* IP5_14_13 [2] */
3438             FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0,
3439             /* IP5_12_11 [2] */
3440             FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0,
3441             /* IP5_10_9 [2] */
3442             FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D,
3443             /* IP5_8 [1] */
3444             FN_DU1_DB7, FN_SDA2_D,
3445             /* IP5_7 [1] */
3446             FN_DU1_DB6, FN_SCL2_D,
3447             /* IP5_6 [1] */
3448             FN_DU1_DB5, FN_VI2_R7,
3449             /* IP5_5 [1] */
3450             FN_DU1_DB4, FN_VI2_R6,
3451             /* IP5_4 [1] */
3452             FN_DU1_DB3, FN_VI2_R5,
3453             /* IP5_3 [1] */
3454             FN_DU1_DB2, FN_VI2_R4,
3455             /* IP5_2_0 [3] */
3456             FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
3457             FN_RX5, FN_RTS0_D_TANS_D, 0, 0 }
3458         },
3459         { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3460                              1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) {
3461             /* IP6_31 [1] */
3462             0, 0,
3463             /* IP6_30_29 [2] */
3464             FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
3465             /* IP_28_27 [2] */
3466             0, 0, 0, 0,
3467             /* IP6_26_25 [2] */
3468             FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
3469             /* IP6_24_23 [2] */
3470             FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX,
3471             /* IP6_22_20 [3] */
3472             FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3,
3473             FN_TCLK0_D, 0, 0, 0,
3474             /* IP6_19_18 [2] */
3475             FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0,
3476             /* IP6_17_15 [3] */
3477             FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
3478             FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0,
3479             /* IP6_14_12 [3] */
3480             FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX,
3481             FN_SSI_WS9_C, 0, 0, 0,
3482             /* IP6_11_9 [3] */
3483             FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX,
3484             FN_SSI_SCK9_C, 0, 0, 0,
3485             /* IP6_8 [1] */
3486             FN_SSI_SDATA2, FN_CAN_DEBUGOUT5,
3487             /* IP6_7_6 [2] */
3488             FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0,
3489             /* IP6_5_4 [2] */
3490             FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0,
3491             /* IP6_3_2 [2] */
3492             FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
3493             /* IP6_1_0 [2] */
3494             FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 }
3495         },
3496         { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3497                              1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) {
3498             /* IP7_31 [1] */
3499             0, 0,
3500             /* IP7_30_29 [2] */
3501             FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
3502             /* IP7_28_27 [2] */
3503             FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0,
3504             /* IP7_26_25 [2] */
3505             FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI,
3506             /* IP7_24_23 [2] */
3507             FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK,
3508             /* IP7_22_21 [2] */
3509             FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS,
3510             /* IP7_20_19 [2] */
3511             FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST,
3512             /* IP7_18_17 [2] */
3513             FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO,
3514             /* IP7_16_15 [2] */
3515             FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0,
3516             /* IP7_14_13 [2] */
3517             FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C,
3518             /* IP7_12_10 [3] */
3519             FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C,
3520             FN_HSPI_TX1_C, 0, 0, 0,
3521             /* IP7_9_7 [3] */
3522             FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B,
3523             FN_HSPI_CS1_C, 0, 0, 0,
3524             /* IP7_6_4 [3] */
3525             FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
3526             FN_HSPI_CLK1_C, 0, 0, 0,
3527             /* IP7_3_2 [2] */
3528             FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
3529             /* IP7_1_0 [2] */
3530             FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B }
3531         },
3532         { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
3533                              1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) {
3534             /* IP8_31 [1] */
3535             0, 0,
3536             /* IP8_30_28 [3] */
3537             FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
3538             FN_PWMFSW0_C, 0, 0, 0,
3539             /* IP8_27_25 [3] */
3540             FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
3541             FN_MMC1_CMD, FN_HSCK1_B, 0, 0,
3542             /* IP8_24_23 [2] */
3543             FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0,
3544             /* IP8_22_21 [2] */
3545             FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC,
3546             /* IP8_20 [1] */
3547             FN_VI0_CLK, FN_MMC1_CLK,
3548             /* IP8_19 [1] */
3549             FN_FMIN, FN_RDS_DATA,
3550             /* IP8_18 [1] */
3551             FN_BPFCLK, FN_PCMWE,
3552             /* IP8_17_16 [2] */
3553             FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0,
3554             /* IP8_15_12 [4] */
3555             FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS,
3556             FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31,
3557             FN_CC5_STATE39, 0, 0, 0,
3558             0, 0, 0, 0,
3559             /* IP8_11_8 [4] */
3560             FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO,
3561             FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30,
3562             FN_CC5_STATE38, 0, 0, 0,
3563             0, 0, 0, 0,
3564             /* IP8_7_4 [4] */
3565             FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI,
3566             FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29,
3567             FN_CC5_STATE37, 0, 0, 0,
3568             0, 0, 0, 0,
3569             /* IP8_3_0 [4] */
3570             FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
3571             FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
3572             FN_CC5_STATE36, 0, 0, 0,
3573             0, 0, 0, 0 }
3574         },
3575         { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
3576                              2, 2, 2, 2, 2, 3, 3, 2, 2,
3577                              2, 2, 1, 1, 1, 1, 2, 2) {
3578             /* IP9_31_30 [2] */
3579             0, 0, 0, 0,
3580             /* IP9_29_28 [2] */
3581             FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
3582             /* IP9_27_26 [2] */
3583             FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8,
3584             /* IP9_25_24 [2] */
3585             FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7,
3586             /* IP9_23_22 [2] */
3587             FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6,
3588             /* IP9_21_19 [3] */
3589             FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5,
3590             FN_TS_SDAT0, 0, 0, 0,
3591             /* IP9_18_16 [3] */
3592             FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4,
3593             FN_TS_SPSYNC0, 0, 0, 0,
3594             /* IP9_15_14 [2] */
3595             FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3,
3596             /* IP9_13_12 [2] */
3597             FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2,
3598             /* IP9_11_10 [2] */
3599             FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0,
3600             /* IP9_9_8 [2] */
3601             FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0,
3602             /* IP9_7 [1] */
3603             FN_VI0_DATA5_VI0_B5, FN_MMC1_D3,
3604             /* IP9_6 [1] */
3605             FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
3606             /* IP9_5 [1] */
3607             FN_VI0_DATA3_VI0_B3, FN_MMC1_D1,
3608             /* IP9_4 [1] */
3609             FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
3610             /* IP9_3_2 [2] */
3611             FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
3612             /* IP9_1_0 [2] */
3613             FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 }
3614         },
3615         { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
3616                              3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
3617             /* IP10_31_29 [3] */
3618             FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
3619             FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
3620             /* IP10_28_26 [3] */
3621             FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
3622             FN_PWMFSW0_E, 0, 0, 0,
3623             /* IP10_25_24 [2] */
3624             FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0,
3625             /* IP10_23_21 [3] */
3626             FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B,
3627             FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0,
3628             /* IP10_20_18 [3] */
3629             FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B,
3630             FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0,
3631             /* IP10_17_15 [3] */
3632             FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
3633             FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0,
3634             /* IP10_14_12 [3] */
3635             FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B,
3636             FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0,
3637             /* IP10_11_9 [3] */
3638             FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3,
3639             FN_ARM_TRACEDATA_13, 0, 0, 0,
3640             /* IP10_8_6 [3] */
3641             FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
3642             FN_ARM_TRACEDATA_12, 0, 0, 0,
3643             /* IP10_5_3 [3] */
3644             FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11,
3645             FN_DACK0_C, FN_DRACK0_C, 0, 0,
3646             /* IP10_2_0 [3] */
3647             FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
3648             FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 }
3649         },
3650         { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
3651                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3652             /* IP11_31_30 [2] */
3653             0, 0, 0, 0,
3654             /* IP11_29_27 [3] */
3655             FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
3656             FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
3657             /* IP11_26_24 [3] */
3658             FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1,
3659             FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
3660             /* IP11_23_21 [3] */
3661             FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
3662             FN_HSPI_RX1_D, 0, 0, 0,
3663             /* IP11_20_18 [3] */
3664             FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
3665             FN_HSPI_TX1_D, 0, 0, 0,
3666             /* IP11_17_15 [3] */
3667             FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK,
3668             FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0,
3669             /* IP11_14_12 [3] */
3670             FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
3671             FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0,
3672             /* IP11_11_9 [3] */
3673             FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO,
3674             FN_ADICHS0_B, 0, 0, 0,
3675             /* IP11_8_6 [3] */
3676             FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI,
3677             FN_ADIDATA_B, 0, 0, 0,
3678             /* IP11_5_3 [3] */
3679             FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS,
3680             FN_ADICS_B_SAMP_B, 0, 0, 0,
3681             /* IP11_2_0 [3] */
3682             FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
3683             FN_ADICLK_B, 0, 0, 0 }
3684         },
3685         { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
3686                              4, 4, 4, 2, 3, 3, 3, 3, 3, 3) {
3687             /* IP12_31_28 [4] */
3688             0, 0, 0, 0, 0, 0, 0, 0,
3689             0, 0, 0, 0, 0, 0, 0, 0,
3690             /* IP12_27_24 [4] */
3691             0, 0, 0, 0, 0, 0, 0, 0,
3692             0, 0, 0, 0, 0, 0, 0, 0,
3693             /* IP12_23_20 [4] */
3694             0, 0, 0, 0, 0, 0, 0, 0,
3695             0, 0, 0, 0, 0, 0, 0, 0,
3696             /* IP12_19_18 [2] */
3697             0, 0, 0, 0,
3698             /* IP12_17_15 [3] */
3699             FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE,
3700             FN_SCK4_B, 0, 0, 0,
3701             /* IP12_14_12 [3] */
3702             FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
3703             FN_RX4_B, FN_SIM_CLK_B, 0, 0,
3704             /* IP12_11_9 [3] */
3705             FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE,
3706             FN_TX4_B, FN_SIM_D_B, 0, 0,
3707             /* IP12_8_6 [3] */
3708             FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
3709             FN_SIM_RST_B, FN_HRX0_B, 0, 0,
3710             /* IP12_5_3 [3] */
3711             FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1,
3712             FN_SCL1_C, FN_HTX0_B, 0, 0,
3713             /* IP12_2_0 [3] */
3714             FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
3715             FN_SCK2, FN_HSCK0_B, 0, 0 }
3716         },
3717         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,
3718                              2, 2, 3, 3, 2, 2, 2, 2, 2,
3719                              1, 1, 1, 1, 1, 1, 1, 2, 1, 2) {
3720             /* SEL_SCIF5 [2] */
3721             FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
3722             /* SEL_SCIF4 [2] */
3723             FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
3724             /* SEL_SCIF3 [3] */
3725             FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
3726             FN_SEL_SCIF3_4, 0, 0, 0,
3727             /* SEL_SCIF2 [3] */
3728             FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
3729             FN_SEL_SCIF2_4, 0, 0, 0,
3730             /* SEL_SCIF1 [2] */
3731             FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
3732             /* SEL_SCIF0 [2] */
3733             FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
3734             /* SEL_SSI9 [2] */
3735             FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0,
3736             /* SEL_SSI8 [2] */
3737             FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0,
3738             /* SEL_SSI7 [2] */
3739             FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
3740             /* SEL_VI0 [1] */
3741             FN_SEL_VI0_0, FN_SEL_VI0_1,
3742             /* SEL_SD2 [1] */
3743             FN_SEL_SD2_0, FN_SEL_SD2_1,
3744             /* SEL_INT3 [1] */
3745             FN_SEL_INT3_0, FN_SEL_INT3_1,
3746             /* SEL_INT2 [1] */
3747             FN_SEL_INT2_0, FN_SEL_INT2_1,
3748             /* SEL_INT1 [1] */
3749             FN_SEL_INT1_0, FN_SEL_INT1_1,
3750             /* SEL_INT0 [1] */
3751             FN_SEL_INT0_0, FN_SEL_INT0_1,
3752             /* SEL_IE [1] */
3753             FN_SEL_IE_0, FN_SEL_IE_1,
3754             /* SEL_EXBUS2 [2] */
3755             FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0,
3756             /* SEL_EXBUS1 [1] */
3757             FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
3758             /* SEL_EXBUS0 [2] */
3759             FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 }
3760         },
3761         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
3762                              2, 2, 2, 2, 1, 1, 1, 3, 1,
3763                              2, 2, 2, 2, 1, 1, 2, 1, 2, 2) {
3764             /* SEL_TMU1 [2] */
3765             FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,
3766             /* SEL_TMU0 [2] */
3767             FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
3768             /* SEL_SCIF [2] */
3769             FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
3770             /* SEL_CANCLK [2] */
3771             FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0,
3772             /* SEL_CAN0 [1] */
3773             FN_SEL_CAN0_0, FN_SEL_CAN0_1,
3774             /* SEL_HSCIF1 [1] */
3775             FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
3776             /* SEL_HSCIF0 [1] */
3777             FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
3778             /* SEL_PWMFSW [3] */
3779             FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
3780             FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0,
3781             /* SEL_ADI [1] */
3782             FN_SEL_ADI_0, FN_SEL_ADI_1,
3783             /* [2] */
3784             0, 0, 0, 0,
3785             /* [2] */
3786             0, 0, 0, 0,
3787             /* [2] */
3788             0, 0, 0, 0,
3789             /* SEL_GPS [2] */
3790             FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
3791             /* SEL_SIM [1] */
3792             FN_SEL_SIM_0, FN_SEL_SIM_1,
3793             /* SEL_HSPI2 [1] */
3794             FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
3795             /* SEL_HSPI1 [2] */
3796             FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
3797             /* SEL_I2C3 [1] */
3798             FN_SEL_I2C3_0, FN_SEL_I2C3_1,
3799             /* SEL_I2C2 [2] */
3800             FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
3801             /* SEL_I2C1 [2] */
3802             FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
3803         },
3804         { },
3805 };
3806
3807 const struct sh_pfc_soc_info r8a7779_pinmux_info = {
3808         .name = "r8a7779_pfc",
3809
3810         .unlock_reg = 0xfffc0000, /* PMMR */
3811
3812         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3813
3814         .pins = pinmux_pins,
3815         .nr_pins = ARRAY_SIZE(pinmux_pins),
3816         .groups = pinmux_groups,
3817         .nr_groups = ARRAY_SIZE(pinmux_groups),
3818         .functions = pinmux_functions,
3819         .nr_functions = ARRAY_SIZE(pinmux_functions),
3820
3821         .cfg_regs = pinmux_config_regs,
3822
3823         .gpio_data = pinmux_data,
3824         .gpio_data_size = ARRAY_SIZE(pinmux_data),
3825 };